2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include "cx25821-medusa-video.h"
27 #include "cx25821-biffuncs.h"
30 * medusa_enable_bluefield_output()
32 * Enable the generation of blue filed output if no video
35 static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel,
40 int out_ctrl = OUT_CTRL1;
41 int out_ctrl_ns = OUT_CTRL_NS;
48 out_ctrl = VDEC_B_OUT_CTRL1;
49 out_ctrl_ns = VDEC_B_OUT_CTRL_NS;
52 out_ctrl = VDEC_C_OUT_CTRL1;
53 out_ctrl_ns = VDEC_C_OUT_CTRL_NS;
56 out_ctrl = VDEC_D_OUT_CTRL1;
57 out_ctrl_ns = VDEC_D_OUT_CTRL_NS;
60 out_ctrl = VDEC_E_OUT_CTRL1;
61 out_ctrl_ns = VDEC_E_OUT_CTRL_NS;
64 out_ctrl = VDEC_F_OUT_CTRL1;
65 out_ctrl_ns = VDEC_F_OUT_CTRL_NS;
68 out_ctrl = VDEC_G_OUT_CTRL1;
69 out_ctrl_ns = VDEC_G_OUT_CTRL_NS;
72 out_ctrl = VDEC_H_OUT_CTRL1;
73 out_ctrl_ns = VDEC_H_OUT_CTRL_NS;
77 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp);
78 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */
80 value |= 0x00000080; /* set BLUE_FIELD_EN */
81 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value);
83 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp);
86 value |= 0x00000080; /* set BLUE_FIELD_EN */
87 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value);
90 static int medusa_initialize_ntsc(struct cx25821_dev *dev)
97 for (i = 0; i < MAX_DECODERS; i++) {
98 /* set video format NTSC-M */
99 value = cx25821_i2c_read(&dev->i2c_bus[0],
100 MODE_CTRL + (0x200 * i), &tmp);
102 /* enable the fast locking mode bit[16] */
104 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
105 MODE_CTRL + (0x200 * i), value);
107 /* resolution NTSC 720x480 */
108 value = cx25821_i2c_read(&dev->i2c_bus[0],
109 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
112 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
113 HORIZ_TIM_CTRL + (0x200 * i), value);
115 value = cx25821_i2c_read(&dev->i2c_bus[0],
116 VERT_TIM_CTRL + (0x200 * i), &tmp);
118 value |= 0x1C1E001A; /* vblank_cnt + 2 to get camera ID */
119 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
120 VERT_TIM_CTRL + (0x200 * i), value);
122 /* chroma subcarrier step size */
123 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
124 SC_STEP_SIZE + (0x200 * i), 0x43E00000);
126 /* enable VIP optional active */
127 value = cx25821_i2c_read(&dev->i2c_bus[0],
128 OUT_CTRL_NS + (0x200 * i), &tmp);
131 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
132 OUT_CTRL_NS + (0x200 * i), value);
134 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
135 value = cx25821_i2c_read(&dev->i2c_bus[0],
136 OUT_CTRL1 + (0x200 * i), &tmp);
139 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
140 OUT_CTRL1 + (0x200 * i), value);
143 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
144 * when the input switching rate < 16 fields
146 value = cx25821_i2c_read(&dev->i2c_bus[0],
147 MISC_TIM_CTRL + (0x200 * i), &tmp);
148 /* disable special play detection */
149 value = setBitAtPos(value, 14);
150 value = clearBitAtPos(value, 15);
151 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
152 MISC_TIM_CTRL + (0x200 * i), value);
154 /* set vbi_gate_en to 0 */
155 value = cx25821_i2c_read(&dev->i2c_bus[0],
156 DFE_CTRL1 + (0x200 * i), &tmp);
157 value = clearBitAtPos(value, 29);
158 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
159 DFE_CTRL1 + (0x200 * i), value);
161 /* Enable the generation of blue field output if no video */
162 medusa_enable_bluefield_output(dev, i, 1);
165 for (i = 0; i < MAX_ENCODERS; i++) {
167 value = cx25821_i2c_read(&dev->i2c_bus[0],
168 DENC_A_REG_1 + (0x100 * i), &tmp);
171 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
172 DENC_A_REG_1 + (0x100 * i), value);
174 /* burst begin and burst end */
175 value = cx25821_i2c_read(&dev->i2c_bus[0],
176 DENC_A_REG_2 + (0x100 * i), &tmp);
179 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
180 DENC_A_REG_2 + (0x100 * i), value);
182 value = cx25821_i2c_read(&dev->i2c_bus[0],
183 DENC_A_REG_3 + (0x100 * i), &tmp);
186 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
187 DENC_A_REG_3 + (0x100 * i), value);
189 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */
190 value = cx25821_i2c_read(&dev->i2c_bus[0],
191 DENC_A_REG_4 + (0x100 * i), &tmp);
194 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
195 DENC_A_REG_4 + (0x100 * i), value);
197 value = cx25821_i2c_read(&dev->i2c_bus[0],
198 DENC_A_REG_5 + (0x100 * i), &tmp);
201 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
202 DENC_A_REG_5 + (0x100 * i), value);
204 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
205 DENC_A_REG_6 + (0x100 * i), 0x009A89C1);
207 /* Subcarrier Increment */
208 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
209 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F);
212 /* set picture resolutions */
214 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
216 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
218 /* set Bypass input format to NTSC 525 lines */
219 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
221 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
226 static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
229 u32 value = 0, tmp = 0;
231 /* Setup for 2D threshold */
232 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
233 COMB_2D_HFS_CFG + (0x200 * dec), 0x20002861);
234 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
235 COMB_2D_HFD_CFG + (0x200 * dec), 0x20002861);
236 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
237 COMB_2D_LF_CFG + (0x200 * dec), 0x200A1023);
239 /* Setup flat chroma and luma thresholds */
240 value = cx25821_i2c_read(&dev->i2c_bus[0],
241 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp);
243 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
244 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value);
246 /* set comb 2D blend */
247 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
248 COMB_2D_BLEND + (0x200 * dec), 0x210F0F0F);
250 /* COMB MISC CONTROL */
251 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
252 COMB_MISC_CTRL + (0x200 * dec), 0x41120A7F);
257 static int medusa_initialize_pal(struct cx25821_dev *dev)
264 for (i = 0; i < MAX_DECODERS; i++) {
265 /* set video format PAL-BDGHI */
266 value = cx25821_i2c_read(&dev->i2c_bus[0],
267 MODE_CTRL + (0x200 * i), &tmp);
269 /* enable the fast locking mode bit[16] */
271 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
272 MODE_CTRL + (0x200 * i), value);
274 /* resolution PAL 720x576 */
275 value = cx25821_i2c_read(&dev->i2c_bus[0],
276 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
279 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
280 HORIZ_TIM_CTRL + (0x200 * i), value);
282 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */
283 value = cx25821_i2c_read(&dev->i2c_bus[0],
284 VERT_TIM_CTRL + (0x200 * i), &tmp);
286 value |= 0x28240026; /* vblank_cnt + 2 to get camera ID */
287 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
288 VERT_TIM_CTRL + (0x200 * i), value);
290 /* chroma subcarrier step size */
291 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
292 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0);
294 /* enable VIP optional active */
295 value = cx25821_i2c_read(&dev->i2c_bus[0],
296 OUT_CTRL_NS + (0x200 * i), &tmp);
299 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
300 OUT_CTRL_NS + (0x200 * i), value);
302 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
303 value = cx25821_i2c_read(&dev->i2c_bus[0],
304 OUT_CTRL1 + (0x200 * i), &tmp);
307 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
308 OUT_CTRL1 + (0x200 * i), value);
311 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
312 * when the input switching rate < 16 fields
314 value = cx25821_i2c_read(&dev->i2c_bus[0],
315 MISC_TIM_CTRL + (0x200 * i), &tmp);
316 /* disable special play detection */
317 value = setBitAtPos(value, 14);
318 value = clearBitAtPos(value, 15);
319 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
320 MISC_TIM_CTRL + (0x200 * i), value);
322 /* set vbi_gate_en to 0 */
323 value = cx25821_i2c_read(&dev->i2c_bus[0],
324 DFE_CTRL1 + (0x200 * i), &tmp);
325 value = clearBitAtPos(value, 29);
326 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
327 DFE_CTRL1 + (0x200 * i), value);
329 medusa_PALCombInit(dev, i);
331 /* Enable the generation of blue field output if no video */
332 medusa_enable_bluefield_output(dev, i, 1);
335 for (i = 0; i < MAX_ENCODERS; i++) {
337 value = cx25821_i2c_read(&dev->i2c_bus[0],
338 DENC_A_REG_1 + (0x100 * i), &tmp);
341 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
342 DENC_A_REG_1 + (0x100 * i), value);
344 /* burst begin and burst end */
345 value = cx25821_i2c_read(&dev->i2c_bus[0],
346 DENC_A_REG_2 + (0x100 * i), &tmp);
349 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
350 DENC_A_REG_2 + (0x100 * i), value);
352 /* hblank and vactive */
353 value = cx25821_i2c_read(&dev->i2c_bus[0],
354 DENC_A_REG_3 + (0x100 * i), &tmp);
357 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
358 DENC_A_REG_3 + (0x100 * i), value);
360 /* set PAL vblank, phase alternation, 0 IRE pedestal */
361 value = cx25821_i2c_read(&dev->i2c_bus[0],
362 DENC_A_REG_4 + (0x100 * i), &tmp);
365 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
366 DENC_A_REG_4 + (0x100 * i), value);
368 value = cx25821_i2c_read(&dev->i2c_bus[0],
369 DENC_A_REG_5 + (0x100 * i), &tmp);
372 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
373 DENC_A_REG_5 + (0x100 * i), value);
375 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
376 DENC_A_REG_6 + (0x100 * i), 0x00A493CF);
378 /* Subcarrier Increment */
379 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
380 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB);
383 /* set picture resolutions */
385 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
387 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
389 /* set Bypass input format to PAL 625 lines */
390 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
392 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
397 int medusa_set_videostandard(struct cx25821_dev *dev)
400 u32 value = 0, tmp = 0;
402 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
403 status = medusa_initialize_pal(dev);
405 status = medusa_initialize_ntsc(dev);
407 /* Enable DENC_A output */
408 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp);
409 value = setBitAtPos(value, 4);
410 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value);
412 /* Enable DENC_B output */
413 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp);
414 value = setBitAtPos(value, 4);
415 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value);
420 void medusa_set_resolution(struct cx25821_dev *dev, int width,
424 int decoder_count = 0;
427 const int MAX_WIDTH = 720;
429 /* validate the width */
430 if (width > MAX_WIDTH) {
431 pr_info("%s(): width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n",
432 __func__, width, MAX_WIDTH);
436 if (decoder_select <= 7 && decoder_select >= 0) {
437 decoder = decoder_select;
438 decoder_count = decoder_select + 1;
441 decoder_count = _num_decoders;
471 for (; decoder < decoder_count; decoder++) {
472 /* write scaling values for each decoder */
473 cx25821_i2c_write(&dev->i2c_bus[0],
474 HSCALE_CTRL + (0x200 * decoder), hscale);
475 cx25821_i2c_write(&dev->i2c_bus[0],
476 VSCALE_CTRL + (0x200 * decoder), vscale);
480 static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
485 u32 disp_cnt_reg = DISP_AB_CNT;
488 if (decoder < VDEC_A || decoder > VDEC_H) {
497 disp_cnt_reg = DISP_CD_CNT;
501 disp_cnt_reg = DISP_EF_CNT;
505 disp_cnt_reg = DISP_GH_CNT;
509 _display_field_cnt[decoder] = duration;
511 /* update hardware */
512 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp);
514 if (!(decoder % 2)) { /* EVEN decoder */
515 fld_cnt &= 0xFFFF0000;
518 fld_cnt &= 0x0000FFFF;
519 fld_cnt |= ((u32) duration) << 16;
522 cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt);
525 /* Map to Medusa register setting */
526 static int mapM(int srcMin, int srcMax, int srcVal, int dstMin, int dstMax,
533 if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax))
536 * This is the overall expression used:
538 * (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin;
539 * but we need to account for rounding so below we use the modulus
540 * operator to find the remainder and increment if necessary.
542 numerator = (srcVal - srcMin) * (dstMax - dstMin);
543 denominator = srcMax - srcMin;
544 quotient = numerator / denominator;
546 if (2 * (numerator % denominator) >= denominator)
549 *dstVal = quotient + dstMin;
554 static unsigned long convert_to_twos(long numeric, unsigned long bits_len)
561 temp = ~(abs(numeric) & 0xFF);
567 int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder)
571 u32 val = 0, tmp = 0;
573 if ((brightness > VIDEO_PROCAMP_MAX) ||
574 (brightness < VIDEO_PROCAMP_MIN)) {
577 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness,
578 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
579 value = convert_to_twos(value, 8);
580 val = cx25821_i2c_read(&dev->i2c_bus[0],
581 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp);
583 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
584 VDEC_A_BRITE_CTRL + (0x200 * decoder), val | value);
588 int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder)
592 u32 val = 0, tmp = 0;
594 if ((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN)) {
598 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast,
599 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
600 val = cx25821_i2c_read(&dev->i2c_bus[0],
601 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp);
603 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
604 VDEC_A_CNTRST_CTRL + (0x200 * decoder), val | value);
609 int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder)
613 u32 val = 0, tmp = 0;
615 if ((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) {
619 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue,
620 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
622 value = convert_to_twos(value, 8);
623 val = cx25821_i2c_read(&dev->i2c_bus[0],
624 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp);
627 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
628 VDEC_A_HUE_CTRL + (0x200 * decoder), val | value);
633 int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder)
637 u32 val = 0, tmp = 0;
639 if ((saturation > VIDEO_PROCAMP_MAX) ||
640 (saturation < VIDEO_PROCAMP_MIN)) {
644 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation,
645 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
647 val = cx25821_i2c_read(&dev->i2c_bus[0],
648 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp);
650 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
651 VDEC_A_USAT_CTRL + (0x200 * decoder), val | value);
653 val = cx25821_i2c_read(&dev->i2c_bus[0],
654 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp);
656 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
657 VDEC_A_VSAT_CTRL + (0x200 * decoder), val | value);
662 /* Program the display sequence and monitor output. */
664 int medusa_video_init(struct cx25821_dev *dev)
666 u32 value = 0, tmp = 0;
670 _num_decoders = dev->_max_num_decoders;
672 /* disable Auto source selection on all video decoders */
673 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
675 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
680 /* Turn off Master source switch enable */
681 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
683 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
688 for (i = 0; i < _num_decoders; i++)
689 medusa_set_decoderduration(dev, i, _display_field_cnt[i]);
691 /* Select monitor as DENC A input, power up the DAC */
692 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp);
694 value |= 0x00090008; /* set en_active */
695 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value);
700 /* enable input is VIP/656 */
701 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
702 value |= 0x00040100; /* enable VIP */
703 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
708 /* select AFE clock to output mode */
709 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
711 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL,
717 /* Turn on all of the data out and control output pins. */
718 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp);
720 if (_num_decoders == MAX_DECODERS) {
722 * Note: The octal board does not support control pins(bit16-19)
723 * These bits are ignored in the octal board.
725 * disable VDEC A-C port, default to Mobilygen Interface
729 /* disable VDEC A-C port, default to Mobilygen Interface */
734 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value);
739 ret_val = medusa_set_videostandard(dev);