2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/kref.h>
35 #include <linux/random.h>
36 #include <linux/debugfs.h>
37 #include <linux/export.h>
38 #include <linux/delay.h>
39 #include <rdma/ib_umem.h>
43 MAX_PENDING_REG_MR = 8,
50 static __be64 *mr_align(__be64 *ptr, int align)
52 unsigned long mask = align - 1;
54 return (__be64 *)(((unsigned long)ptr + mask) & ~mask);
57 static int order2idx(struct mlx5_ib_dev *dev, int order)
59 struct mlx5_mr_cache *cache = &dev->cache;
61 if (order < cache->ent[0].order)
64 return order - cache->ent[0].order;
67 static void reg_mr_callback(int status, void *context)
69 struct mlx5_ib_mr *mr = context;
70 struct mlx5_ib_dev *dev = mr->dev;
71 struct mlx5_mr_cache *cache = &dev->cache;
72 int c = order2idx(dev, mr->order);
73 struct mlx5_cache_ent *ent = &cache->ent[c];
77 spin_lock_irqsave(&ent->lock, flags);
79 spin_unlock_irqrestore(&ent->lock, flags);
81 mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status);
84 mod_timer(&dev->delay_timer, jiffies + HZ);
88 if (mr->out.hdr.status) {
89 mlx5_ib_warn(dev, "failed - status %d, syndorme 0x%x\n",
91 be32_to_cpu(mr->out.hdr.syndrome));
94 mod_timer(&dev->delay_timer, jiffies + HZ);
98 spin_lock_irqsave(&dev->mdev.priv.mkey_lock, flags);
99 key = dev->mdev.priv.mkey_key++;
100 spin_unlock_irqrestore(&dev->mdev.priv.mkey_lock, flags);
101 mr->mmr.key = mlx5_idx_to_mkey(be32_to_cpu(mr->out.mkey) & 0xffffff) | key;
103 cache->last_add = jiffies;
105 spin_lock_irqsave(&ent->lock, flags);
106 list_add_tail(&mr->list, &ent->head);
109 spin_unlock_irqrestore(&ent->lock, flags);
112 static int add_keys(struct mlx5_ib_dev *dev, int c, int num)
114 struct mlx5_mr_cache *cache = &dev->cache;
115 struct mlx5_cache_ent *ent = &cache->ent[c];
116 struct mlx5_create_mkey_mbox_in *in;
117 struct mlx5_ib_mr *mr;
118 int npages = 1 << ent->order;
122 in = kzalloc(sizeof(*in), GFP_KERNEL);
126 for (i = 0; i < num; i++) {
127 if (ent->pending >= MAX_PENDING_REG_MR) {
132 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
137 mr->order = ent->order;
140 in->seg.status = 1 << 6;
141 in->seg.xlt_oct_size = cpu_to_be32((npages + 1) / 2);
142 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
143 in->seg.flags = MLX5_ACCESS_MODE_MTT | MLX5_PERM_UMR_EN;
144 in->seg.log2_page_size = 12;
146 spin_lock_irq(&ent->lock);
148 spin_unlock_irq(&ent->lock);
150 err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in,
151 sizeof(*in), reg_mr_callback,
154 mlx5_ib_warn(dev, "create mkey failed %d\n", err);
164 static void remove_keys(struct mlx5_ib_dev *dev, int c, int num)
166 struct mlx5_mr_cache *cache = &dev->cache;
167 struct mlx5_cache_ent *ent = &cache->ent[c];
168 struct mlx5_ib_mr *mr;
172 for (i = 0; i < num; i++) {
173 spin_lock_irq(&ent->lock);
174 if (list_empty(&ent->head)) {
175 spin_unlock_irq(&ent->lock);
178 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
182 spin_unlock_irq(&ent->lock);
183 err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
185 mlx5_ib_warn(dev, "failed destroy mkey\n");
191 static ssize_t size_write(struct file *filp, const char __user *buf,
192 size_t count, loff_t *pos)
194 struct mlx5_cache_ent *ent = filp->private_data;
195 struct mlx5_ib_dev *dev = ent->dev;
201 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
204 c = order2idx(dev, ent->order);
205 lbuf[sizeof(lbuf) - 1] = 0;
207 if (sscanf(lbuf, "%u", &var) != 1)
210 if (var < ent->limit)
213 if (var > ent->size) {
215 err = add_keys(dev, c, var - ent->size);
216 if (err && err != -EAGAIN)
219 usleep_range(3000, 5000);
221 } else if (var < ent->size) {
222 remove_keys(dev, c, ent->size - var);
228 static ssize_t size_read(struct file *filp, char __user *buf, size_t count,
231 struct mlx5_cache_ent *ent = filp->private_data;
238 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size);
242 if (copy_to_user(buf, lbuf, err))
250 static const struct file_operations size_fops = {
251 .owner = THIS_MODULE,
257 static ssize_t limit_write(struct file *filp, const char __user *buf,
258 size_t count, loff_t *pos)
260 struct mlx5_cache_ent *ent = filp->private_data;
261 struct mlx5_ib_dev *dev = ent->dev;
267 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
270 c = order2idx(dev, ent->order);
271 lbuf[sizeof(lbuf) - 1] = 0;
273 if (sscanf(lbuf, "%u", &var) != 1)
281 if (ent->cur < ent->limit) {
282 err = add_keys(dev, c, 2 * ent->limit - ent->cur);
290 static ssize_t limit_read(struct file *filp, char __user *buf, size_t count,
293 struct mlx5_cache_ent *ent = filp->private_data;
300 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit);
304 if (copy_to_user(buf, lbuf, err))
312 static const struct file_operations limit_fops = {
313 .owner = THIS_MODULE,
315 .write = limit_write,
319 static int someone_adding(struct mlx5_mr_cache *cache)
323 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
324 if (cache->ent[i].cur < cache->ent[i].limit)
331 static void __cache_work_func(struct mlx5_cache_ent *ent)
333 struct mlx5_ib_dev *dev = ent->dev;
334 struct mlx5_mr_cache *cache = &dev->cache;
335 int i = order2idx(dev, ent->order);
341 ent = &dev->cache.ent[i];
342 if (ent->cur < 2 * ent->limit && !dev->fill_delay) {
343 err = add_keys(dev, i, 1);
344 if (ent->cur < 2 * ent->limit) {
345 if (err == -EAGAIN) {
346 mlx5_ib_dbg(dev, "returned eagain, order %d\n",
348 queue_delayed_work(cache->wq, &ent->dwork,
349 msecs_to_jiffies(3));
351 mlx5_ib_warn(dev, "command failed order %d, err %d\n",
353 queue_delayed_work(cache->wq, &ent->dwork,
354 msecs_to_jiffies(1000));
356 queue_work(cache->wq, &ent->work);
359 } else if (ent->cur > 2 * ent->limit) {
360 if (!someone_adding(cache) &&
361 time_after(jiffies, cache->last_add + 300 * HZ)) {
362 remove_keys(dev, i, 1);
363 if (ent->cur > ent->limit)
364 queue_work(cache->wq, &ent->work);
366 queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ);
371 static void delayed_cache_work_func(struct work_struct *work)
373 struct mlx5_cache_ent *ent;
375 ent = container_of(work, struct mlx5_cache_ent, dwork.work);
376 __cache_work_func(ent);
379 static void cache_work_func(struct work_struct *work)
381 struct mlx5_cache_ent *ent;
383 ent = container_of(work, struct mlx5_cache_ent, work);
384 __cache_work_func(ent);
387 static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order)
389 struct mlx5_mr_cache *cache = &dev->cache;
390 struct mlx5_ib_mr *mr = NULL;
391 struct mlx5_cache_ent *ent;
395 c = order2idx(dev, order);
396 if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
397 mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
401 for (i = c; i < MAX_MR_CACHE_ENTRIES; i++) {
402 ent = &cache->ent[i];
404 mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);
406 spin_lock_irq(&ent->lock);
407 if (!list_empty(&ent->head)) {
408 mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
412 spin_unlock_irq(&ent->lock);
413 if (ent->cur < ent->limit)
414 queue_work(cache->wq, &ent->work);
417 spin_unlock_irq(&ent->lock);
419 queue_work(cache->wq, &ent->work);
426 cache->ent[c].miss++;
431 static void free_cached_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
433 struct mlx5_mr_cache *cache = &dev->cache;
434 struct mlx5_cache_ent *ent;
438 c = order2idx(dev, mr->order);
439 if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
440 mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c);
443 ent = &cache->ent[c];
444 spin_lock_irq(&ent->lock);
445 list_add_tail(&mr->list, &ent->head);
447 if (ent->cur > 2 * ent->limit)
449 spin_unlock_irq(&ent->lock);
452 queue_work(cache->wq, &ent->work);
455 static void clean_keys(struct mlx5_ib_dev *dev, int c)
457 struct mlx5_mr_cache *cache = &dev->cache;
458 struct mlx5_cache_ent *ent = &cache->ent[c];
459 struct mlx5_ib_mr *mr;
462 cancel_delayed_work(&ent->dwork);
464 spin_lock_irq(&ent->lock);
465 if (list_empty(&ent->head)) {
466 spin_unlock_irq(&ent->lock);
469 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
473 spin_unlock_irq(&ent->lock);
474 err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
476 mlx5_ib_warn(dev, "failed destroy mkey\n");
482 static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev)
484 struct mlx5_mr_cache *cache = &dev->cache;
485 struct mlx5_cache_ent *ent;
488 if (!mlx5_debugfs_root)
491 cache->root = debugfs_create_dir("mr_cache", dev->mdev.priv.dbg_root);
495 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
496 ent = &cache->ent[i];
497 sprintf(ent->name, "%d", ent->order);
498 ent->dir = debugfs_create_dir(ent->name, cache->root);
502 ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent,
507 ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent,
512 ent->fcur = debugfs_create_u32("cur", 0400, ent->dir,
517 ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir,
526 static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev)
528 if (!mlx5_debugfs_root)
531 debugfs_remove_recursive(dev->cache.root);
534 static void delay_time_func(unsigned long ctx)
536 struct mlx5_ib_dev *dev = (struct mlx5_ib_dev *)ctx;
541 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
543 struct mlx5_mr_cache *cache = &dev->cache;
544 struct mlx5_cache_ent *ent;
549 cache->wq = create_singlethread_workqueue("mkey_cache");
551 mlx5_ib_warn(dev, "failed to create work queue\n");
555 setup_timer(&dev->delay_timer, delay_time_func, (unsigned long)dev);
556 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
557 INIT_LIST_HEAD(&cache->ent[i].head);
558 spin_lock_init(&cache->ent[i].lock);
560 ent = &cache->ent[i];
561 INIT_LIST_HEAD(&ent->head);
562 spin_lock_init(&ent->lock);
566 if (dev->mdev.profile->mask & MLX5_PROF_MASK_MR_CACHE)
567 limit = dev->mdev.profile->mr_cache[i].limit;
571 INIT_WORK(&ent->work, cache_work_func);
572 INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
574 queue_work(cache->wq, &ent->work);
577 err = mlx5_mr_cache_debugfs_init(dev);
579 mlx5_ib_warn(dev, "cache debugfs failure\n");
584 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
588 dev->cache.stopped = 1;
589 flush_workqueue(dev->cache.wq);
591 mlx5_mr_cache_debugfs_cleanup(dev);
593 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++)
596 destroy_workqueue(dev->cache.wq);
597 del_timer_sync(&dev->delay_timer);
602 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc)
604 struct mlx5_ib_dev *dev = to_mdev(pd->device);
605 struct mlx5_core_dev *mdev = &dev->mdev;
606 struct mlx5_create_mkey_mbox_in *in;
607 struct mlx5_mkey_seg *seg;
608 struct mlx5_ib_mr *mr;
611 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
613 return ERR_PTR(-ENOMEM);
615 in = kzalloc(sizeof(*in), GFP_KERNEL);
622 seg->flags = convert_access(acc) | MLX5_ACCESS_MODE_PA;
623 seg->flags_pd = cpu_to_be32(to_mpd(pd)->pdn | MLX5_MKEY_LEN64);
624 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
627 err = mlx5_core_create_mkey(mdev, &mr->mmr, in, sizeof(*in), NULL, NULL,
633 mr->ibmr.lkey = mr->mmr.key;
634 mr->ibmr.rkey = mr->mmr.key;
648 static int get_octo_len(u64 addr, u64 len, int page_size)
653 offset = addr & (page_size - 1);
654 npages = ALIGN(len + offset, page_size) >> ilog2(page_size);
655 return (npages + 1) / 2;
658 static int use_umr(int order)
663 static void prep_umr_reg_wqe(struct ib_pd *pd, struct ib_send_wr *wr,
664 struct ib_sge *sg, u64 dma, int n, u32 key,
665 int page_shift, u64 virt_addr, u64 len,
668 struct mlx5_ib_dev *dev = to_mdev(pd->device);
669 struct ib_mr *mr = dev->umrc.mr;
672 sg->length = ALIGN(sizeof(u64) * n, 64);
683 wr->opcode = MLX5_IB_WR_UMR;
684 wr->wr.fast_reg.page_list_len = n;
685 wr->wr.fast_reg.page_shift = page_shift;
686 wr->wr.fast_reg.rkey = key;
687 wr->wr.fast_reg.iova_start = virt_addr;
688 wr->wr.fast_reg.length = len;
689 wr->wr.fast_reg.access_flags = access_flags;
690 wr->wr.fast_reg.page_list = (struct ib_fast_reg_page_list *)pd;
693 static void prep_umr_unreg_wqe(struct mlx5_ib_dev *dev,
694 struct ib_send_wr *wr, u32 key)
696 wr->send_flags = MLX5_IB_SEND_UMR_UNREG;
697 wr->opcode = MLX5_IB_WR_UMR;
698 wr->wr.fast_reg.rkey = key;
701 void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context)
703 struct mlx5_ib_mr *mr;
708 err = ib_poll_cq(cq, 1, &wc);
710 pr_warn("poll cq error %d\n", err);
716 mr = (struct mlx5_ib_mr *)(unsigned long)wc.wr_id;
717 mr->status = wc.status;
720 ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
723 static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem,
724 u64 virt_addr, u64 len, int npages,
725 int page_shift, int order, int access_flags)
727 struct mlx5_ib_dev *dev = to_mdev(pd->device);
728 struct device *ddev = dev->ib_dev.dma_device;
729 struct umr_common *umrc = &dev->umrc;
730 struct ib_send_wr wr, *bad;
731 struct mlx5_ib_mr *mr;
733 int size = sizeof(u64) * npages;
737 for (i = 0; i < 1; i++) {
738 mr = alloc_cached_mr(dev, order);
742 err = add_keys(dev, order2idx(dev, order), 1);
743 if (err && err != -EAGAIN) {
744 mlx5_ib_warn(dev, "add_keys failed, err %d\n", err);
750 return ERR_PTR(-EAGAIN);
752 mr->pas = kmalloc(size + MLX5_UMR_ALIGN - 1, GFP_KERNEL);
758 mlx5_ib_populate_pas(dev, umem, page_shift,
759 mr_align(mr->pas, MLX5_UMR_ALIGN), 1);
761 mr->dma = dma_map_single(ddev, mr_align(mr->pas, MLX5_UMR_ALIGN), size,
763 if (dma_mapping_error(ddev, mr->dma)) {
769 memset(&wr, 0, sizeof(wr));
770 wr.wr_id = (u64)(unsigned long)mr;
771 prep_umr_reg_wqe(pd, &wr, &sg, mr->dma, npages, mr->mmr.key, page_shift, virt_addr, len, access_flags);
773 /* We serialize polls so one process does not kidnap another's
774 * completion. This is not a problem since wr is completed in
778 init_completion(&mr->done);
779 err = ib_post_send(umrc->qp, &wr, &bad);
781 mlx5_ib_warn(dev, "post send failed, err %d\n", err);
785 wait_for_completion(&mr->done);
788 dma_unmap_single(ddev, mr->dma, size, DMA_TO_DEVICE);
791 if (mr->status != IB_WC_SUCCESS) {
792 mlx5_ib_warn(dev, "reg umr failed\n");
800 free_cached_mr(dev, mr);
804 static struct mlx5_ib_mr *reg_create(struct ib_pd *pd, u64 virt_addr,
805 u64 length, struct ib_umem *umem,
806 int npages, int page_shift,
809 struct mlx5_ib_dev *dev = to_mdev(pd->device);
810 struct mlx5_create_mkey_mbox_in *in;
811 struct mlx5_ib_mr *mr;
815 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
817 return ERR_PTR(-ENOMEM);
819 inlen = sizeof(*in) + sizeof(*in->pas) * ((npages + 1) / 2) * 2;
820 in = mlx5_vzalloc(inlen);
825 mlx5_ib_populate_pas(dev, umem, page_shift, in->pas, 0);
827 in->seg.flags = convert_access(access_flags) |
828 MLX5_ACCESS_MODE_MTT;
829 in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
830 in->seg.start_addr = cpu_to_be64(virt_addr);
831 in->seg.len = cpu_to_be64(length);
832 in->seg.bsfs_octo_size = 0;
833 in->seg.xlt_oct_size = cpu_to_be32(get_octo_len(virt_addr, length, 1 << page_shift));
834 in->seg.log2_page_size = page_shift;
835 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
836 in->xlat_oct_act_size = cpu_to_be32(get_octo_len(virt_addr, length,
838 err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, inlen, NULL,
841 mlx5_ib_warn(dev, "create mkey failed\n");
847 mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmr.key);
860 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
861 u64 virt_addr, int access_flags,
862 struct ib_udata *udata)
864 struct mlx5_ib_dev *dev = to_mdev(pd->device);
865 struct mlx5_ib_mr *mr = NULL;
866 struct ib_umem *umem;
873 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx\n",
874 start, virt_addr, length);
875 umem = ib_umem_get(pd->uobject->context, start, length, access_flags,
878 mlx5_ib_dbg(dev, "umem get failed\n");
882 mlx5_ib_cont_pages(umem, start, &npages, &page_shift, &ncont, &order);
884 mlx5_ib_warn(dev, "avoid zero region\n");
889 mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n",
890 npages, ncont, order, page_shift);
892 if (use_umr(order)) {
893 mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift,
894 order, access_flags);
895 if (PTR_ERR(mr) == -EAGAIN) {
896 mlx5_ib_dbg(dev, "cache empty for order %d", order);
902 mr = reg_create(pd, virt_addr, length, umem, ncont, page_shift,
910 mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmr.key);
914 spin_lock(&dev->mr_lock);
915 dev->mdev.priv.reg_pages += npages;
916 spin_unlock(&dev->mr_lock);
917 mr->ibmr.lkey = mr->mmr.key;
918 mr->ibmr.rkey = mr->mmr.key;
923 ib_umem_release(umem);
927 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
929 struct umr_common *umrc = &dev->umrc;
930 struct ib_send_wr wr, *bad;
933 memset(&wr, 0, sizeof(wr));
934 wr.wr_id = (u64)(unsigned long)mr;
935 prep_umr_unreg_wqe(dev, &wr, mr->mmr.key);
938 init_completion(&mr->done);
939 err = ib_post_send(umrc->qp, &wr, &bad);
942 mlx5_ib_dbg(dev, "err %d\n", err);
945 wait_for_completion(&mr->done);
947 if (mr->status != IB_WC_SUCCESS) {
948 mlx5_ib_warn(dev, "unreg umr failed\n");
958 int mlx5_ib_dereg_mr(struct ib_mr *ibmr)
960 struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
961 struct mlx5_ib_mr *mr = to_mmr(ibmr);
962 struct ib_umem *umem = mr->umem;
963 int npages = mr->npages;
964 int umred = mr->umred;
968 err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
970 mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n",
975 err = unreg_umr(dev, mr);
977 mlx5_ib_warn(dev, "failed unregister\n");
980 free_cached_mr(dev, mr);
984 ib_umem_release(umem);
985 spin_lock(&dev->mr_lock);
986 dev->mdev.priv.reg_pages -= npages;
987 spin_unlock(&dev->mr_lock);
996 struct ib_mr *mlx5_ib_alloc_fast_reg_mr(struct ib_pd *pd,
997 int max_page_list_len)
999 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1000 struct mlx5_create_mkey_mbox_in *in;
1001 struct mlx5_ib_mr *mr;
1004 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1006 return ERR_PTR(-ENOMEM);
1008 in = kzalloc(sizeof(*in), GFP_KERNEL);
1014 in->seg.status = 1 << 6; /* free */
1015 in->seg.xlt_oct_size = cpu_to_be32((max_page_list_len + 1) / 2);
1016 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1017 in->seg.flags = MLX5_PERM_UMR_EN | MLX5_ACCESS_MODE_MTT;
1018 in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
1020 * TBD not needed - issue 197292 */
1021 in->seg.log2_page_size = PAGE_SHIFT;
1023 err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, sizeof(*in), NULL,
1029 mr->ibmr.lkey = mr->mmr.key;
1030 mr->ibmr.rkey = mr->mmr.key;
1037 return ERR_PTR(err);
1040 struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev,
1043 struct mlx5_ib_fast_reg_page_list *mfrpl;
1044 int size = page_list_len * sizeof(u64);
1046 mfrpl = kmalloc(sizeof(*mfrpl), GFP_KERNEL);
1048 return ERR_PTR(-ENOMEM);
1050 mfrpl->ibfrpl.page_list = kmalloc(size, GFP_KERNEL);
1051 if (!mfrpl->ibfrpl.page_list)
1054 mfrpl->mapped_page_list = dma_alloc_coherent(ibdev->dma_device,
1057 if (!mfrpl->mapped_page_list)
1060 WARN_ON(mfrpl->map & 0x3f);
1062 return &mfrpl->ibfrpl;
1065 kfree(mfrpl->ibfrpl.page_list);
1067 return ERR_PTR(-ENOMEM);
1070 void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list)
1072 struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(page_list);
1073 struct mlx5_ib_dev *dev = to_mdev(page_list->device);
1074 int size = page_list->max_page_list_len * sizeof(u64);
1076 dma_free_coherent(&dev->mdev.pdev->dev, size, mfrpl->mapped_page_list,
1078 kfree(mfrpl->ibfrpl.page_list);