drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2010, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/clockchips.h>
  59 #include <trace/events/power.h>
  60 #include <linux/sched.h>
  61 #include <linux/notifier.h>
  62 #include <linux/cpu.h>
  63 #include <linux/module.h>
  64 #include <asm/cpu_device_id.h>
  65 #include <asm/mwait.h>
  66 #include <asm/msr.h>
  67
  68 #define INTEL_IDLE_VERSION "0.4"
  69 #define PREFIX "intel_idle: "
  70
  71 static struct cpuidle_driver intel_idle_driver = {
  72         .name = "intel_idle",
  73         .owner = THIS_MODULE,
  74         .en_core_tk_irqen = 1,
  75 };
  76 /* intel_idle.max_cstate=0 disables driver */
  77 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
  78
  79 static unsigned int mwait_substates;
  80
  81 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
  82 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  83 static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
  84
  85 struct idle_cpu {
  86         struct cpuidle_state *state_table;
  87
  88         /*
  89          * Hardware C-state auto-demotion may not always be optimal.
  90          * Indicate which enable bits to clear here.
  91          */
  92         unsigned long auto_demotion_disable_flags;
  93 };
  94
  95 static const struct idle_cpu *icpu;
  96 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  97 static int intel_idle(struct cpuidle_device *dev,
  98                         struct cpuidle_driver *drv, int index);
  99 static int intel_idle_cpu_init(int cpu);
 100
 101 static struct cpuidle_state *cpuidle_state_table;
 102
 103 /*
 104  * Set this flag for states where the HW flushes the TLB for us
 105  * and so we don't need cross-calls to keep it consistent.
 106  * If this flag is set, SW flushes the TLB, so even if the
 107  * HW doesn't do the flushing, this flag is safe to use.
 108  */
 109 #define CPUIDLE_FLAG_TLB_FLUSHED        0x10000
 110
 111 /*
 112  * MWAIT takes an 8-bit "hint" in EAX "suggesting"
 113  * the C-state (top nibble) and sub-state (bottom nibble)
 114  * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
 115  *
 116  * We store the hint at the top of our "flags" for each state.
 117  */
 118 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
 119 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
 120
 121 /*
 122  * States are indexed by the cstate number,
 123  * which is also the index into the MWAIT hint array.
 124  * Thus C0 is a dummy.
 125  */
 126 static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
 127         { /* MWAIT C0 */ },
 128         { /* MWAIT C1 */
 129                 .name = "C1-NHM",
 130                 .desc = "MWAIT 0x00",
 131                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 132                 .exit_latency = 3,
 133                 .target_residency = 6,
 134                 .enter = &intel_idle },
 135         { /* MWAIT C2 */
 136                 .name = "C3-NHM",
 137                 .desc = "MWAIT 0x10",
 138                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 139                 .exit_latency = 20,
 140                 .target_residency = 80,
 141                 .enter = &intel_idle },
 142         { /* MWAIT C3 */
 143                 .name = "C6-NHM",
 144                 .desc = "MWAIT 0x20",
 145                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 146                 .exit_latency = 200,
 147                 .target_residency = 800,
 148                 .enter = &intel_idle },
 149 };
 150
 151 static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
 152         { /* MWAIT C0 */ },
 153         { /* MWAIT C1 */
 154                 .name = "C1-SNB",
 155                 .desc = "MWAIT 0x00",
 156                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 157                 .exit_latency = 1,
 158                 .target_residency = 1,
 159                 .enter = &intel_idle },
 160         { /* MWAIT C2 */
 161                 .name = "C3-SNB",
 162                 .desc = "MWAIT 0x10",
 163                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 164                 .exit_latency = 80,
 165                 .target_residency = 211,
 166                 .enter = &intel_idle },
 167         { /* MWAIT C3 */
 168                 .name = "C6-SNB",
 169                 .desc = "MWAIT 0x20",
 170                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 171                 .exit_latency = 104,
 172                 .target_residency = 345,
 173                 .enter = &intel_idle },
 174         { /* MWAIT C4 */
 175                 .name = "C7-SNB",
 176                 .desc = "MWAIT 0x30",
 177                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 178                 .exit_latency = 109,
 179                 .target_residency = 345,
 180                 .enter = &intel_idle },
 181 };
 182
 183 static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = {
 184         { /* MWAIT C0 */ },
 185         { /* MWAIT C1 */
 186                 .name = "C1-IVB",
 187                 .desc = "MWAIT 0x00",
 188                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 189                 .exit_latency = 1,
 190                 .target_residency = 1,
 191                 .enter = &intel_idle },
 192         { /* MWAIT C2 */
 193                 .name = "C3-IVB",
 194                 .desc = "MWAIT 0x10",
 195                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 196                 .exit_latency = 59,
 197                 .target_residency = 156,
 198                 .enter = &intel_idle },
 199         { /* MWAIT C3 */
 200                 .name = "C6-IVB",
 201                 .desc = "MWAIT 0x20",
 202                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 203                 .exit_latency = 80,
 204                 .target_residency = 300,
 205                 .enter = &intel_idle },
 206         { /* MWAIT C4 */
 207                 .name = "C7-IVB",
 208                 .desc = "MWAIT 0x30",
 209                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 210                 .exit_latency = 87,
 211                 .target_residency = 300,
 212                 .enter = &intel_idle },
 213 };
 214
 215 static struct cpuidle_state hsw_cstates[MWAIT_MAX_NUM_CSTATES] = {
 216         { /* MWAIT C0 */ },
 217         { /* MWAIT C1 */
 218                 .name = "C1-HSW",
 219                 .desc = "MWAIT 0x00",
 220                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 221                 .exit_latency = 2,
 222                 .target_residency = 2,
 223                 .enter = &intel_idle },
 224         { /* MWAIT C2 */
 225                 .name = "C3-HSW",
 226                 .desc = "MWAIT 0x10",
 227                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 228                 .exit_latency = 33,
 229                 .target_residency = 100,
 230                 .enter = &intel_idle },
 231         { /* MWAIT C3 */
 232                 .name = "C6-HSW",
 233                 .desc = "MWAIT 0x20",
 234                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 235                 .exit_latency = 133,
 236                 .target_residency = 400,
 237                 .enter = &intel_idle },
 238         { /* MWAIT C4 */
 239                 .name = "C7s-HSW",
 240                 .desc = "MWAIT 0x32",
 241                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 242                 .exit_latency = 166,
 243                 .target_residency = 500,
 244                 .enter = &intel_idle },
 245 };
 246
 247 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
 248         { /* MWAIT C0 */ },
 249         { /* MWAIT C1 */
 250                 .name = "C1-ATM",
 251                 .desc = "MWAIT 0x00",
 252                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 253                 .exit_latency = 1,
 254                 .target_residency = 4,
 255                 .enter = &intel_idle },
 256         { /* MWAIT C2 */
 257                 .name = "C2-ATM",
 258                 .desc = "MWAIT 0x10",
 259                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,
 260                 .exit_latency = 20,
 261                 .target_residency = 80,
 262                 .enter = &intel_idle },
 263         { /* MWAIT C3 */ },
 264         { /* MWAIT C4 */
 265                 .name = "C4-ATM",
 266                 .desc = "MWAIT 0x30",
 267                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 268                 .exit_latency = 100,
 269                 .target_residency = 400,
 270                 .enter = &intel_idle },
 271         { /* MWAIT C5 */ },
 272         { /* MWAIT C6 */
 273                 .name = "C6-ATM",
 274                 .desc = "MWAIT 0x52",
 275                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 276                 .exit_latency = 140,
 277                 .target_residency = 560,
 278                 .enter = &intel_idle },
 279 };
 280
 281 /**
 282  * intel_idle
 283  * @dev: cpuidle_device
 284  * @drv: cpuidle driver
 285  * @index: index of cpuidle state
 286  *
 287  * Must be called under local_irq_disable().
 288  */
 289 static int intel_idle(struct cpuidle_device *dev,
 290                 struct cpuidle_driver *drv, int index)
 291 {
 292         unsigned long ecx = 1; /* break on interrupt flag */
 293         struct cpuidle_state *state = &drv->states[index];
 294         unsigned long eax = flg2MWAIT(state->flags);
 295         unsigned int cstate;
 296         int cpu = smp_processor_id();
 297
 298         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 299
 300         /*
 301          * leave_mm() to avoid costly and often unnecessary wakeups
 302          * for flushing the user TLB's associated with the active mm.
 303          */
 304         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 305                 leave_mm(cpu);
 306
 307         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 308                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 309
 310         stop_critical_timings();
 311         if (!need_resched()) {
 312
 313                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 314                 smp_mb();
 315                 if (!need_resched())
 316                         __mwait(eax, ecx);
 317         }
 318
 319         start_critical_timings();
 320
 321         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 322                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 323
 324         return index;
 325 }
 326
 327 static void __setup_broadcast_timer(void *arg)
 328 {
 329         unsigned long reason = (unsigned long)arg;
 330         int cpu = smp_processor_id();
 331
 332         reason = reason ?
 333                 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
 334
 335         clockevents_notify(reason, &cpu);
 336 }
 337
 338 static int cpu_hotplug_notify(struct notifier_block *n,
 339                               unsigned long action, void *hcpu)
 340 {
 341         int hotcpu = (unsigned long)hcpu;
 342         struct cpuidle_device *dev;
 343
 344         switch (action & 0xf) {
 345         case CPU_ONLINE:
 346
 347                 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 348                         smp_call_function_single(hotcpu, __setup_broadcast_timer,
 349                                                  (void *)true, 1);
 350
 351                 /*
 352                  * Some systems can hotplug a cpu at runtime after
 353                  * the kernel has booted, we have to initialize the
 354                  * driver in this case
 355                  */
 356                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
 357                 if (!dev->registered)
 358                         intel_idle_cpu_init(hotcpu);
 359
 360                 break;
 361         }
 362         return NOTIFY_OK;
 363 }
 364
 365 static struct notifier_block cpu_hotplug_notifier = {
 366         .notifier_call = cpu_hotplug_notify,
 367 };
 368
 369 static void auto_demotion_disable(void *dummy)
 370 {
 371         unsigned long long msr_bits;
 372
 373         rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 374         msr_bits &= ~(icpu->auto_demotion_disable_flags);
 375         wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 376 }
 377
 378 static const struct idle_cpu idle_cpu_nehalem = {
 379         .state_table = nehalem_cstates,
 380         .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
 381 };
 382
 383 static const struct idle_cpu idle_cpu_atom = {
 384         .state_table = atom_cstates,
 385 };
 386
 387 static const struct idle_cpu idle_cpu_lincroft = {
 388         .state_table = atom_cstates,
 389         .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
 390 };
 391
 392 static const struct idle_cpu idle_cpu_snb = {
 393         .state_table = snb_cstates,
 394 };
 395
 396 static const struct idle_cpu idle_cpu_ivb = {
 397         .state_table = ivb_cstates,
 398 };
 399
 400 static const struct idle_cpu idle_cpu_hsw = {
 401         .state_table = hsw_cstates,
 402 };
 403
 404 #define ICPU(model, cpu) \
 405         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
 406
 407 static const struct x86_cpu_id intel_idle_ids[] = {
 408         ICPU(0x1a, idle_cpu_nehalem),
 409         ICPU(0x1e, idle_cpu_nehalem),
 410         ICPU(0x1f, idle_cpu_nehalem),
 411         ICPU(0x25, idle_cpu_nehalem),
 412         ICPU(0x2c, idle_cpu_nehalem),
 413         ICPU(0x2e, idle_cpu_nehalem),
 414         ICPU(0x1c, idle_cpu_atom),
 415         ICPU(0x26, idle_cpu_lincroft),
 416         ICPU(0x2f, idle_cpu_nehalem),
 417         ICPU(0x2a, idle_cpu_snb),
 418         ICPU(0x2d, idle_cpu_snb),
 419         ICPU(0x3a, idle_cpu_ivb),
 420         ICPU(0x3e, idle_cpu_ivb),
 421         ICPU(0x3c, idle_cpu_hsw),
 422         ICPU(0x3f, idle_cpu_hsw),
 423         ICPU(0x45, idle_cpu_hsw),
 424         {}
 425 };
 426 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
 427
 428 /*
 429  * intel_idle_probe()
 430  */
 431 static int intel_idle_probe(void)
 432 {
 433         unsigned int eax, ebx, ecx;
 434         const struct x86_cpu_id *id;
 435
 436         if (max_cstate == 0) {
 437                 pr_debug(PREFIX "disabled\n");
 438                 return -EPERM;
 439         }
 440
 441         id = x86_match_cpu(intel_idle_ids);
 442         if (!id) {
 443                 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 444                     boot_cpu_data.x86 == 6)
 445                         pr_debug(PREFIX "does not run on family %d model %d\n",
 446                                 boot_cpu_data.x86, boot_cpu_data.x86_model);
 447                 return -ENODEV;
 448         }
 449
 450         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 451                 return -ENODEV;
 452
 453         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 454
 455         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 456             !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
 457             !mwait_substates)
 458                         return -ENODEV;
 459
 460         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 461
 462         icpu = (const struct idle_cpu *)id->driver_data;
 463         cpuidle_state_table = icpu->state_table;
 464
 465         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
 466                 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 467         else
 468                 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
 469
 470         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
 471                 " model 0x%X\n", boot_cpu_data.x86_model);
 472
 473         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
 474                 lapic_timer_reliable_states);
 475         return 0;
 476 }
 477
 478 /*
 479  * intel_idle_cpuidle_devices_uninit()
 480  * unregister, free cpuidle_devices
 481  */
 482 static void intel_idle_cpuidle_devices_uninit(void)
 483 {
 484         int i;
 485         struct cpuidle_device *dev;
 486
 487         for_each_online_cpu(i) {
 488                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 489                 cpuidle_unregister_device(dev);
 490         }
 491
 492         free_percpu(intel_idle_cpuidle_devices);
 493         return;
 494 }
 495 /*
 496  * intel_idle_cpuidle_driver_init()
 497  * allocate, initialize cpuidle_states
 498  */
 499 static int intel_idle_cpuidle_driver_init(void)
 500 {
 501         int cstate;
 502         struct cpuidle_driver *drv = &intel_idle_driver;
 503
 504         drv->state_count = 1;
 505
 506         for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
 507                 int num_substates;
 508
 509                 if (cstate > max_cstate) {
 510                         printk(PREFIX "max_cstate %d reached\n",
 511                                 max_cstate);
 512                         break;
 513                 }
 514
 515                 /* does the state exist in CPUID.MWAIT? */
 516                 num_substates = (mwait_substates >> ((cstate) * 4))
 517                                         & MWAIT_SUBSTATE_MASK;
 518                 if (num_substates == 0)
 519                         continue;
 520                 /* is the state not enabled? */
 521                 if (cpuidle_state_table[cstate].enter == NULL) {
 522                         /* does the driver not know about the state? */
 523                         if (*cpuidle_state_table[cstate].name == '\0')
 524                                 pr_debug(PREFIX "unaware of model 0x%x"
 525                                         " MWAIT %d please"
 526                                         " contact lenb@kernel.org\n",
 527                                 boot_cpu_data.x86_model, cstate);
 528                         continue;
 529                 }
 530
 531                 if ((cstate > 2) &&
 532                         !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 533                         mark_tsc_unstable("TSC halts in idle"
 534                                         " states deeper than C2");
 535
 536                 drv->states[drv->state_count] = /* structure copy */
 537                         cpuidle_state_table[cstate];
 538
 539                 drv->state_count += 1;
 540         }
 541
 542         if (icpu->auto_demotion_disable_flags)
 543                 on_each_cpu(auto_demotion_disable, NULL, 1);
 544
 545         return 0;
 546 }
 547
 548
 549 /*
 550  * intel_idle_cpu_init()
 551  * allocate, initialize, register cpuidle_devices
 552  * @cpu: cpu/core to initialize
 553  */
 554 static int intel_idle_cpu_init(int cpu)
 555 {
 556         int cstate;
 557         struct cpuidle_device *dev;
 558
 559         dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
 560
 561         dev->state_count = 1;
 562
 563         for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
 564                 int num_substates;
 565
 566                 if (cstate > max_cstate) {
 567                         printk(PREFIX "max_cstate %d reached\n", max_cstate);
 568                         break;
 569                 }
 570
 571                 /* does the state exist in CPUID.MWAIT? */
 572                 num_substates = (mwait_substates >> ((cstate) * 4))
 573                         & MWAIT_SUBSTATE_MASK;
 574                 if (num_substates == 0)
 575                         continue;
 576                 /* is the state not enabled? */
 577                 if (cpuidle_state_table[cstate].enter == NULL)
 578                         continue;
 579
 580                 dev->state_count += 1;
 581         }
 582
 583         dev->cpu = cpu;
 584
 585         if (cpuidle_register_device(dev)) {
 586                 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
 587                 intel_idle_cpuidle_devices_uninit();
 588                 return -EIO;
 589         }
 590
 591         if (icpu->auto_demotion_disable_flags)
 592                 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
 593
 594         return 0;
 595 }
 596
 597 static int __init intel_idle_init(void)
 598 {
 599         int retval, i;
 600
 601         /* Do not load intel_idle at all for now if idle= is passed */
 602         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
 603                 return -ENODEV;
 604
 605         retval = intel_idle_probe();
 606         if (retval)
 607                 return retval;
 608
 609         intel_idle_cpuidle_driver_init();
 610         retval = cpuidle_register_driver(&intel_idle_driver);
 611         if (retval) {
 612                 struct cpuidle_driver *drv = cpuidle_get_driver();
 613                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
 614                         drv ? drv->name : "none");
 615                 return retval;
 616         }
 617
 618         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
 619         if (intel_idle_cpuidle_devices == NULL)
 620                 return -ENOMEM;
 621
 622         for_each_online_cpu(i) {
 623                 retval = intel_idle_cpu_init(i);
 624                 if (retval) {
 625                         cpuidle_unregister_driver(&intel_idle_driver);
 626                         return retval;
 627                 }
 628         }
 629         register_cpu_notifier(&cpu_hotplug_notifier);
 630
 631         return 0;
 632 }
 633
 634 static void __exit intel_idle_exit(void)
 635 {
 636         intel_idle_cpuidle_devices_uninit();
 637         cpuidle_unregister_driver(&intel_idle_driver);
 638
 639
 640         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 641                 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
 642         unregister_cpu_notifier(&cpu_hotplug_notifier);
 643
 644         return;
 645 }
 646
 647 module_init(intel_idle_init);
 648 module_exit(intel_idle_exit);
 649
 650 module_param(max_cstate, int, 0444);
 651
 652 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
 653 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
 654 MODULE_LICENSE("GPL");