drivers/i2c/busses/i2c-qup.c

   1 /*
   2  * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
   3  * Copyright (c) 2014, Sony Mobile Communications AB.
   4  *
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 and
   8  * only version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/i2c.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27
  28 /* QUP Registers */
  29 #define QUP_CONFIG              0x000
  30 #define QUP_STATE               0x004
  31 #define QUP_IO_MODE             0x008
  32 #define QUP_SW_RESET            0x00c
  33 #define QUP_OPERATIONAL         0x018
  34 #define QUP_ERROR_FLAGS         0x01c
  35 #define QUP_ERROR_FLAGS_EN      0x020
  36 #define QUP_HW_VERSION          0x030
  37 #define QUP_MX_OUTPUT_CNT       0x100
  38 #define QUP_OUT_FIFO_BASE       0x110
  39 #define QUP_MX_WRITE_CNT        0x150
  40 #define QUP_MX_INPUT_CNT        0x200
  41 #define QUP_MX_READ_CNT         0x208
  42 #define QUP_IN_FIFO_BASE        0x218
  43 #define QUP_I2C_CLK_CTL         0x400
  44 #define QUP_I2C_STATUS          0x404
  45
  46 /* QUP States and reset values */
  47 #define QUP_RESET_STATE         0
  48 #define QUP_RUN_STATE           1
  49 #define QUP_PAUSE_STATE         3
  50 #define QUP_STATE_MASK          3
  51
  52 #define QUP_STATE_VALID         BIT(2)
  53 #define QUP_I2C_MAST_GEN        BIT(4)
  54
  55 #define QUP_OPERATIONAL_RESET   0x000ff0
  56 #define QUP_I2C_STATUS_RESET    0xfffffc
  57
  58 /* QUP OPERATIONAL FLAGS */
  59 #define QUP_I2C_NACK_FLAG       BIT(3)
  60 #define QUP_OUT_NOT_EMPTY       BIT(4)
  61 #define QUP_IN_NOT_EMPTY        BIT(5)
  62 #define QUP_OUT_FULL            BIT(6)
  63 #define QUP_OUT_SVC_FLAG        BIT(8)
  64 #define QUP_IN_SVC_FLAG         BIT(9)
  65 #define QUP_MX_OUTPUT_DONE      BIT(10)
  66 #define QUP_MX_INPUT_DONE       BIT(11)
  67
  68 /* I2C mini core related values */
  69 #define QUP_CLOCK_AUTO_GATE     BIT(13)
  70 #define I2C_MINI_CORE           (2 << 8)
  71 #define I2C_N_VAL               15
  72 /* Most significant word offset in FIFO port */
  73 #define QUP_MSW_SHIFT           (I2C_N_VAL + 1)
  74
  75 /* Packing/Unpacking words in FIFOs, and IO modes */
  76 #define QUP_OUTPUT_BLK_MODE     (1 << 10)
  77 #define QUP_INPUT_BLK_MODE      (1 << 12)
  78 #define QUP_UNPACK_EN           BIT(14)
  79 #define QUP_PACK_EN             BIT(15)
  80
  81 #define QUP_REPACK_EN           (QUP_UNPACK_EN | QUP_PACK_EN)
  82
  83 #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
  84 #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
  85 #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
  86 #define QUP_INPUT_FIFO_SIZE(x)  (((x) >> 7) & 0x07)
  87
  88 /* QUP tags */
  89 #define QUP_TAG_START           (1 << 8)
  90 #define QUP_TAG_DATA            (2 << 8)
  91 #define QUP_TAG_STOP            (3 << 8)
  92 #define QUP_TAG_REC             (4 << 8)
  93
  94 /* Status, Error flags */
  95 #define I2C_STATUS_WR_BUFFER_FULL       BIT(0)
  96 #define I2C_STATUS_BUS_ACTIVE           BIT(8)
  97 #define I2C_STATUS_ERROR_MASK           0x38000fc
  98 #define QUP_STATUS_ERROR_FLAGS          0x7c
  99
 100 #define QUP_READ_LIMIT                  256
 101
 102 struct qup_i2c_dev {
 103         struct device           *dev;
 104         void __iomem            *base;
 105         int                     irq;
 106         struct clk              *clk;
 107         struct clk              *pclk;
 108         struct i2c_adapter      adap;
 109
 110         int                     clk_ctl;
 111         int                     out_fifo_sz;
 112         int                     in_fifo_sz;
 113         int                     out_blk_sz;
 114         int                     in_blk_sz;
 115
 116         unsigned long           one_byte_t;
 117
 118         struct i2c_msg          *msg;
 119         /* Current posion in user message buffer */
 120         int                     pos;
 121         /* I2C protocol errors */
 122         u32                     bus_err;
 123         /* QUP core errors */
 124         u32                     qup_err;
 125
 126         struct completion       xfer;
 127 };
 128
 129 static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
 130 {
 131         struct qup_i2c_dev *qup = dev;
 132         u32 bus_err;
 133         u32 qup_err;
 134         u32 opflags;
 135
 136         bus_err = readl(qup->base + QUP_I2C_STATUS);
 137         qup_err = readl(qup->base + QUP_ERROR_FLAGS);
 138         opflags = readl(qup->base + QUP_OPERATIONAL);
 139
 140         if (!qup->msg) {
 141                 /* Clear Error interrupt */
 142                 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
 143                 return IRQ_HANDLED;
 144         }
 145
 146         bus_err &= I2C_STATUS_ERROR_MASK;
 147         qup_err &= QUP_STATUS_ERROR_FLAGS;
 148
 149         if (qup_err) {
 150                 /* Clear Error interrupt */
 151                 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
 152                 goto done;
 153         }
 154
 155         if (bus_err) {
 156                 /* Clear Error interrupt */
 157                 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
 158                 goto done;
 159         }
 160
 161         if (opflags & QUP_IN_SVC_FLAG)
 162                 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 163
 164         if (opflags & QUP_OUT_SVC_FLAG)
 165                 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 166
 167 done:
 168         qup->qup_err = qup_err;
 169         qup->bus_err = bus_err;
 170         complete(&qup->xfer);
 171         return IRQ_HANDLED;
 172 }
 173
 174 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
 175                                    u32 req_state, u32 req_mask)
 176 {
 177         int retries = 1;
 178         u32 state;
 179
 180         /*
 181          * State transition takes 3 AHB clocks cycles + 3 I2C master clock
 182          * cycles. So retry once after a 1uS delay.
 183          */
 184         do {
 185                 state = readl(qup->base + QUP_STATE);
 186
 187                 if (state & QUP_STATE_VALID &&
 188                     (state & req_mask) == req_state)
 189                         return 0;
 190
 191                 udelay(1);
 192         } while (retries--);
 193
 194         return -ETIMEDOUT;
 195 }
 196
 197 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
 198 {
 199         return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
 200 }
 201
 202 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
 203 {
 204         return qup_i2c_poll_state_mask(qup, 0, 0);
 205 }
 206
 207 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
 208 {
 209         return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
 210 }
 211
 212 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
 213 {
 214         if (qup_i2c_poll_state_valid(qup) != 0)
 215                 return -EIO;
 216
 217         writel(state, qup->base + QUP_STATE);
 218
 219         if (qup_i2c_poll_state(qup, state) != 0)
 220                 return -EIO;
 221         return 0;
 222 }
 223
 224 static int qup_i2c_wait_writeready(struct qup_i2c_dev *qup)
 225 {
 226         unsigned long timeout;
 227         u32 opflags;
 228         u32 status;
 229
 230         timeout = jiffies + HZ;
 231
 232         for (;;) {
 233                 opflags = readl(qup->base + QUP_OPERATIONAL);
 234                 status = readl(qup->base + QUP_I2C_STATUS);
 235
 236                 if (!(opflags & QUP_OUT_NOT_EMPTY) &&
 237                     !(status & I2C_STATUS_BUS_ACTIVE))
 238                         return 0;
 239
 240                 if (time_after(jiffies, timeout))
 241                         return -ETIMEDOUT;
 242
 243                 usleep_range(qup->one_byte_t, qup->one_byte_t * 2);
 244         }
 245 }
 246
 247 static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 248 {
 249         /* Number of entries to shift out, including the start */
 250         int total = msg->len + 1;
 251
 252         if (total < qup->out_fifo_sz) {
 253                 /* FIFO mode */
 254                 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
 255                 writel(total, qup->base + QUP_MX_WRITE_CNT);
 256         } else {
 257                 /* BLOCK mode (transfer data on chunks) */
 258                 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
 259                        qup->base + QUP_IO_MODE);
 260                 writel(total, qup->base + QUP_MX_OUTPUT_CNT);
 261         }
 262 }
 263
 264 static void qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 265 {
 266         u32 addr = msg->addr << 1;
 267         u32 qup_tag;
 268         u32 opflags;
 269         int idx;
 270         u32 val;
 271
 272         if (qup->pos == 0) {
 273                 val = QUP_TAG_START | addr;
 274                 idx = 1;
 275         } else {
 276                 val = 0;
 277                 idx = 0;
 278         }
 279
 280         while (qup->pos < msg->len) {
 281                 /* Check that there's space in the FIFO for our pair */
 282                 opflags = readl(qup->base + QUP_OPERATIONAL);
 283                 if (opflags & QUP_OUT_FULL)
 284                         break;
 285
 286                 if (qup->pos == msg->len - 1)
 287                         qup_tag = QUP_TAG_STOP;
 288                 else
 289                         qup_tag = QUP_TAG_DATA;
 290
 291                 if (idx & 1)
 292                         val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
 293                 else
 294                         val = qup_tag | msg->buf[qup->pos];
 295
 296                 /* Write out the pair and the last odd value */
 297                 if (idx & 1 || qup->pos == msg->len - 1)
 298                         writel(val, qup->base + QUP_OUT_FIFO_BASE);
 299
 300                 qup->pos++;
 301                 idx++;
 302         }
 303 }
 304
 305 static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 306 {
 307         unsigned long left;
 308         int ret;
 309
 310         qup->msg = msg;
 311         qup->pos = 0;
 312
 313         enable_irq(qup->irq);
 314
 315         qup_i2c_set_write_mode(qup, msg);
 316
 317         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 318         if (ret)
 319                 goto err;
 320
 321         writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
 322
 323         do {
 324                 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 325                 if (ret)
 326                         goto err;
 327
 328                 qup_i2c_issue_write(qup, msg);
 329
 330                 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 331                 if (ret)
 332                         goto err;
 333
 334                 left = wait_for_completion_timeout(&qup->xfer, HZ);
 335                 if (!left) {
 336                         writel(1, qup->base + QUP_SW_RESET);
 337                         ret = -ETIMEDOUT;
 338                         goto err;
 339                 }
 340
 341                 if (qup->bus_err || qup->qup_err) {
 342                         if (qup->bus_err & QUP_I2C_NACK_FLAG)
 343                                 dev_err(qup->dev, "NACK from %x\n", msg->addr);
 344                         ret = -EIO;
 345                         goto err;
 346                 }
 347         } while (qup->pos < msg->len);
 348
 349         /* Wait for the outstanding data in the fifo to drain */
 350         ret = qup_i2c_wait_writeready(qup);
 351
 352 err:
 353         disable_irq(qup->irq);
 354         qup->msg = NULL;
 355
 356         return ret;
 357 }
 358
 359 static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
 360 {
 361         if (len < qup->in_fifo_sz) {
 362                 /* FIFO mode */
 363                 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
 364                 writel(len, qup->base + QUP_MX_READ_CNT);
 365         } else {
 366                 /* BLOCK mode (transfer data on chunks) */
 367                 writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
 368                        qup->base + QUP_IO_MODE);
 369                 writel(len, qup->base + QUP_MX_INPUT_CNT);
 370         }
 371 }
 372
 373 static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 374 {
 375         u32 addr, len, val;
 376
 377         addr = (msg->addr << 1) | 1;
 378
 379         /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
 380         len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
 381
 382         val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
 383         writel(val, qup->base + QUP_OUT_FIFO_BASE);
 384 }
 385
 386
 387 static void qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 388 {
 389         u32 opflags;
 390         u32 val = 0;
 391         int idx;
 392
 393         for (idx = 0; qup->pos < msg->len; idx++) {
 394                 if ((idx & 1) == 0) {
 395                         /* Check that FIFO have data */
 396                         opflags = readl(qup->base + QUP_OPERATIONAL);
 397                         if (!(opflags & QUP_IN_NOT_EMPTY))
 398                                 break;
 399
 400                         /* Reading 2 words at time */
 401                         val = readl(qup->base + QUP_IN_FIFO_BASE);
 402
 403                         msg->buf[qup->pos++] = val & 0xFF;
 404                 } else {
 405                         msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
 406                 }
 407         }
 408 }
 409
 410 static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 411 {
 412         unsigned long left;
 413         int ret;
 414
 415         /*
 416          * The QUP block will issue a NACK and STOP on the bus when reaching
 417          * the end of the read, the length of the read is specified as one byte
 418          * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
 419          */
 420         if (msg->len > QUP_READ_LIMIT) {
 421                 dev_err(qup->dev, "HW not capable of reads over %d bytes\n",
 422                         QUP_READ_LIMIT);
 423                 return -EINVAL;
 424         }
 425
 426         qup->msg = msg;
 427         qup->pos  = 0;
 428
 429         enable_irq(qup->irq);
 430
 431         qup_i2c_set_read_mode(qup, msg->len);
 432
 433         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 434         if (ret)
 435                 goto err;
 436
 437         writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
 438
 439         ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 440         if (ret)
 441                 goto err;
 442
 443         qup_i2c_issue_read(qup, msg);
 444
 445         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 446         if (ret)
 447                 goto err;
 448
 449         do {
 450                 left = wait_for_completion_timeout(&qup->xfer, HZ);
 451                 if (!left) {
 452                         writel(1, qup->base + QUP_SW_RESET);
 453                         ret = -ETIMEDOUT;
 454                         goto err;
 455                 }
 456
 457                 if (qup->bus_err || qup->qup_err) {
 458                         if (qup->bus_err & QUP_I2C_NACK_FLAG)
 459                                 dev_err(qup->dev, "NACK from %x\n", msg->addr);
 460                         ret = -EIO;
 461                         goto err;
 462                 }
 463
 464                 qup_i2c_read_fifo(qup, msg);
 465         } while (qup->pos < msg->len);
 466
 467 err:
 468         disable_irq(qup->irq);
 469         qup->msg = NULL;
 470
 471         return ret;
 472 }
 473
 474 static int qup_i2c_xfer(struct i2c_adapter *adap,
 475                         struct i2c_msg msgs[],
 476                         int num)
 477 {
 478         struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
 479         int ret, idx;
 480
 481         ret = pm_runtime_get_sync(qup->dev);
 482         if (ret)
 483                 goto out;
 484
 485         writel(1, qup->base + QUP_SW_RESET);
 486         ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
 487         if (ret)
 488                 goto out;
 489
 490         /* Configure QUP as I2C mini core */
 491         writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
 492
 493         for (idx = 0; idx < num; idx++) {
 494                 if (msgs[idx].len == 0) {
 495                         ret = -EINVAL;
 496                         goto out;
 497                 }
 498
 499                 if (qup_i2c_poll_state_i2c_master(qup)) {
 500                         ret = -EIO;
 501                         goto out;
 502                 }
 503
 504                 if (msgs[idx].flags & I2C_M_RD)
 505                         ret = qup_i2c_read_one(qup, &msgs[idx]);
 506                 else
 507                         ret = qup_i2c_write_one(qup, &msgs[idx]);
 508
 509                 if (ret)
 510                         break;
 511
 512                 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
 513                 if (ret)
 514                         break;
 515         }
 516
 517         if (ret == 0)
 518                 ret = num;
 519 out:
 520
 521         pm_runtime_mark_last_busy(qup->dev);
 522         pm_runtime_put_autosuspend(qup->dev);
 523
 524         return ret;
 525 }
 526
 527 static u32 qup_i2c_func(struct i2c_adapter *adap)
 528 {
 529         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 530 }
 531
 532 static const struct i2c_algorithm qup_i2c_algo = {
 533         .master_xfer    = qup_i2c_xfer,
 534         .functionality  = qup_i2c_func,
 535 };
 536
 537 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
 538 {
 539         clk_prepare_enable(qup->clk);
 540         clk_prepare_enable(qup->pclk);
 541 }
 542
 543 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
 544 {
 545         u32 config;
 546
 547         qup_i2c_change_state(qup, QUP_RESET_STATE);
 548         clk_disable_unprepare(qup->clk);
 549         config = readl(qup->base + QUP_CONFIG);
 550         config |= QUP_CLOCK_AUTO_GATE;
 551         writel(config, qup->base + QUP_CONFIG);
 552         clk_disable_unprepare(qup->pclk);
 553 }
 554
 555 static int qup_i2c_probe(struct platform_device *pdev)
 556 {
 557         static const int blk_sizes[] = {4, 16, 32};
 558         struct device_node *node = pdev->dev.of_node;
 559         struct qup_i2c_dev *qup;
 560         unsigned long one_bit_t;
 561         struct resource *res;
 562         u32 io_mode, hw_ver, size;
 563         int ret, fs_div, hs_div;
 564         int src_clk_freq;
 565         u32 clk_freq = 100000;
 566
 567         qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
 568         if (!qup)
 569                 return -ENOMEM;
 570
 571         qup->dev = &pdev->dev;
 572         init_completion(&qup->xfer);
 573         platform_set_drvdata(pdev, qup);
 574
 575         of_property_read_u32(node, "clock-frequency", &clk_freq);
 576
 577         /* We support frequencies up to FAST Mode (400KHz) */
 578         if (!clk_freq || clk_freq > 400000) {
 579                 dev_err(qup->dev, "clock frequency not supported %d\n",
 580                         clk_freq);
 581                 return -EINVAL;
 582         }
 583
 584         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 585         qup->base = devm_ioremap_resource(qup->dev, res);
 586         if (IS_ERR(qup->base))
 587                 return PTR_ERR(qup->base);
 588
 589         qup->irq = platform_get_irq(pdev, 0);
 590         if (qup->irq < 0) {
 591                 dev_err(qup->dev, "No IRQ defined\n");
 592                 return qup->irq;
 593         }
 594
 595         qup->clk = devm_clk_get(qup->dev, "core");
 596         if (IS_ERR(qup->clk)) {
 597                 dev_err(qup->dev, "Could not get core clock\n");
 598                 return PTR_ERR(qup->clk);
 599         }
 600
 601         qup->pclk = devm_clk_get(qup->dev, "iface");
 602         if (IS_ERR(qup->pclk)) {
 603                 dev_err(qup->dev, "Could not get iface clock\n");
 604                 return PTR_ERR(qup->pclk);
 605         }
 606
 607         qup_i2c_enable_clocks(qup);
 608
 609         /*
 610          * Bootloaders might leave a pending interrupt on certain QUP's,
 611          * so we reset the core before registering for interrupts.
 612          */
 613         writel(1, qup->base + QUP_SW_RESET);
 614         ret = qup_i2c_poll_state_valid(qup);
 615         if (ret)
 616                 goto fail;
 617
 618         ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
 619                                IRQF_TRIGGER_HIGH, "i2c_qup", qup);
 620         if (ret) {
 621                 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
 622                 goto fail;
 623         }
 624         disable_irq(qup->irq);
 625
 626         hw_ver = readl(qup->base + QUP_HW_VERSION);
 627         dev_dbg(qup->dev, "Revision %x\n", hw_ver);
 628
 629         io_mode = readl(qup->base + QUP_IO_MODE);
 630
 631         /*
 632          * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
 633          * associated with each byte written/received
 634          */
 635         size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
 636         if (size >= ARRAY_SIZE(blk_sizes))
 637                 return -EIO;
 638         qup->out_blk_sz = blk_sizes[size] / 2;
 639
 640         size = QUP_INPUT_BLOCK_SIZE(io_mode);
 641         if (size >= ARRAY_SIZE(blk_sizes))
 642                 return -EIO;
 643         qup->in_blk_sz = blk_sizes[size] / 2;
 644
 645         size = QUP_OUTPUT_FIFO_SIZE(io_mode);
 646         qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
 647
 648         size = QUP_INPUT_FIFO_SIZE(io_mode);
 649         qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
 650
 651         src_clk_freq = clk_get_rate(qup->clk);
 652         fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
 653         hs_div = 3;
 654         qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
 655
 656         /*
 657          * Time it takes for a byte to be clocked out on the bus.
 658          * Each byte takes 9 clock cycles (8 bits + 1 ack).
 659          */
 660         one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
 661         qup->one_byte_t = one_bit_t * 9;
 662
 663         dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
 664                 qup->in_blk_sz, qup->in_fifo_sz,
 665                 qup->out_blk_sz, qup->out_fifo_sz);
 666
 667         i2c_set_adapdata(&qup->adap, qup);
 668         qup->adap.algo = &qup_i2c_algo;
 669         qup->adap.dev.parent = qup->dev;
 670         qup->adap.dev.of_node = pdev->dev.of_node;
 671         strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
 672
 673         ret = i2c_add_adapter(&qup->adap);
 674         if (ret)
 675                 goto fail;
 676
 677         pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
 678         pm_runtime_use_autosuspend(qup->dev);
 679         pm_runtime_set_active(qup->dev);
 680         pm_runtime_enable(qup->dev);
 681         return 0;
 682
 683 fail:
 684         qup_i2c_disable_clocks(qup);
 685         return ret;
 686 }
 687
 688 static int qup_i2c_remove(struct platform_device *pdev)
 689 {
 690         struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
 691
 692         disable_irq(qup->irq);
 693         qup_i2c_disable_clocks(qup);
 694         i2c_del_adapter(&qup->adap);
 695         pm_runtime_disable(qup->dev);
 696         pm_runtime_set_suspended(qup->dev);
 697         return 0;
 698 }
 699
 700 #ifdef CONFIG_PM
 701 static int qup_i2c_pm_suspend_runtime(struct device *device)
 702 {
 703         struct qup_i2c_dev *qup = dev_get_drvdata(device);
 704
 705         dev_dbg(device, "pm_runtime: suspending...\n");
 706         qup_i2c_disable_clocks(qup);
 707         return 0;
 708 }
 709
 710 static int qup_i2c_pm_resume_runtime(struct device *device)
 711 {
 712         struct qup_i2c_dev *qup = dev_get_drvdata(device);
 713
 714         dev_dbg(device, "pm_runtime: resuming...\n");
 715         qup_i2c_enable_clocks(qup);
 716         return 0;
 717 }
 718 #endif
 719
 720 #ifdef CONFIG_PM_SLEEP
 721 static int qup_i2c_suspend(struct device *device)
 722 {
 723         qup_i2c_pm_suspend_runtime(device);
 724         return 0;
 725 }
 726
 727 static int qup_i2c_resume(struct device *device)
 728 {
 729         qup_i2c_pm_resume_runtime(device);
 730         pm_runtime_mark_last_busy(device);
 731         pm_request_autosuspend(device);
 732         return 0;
 733 }
 734 #endif
 735
 736 static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
 737         SET_SYSTEM_SLEEP_PM_OPS(
 738                 qup_i2c_suspend,
 739                 qup_i2c_resume)
 740         SET_RUNTIME_PM_OPS(
 741                 qup_i2c_pm_suspend_runtime,
 742                 qup_i2c_pm_resume_runtime,
 743                 NULL)
 744 };
 745
 746 static const struct of_device_id qup_i2c_dt_match[] = {
 747         { .compatible = "qcom,i2c-qup-v1.1.1" },
 748         { .compatible = "qcom,i2c-qup-v2.1.1" },
 749         { .compatible = "qcom,i2c-qup-v2.2.1" },
 750         {}
 751 };
 752 MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
 753
 754 static struct platform_driver qup_i2c_driver = {
 755         .probe  = qup_i2c_probe,
 756         .remove = qup_i2c_remove,
 757         .driver = {
 758                 .name = "i2c_qup",
 759                 .owner = THIS_MODULE,
 760                 .pm = &qup_i2c_qup_pm_ops,
 761                 .of_match_table = qup_i2c_dt_match,
 762         },
 763 };
 764
 765 module_platform_driver(qup_i2c_driver);
 766
 767 MODULE_LICENSE("GPL v2");
 768 MODULE_ALIAS("platform:i2c_qup");