2 * Copyright (C) 2009 ST-Ericsson SA
3 * Copyright (C) 2009 STMicroelectronics
5 * I2C master mode controller driver, used in Nomadik 8815
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/amba/bus.h>
18 #include <linux/slab.h>
19 #include <linux/interrupt.h>
20 #include <linux/i2c.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/pinctrl/consumer.h>
28 #define DRIVER_NAME "nmk-i2c"
30 /* I2C Controller register offsets */
31 #define I2C_CR (0x000)
32 #define I2C_SCR (0x004)
33 #define I2C_HSMCR (0x008)
34 #define I2C_MCR (0x00C)
35 #define I2C_TFR (0x010)
36 #define I2C_SR (0x014)
37 #define I2C_RFR (0x018)
38 #define I2C_TFTR (0x01C)
39 #define I2C_RFTR (0x020)
40 #define I2C_DMAR (0x024)
41 #define I2C_BRCR (0x028)
42 #define I2C_IMSCR (0x02C)
43 #define I2C_RISR (0x030)
44 #define I2C_MISR (0x034)
45 #define I2C_ICR (0x038)
47 /* Control registers */
48 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
49 #define I2C_CR_OM (0x3 << 1) /* Operating mode */
50 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
51 #define I2C_CR_SM (0x3 << 4) /* Speed mode */
52 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
53 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
54 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
55 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
56 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
57 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
58 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */
59 #define I2C_CR_FON (0x3 << 13) /* Filtering on */
60 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */
62 /* Master controller (MCR) register */
63 #define I2C_MCR_OP (0x1 << 0) /* Operation */
64 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
65 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
66 #define I2C_MCR_SB (0x1 << 11) /* Extended address */
67 #define I2C_MCR_AM (0x3 << 12) /* Address type */
68 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
69 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
71 /* Status register (SR) */
72 #define I2C_SR_OP (0x3 << 0) /* Operation */
73 #define I2C_SR_STATUS (0x3 << 2) /* controller status */
74 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
75 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */
76 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
78 /* Interrupt mask set/clear (IMSCR) bits */
79 #define I2C_IT_TXFE (0x1 << 0)
80 #define I2C_IT_TXFNE (0x1 << 1)
81 #define I2C_IT_TXFF (0x1 << 2)
82 #define I2C_IT_TXFOVR (0x1 << 3)
83 #define I2C_IT_RXFE (0x1 << 4)
84 #define I2C_IT_RXFNF (0x1 << 5)
85 #define I2C_IT_RXFF (0x1 << 6)
86 #define I2C_IT_RFSR (0x1 << 16)
87 #define I2C_IT_RFSE (0x1 << 17)
88 #define I2C_IT_WTSR (0x1 << 18)
89 #define I2C_IT_MTD (0x1 << 19)
90 #define I2C_IT_STD (0x1 << 20)
91 #define I2C_IT_MAL (0x1 << 24)
92 #define I2C_IT_BERR (0x1 << 25)
93 #define I2C_IT_MTDWS (0x1 << 28)
95 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
97 /* some bits in ICR are reserved */
98 #define I2C_CLEAR_ALL_INTS 0x131f007f
100 /* first three msb bits are reserved */
101 #define IRQ_MASK(mask) (mask & 0x1fffffff)
103 /* maximum threshold value */
104 #define MAX_I2C_FIFO_THRESHOLD 15
107 I2C_FREQ_MODE_STANDARD, /* up to 100 Kb/s */
108 I2C_FREQ_MODE_FAST, /* up to 400 Kb/s */
109 I2C_FREQ_MODE_HIGH_SPEED, /* up to 3.4 Mb/s */
110 I2C_FREQ_MODE_FAST_PLUS, /* up to 1 Mb/s */
114 * struct i2c_vendor_data - per-vendor variations
115 * @has_mtdws: variant has the MTDWS bit
116 * @fifodepth: variant FIFO depth
118 struct i2c_vendor_data {
132 I2C_NO_OPERATION = 0xff,
138 * struct i2c_nmk_client - client specific data
139 * @slave_adr: 7-bit slave address
140 * @count: no. bytes to be transferred
141 * @buffer: client data buffer
142 * @xfer_bytes: bytes transferred till now
143 * @operation: current I2C operation
145 struct i2c_nmk_client {
146 unsigned short slave_adr;
148 unsigned char *buffer;
149 unsigned long xfer_bytes;
150 enum i2c_operation operation;
154 * struct nmk_i2c_dev - private data structure of the controller.
155 * @vendor: vendor data for this variant.
156 * @adev: parent amba device.
157 * @adap: corresponding I2C adapter.
158 * @irq: interrupt line for the controller.
159 * @virtbase: virtual io memory area.
160 * @clk: hardware i2c block clock.
161 * @cli: holder of client specific data.
162 * @clk_freq: clock frequency for the operation mode
163 * @tft: Tx FIFO Threshold in bytes
164 * @rft: Rx FIFO Threshold in bytes
165 * @timeout Slave response timeout (ms)
167 * @stop: stop condition.
168 * @xfer_complete: acknowledge completion for a I2C message.
169 * @result: controller propogated result.
170 * @busy: Busy doing transfer.
173 struct i2c_vendor_data *vendor;
174 struct amba_device *adev;
175 struct i2c_adapter adap;
177 void __iomem *virtbase;
179 struct i2c_nmk_client cli;
184 enum i2c_freq_mode sm;
186 struct completion xfer_complete;
191 /* controller's abort causes */
192 static const char *abort_causes[] = {
193 "no ack received after address transmission",
194 "no ack received during data phase",
195 "ack received after xmission of master code",
196 "master lost arbitration",
199 "overflow, maxsize is 2047 bytes",
202 static inline void i2c_set_bit(void __iomem *reg, u32 mask)
204 writel(readl(reg) | mask, reg);
207 static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
209 writel(readl(reg) & ~mask, reg);
213 * flush_i2c_fifo() - This function flushes the I2C FIFO
214 * @dev: private data of I2C Driver
216 * This function flushes the I2C Tx and Rx FIFOs. It returns
217 * 0 on successful flushing of FIFO
219 static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
221 #define LOOP_ATTEMPTS 10
223 unsigned long timeout;
226 * flush the transmit and receive FIFO. The flushing
227 * operation takes several cycles before to be completed.
228 * On the completion, the I2C internal logic clears these
229 * bits, until then no one must access Tx, Rx FIFO and
230 * should poll on these bits waiting for the completion.
232 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
234 for (i = 0; i < LOOP_ATTEMPTS; i++) {
235 timeout = jiffies + dev->adap.timeout;
237 while (!time_after(jiffies, timeout)) {
238 if ((readl(dev->virtbase + I2C_CR) &
239 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
244 dev_err(&dev->adev->dev,
245 "flushing operation timed out giving up after %d attempts",
252 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
253 * @dev: private data of I2C Driver
255 static void disable_all_interrupts(struct nmk_i2c_dev *dev)
257 u32 mask = IRQ_MASK(0);
258 writel(mask, dev->virtbase + I2C_IMSCR);
262 * clear_all_interrupts() - Clear all interrupts of I2C Controller
263 * @dev: private data of I2C Driver
265 static void clear_all_interrupts(struct nmk_i2c_dev *dev)
268 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
269 writel(mask, dev->virtbase + I2C_ICR);
273 * init_hw() - initialize the I2C hardware
274 * @dev: private data of I2C Driver
276 static int init_hw(struct nmk_i2c_dev *dev)
280 stat = flush_i2c_fifo(dev);
284 /* disable the controller */
285 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
287 disable_all_interrupts(dev);
289 clear_all_interrupts(dev);
291 dev->cli.operation = I2C_NO_OPERATION;
297 /* enable peripheral, master mode operation */
298 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
301 * load_i2c_mcr_reg() - load the MCR register
302 * @dev: private data of controller
303 * @flags: message flags
305 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
308 unsigned short slave_adr_3msb_bits;
310 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
312 if (unlikely(flags & I2C_M_TEN)) {
313 /* 10-bit address transaction */
314 mcr |= GEN_MASK(2, I2C_MCR_AM, 12);
316 * Get the top 3 bits.
317 * EA10 represents extended address in MCR. This includes
318 * the extension (MSB bits) of the 7 bit address loaded
321 slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7;
323 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8);
325 /* 7-bit address transaction */
326 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
329 /* start byte procedure not applied */
330 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
332 /* check the operation, master read/write? */
333 if (dev->cli.operation == I2C_WRITE)
334 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
336 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
338 /* stop or repeated start? */
340 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
342 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
344 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
350 * setup_i2c_controller() - setup the controller
351 * @dev: private data of controller
353 static void setup_i2c_controller(struct nmk_i2c_dev *dev)
360 writel(0x0, dev->virtbase + I2C_CR);
361 writel(0x0, dev->virtbase + I2C_HSMCR);
362 writel(0x0, dev->virtbase + I2C_TFTR);
363 writel(0x0, dev->virtbase + I2C_RFTR);
364 writel(0x0, dev->virtbase + I2C_DMAR);
366 i2c_clk = clk_get_rate(dev->clk);
371 * slsu defines the data setup time after SCL clock
372 * stretching in terms of i2c clk cycles + 1 (zero means
373 * "wait one cycle"), the needed setup time for the three
374 * modes are 250ns, 100ns, 10ns respectively.
376 * As the time for one cycle T in nanoseconds is
377 * T = (1/f) * 1000000000 =>
378 * slsu = cycles / (1000000000 / f) + 1
380 ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk);
382 case I2C_FREQ_MODE_FAST:
383 case I2C_FREQ_MODE_FAST_PLUS:
384 slsu = DIV_ROUND_UP(100, ns); /* Fast */
386 case I2C_FREQ_MODE_HIGH_SPEED:
387 slsu = DIV_ROUND_UP(10, ns); /* High */
389 case I2C_FREQ_MODE_STANDARD:
391 slsu = DIV_ROUND_UP(250, ns); /* Standard */
396 dev_dbg(&dev->adev->dev, "calculated SLSU = %04x\n", slsu);
397 writel(slsu << 16, dev->virtbase + I2C_SCR);
400 * The spec says, in case of std. mode the divider is
401 * 2 whereas it is 3 for fast and fastplus mode of
402 * operation. TODO - high speed support.
404 div = (dev->clk_freq > 100000) ? 3 : 2;
407 * generate the mask for baud rate counters. The controller
408 * has two baud rate counters. One is used for High speed
409 * operation, and the other is for std, fast mode, fast mode
410 * plus operation. Currently we do not supprt high speed mode
414 brcr2 = (i2c_clk/(dev->clk_freq * div)) & 0xffff;
416 /* set the baud rate counter register */
417 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
420 * set the speed mode. Currently we support
421 * only standard and fast mode of operation
422 * TODO - support for fast mode plus (up to 1Mb/s)
423 * and high speed (up to 3.4 Mb/s)
425 if (dev->sm > I2C_FREQ_MODE_FAST) {
426 dev_err(&dev->adev->dev,
427 "do not support this mode defaulting to std. mode\n");
428 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
429 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
430 writel(I2C_FREQ_MODE_STANDARD << 4,
431 dev->virtbase + I2C_CR);
433 writel(dev->sm << 4, dev->virtbase + I2C_CR);
435 /* set the Tx and Rx FIFO threshold */
436 writel(dev->tft, dev->virtbase + I2C_TFTR);
437 writel(dev->rft, dev->virtbase + I2C_RFTR);
441 * read_i2c() - Read from I2C client device
442 * @dev: private data of I2C Driver
443 * @flags: message flags
445 * This function reads from i2c client device when controller is in
446 * master mode. There is a completion timeout. If there is no transfer
447 * before timeout error is returned.
449 static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
455 mcr = load_i2c_mcr_reg(dev, flags);
456 writel(mcr, dev->virtbase + I2C_MCR);
458 /* load the current CR value */
459 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
460 dev->virtbase + I2C_CR);
462 /* enable the controller */
463 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
465 init_completion(&dev->xfer_complete);
467 /* enable interrupts by setting the mask */
468 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
469 I2C_IT_MAL | I2C_IT_BERR);
471 if (dev->stop || !dev->vendor->has_mtdws)
472 irq_mask |= I2C_IT_MTD;
474 irq_mask |= I2C_IT_MTDWS;
476 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
478 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
479 dev->virtbase + I2C_IMSCR);
481 timeout = wait_for_completion_timeout(
482 &dev->xfer_complete, dev->adap.timeout);
485 /* Controller timed out */
486 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",
493 static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
497 for (count = (no_bytes - 2);
499 (dev->cli.count != 0);
501 /* write to the Tx FIFO */
502 writeb(*dev->cli.buffer,
503 dev->virtbase + I2C_TFR);
506 dev->cli.xfer_bytes++;
512 * write_i2c() - Write data to I2C client.
513 * @dev: private data of I2C Driver
514 * @flags: message flags
516 * This function writes data to I2C client
518 static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
524 mcr = load_i2c_mcr_reg(dev, flags);
526 writel(mcr, dev->virtbase + I2C_MCR);
528 /* load the current CR value */
529 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
530 dev->virtbase + I2C_CR);
532 /* enable the controller */
533 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
535 init_completion(&dev->xfer_complete);
537 /* enable interrupts by settings the masks */
538 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
540 /* Fill the TX FIFO with transmit data */
541 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
543 if (dev->cli.count != 0)
544 irq_mask |= I2C_IT_TXFNE;
547 * check if we want to transfer a single or multiple bytes, if so
548 * set the MTDWS bit (Master Transaction Done Without Stop)
549 * to start repeated start operation
551 if (dev->stop || !dev->vendor->has_mtdws)
552 irq_mask |= I2C_IT_MTD;
554 irq_mask |= I2C_IT_MTDWS;
556 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
558 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
559 dev->virtbase + I2C_IMSCR);
561 timeout = wait_for_completion_timeout(
562 &dev->xfer_complete, dev->adap.timeout);
565 /* Controller timed out */
566 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",
575 * nmk_i2c_xfer_one() - transmit a single I2C message
576 * @dev: device with a message encoded into it
577 * @flags: message flags
579 static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
583 if (flags & I2C_M_RD) {
585 dev->cli.operation = I2C_READ;
586 status = read_i2c(dev, flags);
588 /* write operation */
589 dev->cli.operation = I2C_WRITE;
590 status = write_i2c(dev, flags);
593 if (status || (dev->result)) {
597 i2c_sr = readl(dev->virtbase + I2C_SR);
599 * Check if the controller I2C operation status
600 * is set to ABORT(11b).
602 if (((i2c_sr >> 2) & 0x3) == 0x3) {
603 /* get the abort cause */
604 cause = (i2c_sr >> 4) & 0x7;
605 dev_err(&dev->adev->dev, "%s\n",
606 cause >= ARRAY_SIZE(abort_causes) ?
608 abort_causes[cause]);
613 status = status ? status : dev->result;
620 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
621 * @i2c_adap: Adapter pointer to the controller
622 * @msgs: Pointer to data to be written.
623 * @num_msgs: Number of messages to be executed
625 * This is the function called by the generic kernel i2c_transfer()
626 * or i2c_smbus...() API calls. Note that this code is protected by the
627 * semaphore set in the kernel i2c_transfer() function.
630 * READ TRANSFER : We impose a restriction of the first message to be the
631 * index message for any read transaction.
632 * - a no index is coded as '0',
633 * - 2byte big endian index is coded as '3'
634 * !!! msg[0].buf holds the actual index.
635 * This is compatible with generic messages of smbus emulator
636 * that send a one byte index.
637 * eg. a I2C transation to read 2 bytes from index 0
639 * msg[0].addr = client->addr;
640 * msg[0].flags = 0x0;
644 * msg[1].addr = client->addr;
645 * msg[1].flags = I2C_M_RD;
647 * msg[1].buf = rd_buff
648 * i2c_transfer(adap, msg, 2);
650 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
651 * If you want to emulate an SMBUS write transaction put the
652 * index as first byte(or first and second) in the payload.
653 * eg. a I2C transation to write 2 bytes from index 1
657 * msg[0].flags = 0x0;
659 * msg[0].buf = wr_buff;
660 * i2c_transfer(adap, msg, 1);
662 * To read or write a block of data (multiple bytes) using SMBUS emulation
663 * please use the i2c_smbus_read_i2c_block_data()
664 * or i2c_smbus_write_i2c_block_data() API
666 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
667 struct i2c_msg msgs[], int num_msgs)
671 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
676 pm_runtime_get_sync(&dev->adev->dev);
678 status = clk_prepare_enable(dev->clk);
680 dev_err(&dev->adev->dev, "can't prepare_enable clock\n");
684 /* Optionaly enable pins to be muxed in and configured */
685 pinctrl_pm_select_default_state(&dev->adev->dev);
687 status = init_hw(dev);
691 /* Attempt three times to send the message queue */
692 for (j = 0; j < 3; j++) {
693 /* setup the i2c controller */
694 setup_i2c_controller(dev);
696 for (i = 0; i < num_msgs; i++) {
697 dev->cli.slave_adr = msgs[i].addr;
698 dev->cli.buffer = msgs[i].buf;
699 dev->cli.count = msgs[i].len;
700 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
703 status = nmk_i2c_xfer_one(dev, msgs[i].flags);
712 clk_disable_unprepare(dev->clk);
714 /* Optionally let pins go into idle state */
715 pinctrl_pm_select_idle_state(&dev->adev->dev);
717 pm_runtime_put_sync(&dev->adev->dev);
721 /* return the no. messages processed */
729 * disable_interrupts() - disable the interrupts
730 * @dev: private data of controller
731 * @irq: interrupt number
733 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
736 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
737 dev->virtbase + I2C_IMSCR);
742 * i2c_irq_handler() - interrupt routine
743 * @irq: interrupt number
744 * @arg: data passed to the handler
746 * This is the interrupt handler for the i2c driver. Currently
747 * it handles the major interrupts like Rx & Tx FIFO management
748 * interrupts, master transaction interrupts, arbitration and
749 * bus error interrupts. The rest of the interrupts are treated as
752 static irqreturn_t i2c_irq_handler(int irq, void *arg)
754 struct nmk_i2c_dev *dev = arg;
759 /* load Tx FIFO and Rx FIFO threshold values */
760 tft = readl(dev->virtbase + I2C_TFTR);
761 rft = readl(dev->virtbase + I2C_RFTR);
763 /* read interrupt status register */
764 misr = readl(dev->virtbase + I2C_MISR);
767 switch ((1 << src)) {
769 /* Transmit FIFO nearly empty interrupt */
772 if (dev->cli.operation == I2C_READ) {
774 * in read operation why do we care for writing?
775 * so disable the Transmit FIFO interrupt
777 disable_interrupts(dev, I2C_IT_TXFNE);
779 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
781 * if done, close the transfer by disabling the
782 * corresponding TXFNE interrupt
784 if (dev->cli.count == 0)
785 disable_interrupts(dev, I2C_IT_TXFNE);
791 * Rx FIFO nearly full interrupt.
792 * This is set when the numer of entries in Rx FIFO is
793 * greater or equal than the threshold value programmed
797 for (count = rft; count > 0; count--) {
798 /* Read the Rx FIFO */
799 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
802 dev->cli.count -= rft;
803 dev->cli.xfer_bytes += rft;
808 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
809 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
812 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
813 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
816 /* Master Transaction Done with/without stop */
819 if (dev->cli.operation == I2C_READ) {
820 while (!(readl(dev->virtbase + I2C_RISR)
822 if (dev->cli.count == 0)
825 readb(dev->virtbase + I2C_RFR);
828 dev->cli.xfer_bytes++;
832 disable_all_interrupts(dev);
833 clear_all_interrupts(dev);
835 if (dev->cli.count) {
837 dev_err(&dev->adev->dev,
838 "%lu bytes still remain to be xfered\n",
842 complete(&dev->xfer_complete);
846 /* Master Arbitration lost interrupt */
851 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
852 complete(&dev->xfer_complete);
857 * Bus Error interrupt.
858 * This happens when an unexpected start/stop condition occurs
859 * during the transaction.
864 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
867 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
868 complete(&dev->xfer_complete);
873 * Tx FIFO overrun interrupt.
874 * This is set when a write operation in Tx FIFO is performed and
875 * the Tx FIFO is full.
881 dev_err(&dev->adev->dev, "Tx Fifo Over run\n");
882 complete(&dev->xfer_complete);
886 /* unhandled interrupts by this driver - TODO*/
894 dev_err(&dev->adev->dev, "unhandled Interrupt\n");
897 dev_err(&dev->adev->dev, "spurious Interrupt..\n");
906 static int nmk_i2c_suspend(struct device *dev)
908 struct amba_device *adev = to_amba_device(dev);
909 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
914 pinctrl_pm_select_sleep_state(dev);
919 static int nmk_i2c_resume(struct device *dev)
921 /* First go to the default state */
922 pinctrl_pm_select_default_state(dev);
923 /* Then let's idle the pins until the next transfer happens */
924 pinctrl_pm_select_idle_state(dev);
929 #define nmk_i2c_suspend NULL
930 #define nmk_i2c_resume NULL
934 * We use noirq so that we suspend late and resume before the wakeup interrupt
935 * to ensure that we do the !pm_runtime_suspended() check in resume before
936 * there has been a regular pm runtime resume (via pm_runtime_get_sync()).
938 static const struct dev_pm_ops nmk_i2c_pm = {
939 .suspend_noirq = nmk_i2c_suspend,
940 .resume_noirq = nmk_i2c_resume,
943 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
945 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
948 static const struct i2c_algorithm nmk_i2c_algo = {
949 .master_xfer = nmk_i2c_xfer,
950 .functionality = nmk_i2c_functionality
953 static void nmk_i2c_of_probe(struct device_node *np,
954 struct nmk_i2c_dev *nmk)
956 /* Default to 100 kHz if no frequency is given in the node */
957 if (of_property_read_u32(np, "clock-frequency", &nmk->clk_freq))
958 nmk->clk_freq = 100000;
960 /* This driver only supports 'standard' and 'fast' modes of operation. */
961 if (nmk->clk_freq <= 100000)
962 nmk->sm = I2C_FREQ_MODE_STANDARD;
964 nmk->sm = I2C_FREQ_MODE_FAST;
965 nmk->tft = 1; /* Tx FIFO threshold */
966 nmk->rft = 8; /* Rx FIFO threshold */
967 nmk->timeout = 200; /* Slave response timeout(ms) */
970 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
973 struct device_node *np = adev->dev.of_node;
974 struct nmk_i2c_dev *dev;
975 struct i2c_adapter *adap;
976 struct i2c_vendor_data *vendor = id->data;
977 u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;
979 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
981 dev_err(&adev->dev, "cannot allocate memory\n");
985 dev->vendor = vendor;
988 nmk_i2c_of_probe(np, dev);
990 if (dev->tft > max_fifo_threshold) {
991 dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n",
992 dev->tft, max_fifo_threshold);
993 dev->tft = max_fifo_threshold;
996 if (dev->rft > max_fifo_threshold) {
997 dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n",
998 dev->rft, max_fifo_threshold);
999 dev->rft = max_fifo_threshold;
1002 amba_set_drvdata(adev, dev);
1004 /* Select default pin state */
1005 pinctrl_pm_select_default_state(&adev->dev);
1006 /* If possible, let's go to idle until the first transfer */
1007 pinctrl_pm_select_idle_state(&adev->dev);
1009 dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
1010 if (!dev->virtbase) {
1012 goto err_no_ioremap;
1015 dev->irq = adev->irq[0];
1016 ret = request_irq(dev->irq, i2c_irq_handler, 0,
1019 dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq);
1023 pm_suspend_ignore_children(&adev->dev, true);
1025 dev->clk = clk_get(&adev->dev, NULL);
1026 if (IS_ERR(dev->clk)) {
1027 dev_err(&adev->dev, "could not get i2c clock\n");
1028 ret = PTR_ERR(dev->clk);
1033 adap->dev.of_node = np;
1034 adap->dev.parent = &adev->dev;
1035 adap->owner = THIS_MODULE;
1036 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1037 adap->algo = &nmk_i2c_algo;
1038 adap->timeout = msecs_to_jiffies(dev->timeout);
1039 snprintf(adap->name, sizeof(adap->name),
1040 "Nomadik I2C at %pR", &adev->res);
1042 i2c_set_adapdata(adap, dev);
1044 dev_info(&adev->dev,
1045 "initialize %s on virtual base %p\n",
1046 adap->name, dev->virtbase);
1048 ret = i2c_add_adapter(adap);
1050 dev_err(&adev->dev, "failed to add adapter\n");
1054 pm_runtime_put(&adev->dev);
1061 free_irq(dev->irq, dev);
1063 iounmap(dev->virtbase);
1071 static int nmk_i2c_remove(struct amba_device *adev)
1073 struct resource *res = &adev->res;
1074 struct nmk_i2c_dev *dev = amba_get_drvdata(adev);
1076 i2c_del_adapter(&dev->adap);
1077 flush_i2c_fifo(dev);
1078 disable_all_interrupts(dev);
1079 clear_all_interrupts(dev);
1080 /* disable the controller */
1081 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
1082 free_irq(dev->irq, dev);
1083 iounmap(dev->virtbase);
1085 release_mem_region(res->start, resource_size(res));
1087 pm_runtime_disable(&adev->dev);
1093 static struct i2c_vendor_data vendor_stn8815 = {
1095 .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */
1098 static struct i2c_vendor_data vendor_db8500 = {
1100 .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */
1103 static struct amba_id nmk_i2c_ids[] = {
1107 .data = &vendor_stn8815,
1112 .data = &vendor_db8500,
1117 MODULE_DEVICE_TABLE(amba, nmk_i2c_ids);
1119 static struct amba_driver nmk_i2c_driver = {
1121 .owner = THIS_MODULE,
1122 .name = DRIVER_NAME,
1125 .id_table = nmk_i2c_ids,
1126 .probe = nmk_i2c_probe,
1127 .remove = nmk_i2c_remove,
1130 static int __init nmk_i2c_init(void)
1132 return amba_driver_register(&nmk_i2c_driver);
1135 static void __exit nmk_i2c_exit(void)
1137 amba_driver_unregister(&nmk_i2c_driver);
1140 subsys_initcall(nmk_i2c_init);
1141 module_exit(nmk_i2c_exit);
1143 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
1144 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1145 MODULE_LICENSE("GPL");