2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101 extern int radeon_runtime_pm;
104 * Copy from radeon_drv.h so we don't have to include both and have conflicting
107 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
108 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
109 /* RADEON_IB_POOL_SIZE must be a power of 2 */
110 #define RADEON_IB_POOL_SIZE 16
111 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
112 #define RADEONFB_CONN_LIMIT 4
113 #define RADEON_BIOS_NUM_SCRATCH 8
115 /* max number of rings */
116 #define RADEON_NUM_RINGS 6
118 /* fence seq are set to this number when signaled */
119 #define RADEON_FENCE_SIGNALED_SEQ 0LL
121 /* internal ring indices */
122 /* r1xx+ has gfx CP ring */
123 #define RADEON_RING_TYPE_GFX_INDEX 0
125 /* cayman has 2 compute CP rings */
126 #define CAYMAN_RING_TYPE_CP1_INDEX 1
127 #define CAYMAN_RING_TYPE_CP2_INDEX 2
129 /* R600+ has an async dma ring */
130 #define R600_RING_TYPE_DMA_INDEX 3
131 /* cayman add a second async dma ring */
132 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
135 #define R600_RING_TYPE_UVD_INDEX 5
137 /* hardcode those limit for now */
138 #define RADEON_VA_IB_OFFSET (1 << 20)
139 #define RADEON_VA_RESERVED_SIZE (8 << 20)
140 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
143 #define RADEON_RESET_GFX (1 << 0)
144 #define RADEON_RESET_COMPUTE (1 << 1)
145 #define RADEON_RESET_DMA (1 << 2)
146 #define RADEON_RESET_CP (1 << 3)
147 #define RADEON_RESET_GRBM (1 << 4)
148 #define RADEON_RESET_DMA1 (1 << 5)
149 #define RADEON_RESET_RLC (1 << 6)
150 #define RADEON_RESET_SEM (1 << 7)
151 #define RADEON_RESET_IH (1 << 8)
152 #define RADEON_RESET_VMC (1 << 9)
153 #define RADEON_RESET_MC (1 << 10)
154 #define RADEON_RESET_DISPLAY (1 << 11)
157 #define RADEON_CG_BLOCK_GFX (1 << 0)
158 #define RADEON_CG_BLOCK_MC (1 << 1)
159 #define RADEON_CG_BLOCK_SDMA (1 << 2)
160 #define RADEON_CG_BLOCK_UVD (1 << 3)
161 #define RADEON_CG_BLOCK_VCE (1 << 4)
162 #define RADEON_CG_BLOCK_HDP (1 << 5)
163 #define RADEON_CG_BLOCK_BIF (1 << 6)
166 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
167 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
168 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
169 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
170 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
171 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
172 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
173 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
174 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
175 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
176 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
177 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
178 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
179 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
180 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
181 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
182 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
185 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
186 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
187 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
188 #define RADEON_PG_SUPPORT_UVD (1 << 3)
189 #define RADEON_PG_SUPPORT_VCE (1 << 4)
190 #define RADEON_PG_SUPPORT_CP (1 << 5)
191 #define RADEON_PG_SUPPORT_GDS (1 << 6)
192 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
193 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
194 #define RADEON_PG_SUPPORT_ACP (1 << 9)
195 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
197 /* max cursor sizes (in pixels) */
198 #define CURSOR_WIDTH 64
199 #define CURSOR_HEIGHT 64
201 #define CIK_CURSOR_WIDTH 128
202 #define CIK_CURSOR_HEIGHT 128
205 * Errata workarounds.
207 enum radeon_pll_errata {
208 CHIP_ERRATA_R300_CG = 0x00000001,
209 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
210 CHIP_ERRATA_PLL_DELAY = 0x00000004
214 struct radeon_device;
220 bool radeon_get_bios(struct radeon_device *rdev);
225 struct radeon_dummy_page {
229 int radeon_dummy_page_init(struct radeon_device *rdev);
230 void radeon_dummy_page_fini(struct radeon_device *rdev);
236 struct radeon_clock {
237 struct radeon_pll p1pll;
238 struct radeon_pll p2pll;
239 struct radeon_pll dcpll;
240 struct radeon_pll spll;
241 struct radeon_pll mpll;
243 uint32_t default_mclk;
244 uint32_t default_sclk;
245 uint32_t default_dispclk;
246 uint32_t current_dispclk;
248 uint32_t max_pixel_clock;
254 int radeon_pm_init(struct radeon_device *rdev);
255 void radeon_pm_fini(struct radeon_device *rdev);
256 void radeon_pm_compute_clocks(struct radeon_device *rdev);
257 void radeon_pm_suspend(struct radeon_device *rdev);
258 void radeon_pm_resume(struct radeon_device *rdev);
259 void radeon_combios_get_power_modes(struct radeon_device *rdev);
260 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
261 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
265 struct atom_clock_dividers *dividers);
266 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
269 struct atom_mpll_param *mpll_param);
270 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
271 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
272 u16 voltage_level, u8 voltage_type,
273 u32 *gpio_value, u32 *gpio_mask);
274 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
275 u32 eng_clock, u32 mem_clock);
276 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
277 u8 voltage_type, u16 *voltage_step);
278 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
279 u16 voltage_id, u16 *voltage);
280 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
283 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
285 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
286 u16 *vddc, u16 *vddci,
287 u16 virtual_voltage_id,
288 u16 vbios_voltage_id);
289 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
293 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
294 u8 voltage_type, u16 *min_voltage);
295 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
296 u8 voltage_type, u16 *max_voltage);
297 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
298 u8 voltage_type, u8 voltage_mode,
299 struct atom_voltage_table *voltage_table);
300 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
301 u8 voltage_type, u8 voltage_mode);
302 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
304 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
306 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
308 struct atom_mc_reg_table *reg_table);
309 int radeon_atom_get_memory_info(struct radeon_device *rdev,
310 u8 module_index, struct atom_memory_info *mem_info);
311 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
312 bool gddr5, u8 module_index,
313 struct atom_memory_clock_range_table *mclk_range_table);
314 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
315 u16 voltage_id, u16 *voltage);
316 void rs690_pm_info(struct radeon_device *rdev);
317 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
318 unsigned *bankh, unsigned *mtaspect,
319 unsigned *tile_split);
324 struct radeon_fence_driver {
325 uint32_t scratch_reg;
327 volatile uint32_t *cpu_addr;
328 /* sync_seq is protected by ring emission lock */
329 uint64_t sync_seq[RADEON_NUM_RINGS];
334 struct radeon_fence {
335 struct radeon_device *rdev;
337 /* protected by radeon_fence.lock */
343 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
344 int radeon_fence_driver_init(struct radeon_device *rdev);
345 void radeon_fence_driver_fini(struct radeon_device *rdev);
346 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
347 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
348 void radeon_fence_process(struct radeon_device *rdev, int ring);
349 bool radeon_fence_signaled(struct radeon_fence *fence);
350 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
351 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
352 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
353 int radeon_fence_wait_any(struct radeon_device *rdev,
354 struct radeon_fence **fences,
356 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
357 void radeon_fence_unref(struct radeon_fence **fence);
358 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
359 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
360 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
361 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
362 struct radeon_fence *b)
372 BUG_ON(a->ring != b->ring);
374 if (a->seq > b->seq) {
381 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
382 struct radeon_fence *b)
392 BUG_ON(a->ring != b->ring);
394 return a->seq < b->seq;
400 struct radeon_surface_reg {
401 struct radeon_bo *bo;
404 #define RADEON_GEM_MAX_SURFACES 8
410 struct ttm_bo_global_ref bo_global_ref;
411 struct drm_global_reference mem_global_ref;
412 struct ttm_bo_device bdev;
413 bool mem_global_referenced;
417 /* bo virtual address in a specific vm */
418 struct radeon_bo_va {
419 /* protected by bo being reserved */
420 struct list_head bo_list;
427 /* protected by vm mutex */
428 struct list_head vm_list;
430 /* constant after initialization */
431 struct radeon_vm *vm;
432 struct radeon_bo *bo;
436 /* Protected by gem.mutex */
437 struct list_head list;
438 /* Protected by tbo.reserved */
440 struct ttm_placement placement;
441 struct ttm_buffer_object tbo;
442 struct ttm_bo_kmap_obj kmap;
448 /* list of all virtual address to which this bo
452 /* Constant after initialization */
453 struct radeon_device *rdev;
454 struct drm_gem_object gem_base;
456 struct ttm_bo_kmap_obj dma_buf_vmap;
459 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
461 struct radeon_bo_list {
462 struct ttm_validate_buffer tv;
463 struct radeon_bo *bo;
471 int radeon_gem_debugfs_init(struct radeon_device *rdev);
473 /* sub-allocation manager, it has to be protected by another lock.
474 * By conception this is an helper for other part of the driver
475 * like the indirect buffer or semaphore, which both have their
478 * Principe is simple, we keep a list of sub allocation in offset
479 * order (first entry has offset == 0, last entry has the highest
482 * When allocating new object we first check if there is room at
483 * the end total_size - (last_object_offset + last_object_size) >=
484 * alloc_size. If so we allocate new object there.
486 * When there is not enough room at the end, we start waiting for
487 * each sub object until we reach object_offset+object_size >=
488 * alloc_size, this object then become the sub object we return.
490 * Alignment can't be bigger than page size.
492 * Hole are not considered for allocation to keep things simple.
493 * Assumption is that there won't be hole (all object on same
496 struct radeon_sa_manager {
497 wait_queue_head_t wq;
498 struct radeon_bo *bo;
499 struct list_head *hole;
500 struct list_head flist[RADEON_NUM_RINGS];
501 struct list_head olist;
511 /* sub-allocation buffer */
512 struct radeon_sa_bo {
513 struct list_head olist;
514 struct list_head flist;
515 struct radeon_sa_manager *manager;
518 struct radeon_fence *fence;
526 struct list_head objects;
529 int radeon_gem_init(struct radeon_device *rdev);
530 void radeon_gem_fini(struct radeon_device *rdev);
531 int radeon_gem_object_create(struct radeon_device *rdev, int size,
532 int alignment, int initial_domain,
533 bool discardable, bool kernel,
534 struct drm_gem_object **obj);
536 int radeon_mode_dumb_create(struct drm_file *file_priv,
537 struct drm_device *dev,
538 struct drm_mode_create_dumb *args);
539 int radeon_mode_dumb_mmap(struct drm_file *filp,
540 struct drm_device *dev,
541 uint32_t handle, uint64_t *offset_p);
546 /* everything here is constant */
547 struct radeon_semaphore {
548 struct radeon_sa_bo *sa_bo;
553 int radeon_semaphore_create(struct radeon_device *rdev,
554 struct radeon_semaphore **semaphore);
555 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
556 struct radeon_semaphore *semaphore);
557 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
558 struct radeon_semaphore *semaphore);
559 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
560 struct radeon_semaphore *semaphore,
561 int signaler, int waiter);
562 void radeon_semaphore_free(struct radeon_device *rdev,
563 struct radeon_semaphore **semaphore,
564 struct radeon_fence *fence);
567 * GART structures, functions & helpers
571 #define RADEON_GPU_PAGE_SIZE 4096
572 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
573 #define RADEON_GPU_PAGE_SHIFT 12
574 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
577 dma_addr_t table_addr;
578 struct radeon_bo *robj;
580 unsigned num_gpu_pages;
581 unsigned num_cpu_pages;
584 dma_addr_t *pages_addr;
588 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
589 void radeon_gart_table_ram_free(struct radeon_device *rdev);
590 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
591 void radeon_gart_table_vram_free(struct radeon_device *rdev);
592 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
593 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
594 int radeon_gart_init(struct radeon_device *rdev);
595 void radeon_gart_fini(struct radeon_device *rdev);
596 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
598 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
599 int pages, struct page **pagelist,
600 dma_addr_t *dma_addr);
601 void radeon_gart_restore(struct radeon_device *rdev);
605 * GPU MC structures, functions & helpers
608 resource_size_t aper_size;
609 resource_size_t aper_base;
610 resource_size_t agp_base;
611 /* for some chips with <= 32MB we need to lie
612 * about vram size near mc fb location */
614 u64 visible_vram_size;
624 bool igp_sideport_enabled;
629 bool radeon_combios_sideport_present(struct radeon_device *rdev);
630 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
633 * GPU scratch registers structures, functions & helpers
635 struct radeon_scratch {
642 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
643 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
646 * GPU doorbell structures, functions & helpers
648 struct radeon_doorbell {
652 resource_size_t base;
653 resource_size_t size;
657 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
658 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
664 struct radeon_unpin_work {
665 struct work_struct work;
666 struct radeon_device *rdev;
668 struct radeon_fence *fence;
669 struct drm_pending_vblank_event *event;
670 struct radeon_bo *old_rbo;
674 struct r500_irq_stat_regs {
679 struct r600_irq_stat_regs {
689 struct evergreen_irq_stat_regs {
710 struct cik_irq_stat_regs {
720 union radeon_irq_stat_regs {
721 struct r500_irq_stat_regs r500;
722 struct r600_irq_stat_regs r600;
723 struct evergreen_irq_stat_regs evergreen;
724 struct cik_irq_stat_regs cik;
727 #define RADEON_MAX_HPD_PINS 6
728 #define RADEON_MAX_CRTCS 6
729 #define RADEON_MAX_AFMT_BLOCKS 7
734 atomic_t ring_int[RADEON_NUM_RINGS];
735 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736 atomic_t pflip[RADEON_MAX_CRTCS];
737 wait_queue_head_t vblank_queue;
738 bool hpd[RADEON_MAX_HPD_PINS];
739 bool afmt[RADEON_MAX_AFMT_BLOCKS];
740 union radeon_irq_stat_regs stat_regs;
744 int radeon_irq_kms_init(struct radeon_device *rdev);
745 void radeon_irq_kms_fini(struct radeon_device *rdev);
746 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
747 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
748 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
749 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
750 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
751 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
752 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
753 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
760 struct radeon_sa_bo *sa_bo;
765 struct radeon_fence *fence;
766 struct radeon_vm *vm;
768 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
769 struct radeon_semaphore *semaphore;
773 struct radeon_bo *ring_obj;
774 volatile uint32_t *ring;
778 unsigned rptr_save_reg;
779 u64 next_rptr_gpu_addr;
780 volatile u32 *next_rptr_cpu_addr;
785 unsigned ring_free_dw;
787 unsigned long last_activity;
795 u64 last_semaphore_signal_addr;
796 u64 last_semaphore_wait_addr;
801 struct radeon_bo *mqd_obj;
802 u32 doorbell_page_num;
808 struct radeon_bo *hpd_eop_obj;
809 u64 hpd_eop_gpu_addr;
819 /* maximum number of VMIDs */
820 #define RADEON_NUM_VM 16
822 /* defines number of bits in page table versus page directory,
823 * a page is 4KB so we have 12 bits offset, 9 bits in the page
824 * table and the remaining 19 bits are in the page directory */
825 #define RADEON_VM_BLOCK_SIZE 9
827 /* number of entries in page table */
828 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
830 /* PTBs (Page Table Blocks) need to be aligned to 32K */
831 #define RADEON_VM_PTB_ALIGN_SIZE 32768
832 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
833 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
835 #define R600_PTE_VALID (1 << 0)
836 #define R600_PTE_SYSTEM (1 << 1)
837 #define R600_PTE_SNOOPED (1 << 2)
838 #define R600_PTE_READABLE (1 << 5)
839 #define R600_PTE_WRITEABLE (1 << 6)
842 struct list_head list;
846 /* contains the page directory */
847 struct radeon_sa_bo *page_directory;
848 uint64_t pd_gpu_addr;
850 /* array of page tables, one for each page directory entry */
851 struct radeon_sa_bo **page_tables;
854 /* last fence for cs using this vm */
855 struct radeon_fence *fence;
856 /* last flush or NULL if we still need to flush */
857 struct radeon_fence *last_flush;
860 struct radeon_vm_manager {
862 struct list_head lru_vm;
863 struct radeon_fence *active[RADEON_NUM_VM];
864 struct radeon_sa_manager sa_manager;
866 /* number of VMIDs */
868 /* vram base address for page table entry */
869 u64 vram_base_offset;
875 * file private structure
877 struct radeon_fpriv {
885 struct radeon_bo *ring_obj;
886 volatile uint32_t *ring;
898 #include "clearstate_defs.h"
901 /* for power gating */
902 struct radeon_bo *save_restore_obj;
903 uint64_t save_restore_gpu_addr;
904 volatile uint32_t *sr_ptr;
907 /* for clear state */
908 struct radeon_bo *clear_state_obj;
909 uint64_t clear_state_gpu_addr;
910 volatile uint32_t *cs_ptr;
911 const struct cs_section_def *cs_data;
912 u32 clear_state_size;
914 struct radeon_bo *cp_table_obj;
915 uint64_t cp_table_gpu_addr;
916 volatile uint32_t *cp_table_ptr;
920 int radeon_ib_get(struct radeon_device *rdev, int ring,
921 struct radeon_ib *ib, struct radeon_vm *vm,
923 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
924 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
925 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
926 struct radeon_ib *const_ib);
927 int radeon_ib_pool_init(struct radeon_device *rdev);
928 void radeon_ib_pool_fini(struct radeon_device *rdev);
929 int radeon_ib_ring_tests(struct radeon_device *rdev);
930 /* Ring access between begin & end cannot sleep */
931 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
932 struct radeon_ring *ring);
933 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
934 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
935 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
936 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
937 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
938 void radeon_ring_undo(struct radeon_ring *ring);
939 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
940 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
941 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
942 void radeon_ring_lockup_update(struct radeon_ring *ring);
943 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
944 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
946 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
947 unsigned size, uint32_t *data);
948 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
949 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop);
950 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
954 void r600_dma_stop(struct radeon_device *rdev);
955 int r600_dma_resume(struct radeon_device *rdev);
956 void r600_dma_fini(struct radeon_device *rdev);
958 void cayman_dma_stop(struct radeon_device *rdev);
959 int cayman_dma_resume(struct radeon_device *rdev);
960 void cayman_dma_fini(struct radeon_device *rdev);
965 struct radeon_cs_reloc {
966 struct drm_gem_object *gobj;
967 struct radeon_bo *robj;
968 struct radeon_bo_list lobj;
973 struct radeon_cs_chunk {
977 void __user *user_ptr;
980 struct radeon_cs_parser {
982 struct radeon_device *rdev;
983 struct drm_file *filp;
986 struct radeon_cs_chunk *chunks;
987 uint64_t *chunks_array;
992 struct radeon_cs_reloc *relocs;
993 struct radeon_cs_reloc **relocs_ptr;
994 struct list_head validated;
995 unsigned dma_reloc_idx;
996 /* indices of various chunks */
998 int chunk_relocs_idx;
1000 int chunk_const_ib_idx;
1001 struct radeon_ib ib;
1002 struct radeon_ib const_ib;
1009 struct ww_acquire_ctx ticket;
1012 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1014 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1017 return ibc->kdata[idx];
1018 return p->ib.ptr[idx];
1022 struct radeon_cs_packet {
1028 unsigned one_reg_wr;
1031 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1032 struct radeon_cs_packet *pkt,
1033 unsigned idx, unsigned reg);
1034 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1035 struct radeon_cs_packet *pkt);
1041 int radeon_agp_init(struct radeon_device *rdev);
1042 void radeon_agp_resume(struct radeon_device *rdev);
1043 void radeon_agp_suspend(struct radeon_device *rdev);
1044 void radeon_agp_fini(struct radeon_device *rdev);
1051 struct radeon_bo *wb_obj;
1052 volatile uint32_t *wb;
1058 #define RADEON_WB_SCRATCH_OFFSET 0
1059 #define RADEON_WB_RING0_NEXT_RPTR 256
1060 #define RADEON_WB_CP_RPTR_OFFSET 1024
1061 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1062 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1063 #define R600_WB_DMA_RPTR_OFFSET 1792
1064 #define R600_WB_IH_WPTR_OFFSET 2048
1065 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1066 #define R600_WB_EVENT_OFFSET 3072
1067 #define CIK_WB_CP1_WPTR_OFFSET 3328
1068 #define CIK_WB_CP2_WPTR_OFFSET 3584
1071 * struct radeon_pm - power management datas
1072 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1073 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1074 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1075 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1076 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1077 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1078 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1079 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1080 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1081 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1082 * @needed_bandwidth: current bandwidth needs
1084 * It keeps track of various data needed to take powermanagement decision.
1085 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1086 * Equation between gpu/memory clock and available bandwidth is hw dependent
1087 * (type of memory, bus size, efficiency, ...)
1090 enum radeon_pm_method {
1096 enum radeon_dynpm_state {
1097 DYNPM_STATE_DISABLED,
1098 DYNPM_STATE_MINIMUM,
1101 DYNPM_STATE_SUSPENDED,
1103 enum radeon_dynpm_action {
1105 DYNPM_ACTION_MINIMUM,
1106 DYNPM_ACTION_DOWNCLOCK,
1107 DYNPM_ACTION_UPCLOCK,
1108 DYNPM_ACTION_DEFAULT
1111 enum radeon_voltage_type {
1118 enum radeon_pm_state_type {
1119 /* not used for dpm */
1120 POWER_STATE_TYPE_DEFAULT,
1121 POWER_STATE_TYPE_POWERSAVE,
1122 /* user selectable states */
1123 POWER_STATE_TYPE_BATTERY,
1124 POWER_STATE_TYPE_BALANCED,
1125 POWER_STATE_TYPE_PERFORMANCE,
1126 /* internal states */
1127 POWER_STATE_TYPE_INTERNAL_UVD,
1128 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1129 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1130 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1131 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1132 POWER_STATE_TYPE_INTERNAL_BOOT,
1133 POWER_STATE_TYPE_INTERNAL_THERMAL,
1134 POWER_STATE_TYPE_INTERNAL_ACPI,
1135 POWER_STATE_TYPE_INTERNAL_ULV,
1136 POWER_STATE_TYPE_INTERNAL_3DPERF,
1139 enum radeon_pm_profile_type {
1147 #define PM_PROFILE_DEFAULT_IDX 0
1148 #define PM_PROFILE_LOW_SH_IDX 1
1149 #define PM_PROFILE_MID_SH_IDX 2
1150 #define PM_PROFILE_HIGH_SH_IDX 3
1151 #define PM_PROFILE_LOW_MH_IDX 4
1152 #define PM_PROFILE_MID_MH_IDX 5
1153 #define PM_PROFILE_HIGH_MH_IDX 6
1154 #define PM_PROFILE_MAX 7
1156 struct radeon_pm_profile {
1157 int dpms_off_ps_idx;
1159 int dpms_off_cm_idx;
1163 enum radeon_int_thermal_type {
1165 THERMAL_TYPE_EXTERNAL,
1166 THERMAL_TYPE_EXTERNAL_GPIO,
1169 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1170 THERMAL_TYPE_EVERGREEN,
1174 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1179 struct radeon_voltage {
1180 enum radeon_voltage_type type;
1182 struct radeon_gpio_rec gpio;
1183 u32 delay; /* delay in usec from voltage drop to sclk change */
1184 bool active_high; /* voltage drop is active when bit is high */
1186 u8 vddc_id; /* index into vddc voltage table */
1187 u8 vddci_id; /* index into vddci voltage table */
1191 /* evergreen+ vddci */
1195 /* clock mode flags */
1196 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1198 struct radeon_pm_clock_info {
1204 struct radeon_voltage voltage;
1205 /* standardized clock flags */
1210 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1212 struct radeon_power_state {
1213 enum radeon_pm_state_type type;
1214 struct radeon_pm_clock_info *clock_info;
1215 /* number of valid clock modes in this power state */
1216 int num_clock_modes;
1217 struct radeon_pm_clock_info *default_clock_mode;
1218 /* standardized state flags */
1220 u32 misc; /* vbios specific flags */
1221 u32 misc2; /* vbios specific flags */
1222 int pcie_lanes; /* pcie lanes */
1226 * Some modes are overclocked by very low value, accept them
1228 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1230 enum radeon_dpm_auto_throttle_src {
1231 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1232 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1235 enum radeon_dpm_event_src {
1236 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1237 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1238 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1239 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1240 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1244 u32 caps; /* vbios flags */
1245 u32 class; /* vbios flags */
1246 u32 class2; /* vbios flags */
1257 struct radeon_dpm_thermal {
1258 /* thermal interrupt work */
1259 struct work_struct work;
1260 /* low temperature threshold */
1262 /* high temperature threshold */
1264 /* was interrupt low to high or high to low */
1268 enum radeon_clk_action
1274 struct radeon_blacklist_clocks
1278 enum radeon_clk_action action;
1281 struct radeon_clock_and_voltage_limits {
1288 struct radeon_clock_array {
1293 struct radeon_clock_voltage_dependency_entry {
1298 struct radeon_clock_voltage_dependency_table {
1300 struct radeon_clock_voltage_dependency_entry *entries;
1303 union radeon_cac_leakage_entry {
1315 struct radeon_cac_leakage_table {
1317 union radeon_cac_leakage_entry *entries;
1320 struct radeon_phase_shedding_limits_entry {
1326 struct radeon_phase_shedding_limits_table {
1328 struct radeon_phase_shedding_limits_entry *entries;
1331 struct radeon_uvd_clock_voltage_dependency_entry {
1337 struct radeon_uvd_clock_voltage_dependency_table {
1339 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1342 struct radeon_vce_clock_voltage_dependency_entry {
1348 struct radeon_vce_clock_voltage_dependency_table {
1350 struct radeon_vce_clock_voltage_dependency_entry *entries;
1353 struct radeon_ppm_table {
1355 u16 cpu_core_number;
1357 u32 small_ac_platform_tdp;
1359 u32 small_ac_platform_tdc;
1366 struct radeon_cac_tdp_table {
1368 u16 configurable_tdp;
1370 u16 battery_power_limit;
1371 u16 small_power_limit;
1372 u16 low_cac_leakage;
1373 u16 high_cac_leakage;
1374 u16 maximum_power_delivery_limit;
1377 struct radeon_dpm_dynamic_state {
1378 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1379 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1380 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1381 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1382 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1383 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1384 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1385 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1386 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1387 struct radeon_clock_array valid_sclk_values;
1388 struct radeon_clock_array valid_mclk_values;
1389 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1390 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1391 u32 mclk_sclk_ratio;
1392 u32 sclk_mclk_delta;
1393 u16 vddc_vddci_delta;
1394 u16 min_vddc_for_pcie_gen2;
1395 struct radeon_cac_leakage_table cac_leakage_table;
1396 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1397 struct radeon_ppm_table *ppm_table;
1398 struct radeon_cac_tdp_table *cac_tdp_table;
1401 struct radeon_dpm_fan {
1411 bool ucode_fan_control;
1414 enum radeon_pcie_gen {
1415 RADEON_PCIE_GEN1 = 0,
1416 RADEON_PCIE_GEN2 = 1,
1417 RADEON_PCIE_GEN3 = 2,
1418 RADEON_PCIE_GEN_INVALID = 0xffff
1421 enum radeon_dpm_forced_level {
1422 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1423 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1424 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1428 struct radeon_ps *ps;
1429 /* number of valid power states */
1431 /* current power state that is active */
1432 struct radeon_ps *current_ps;
1433 /* requested power state */
1434 struct radeon_ps *requested_ps;
1435 /* boot up power state */
1436 struct radeon_ps *boot_ps;
1437 /* default uvd power state */
1438 struct radeon_ps *uvd_ps;
1439 enum radeon_pm_state_type state;
1440 enum radeon_pm_state_type user_state;
1442 u32 voltage_response_time;
1443 u32 backbias_response_time;
1445 u32 new_active_crtcs;
1446 int new_active_crtc_count;
1447 u32 current_active_crtcs;
1448 int current_active_crtc_count;
1449 struct radeon_dpm_dynamic_state dyn_state;
1450 struct radeon_dpm_fan fan;
1453 u32 near_tdp_limit_adjusted;
1454 u32 sq_ramping_threshold;
1458 u16 load_line_slope;
1461 /* special states active */
1462 bool thermal_active;
1464 /* thermal handling */
1465 struct radeon_dpm_thermal thermal;
1467 enum radeon_dpm_forced_level forced_level;
1468 /* track UVD streams */
1473 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1477 /* write locked while reprogramming mclk */
1478 struct rw_semaphore mclk_lock;
1480 int active_crtc_count;
1483 fixed20_12 max_bandwidth;
1484 fixed20_12 igp_sideport_mclk;
1485 fixed20_12 igp_system_mclk;
1486 fixed20_12 igp_ht_link_clk;
1487 fixed20_12 igp_ht_link_width;
1488 fixed20_12 k8_bandwidth;
1489 fixed20_12 sideport_bandwidth;
1490 fixed20_12 ht_bandwidth;
1491 fixed20_12 core_bandwidth;
1494 fixed20_12 needed_bandwidth;
1495 struct radeon_power_state *power_state;
1496 /* number of valid power states */
1497 int num_power_states;
1498 int current_power_state_index;
1499 int current_clock_mode_index;
1500 int requested_power_state_index;
1501 int requested_clock_mode_index;
1502 int default_power_state_index;
1511 struct radeon_i2c_chan *i2c_bus;
1512 /* selected pm method */
1513 enum radeon_pm_method pm_method;
1514 /* dynpm power management */
1515 struct delayed_work dynpm_idle_work;
1516 enum radeon_dynpm_state dynpm_state;
1517 enum radeon_dynpm_action dynpm_planned_action;
1518 unsigned long dynpm_action_timeout;
1519 bool dynpm_can_upclock;
1520 bool dynpm_can_downclock;
1521 /* profile-based power management */
1522 enum radeon_pm_profile_type profile;
1524 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1525 /* internal thermal controller on rv6xx+ */
1526 enum radeon_int_thermal_type int_thermal_type;
1527 struct device *int_hwmon_dev;
1530 struct radeon_dpm dpm;
1533 int radeon_pm_get_type_index(struct radeon_device *rdev,
1534 enum radeon_pm_state_type ps_type,
1539 #define RADEON_MAX_UVD_HANDLES 10
1540 #define RADEON_UVD_STACK_SIZE (1024*1024)
1541 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1544 struct radeon_bo *vcpu_bo;
1548 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1549 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1550 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1551 struct delayed_work idle_work;
1554 int radeon_uvd_init(struct radeon_device *rdev);
1555 void radeon_uvd_fini(struct radeon_device *rdev);
1556 int radeon_uvd_suspend(struct radeon_device *rdev);
1557 int radeon_uvd_resume(struct radeon_device *rdev);
1558 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1559 uint32_t handle, struct radeon_fence **fence);
1560 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1561 uint32_t handle, struct radeon_fence **fence);
1562 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1563 void radeon_uvd_free_handles(struct radeon_device *rdev,
1564 struct drm_file *filp);
1565 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1566 void radeon_uvd_note_usage(struct radeon_device *rdev);
1567 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1568 unsigned vclk, unsigned dclk,
1569 unsigned vco_min, unsigned vco_max,
1570 unsigned fb_factor, unsigned fb_mask,
1571 unsigned pd_min, unsigned pd_max,
1573 unsigned *optimal_fb_div,
1574 unsigned *optimal_vclk_div,
1575 unsigned *optimal_dclk_div);
1576 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1577 unsigned cg_upll_func_cntl);
1579 struct r600_audio_pin {
1582 int bits_per_sample;
1592 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1599 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1605 void radeon_test_moves(struct radeon_device *rdev);
1606 void radeon_test_ring_sync(struct radeon_device *rdev,
1607 struct radeon_ring *cpA,
1608 struct radeon_ring *cpB);
1609 void radeon_test_syncing(struct radeon_device *rdev);
1615 struct radeon_debugfs {
1616 struct drm_info_list *files;
1620 int radeon_debugfs_add_files(struct radeon_device *rdev,
1621 struct drm_info_list *files,
1623 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1626 * ASIC ring specific functions.
1628 struct radeon_asic_ring {
1629 /* ring read/write ptr handling */
1630 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1631 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1632 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1634 /* validating and patching of IBs */
1635 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1636 int (*cs_parse)(struct radeon_cs_parser *p);
1638 /* command emmit functions */
1639 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1640 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1641 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1642 struct radeon_semaphore *semaphore, bool emit_wait);
1643 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1645 /* testing functions */
1646 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1647 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1648 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1651 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1655 * ASIC specific functions.
1657 struct radeon_asic {
1658 int (*init)(struct radeon_device *rdev);
1659 void (*fini)(struct radeon_device *rdev);
1660 int (*resume)(struct radeon_device *rdev);
1661 int (*suspend)(struct radeon_device *rdev);
1662 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1663 int (*asic_reset)(struct radeon_device *rdev);
1664 /* ioctl hw specific callback. Some hw might want to perform special
1665 * operation on specific ioctl. For instance on wait idle some hw
1666 * might want to perform and HDP flush through MMIO as it seems that
1667 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1670 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1671 /* check if 3D engine is idle */
1672 bool (*gui_idle)(struct radeon_device *rdev);
1673 /* wait for mc_idle */
1674 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1675 /* get the reference clock */
1676 u32 (*get_xclk)(struct radeon_device *rdev);
1677 /* get the gpu clock counter */
1678 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1681 void (*tlb_flush)(struct radeon_device *rdev);
1682 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1685 int (*init)(struct radeon_device *rdev);
1686 void (*fini)(struct radeon_device *rdev);
1687 void (*set_page)(struct radeon_device *rdev,
1688 struct radeon_ib *ib,
1690 uint64_t addr, unsigned count,
1691 uint32_t incr, uint32_t flags);
1693 /* ring specific callbacks */
1694 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1697 int (*set)(struct radeon_device *rdev);
1698 int (*process)(struct radeon_device *rdev);
1702 /* display watermarks */
1703 void (*bandwidth_update)(struct radeon_device *rdev);
1704 /* get frame count */
1705 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1706 /* wait for vblank */
1707 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1708 /* set backlight level */
1709 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1710 /* get backlight level */
1711 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1712 /* audio callbacks */
1713 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1714 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1716 /* copy functions for bo handling */
1718 int (*blit)(struct radeon_device *rdev,
1719 uint64_t src_offset,
1720 uint64_t dst_offset,
1721 unsigned num_gpu_pages,
1722 struct radeon_fence **fence);
1723 u32 blit_ring_index;
1724 int (*dma)(struct radeon_device *rdev,
1725 uint64_t src_offset,
1726 uint64_t dst_offset,
1727 unsigned num_gpu_pages,
1728 struct radeon_fence **fence);
1730 /* method used for bo copy */
1731 int (*copy)(struct radeon_device *rdev,
1732 uint64_t src_offset,
1733 uint64_t dst_offset,
1734 unsigned num_gpu_pages,
1735 struct radeon_fence **fence);
1736 /* ring used for bo copies */
1737 u32 copy_ring_index;
1741 int (*set_reg)(struct radeon_device *rdev, int reg,
1742 uint32_t tiling_flags, uint32_t pitch,
1743 uint32_t offset, uint32_t obj_size);
1744 void (*clear_reg)(struct radeon_device *rdev, int reg);
1746 /* hotplug detect */
1748 void (*init)(struct radeon_device *rdev);
1749 void (*fini)(struct radeon_device *rdev);
1750 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1751 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1753 /* static power management */
1755 void (*misc)(struct radeon_device *rdev);
1756 void (*prepare)(struct radeon_device *rdev);
1757 void (*finish)(struct radeon_device *rdev);
1758 void (*init_profile)(struct radeon_device *rdev);
1759 void (*get_dynpm_state)(struct radeon_device *rdev);
1760 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1761 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1762 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1763 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1764 int (*get_pcie_lanes)(struct radeon_device *rdev);
1765 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1766 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1767 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1768 int (*get_temperature)(struct radeon_device *rdev);
1770 /* dynamic power management */
1772 int (*init)(struct radeon_device *rdev);
1773 void (*setup_asic)(struct radeon_device *rdev);
1774 int (*enable)(struct radeon_device *rdev);
1775 void (*disable)(struct radeon_device *rdev);
1776 int (*pre_set_power_state)(struct radeon_device *rdev);
1777 int (*set_power_state)(struct radeon_device *rdev);
1778 void (*post_set_power_state)(struct radeon_device *rdev);
1779 void (*display_configuration_changed)(struct radeon_device *rdev);
1780 void (*fini)(struct radeon_device *rdev);
1781 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1782 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1783 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1784 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1785 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1786 bool (*vblank_too_short)(struct radeon_device *rdev);
1787 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1788 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1792 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1793 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1794 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1802 const unsigned *reg_safe_bm;
1803 unsigned reg_safe_bm_size;
1808 const unsigned *reg_safe_bm;
1809 unsigned reg_safe_bm_size;
1816 unsigned max_tile_pipes;
1818 unsigned max_backends;
1820 unsigned max_threads;
1821 unsigned max_stack_entries;
1822 unsigned max_hw_contexts;
1823 unsigned max_gs_threads;
1824 unsigned sx_max_export_size;
1825 unsigned sx_max_export_pos_size;
1826 unsigned sx_max_export_smx_size;
1827 unsigned sq_num_cf_insts;
1828 unsigned tiling_nbanks;
1829 unsigned tiling_npipes;
1830 unsigned tiling_group_size;
1831 unsigned tile_config;
1832 unsigned backend_map;
1837 unsigned max_tile_pipes;
1839 unsigned max_backends;
1841 unsigned max_threads;
1842 unsigned max_stack_entries;
1843 unsigned max_hw_contexts;
1844 unsigned max_gs_threads;
1845 unsigned sx_max_export_size;
1846 unsigned sx_max_export_pos_size;
1847 unsigned sx_max_export_smx_size;
1848 unsigned sq_num_cf_insts;
1849 unsigned sx_num_of_sets;
1850 unsigned sc_prim_fifo_size;
1851 unsigned sc_hiz_tile_fifo_size;
1852 unsigned sc_earlyz_tile_fifo_fize;
1853 unsigned tiling_nbanks;
1854 unsigned tiling_npipes;
1855 unsigned tiling_group_size;
1856 unsigned tile_config;
1857 unsigned backend_map;
1860 struct evergreen_asic {
1863 unsigned max_tile_pipes;
1865 unsigned max_backends;
1867 unsigned max_threads;
1868 unsigned max_stack_entries;
1869 unsigned max_hw_contexts;
1870 unsigned max_gs_threads;
1871 unsigned sx_max_export_size;
1872 unsigned sx_max_export_pos_size;
1873 unsigned sx_max_export_smx_size;
1874 unsigned sq_num_cf_insts;
1875 unsigned sx_num_of_sets;
1876 unsigned sc_prim_fifo_size;
1877 unsigned sc_hiz_tile_fifo_size;
1878 unsigned sc_earlyz_tile_fifo_size;
1879 unsigned tiling_nbanks;
1880 unsigned tiling_npipes;
1881 unsigned tiling_group_size;
1882 unsigned tile_config;
1883 unsigned backend_map;
1886 struct cayman_asic {
1887 unsigned max_shader_engines;
1888 unsigned max_pipes_per_simd;
1889 unsigned max_tile_pipes;
1890 unsigned max_simds_per_se;
1891 unsigned max_backends_per_se;
1892 unsigned max_texture_channel_caches;
1894 unsigned max_threads;
1895 unsigned max_gs_threads;
1896 unsigned max_stack_entries;
1897 unsigned sx_num_of_sets;
1898 unsigned sx_max_export_size;
1899 unsigned sx_max_export_pos_size;
1900 unsigned sx_max_export_smx_size;
1901 unsigned max_hw_contexts;
1902 unsigned sq_num_cf_insts;
1903 unsigned sc_prim_fifo_size;
1904 unsigned sc_hiz_tile_fifo_size;
1905 unsigned sc_earlyz_tile_fifo_size;
1907 unsigned num_shader_engines;
1908 unsigned num_shader_pipes_per_simd;
1909 unsigned num_tile_pipes;
1910 unsigned num_simds_per_se;
1911 unsigned num_backends_per_se;
1912 unsigned backend_disable_mask_per_asic;
1913 unsigned backend_map;
1914 unsigned num_texture_channel_caches;
1915 unsigned mem_max_burst_length_bytes;
1916 unsigned mem_row_size_in_kb;
1917 unsigned shader_engine_tile_size;
1919 unsigned multi_gpu_tile_size;
1921 unsigned tile_config;
1925 unsigned max_shader_engines;
1926 unsigned max_tile_pipes;
1927 unsigned max_cu_per_sh;
1928 unsigned max_sh_per_se;
1929 unsigned max_backends_per_se;
1930 unsigned max_texture_channel_caches;
1932 unsigned max_gs_threads;
1933 unsigned max_hw_contexts;
1934 unsigned sc_prim_fifo_size_frontend;
1935 unsigned sc_prim_fifo_size_backend;
1936 unsigned sc_hiz_tile_fifo_size;
1937 unsigned sc_earlyz_tile_fifo_size;
1939 unsigned num_tile_pipes;
1940 unsigned num_backends_per_se;
1941 unsigned backend_disable_mask_per_asic;
1942 unsigned backend_map;
1943 unsigned num_texture_channel_caches;
1944 unsigned mem_max_burst_length_bytes;
1945 unsigned mem_row_size_in_kb;
1946 unsigned shader_engine_tile_size;
1948 unsigned multi_gpu_tile_size;
1950 unsigned tile_config;
1951 uint32_t tile_mode_array[32];
1955 unsigned max_shader_engines;
1956 unsigned max_tile_pipes;
1957 unsigned max_cu_per_sh;
1958 unsigned max_sh_per_se;
1959 unsigned max_backends_per_se;
1960 unsigned max_texture_channel_caches;
1962 unsigned max_gs_threads;
1963 unsigned max_hw_contexts;
1964 unsigned sc_prim_fifo_size_frontend;
1965 unsigned sc_prim_fifo_size_backend;
1966 unsigned sc_hiz_tile_fifo_size;
1967 unsigned sc_earlyz_tile_fifo_size;
1969 unsigned num_tile_pipes;
1970 unsigned num_backends_per_se;
1971 unsigned backend_disable_mask_per_asic;
1972 unsigned backend_map;
1973 unsigned num_texture_channel_caches;
1974 unsigned mem_max_burst_length_bytes;
1975 unsigned mem_row_size_in_kb;
1976 unsigned shader_engine_tile_size;
1978 unsigned multi_gpu_tile_size;
1980 unsigned tile_config;
1981 uint32_t tile_mode_array[32];
1984 union radeon_asic_config {
1985 struct r300_asic r300;
1986 struct r100_asic r100;
1987 struct r600_asic r600;
1988 struct rv770_asic rv770;
1989 struct evergreen_asic evergreen;
1990 struct cayman_asic cayman;
1992 struct cik_asic cik;
1996 * asic initizalization from radeon_asic.c
1998 void radeon_agp_disable(struct radeon_device *rdev);
1999 int radeon_asic_init(struct radeon_device *rdev);
2005 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2006 struct drm_file *filp);
2007 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2008 struct drm_file *filp);
2009 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2010 struct drm_file *file_priv);
2011 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2012 struct drm_file *file_priv);
2013 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2014 struct drm_file *file_priv);
2015 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2016 struct drm_file *file_priv);
2017 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2018 struct drm_file *filp);
2019 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2020 struct drm_file *filp);
2021 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2022 struct drm_file *filp);
2023 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2024 struct drm_file *filp);
2025 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2026 struct drm_file *filp);
2027 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2028 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2029 struct drm_file *filp);
2030 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2031 struct drm_file *filp);
2033 /* VRAM scratch page for HDP bug, default vram page */
2034 struct r600_vram_scratch {
2035 struct radeon_bo *robj;
2036 volatile uint32_t *ptr;
2043 struct radeon_atif_notification_cfg {
2048 struct radeon_atif_notifications {
2049 bool display_switch;
2050 bool expansion_mode_change;
2052 bool forced_power_state;
2053 bool system_power_state;
2054 bool display_conf_change;
2056 bool brightness_change;
2057 bool dgpu_display_event;
2060 struct radeon_atif_functions {
2062 bool sbios_requests;
2063 bool select_active_disp;
2065 bool get_tv_standard;
2066 bool set_tv_standard;
2067 bool get_panel_expansion_mode;
2068 bool set_panel_expansion_mode;
2069 bool temperature_change;
2070 bool graphics_device_types;
2073 struct radeon_atif {
2074 struct radeon_atif_notifications notifications;
2075 struct radeon_atif_functions functions;
2076 struct radeon_atif_notification_cfg notification_cfg;
2077 struct radeon_encoder *encoder_for_bl;
2080 struct radeon_atcs_functions {
2084 bool pcie_bus_width;
2087 struct radeon_atcs {
2088 struct radeon_atcs_functions functions;
2092 * Core structure, functions and helpers.
2094 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2095 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2097 struct radeon_device {
2099 struct drm_device *ddev;
2100 struct pci_dev *pdev;
2101 struct rw_semaphore exclusive_lock;
2103 union radeon_asic_config config;
2104 enum radeon_family family;
2105 unsigned long flags;
2107 enum radeon_pll_errata pll_errata;
2114 uint16_t bios_header_start;
2115 struct radeon_bo *stollen_vga_memory;
2117 resource_size_t rmmio_base;
2118 resource_size_t rmmio_size;
2119 /* protects concurrent MM_INDEX/DATA based register access */
2120 spinlock_t mmio_idx_lock;
2121 /* protects concurrent SMC based register access */
2122 spinlock_t smc_idx_lock;
2123 /* protects concurrent PLL register access */
2124 spinlock_t pll_idx_lock;
2125 /* protects concurrent MC register access */
2126 spinlock_t mc_idx_lock;
2127 /* protects concurrent PCIE register access */
2128 spinlock_t pcie_idx_lock;
2129 /* protects concurrent PCIE_PORT register access */
2130 spinlock_t pciep_idx_lock;
2131 /* protects concurrent PIF register access */
2132 spinlock_t pif_idx_lock;
2133 /* protects concurrent CG register access */
2134 spinlock_t cg_idx_lock;
2135 /* protects concurrent UVD register access */
2136 spinlock_t uvd_idx_lock;
2137 /* protects concurrent RCU register access */
2138 spinlock_t rcu_idx_lock;
2139 /* protects concurrent DIDT register access */
2140 spinlock_t didt_idx_lock;
2141 /* protects concurrent ENDPOINT (audio) register access */
2142 spinlock_t end_idx_lock;
2143 void __iomem *rmmio;
2144 radeon_rreg_t mc_rreg;
2145 radeon_wreg_t mc_wreg;
2146 radeon_rreg_t pll_rreg;
2147 radeon_wreg_t pll_wreg;
2148 uint32_t pcie_reg_mask;
2149 radeon_rreg_t pciep_rreg;
2150 radeon_wreg_t pciep_wreg;
2152 void __iomem *rio_mem;
2153 resource_size_t rio_mem_size;
2154 struct radeon_clock clock;
2155 struct radeon_mc mc;
2156 struct radeon_gart gart;
2157 struct radeon_mode_info mode_info;
2158 struct radeon_scratch scratch;
2159 struct radeon_doorbell doorbell;
2160 struct radeon_mman mman;
2161 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2162 wait_queue_head_t fence_queue;
2163 struct mutex ring_lock;
2164 struct radeon_ring ring[RADEON_NUM_RINGS];
2166 struct radeon_sa_manager ring_tmp_bo;
2167 struct radeon_irq irq;
2168 struct radeon_asic *asic;
2169 struct radeon_gem gem;
2170 struct radeon_pm pm;
2171 struct radeon_uvd uvd;
2172 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2173 struct radeon_wb wb;
2174 struct radeon_dummy_page dummy_page;
2179 bool fastfb_working; /* IGP feature*/
2181 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2182 const struct firmware *me_fw; /* all family ME firmware */
2183 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2184 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2185 const struct firmware *mc_fw; /* NI MC firmware */
2186 const struct firmware *ce_fw; /* SI CE firmware */
2187 const struct firmware *mec_fw; /* CIK MEC firmware */
2188 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2189 const struct firmware *smc_fw; /* SMC firmware */
2190 const struct firmware *uvd_fw; /* UVD firmware */
2191 struct r600_vram_scratch vram_scratch;
2192 int msi_enabled; /* msi enabled */
2193 struct r600_ih ih; /* r6/700 interrupt ring */
2194 struct radeon_rlc rlc;
2195 struct radeon_mec mec;
2196 struct work_struct hotplug_work;
2197 struct work_struct audio_work;
2198 struct work_struct reset_work;
2199 int num_crtc; /* number of crtcs */
2200 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2202 struct r600_audio audio; /* audio stuff */
2203 struct notifier_block acpi_nb;
2204 /* only one userspace can use Hyperz features or CMASK at a time */
2205 struct drm_file *hyperz_filp;
2206 struct drm_file *cmask_filp;
2208 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2210 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2211 unsigned debugfs_count;
2212 /* virtual memory */
2213 struct radeon_vm_manager vm_manager;
2214 struct mutex gpu_clock_mutex;
2215 /* ACPI interface */
2216 struct radeon_atif atif;
2217 struct radeon_atcs atcs;
2218 /* srbm instance registers */
2219 struct mutex srbm_mutex;
2220 /* clock, powergating flags */
2224 struct dev_pm_domain vga_pm_domain;
2225 bool have_disp_power_ref;
2228 int radeon_device_init(struct radeon_device *rdev,
2229 struct drm_device *ddev,
2230 struct pci_dev *pdev,
2232 void radeon_device_fini(struct radeon_device *rdev);
2233 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2235 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2236 bool always_indirect);
2237 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2238 bool always_indirect);
2239 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2240 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2242 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2243 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2248 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2251 * Registers read & write functions.
2253 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2254 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2255 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2256 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2257 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2258 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2259 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2260 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2261 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2262 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2263 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2264 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2265 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2266 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2267 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2268 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2269 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2270 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2271 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2272 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2273 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2274 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2275 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2276 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2277 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2278 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2279 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2280 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2281 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2282 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2283 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2284 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2285 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2286 #define WREG32_P(reg, val, mask) \
2288 uint32_t tmp_ = RREG32(reg); \
2290 tmp_ |= ((val) & ~(mask)); \
2291 WREG32(reg, tmp_); \
2293 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2294 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2295 #define WREG32_PLL_P(reg, val, mask) \
2297 uint32_t tmp_ = RREG32_PLL(reg); \
2299 tmp_ |= ((val) & ~(mask)); \
2300 WREG32_PLL(reg, tmp_); \
2302 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2303 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2304 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2306 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2307 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2310 * Indirect registers accessor
2312 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2314 unsigned long flags;
2317 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2318 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2319 r = RREG32(RADEON_PCIE_DATA);
2320 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2324 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2326 unsigned long flags;
2328 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2329 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2330 WREG32(RADEON_PCIE_DATA, (v));
2331 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2334 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2336 unsigned long flags;
2339 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2340 WREG32(TN_SMC_IND_INDEX_0, (reg));
2341 r = RREG32(TN_SMC_IND_DATA_0);
2342 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2346 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2348 unsigned long flags;
2350 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2351 WREG32(TN_SMC_IND_INDEX_0, (reg));
2352 WREG32(TN_SMC_IND_DATA_0, (v));
2353 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2356 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2358 unsigned long flags;
2361 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2362 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2363 r = RREG32(R600_RCU_DATA);
2364 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2368 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2370 unsigned long flags;
2372 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2373 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2374 WREG32(R600_RCU_DATA, (v));
2375 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2378 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2380 unsigned long flags;
2383 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2384 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2385 r = RREG32(EVERGREEN_CG_IND_DATA);
2386 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2390 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2392 unsigned long flags;
2394 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2395 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2396 WREG32(EVERGREEN_CG_IND_DATA, (v));
2397 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2400 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2402 unsigned long flags;
2405 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2406 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2407 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2408 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2412 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2414 unsigned long flags;
2416 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2417 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2418 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2419 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2422 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2424 unsigned long flags;
2427 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2428 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2429 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2430 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2434 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2436 unsigned long flags;
2438 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2439 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2440 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2441 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2444 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2446 unsigned long flags;
2449 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2450 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2451 r = RREG32(R600_UVD_CTX_DATA);
2452 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2456 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2458 unsigned long flags;
2460 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2461 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2462 WREG32(R600_UVD_CTX_DATA, (v));
2463 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2467 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2469 unsigned long flags;
2472 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2473 WREG32(CIK_DIDT_IND_INDEX, (reg));
2474 r = RREG32(CIK_DIDT_IND_DATA);
2475 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2479 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2481 unsigned long flags;
2483 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2484 WREG32(CIK_DIDT_IND_INDEX, (reg));
2485 WREG32(CIK_DIDT_IND_DATA, (v));
2486 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2489 void r100_pll_errata_after_index(struct radeon_device *rdev);
2495 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2496 (rdev->pdev->device == 0x5969))
2497 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2498 (rdev->family == CHIP_RV200) || \
2499 (rdev->family == CHIP_RS100) || \
2500 (rdev->family == CHIP_RS200) || \
2501 (rdev->family == CHIP_RV250) || \
2502 (rdev->family == CHIP_RV280) || \
2503 (rdev->family == CHIP_RS300))
2504 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2505 (rdev->family == CHIP_RV350) || \
2506 (rdev->family == CHIP_R350) || \
2507 (rdev->family == CHIP_RV380) || \
2508 (rdev->family == CHIP_R420) || \
2509 (rdev->family == CHIP_R423) || \
2510 (rdev->family == CHIP_RV410) || \
2511 (rdev->family == CHIP_RS400) || \
2512 (rdev->family == CHIP_RS480))
2513 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2514 (rdev->ddev->pdev->device == 0x9443) || \
2515 (rdev->ddev->pdev->device == 0x944B) || \
2516 (rdev->ddev->pdev->device == 0x9506) || \
2517 (rdev->ddev->pdev->device == 0x9509) || \
2518 (rdev->ddev->pdev->device == 0x950F) || \
2519 (rdev->ddev->pdev->device == 0x689C) || \
2520 (rdev->ddev->pdev->device == 0x689D))
2521 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2522 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2523 (rdev->family == CHIP_RS690) || \
2524 (rdev->family == CHIP_RS740) || \
2525 (rdev->family >= CHIP_R600))
2526 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2527 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2528 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2529 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2530 (rdev->flags & RADEON_IS_IGP))
2531 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2532 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2533 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2534 (rdev->flags & RADEON_IS_IGP))
2535 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2536 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2537 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2539 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2540 (rdev->ddev->pdev->device == 0x6850) || \
2541 (rdev->ddev->pdev->device == 0x6858) || \
2542 (rdev->ddev->pdev->device == 0x6859) || \
2543 (rdev->ddev->pdev->device == 0x6840) || \
2544 (rdev->ddev->pdev->device == 0x6841) || \
2545 (rdev->ddev->pdev->device == 0x6842) || \
2546 (rdev->ddev->pdev->device == 0x6843))
2551 #define RBIOS8(i) (rdev->bios[i])
2552 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2553 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2555 int radeon_combios_init(struct radeon_device *rdev);
2556 void radeon_combios_fini(struct radeon_device *rdev);
2557 int radeon_atombios_init(struct radeon_device *rdev);
2558 void radeon_atombios_fini(struct radeon_device *rdev);
2564 #if DRM_DEBUG_CODE == 0
2565 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2567 ring->ring[ring->wptr++] = v;
2568 ring->wptr &= ring->ptr_mask;
2570 ring->ring_free_dw--;
2573 /* With debugging this is just too big to inline */
2574 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2580 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2581 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2582 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2583 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2584 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2585 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2586 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2587 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2588 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2589 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2590 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2591 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2592 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2593 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2594 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2595 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2596 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2597 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2598 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2599 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2600 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2601 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2602 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2603 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2604 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2605 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2606 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2607 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2608 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2609 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2610 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2611 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2612 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2613 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2614 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2615 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2616 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2617 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2618 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2619 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2620 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2621 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2622 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2623 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2624 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2625 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2626 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2627 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2628 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2629 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2630 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2631 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2632 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2633 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2634 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2635 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2636 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2637 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2638 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2639 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2640 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2641 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2642 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2643 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2644 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2645 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2646 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2647 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2648 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2649 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2650 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2651 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2652 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2653 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2654 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2655 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2656 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2657 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2658 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2659 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2660 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2661 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2662 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2664 /* Common functions */
2666 extern int radeon_gpu_reset(struct radeon_device *rdev);
2667 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2668 extern void radeon_agp_disable(struct radeon_device *rdev);
2669 extern int radeon_modeset_init(struct radeon_device *rdev);
2670 extern void radeon_modeset_fini(struct radeon_device *rdev);
2671 extern bool radeon_card_posted(struct radeon_device *rdev);
2672 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2673 extern void radeon_update_display_priority(struct radeon_device *rdev);
2674 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2675 extern void radeon_scratch_init(struct radeon_device *rdev);
2676 extern void radeon_wb_fini(struct radeon_device *rdev);
2677 extern int radeon_wb_init(struct radeon_device *rdev);
2678 extern void radeon_wb_disable(struct radeon_device *rdev);
2679 extern void radeon_surface_init(struct radeon_device *rdev);
2680 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2681 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2682 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2683 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2684 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2685 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2686 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2687 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2688 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2689 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2690 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2691 const u32 *registers,
2692 const u32 array_size);
2697 int radeon_vm_manager_init(struct radeon_device *rdev);
2698 void radeon_vm_manager_fini(struct radeon_device *rdev);
2699 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2700 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2701 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2702 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2703 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2704 struct radeon_vm *vm, int ring);
2705 void radeon_vm_fence(struct radeon_device *rdev,
2706 struct radeon_vm *vm,
2707 struct radeon_fence *fence);
2708 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2709 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2710 struct radeon_vm *vm,
2711 struct radeon_bo *bo,
2712 struct ttm_mem_reg *mem);
2713 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2714 struct radeon_bo *bo);
2715 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2716 struct radeon_bo *bo);
2717 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2718 struct radeon_vm *vm,
2719 struct radeon_bo *bo);
2720 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2721 struct radeon_bo_va *bo_va,
2724 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2725 struct radeon_bo_va *bo_va);
2728 void r600_audio_update_hdmi(struct work_struct *work);
2729 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2730 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2733 * R600 vram scratch functions
2735 int r600_vram_scratch_init(struct radeon_device *rdev);
2736 void r600_vram_scratch_fini(struct radeon_device *rdev);
2739 * r600 cs checking helper
2741 unsigned r600_mip_minify(unsigned size, unsigned level);
2742 bool r600_fmt_is_valid_color(u32 format);
2743 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2744 int r600_fmt_get_blocksize(u32 format);
2745 int r600_fmt_get_nblocksx(u32 format, u32 w);
2746 int r600_fmt_get_nblocksy(u32 format, u32 h);
2749 * r600 functions used by radeon_encoder.c
2751 struct radeon_hdmi_acr {
2765 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2767 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2768 u32 tiling_pipe_num,
2770 u32 total_max_rb_num,
2771 u32 enabled_rb_mask);
2774 * evergreen functions used by radeon_encoder.c
2777 extern int ni_init_microcode(struct radeon_device *rdev);
2778 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2781 #if defined(CONFIG_ACPI)
2782 extern int radeon_acpi_init(struct radeon_device *rdev);
2783 extern void radeon_acpi_fini(struct radeon_device *rdev);
2784 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2785 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2786 u8 perf_req, bool advertise);
2787 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2789 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2790 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2793 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2794 struct radeon_cs_packet *pkt,
2796 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2797 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2798 struct radeon_cs_packet *pkt);
2799 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2800 struct radeon_cs_reloc **cs_reloc,
2802 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2803 uint32_t *vline_start_end,
2804 uint32_t *vline_status);
2806 #include "radeon_object.h"