drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "radeon_audio.h"
  31 #include "atom.h"
  32 #include <linux/backlight.h>
  33
  34 extern int atom_debug;
  35
  36 static u8
  37 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  38 {
  39         u8 backlight_level;
  40         u32 bios_2_scratch;
  41
  42         if (rdev->family >= CHIP_R600)
  43                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  44         else
  45                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  46
  47         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  48                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  49
  50         return backlight_level;
  51 }
  52
  53 static void
  54 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  55                                        u8 backlight_level)
  56 {
  57         u32 bios_2_scratch;
  58
  59         if (rdev->family >= CHIP_R600)
  60                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  61         else
  62                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  63
  64         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  65         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  66                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  67
  68         if (rdev->family >= CHIP_R600)
  69                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  70         else
  71                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  72 }
  73
  74 u8
  75 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  76 {
  77         struct drm_device *dev = radeon_encoder->base.dev;
  78         struct radeon_device *rdev = dev->dev_private;
  79
  80         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  81                 return 0;
  82
  83         return radeon_atom_get_backlight_level_from_reg(rdev);
  84 }
  85
  86 void
  87 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  88 {
  89         struct drm_encoder *encoder = &radeon_encoder->base;
  90         struct drm_device *dev = radeon_encoder->base.dev;
  91         struct radeon_device *rdev = dev->dev_private;
  92         struct radeon_encoder_atom_dig *dig;
  93         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  94         int index;
  95
  96         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  97                 return;
  98
  99         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
 100             radeon_encoder->enc_priv) {
 101                 dig = radeon_encoder->enc_priv;
 102                 dig->backlight_level = level;
 103                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 104
 105                 switch (radeon_encoder->encoder_id) {
 106                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 107                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 108                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 109                         if (dig->backlight_level == 0) {
 110                                 args.ucAction = ATOM_LCD_BLOFF;
 111                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 112                         } else {
 113                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 114                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 115                                 args.ucAction = ATOM_LCD_BLON;
 116                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 117                         }
 118                         break;
 119                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 120                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 121                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 122                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 123                         if (dig->backlight_level == 0)
 124                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 125                         else {
 126                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 127                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 128                         }
 129                         break;
 130                 default:
 131                         break;
 132                 }
 133         }
 134 }
 135
 136 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 137
 138 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 139 {
 140         u8 level;
 141
 142         /* Convert brightness to hardware level */
 143         if (bd->props.brightness < 0)
 144                 level = 0;
 145         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 146                 level = RADEON_MAX_BL_LEVEL;
 147         else
 148                 level = bd->props.brightness;
 149
 150         return level;
 151 }
 152
 153 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 154 {
 155         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 156         struct radeon_encoder *radeon_encoder = pdata->encoder;
 157
 158         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 159
 160         return 0;
 161 }
 162
 163 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 164 {
 165         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 166         struct radeon_encoder *radeon_encoder = pdata->encoder;
 167         struct drm_device *dev = radeon_encoder->base.dev;
 168         struct radeon_device *rdev = dev->dev_private;
 169
 170         return radeon_atom_get_backlight_level_from_reg(rdev);
 171 }
 172
 173 static const struct backlight_ops radeon_atom_backlight_ops = {
 174         .get_brightness = radeon_atom_backlight_get_brightness,
 175         .update_status  = radeon_atom_backlight_update_status,
 176 };
 177
 178 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 179                                 struct drm_connector *drm_connector)
 180 {
 181         struct drm_device *dev = radeon_encoder->base.dev;
 182         struct radeon_device *rdev = dev->dev_private;
 183         struct backlight_device *bd;
 184         struct backlight_properties props;
 185         struct radeon_backlight_privdata *pdata;
 186         struct radeon_encoder_atom_dig *dig;
 187         char bl_name[16];
 188
 189         /* Mac laptops with multiple GPUs use the gmux driver for backlight
 190          * so don't register a backlight device
 191          */
 192         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 193             (rdev->pdev->device == 0x6741))
 194                 return;
 195
 196         if (!radeon_encoder->enc_priv)
 197                 return;
 198
 199         if (!rdev->is_atom_bios)
 200                 return;
 201
 202         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 203                 return;
 204
 205         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 206         if (!pdata) {
 207                 DRM_ERROR("Memory allocation failed\n");
 208                 goto error;
 209         }
 210
 211         memset(&props, 0, sizeof(props));
 212         props.max_brightness = RADEON_MAX_BL_LEVEL;
 213         props.type = BACKLIGHT_RAW;
 214         snprintf(bl_name, sizeof(bl_name),
 215                  "radeon_bl%d", dev->primary->index);
 216         bd = backlight_device_register(bl_name, drm_connector->kdev,
 217                                        pdata, &radeon_atom_backlight_ops, &props);
 218         if (IS_ERR(bd)) {
 219                 DRM_ERROR("Backlight registration failed\n");
 220                 goto error;
 221         }
 222
 223         pdata->encoder = radeon_encoder;
 224
 225         dig = radeon_encoder->enc_priv;
 226         dig->bl_dev = bd;
 227
 228         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 229         /* Set a reasonable default here if the level is 0 otherwise
 230          * fbdev will attempt to turn the backlight on after console
 231          * unblanking and it will try and restore 0 which turns the backlight
 232          * off again.
 233          */
 234         if (bd->props.brightness == 0)
 235                 bd->props.brightness = RADEON_MAX_BL_LEVEL;
 236         bd->props.power = FB_BLANK_UNBLANK;
 237         backlight_update_status(bd);
 238
 239         DRM_INFO("radeon atom DIG backlight initialized\n");
 240
 241         return;
 242
 243 error:
 244         kfree(pdata);
 245         return;
 246 }
 247
 248 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 249 {
 250         struct drm_device *dev = radeon_encoder->base.dev;
 251         struct radeon_device *rdev = dev->dev_private;
 252         struct backlight_device *bd = NULL;
 253         struct radeon_encoder_atom_dig *dig;
 254
 255         if (!radeon_encoder->enc_priv)
 256                 return;
 257
 258         if (!rdev->is_atom_bios)
 259                 return;
 260
 261         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 262                 return;
 263
 264         dig = radeon_encoder->enc_priv;
 265         bd = dig->bl_dev;
 266         dig->bl_dev = NULL;
 267
 268         if (bd) {
 269                 struct radeon_legacy_backlight_privdata *pdata;
 270
 271                 pdata = bl_get_data(bd);
 272                 backlight_device_unregister(bd);
 273                 kfree(pdata);
 274
 275                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 276         }
 277 }
 278
 279 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 280
 281 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 282 {
 283 }
 284
 285 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 286 {
 287 }
 288
 289 #endif
 290
 291 /* evil but including atombios.h is much worse */
 292 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 293                                 struct drm_display_mode *mode);
 294
 295 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 296                                    const struct drm_display_mode *mode,
 297                                    struct drm_display_mode *adjusted_mode)
 298 {
 299         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 300         struct drm_device *dev = encoder->dev;
 301         struct radeon_device *rdev = dev->dev_private;
 302
 303         /* set the active encoder to connector routing */
 304         radeon_encoder_set_active_device(encoder);
 305         drm_mode_set_crtcinfo(adjusted_mode, 0);
 306
 307         /* hw bug */
 308         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 309             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 310                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 311
 312         /* get the native mode for scaling */
 313         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 314                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 315         } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 316                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 317                 if (tv_dac) {
 318                         if (tv_dac->tv_std == TV_STD_NTSC ||
 319                             tv_dac->tv_std == TV_STD_NTSC_J ||
 320                             tv_dac->tv_std == TV_STD_PAL_M)
 321                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 322                         else
 323                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 324                 }
 325         } else if (radeon_encoder->rmx_type != RMX_OFF) {
 326                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 327         }
 328
 329         if (ASIC_IS_DCE3(rdev) &&
 330             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 331              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 332                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 333                 radeon_dp_set_link_config(connector, adjusted_mode);
 334         }
 335
 336         return true;
 337 }
 338
 339 static void
 340 atombios_dac_setup(struct drm_encoder *encoder, int action)
 341 {
 342         struct drm_device *dev = encoder->dev;
 343         struct radeon_device *rdev = dev->dev_private;
 344         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 345         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 346         int index = 0;
 347         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 348
 349         memset(&args, 0, sizeof(args));
 350
 351         switch (radeon_encoder->encoder_id) {
 352         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 353         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 354                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 355                 break;
 356         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 357         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 358                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 359                 break;
 360         }
 361
 362         args.ucAction = action;
 363
 364         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 365                 args.ucDacStandard = ATOM_DAC1_PS2;
 366         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 367                 args.ucDacStandard = ATOM_DAC1_CV;
 368         else {
 369                 switch (dac_info->tv_std) {
 370                 case TV_STD_PAL:
 371                 case TV_STD_PAL_M:
 372                 case TV_STD_SCART_PAL:
 373                 case TV_STD_SECAM:
 374                 case TV_STD_PAL_CN:
 375                         args.ucDacStandard = ATOM_DAC1_PAL;
 376                         break;
 377                 case TV_STD_NTSC:
 378                 case TV_STD_NTSC_J:
 379                 case TV_STD_PAL_60:
 380                 default:
 381                         args.ucDacStandard = ATOM_DAC1_NTSC;
 382                         break;
 383                 }
 384         }
 385         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 386
 387         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 388
 389 }
 390
 391 static void
 392 atombios_tv_setup(struct drm_encoder *encoder, int action)
 393 {
 394         struct drm_device *dev = encoder->dev;
 395         struct radeon_device *rdev = dev->dev_private;
 396         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 397         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 398         int index = 0;
 399         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 400
 401         memset(&args, 0, sizeof(args));
 402
 403         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 404
 405         args.sTVEncoder.ucAction = action;
 406
 407         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 408                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 409         else {
 410                 switch (dac_info->tv_std) {
 411                 case TV_STD_NTSC:
 412                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 413                         break;
 414                 case TV_STD_PAL:
 415                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 416                         break;
 417                 case TV_STD_PAL_M:
 418                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 419                         break;
 420                 case TV_STD_PAL_60:
 421                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 422                         break;
 423                 case TV_STD_NTSC_J:
 424                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 425                         break;
 426                 case TV_STD_SCART_PAL:
 427                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 428                         break;
 429                 case TV_STD_SECAM:
 430                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 431                         break;
 432                 case TV_STD_PAL_CN:
 433                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 434                         break;
 435                 default:
 436                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 437                         break;
 438                 }
 439         }
 440
 441         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 442
 443         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 444
 445 }
 446
 447 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 448 {
 449         int bpc = 8;
 450
 451         if (encoder->crtc) {
 452                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 453                 bpc = radeon_crtc->bpc;
 454         }
 455
 456         switch (bpc) {
 457         case 0:
 458                 return PANEL_BPC_UNDEFINE;
 459         case 6:
 460                 return PANEL_6BIT_PER_COLOR;
 461         case 8:
 462         default:
 463                 return PANEL_8BIT_PER_COLOR;
 464         case 10:
 465                 return PANEL_10BIT_PER_COLOR;
 466         case 12:
 467                 return PANEL_12BIT_PER_COLOR;
 468         case 16:
 469                 return PANEL_16BIT_PER_COLOR;
 470         }
 471 }
 472
 473 union dvo_encoder_control {
 474         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 475         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 476         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 477         DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 478 };
 479
 480 void
 481 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 482 {
 483         struct drm_device *dev = encoder->dev;
 484         struct radeon_device *rdev = dev->dev_private;
 485         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 486         union dvo_encoder_control args;
 487         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 488         uint8_t frev, crev;
 489
 490         memset(&args, 0, sizeof(args));
 491
 492         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 493                 return;
 494
 495         /* some R4xx chips have the wrong frev */
 496         if (rdev->family <= CHIP_RV410)
 497                 frev = 1;
 498
 499         switch (frev) {
 500         case 1:
 501                 switch (crev) {
 502                 case 1:
 503                         /* R4xx, R5xx */
 504                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 505
 506                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 507                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 508
 509                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 510                         break;
 511                 case 2:
 512                         /* RS600/690/740 */
 513                         args.dvo.sDVOEncoder.ucAction = action;
 514                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 515                         /* DFP1, CRT1, TV1 depending on the type of port */
 516                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 517
 518                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 519                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 520                         break;
 521                 case 3:
 522                         /* R6xx */
 523                         args.dvo_v3.ucAction = action;
 524                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 525                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 526                         break;
 527                 case 4:
 528                         /* DCE8 */
 529                         args.dvo_v4.ucAction = action;
 530                         args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 531                         args.dvo_v4.ucDVOConfig = 0; /* XXX */
 532                         args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 533                         break;
 534                 default:
 535                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 536                         break;
 537                 }
 538                 break;
 539         default:
 540                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 541                 break;
 542         }
 543
 544         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 545 }
 546
 547 union lvds_encoder_control {
 548         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 549         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 550 };
 551
 552 void
 553 atombios_digital_setup(struct drm_encoder *encoder, int action)
 554 {
 555         struct drm_device *dev = encoder->dev;
 556         struct radeon_device *rdev = dev->dev_private;
 557         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 558         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 559         union lvds_encoder_control args;
 560         int index = 0;
 561         int hdmi_detected = 0;
 562         uint8_t frev, crev;
 563
 564         if (!dig)
 565                 return;
 566
 567         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 568                 hdmi_detected = 1;
 569
 570         memset(&args, 0, sizeof(args));
 571
 572         switch (radeon_encoder->encoder_id) {
 573         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 574                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 575                 break;
 576         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 577         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 578                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 579                 break;
 580         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 581                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 582                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 583                 else
 584                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 585                 break;
 586         }
 587
 588         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 589                 return;
 590
 591         switch (frev) {
 592         case 1:
 593         case 2:
 594                 switch (crev) {
 595                 case 1:
 596                         args.v1.ucMisc = 0;
 597                         args.v1.ucAction = action;
 598                         if (hdmi_detected)
 599                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 600                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 601                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 602                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 603                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 604                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 605                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 606                         } else {
 607                                 if (dig->linkb)
 608                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 609                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 610                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 611                                 /*if (pScrn->rgbBits == 8) */
 612                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 613                         }
 614                         break;
 615                 case 2:
 616                 case 3:
 617                         args.v2.ucMisc = 0;
 618                         args.v2.ucAction = action;
 619                         if (crev == 3) {
 620                                 if (dig->coherent_mode)
 621                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 622                         }
 623                         if (hdmi_detected)
 624                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 625                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 626                         args.v2.ucTruncate = 0;
 627                         args.v2.ucSpatial = 0;
 628                         args.v2.ucTemporal = 0;
 629                         args.v2.ucFRC = 0;
 630                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 631                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 632                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 633                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 634                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 635                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 636                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 637                                 }
 638                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 639                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 640                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 641                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 642                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 643                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 644                                 }
 645                         } else {
 646                                 if (dig->linkb)
 647                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 648                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 649                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 650                         }
 651                         break;
 652                 default:
 653                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 654                         break;
 655                 }
 656                 break;
 657         default:
 658                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 659                 break;
 660         }
 661
 662         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 663 }
 664
 665 int
 666 atombios_get_encoder_mode(struct drm_encoder *encoder)
 667 {
 668         struct drm_device *dev = encoder->dev;
 669         struct radeon_device *rdev = dev->dev_private;
 670         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 671         struct drm_connector *connector;
 672         struct radeon_connector *radeon_connector;
 673         struct radeon_connector_atom_dig *dig_connector;
 674
 675         /* dp bridges are always DP */
 676         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 677                 return ATOM_ENCODER_MODE_DP;
 678
 679         /* DVO is always DVO */
 680         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 681             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 682                 return ATOM_ENCODER_MODE_DVO;
 683
 684         connector = radeon_get_connector_for_encoder(encoder);
 685         /* if we don't have an active device yet, just use one of
 686          * the connectors tied to the encoder.
 687          */
 688         if (!connector)
 689                 connector = radeon_get_connector_for_encoder_init(encoder);
 690         radeon_connector = to_radeon_connector(connector);
 691
 692         switch (connector->connector_type) {
 693         case DRM_MODE_CONNECTOR_DVII:
 694         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 695                 if (radeon_audio != 0) {
 696                         if (radeon_connector->use_digital &&
 697                             (radeon_connector->audio == RADEON_AUDIO_ENABLE))
 698                                 return ATOM_ENCODER_MODE_HDMI;
 699                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 700                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 701                                 return ATOM_ENCODER_MODE_HDMI;
 702                         else if (radeon_connector->use_digital)
 703                                 return ATOM_ENCODER_MODE_DVI;
 704                         else
 705                                 return ATOM_ENCODER_MODE_CRT;
 706                 } else if (radeon_connector->use_digital) {
 707                         return ATOM_ENCODER_MODE_DVI;
 708                 } else {
 709                         return ATOM_ENCODER_MODE_CRT;
 710                 }
 711                 break;
 712         case DRM_MODE_CONNECTOR_DVID:
 713         case DRM_MODE_CONNECTOR_HDMIA:
 714         default:
 715                 if (radeon_audio != 0) {
 716                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 717                                 return ATOM_ENCODER_MODE_HDMI;
 718                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 719                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 720                                 return ATOM_ENCODER_MODE_HDMI;
 721                         else
 722                                 return ATOM_ENCODER_MODE_DVI;
 723                 } else {
 724                         return ATOM_ENCODER_MODE_DVI;
 725                 }
 726                 break;
 727         case DRM_MODE_CONNECTOR_LVDS:
 728                 return ATOM_ENCODER_MODE_LVDS;
 729                 break;
 730         case DRM_MODE_CONNECTOR_DisplayPort:
 731                 dig_connector = radeon_connector->con_priv;
 732                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 733                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 734                         if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 735                                 return ATOM_ENCODER_MODE_DP_AUDIO;
 736                         return ATOM_ENCODER_MODE_DP;
 737                 } else if (radeon_audio != 0) {
 738                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 739                                 return ATOM_ENCODER_MODE_HDMI;
 740                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 741                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 742                                 return ATOM_ENCODER_MODE_HDMI;
 743                         else
 744                                 return ATOM_ENCODER_MODE_DVI;
 745                 } else {
 746                         return ATOM_ENCODER_MODE_DVI;
 747                 }
 748                 break;
 749         case DRM_MODE_CONNECTOR_eDP:
 750                 if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 751                         return ATOM_ENCODER_MODE_DP_AUDIO;
 752                 return ATOM_ENCODER_MODE_DP;
 753         case DRM_MODE_CONNECTOR_DVIA:
 754         case DRM_MODE_CONNECTOR_VGA:
 755                 return ATOM_ENCODER_MODE_CRT;
 756                 break;
 757         case DRM_MODE_CONNECTOR_Composite:
 758         case DRM_MODE_CONNECTOR_SVIDEO:
 759         case DRM_MODE_CONNECTOR_9PinDIN:
 760                 /* fix me */
 761                 return ATOM_ENCODER_MODE_TV;
 762                 /*return ATOM_ENCODER_MODE_CV;*/
 763                 break;
 764         }
 765 }
 766
 767 /*
 768  * DIG Encoder/Transmitter Setup
 769  *
 770  * DCE 3.0/3.1
 771  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 772  * Supports up to 3 digital outputs
 773  * - 2 DIG encoder blocks.
 774  * DIG1 can drive UNIPHY link A or link B
 775  * DIG2 can drive UNIPHY link B or LVTMA
 776  *
 777  * DCE 3.2
 778  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 779  * Supports up to 5 digital outputs
 780  * - 2 DIG encoder blocks.
 781  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 782  *
 783  * DCE 4.0/5.0/6.0
 784  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 785  * Supports up to 6 digital outputs
 786  * - 6 DIG encoder blocks.
 787  * - DIG to PHY mapping is hardcoded
 788  * DIG1 drives UNIPHY0 link A, A+B
 789  * DIG2 drives UNIPHY0 link B
 790  * DIG3 drives UNIPHY1 link A, A+B
 791  * DIG4 drives UNIPHY1 link B
 792  * DIG5 drives UNIPHY2 link A, A+B
 793  * DIG6 drives UNIPHY2 link B
 794  *
 795  * DCE 4.1
 796  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 797  * Supports up to 6 digital outputs
 798  * - 2 DIG encoder blocks.
 799  * llano
 800  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 801  * ontario
 802  * DIG1 drives UNIPHY0/1/2 link A
 803  * DIG2 drives UNIPHY0/1/2 link B
 804  *
 805  * Routing
 806  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 807  * Examples:
 808  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 809  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 810  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 811  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 812  */
 813
 814 union dig_encoder_control {
 815         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 816         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 817         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 818         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 819 };
 820
 821 void
 822 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 823 {
 824         struct drm_device *dev = encoder->dev;
 825         struct radeon_device *rdev = dev->dev_private;
 826         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 827         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 828         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 829         union dig_encoder_control args;
 830         int index = 0;
 831         uint8_t frev, crev;
 832         int dp_clock = 0;
 833         int dp_lane_count = 0;
 834         int hpd_id = RADEON_HPD_NONE;
 835
 836         if (connector) {
 837                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 838                 struct radeon_connector_atom_dig *dig_connector =
 839                         radeon_connector->con_priv;
 840
 841                 dp_clock = dig_connector->dp_clock;
 842                 dp_lane_count = dig_connector->dp_lane_count;
 843                 hpd_id = radeon_connector->hpd.hpd;
 844         }
 845
 846         /* no dig encoder assigned */
 847         if (dig->dig_encoder == -1)
 848                 return;
 849
 850         memset(&args, 0, sizeof(args));
 851
 852         if (ASIC_IS_DCE4(rdev))
 853                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 854         else {
 855                 if (dig->dig_encoder)
 856                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 857                 else
 858                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 859         }
 860
 861         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 862                 return;
 863
 864         switch (frev) {
 865         case 1:
 866                 switch (crev) {
 867                 case 1:
 868                         args.v1.ucAction = action;
 869                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 870                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 871                                 args.v3.ucPanelMode = panel_mode;
 872                         else
 873                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 874
 875                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 876                                 args.v1.ucLaneNum = dp_lane_count;
 877                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 878                                 args.v1.ucLaneNum = 8;
 879                         else
 880                                 args.v1.ucLaneNum = 4;
 881
 882                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 883                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 884                         switch (radeon_encoder->encoder_id) {
 885                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 886                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 887                                 break;
 888                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 889                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 890                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 891                                 break;
 892                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 893                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 894                                 break;
 895                         }
 896                         if (dig->linkb)
 897                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 898                         else
 899                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 900                         break;
 901                 case 2:
 902                 case 3:
 903                         args.v3.ucAction = action;
 904                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 905                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 906                                 args.v3.ucPanelMode = panel_mode;
 907                         else
 908                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 909
 910                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 911                                 args.v3.ucLaneNum = dp_lane_count;
 912                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 913                                 args.v3.ucLaneNum = 8;
 914                         else
 915                                 args.v3.ucLaneNum = 4;
 916
 917                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 918                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 919                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
 920                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 921                         break;
 922                 case 4:
 923                         args.v4.ucAction = action;
 924                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 925                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 926                                 args.v4.ucPanelMode = panel_mode;
 927                         else
 928                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 929
 930                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 931                                 args.v4.ucLaneNum = dp_lane_count;
 932                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 933                                 args.v4.ucLaneNum = 8;
 934                         else
 935                                 args.v4.ucLaneNum = 4;
 936
 937                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 938                                 if (dp_clock == 540000)
 939                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 940                                 else if (dp_clock == 324000)
 941                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
 942                                 else if (dp_clock == 270000)
 943                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 944                                 else
 945                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
 946                         }
 947                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
 948                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 949                         if (hpd_id == RADEON_HPD_NONE)
 950                                 args.v4.ucHPD_ID = 0;
 951                         else
 952                                 args.v4.ucHPD_ID = hpd_id + 1;
 953                         break;
 954                 default:
 955                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 956                         break;
 957                 }
 958                 break;
 959         default:
 960                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 961                 break;
 962         }
 963
 964         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 965
 966 }
 967
 968 union dig_transmitter_control {
 969         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 970         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 971         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 972         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 973         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
 974 };
 975
 976 void
 977 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 978 {
 979         struct drm_device *dev = encoder->dev;
 980         struct radeon_device *rdev = dev->dev_private;
 981         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 982         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 983         struct drm_connector *connector;
 984         union dig_transmitter_control args;
 985         int index = 0;
 986         uint8_t frev, crev;
 987         bool is_dp = false;
 988         int pll_id = 0;
 989         int dp_clock = 0;
 990         int dp_lane_count = 0;
 991         int connector_object_id = 0;
 992         int igp_lane_info = 0;
 993         int dig_encoder = dig->dig_encoder;
 994         int hpd_id = RADEON_HPD_NONE;
 995
 996         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 997                 connector = radeon_get_connector_for_encoder_init(encoder);
 998                 /* just needed to avoid bailing in the encoder check.  the encoder
 999                  * isn't used for init
1000                  */
1001                 dig_encoder = 0;
1002         } else
1003                 connector = radeon_get_connector_for_encoder(encoder);
1004
1005         if (connector) {
1006                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1007                 struct radeon_connector_atom_dig *dig_connector =
1008                         radeon_connector->con_priv;
1009
1010                 hpd_id = radeon_connector->hpd.hpd;
1011                 dp_clock = dig_connector->dp_clock;
1012                 dp_lane_count = dig_connector->dp_lane_count;
1013                 connector_object_id =
1014                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1015                 igp_lane_info = dig_connector->igp_lane_info;
1016         }
1017
1018         if (encoder->crtc) {
1019                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1020                 pll_id = radeon_crtc->pll_id;
1021         }
1022
1023         /* no dig encoder assigned */
1024         if (dig_encoder == -1)
1025                 return;
1026
1027         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1028                 is_dp = true;
1029
1030         memset(&args, 0, sizeof(args));
1031
1032         switch (radeon_encoder->encoder_id) {
1033         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1034                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1035                 break;
1036         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1037         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1038         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1039         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1040                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1041                 break;
1042         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1043                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1044                 break;
1045         }
1046
1047         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1048                 return;
1049
1050         switch (frev) {
1051         case 1:
1052                 switch (crev) {
1053                 case 1:
1054                         args.v1.ucAction = action;
1055                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1056                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1057                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1058                                 args.v1.asMode.ucLaneSel = lane_num;
1059                                 args.v1.asMode.ucLaneSet = lane_set;
1060                         } else {
1061                                 if (is_dp)
1062                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1063                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1064                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1065                                 else
1066                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1067                         }
1068
1069                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1070
1071                         if (dig_encoder)
1072                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1073                         else
1074                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1075
1076                         if ((rdev->flags & RADEON_IS_IGP) &&
1077                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1078                                 if (is_dp ||
1079                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1080                                         if (igp_lane_info & 0x1)
1081                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1082                                         else if (igp_lane_info & 0x2)
1083                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1084                                         else if (igp_lane_info & 0x4)
1085                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1086                                         else if (igp_lane_info & 0x8)
1087                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1088                                 } else {
1089                                         if (igp_lane_info & 0x3)
1090                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1091                                         else if (igp_lane_info & 0xc)
1092                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1093                                 }
1094                         }
1095
1096                         if (dig->linkb)
1097                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1098                         else
1099                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1100
1101                         if (is_dp)
1102                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1103                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1104                                 if (dig->coherent_mode)
1105                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1106                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1107                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1108                         }
1109                         break;
1110                 case 2:
1111                         args.v2.ucAction = action;
1112                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1113                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1114                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1115                                 args.v2.asMode.ucLaneSel = lane_num;
1116                                 args.v2.asMode.ucLaneSet = lane_set;
1117                         } else {
1118                                 if (is_dp)
1119                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1120                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1121                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1122                                 else
1123                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1124                         }
1125
1126                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1127                         if (dig->linkb)
1128                                 args.v2.acConfig.ucLinkSel = 1;
1129
1130                         switch (radeon_encoder->encoder_id) {
1131                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1132                                 args.v2.acConfig.ucTransmitterSel = 0;
1133                                 break;
1134                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1135                                 args.v2.acConfig.ucTransmitterSel = 1;
1136                                 break;
1137                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1138                                 args.v2.acConfig.ucTransmitterSel = 2;
1139                                 break;
1140                         }
1141
1142                         if (is_dp) {
1143                                 args.v2.acConfig.fCoherentMode = 1;
1144                                 args.v2.acConfig.fDPConnector = 1;
1145                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1146                                 if (dig->coherent_mode)
1147                                         args.v2.acConfig.fCoherentMode = 1;
1148                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1149                                         args.v2.acConfig.fDualLinkConnector = 1;
1150                         }
1151                         break;
1152                 case 3:
1153                         args.v3.ucAction = action;
1154                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1155                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1156                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1157                                 args.v3.asMode.ucLaneSel = lane_num;
1158                                 args.v3.asMode.ucLaneSet = lane_set;
1159                         } else {
1160                                 if (is_dp)
1161                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1162                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1163                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1164                                 else
1165                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1166                         }
1167
1168                         if (is_dp)
1169                                 args.v3.ucLaneNum = dp_lane_count;
1170                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1171                                 args.v3.ucLaneNum = 8;
1172                         else
1173                                 args.v3.ucLaneNum = 4;
1174
1175                         if (dig->linkb)
1176                                 args.v3.acConfig.ucLinkSel = 1;
1177                         if (dig_encoder & 1)
1178                                 args.v3.acConfig.ucEncoderSel = 1;
1179
1180                         /* Select the PLL for the PHY
1181                          * DP PHY should be clocked from external src if there is
1182                          * one.
1183                          */
1184                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1185                         if (is_dp && rdev->clock.dp_extclk)
1186                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1187                         else
1188                                 args.v3.acConfig.ucRefClkSource = pll_id;
1189
1190                         switch (radeon_encoder->encoder_id) {
1191                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1192                                 args.v3.acConfig.ucTransmitterSel = 0;
1193                                 break;
1194                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1195                                 args.v3.acConfig.ucTransmitterSel = 1;
1196                                 break;
1197                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1198                                 args.v3.acConfig.ucTransmitterSel = 2;
1199                                 break;
1200                         }
1201
1202                         if (is_dp)
1203                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1204                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1205                                 if (dig->coherent_mode)
1206                                         args.v3.acConfig.fCoherentMode = 1;
1207                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1208                                         args.v3.acConfig.fDualLinkConnector = 1;
1209                         }
1210                         break;
1211                 case 4:
1212                         args.v4.ucAction = action;
1213                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1214                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1215                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1216                                 args.v4.asMode.ucLaneSel = lane_num;
1217                                 args.v4.asMode.ucLaneSet = lane_set;
1218                         } else {
1219                                 if (is_dp)
1220                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1221                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1222                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1223                                 else
1224                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1225                         }
1226
1227                         if (is_dp)
1228                                 args.v4.ucLaneNum = dp_lane_count;
1229                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1230                                 args.v4.ucLaneNum = 8;
1231                         else
1232                                 args.v4.ucLaneNum = 4;
1233
1234                         if (dig->linkb)
1235                                 args.v4.acConfig.ucLinkSel = 1;
1236                         if (dig_encoder & 1)
1237                                 args.v4.acConfig.ucEncoderSel = 1;
1238
1239                         /* Select the PLL for the PHY
1240                          * DP PHY should be clocked from external src if there is
1241                          * one.
1242                          */
1243                         /* On DCE5 DCPLL usually generates the DP ref clock */
1244                         if (is_dp) {
1245                                 if (rdev->clock.dp_extclk)
1246                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1247                                 else
1248                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1249                         } else
1250                                 args.v4.acConfig.ucRefClkSource = pll_id;
1251
1252                         switch (radeon_encoder->encoder_id) {
1253                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1254                                 args.v4.acConfig.ucTransmitterSel = 0;
1255                                 break;
1256                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1257                                 args.v4.acConfig.ucTransmitterSel = 1;
1258                                 break;
1259                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1260                                 args.v4.acConfig.ucTransmitterSel = 2;
1261                                 break;
1262                         }
1263
1264                         if (is_dp)
1265                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1266                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1267                                 if (dig->coherent_mode)
1268                                         args.v4.acConfig.fCoherentMode = 1;
1269                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1270                                         args.v4.acConfig.fDualLinkConnector = 1;
1271                         }
1272                         break;
1273                 case 5:
1274                         args.v5.ucAction = action;
1275                         if (is_dp)
1276                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1277                         else
1278                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1279
1280                         switch (radeon_encoder->encoder_id) {
1281                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1282                                 if (dig->linkb)
1283                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1284                                 else
1285                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1286                                 break;
1287                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1288                                 if (dig->linkb)
1289                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1290                                 else
1291                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1292                                 break;
1293                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1294                                 if (dig->linkb)
1295                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1296                                 else
1297                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1298                                 break;
1299                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1300                                 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1301                                 break;
1302                         }
1303                         if (is_dp)
1304                                 args.v5.ucLaneNum = dp_lane_count;
1305                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1306                                 args.v5.ucLaneNum = 8;
1307                         else
1308                                 args.v5.ucLaneNum = 4;
1309                         args.v5.ucConnObjId = connector_object_id;
1310                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1311
1312                         if (is_dp && rdev->clock.dp_extclk)
1313                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1314                         else
1315                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1316
1317                         if (is_dp)
1318                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1319                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1320                                 if (dig->coherent_mode)
1321                                         args.v5.asConfig.ucCoherentMode = 1;
1322                         }
1323                         if (hpd_id == RADEON_HPD_NONE)
1324                                 args.v5.asConfig.ucHPDSel = 0;
1325                         else
1326                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1327                         args.v5.ucDigEncoderSel = 1 << dig_encoder;
1328                         args.v5.ucDPLaneSet = lane_set;
1329                         break;
1330                 default:
1331                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1332                         break;
1333                 }
1334                 break;
1335         default:
1336                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1337                 break;
1338         }
1339
1340         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1341 }
1342
1343 bool
1344 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1345 {
1346         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1347         struct drm_device *dev = radeon_connector->base.dev;
1348         struct radeon_device *rdev = dev->dev_private;
1349         union dig_transmitter_control args;
1350         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1351         uint8_t frev, crev;
1352
1353         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1354                 goto done;
1355
1356         if (!ASIC_IS_DCE4(rdev))
1357                 goto done;
1358
1359         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1360             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1361                 goto done;
1362
1363         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1364                 goto done;
1365
1366         memset(&args, 0, sizeof(args));
1367
1368         args.v1.ucAction = action;
1369
1370         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1371
1372         /* wait for the panel to power up */
1373         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1374                 int i;
1375
1376                 for (i = 0; i < 300; i++) {
1377                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1378                                 return true;
1379                         mdelay(1);
1380                 }
1381                 return false;
1382         }
1383 done:
1384         return true;
1385 }
1386
1387 union external_encoder_control {
1388         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1389         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1390 };
1391
1392 static void
1393 atombios_external_encoder_setup(struct drm_encoder *encoder,
1394                                 struct drm_encoder *ext_encoder,
1395                                 int action)
1396 {
1397         struct drm_device *dev = encoder->dev;
1398         struct radeon_device *rdev = dev->dev_private;
1399         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1400         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1401         union external_encoder_control args;
1402         struct drm_connector *connector;
1403         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1404         u8 frev, crev;
1405         int dp_clock = 0;
1406         int dp_lane_count = 0;
1407         int connector_object_id = 0;
1408         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1409
1410         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1411                 connector = radeon_get_connector_for_encoder_init(encoder);
1412         else
1413                 connector = radeon_get_connector_for_encoder(encoder);
1414
1415         if (connector) {
1416                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1417                 struct radeon_connector_atom_dig *dig_connector =
1418                         radeon_connector->con_priv;
1419
1420                 dp_clock = dig_connector->dp_clock;
1421                 dp_lane_count = dig_connector->dp_lane_count;
1422                 connector_object_id =
1423                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1424         }
1425
1426         memset(&args, 0, sizeof(args));
1427
1428         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1429                 return;
1430
1431         switch (frev) {
1432         case 1:
1433                 /* no params on frev 1 */
1434                 break;
1435         case 2:
1436                 switch (crev) {
1437                 case 1:
1438                 case 2:
1439                         args.v1.sDigEncoder.ucAction = action;
1440                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1441                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1442
1443                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1444                                 if (dp_clock == 270000)
1445                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1446                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1447                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1448                                 args.v1.sDigEncoder.ucLaneNum = 8;
1449                         else
1450                                 args.v1.sDigEncoder.ucLaneNum = 4;
1451                         break;
1452                 case 3:
1453                         args.v3.sExtEncoder.ucAction = action;
1454                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1455                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1456                         else
1457                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1458                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1459
1460                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1461                                 if (dp_clock == 270000)
1462                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1463                                 else if (dp_clock == 540000)
1464                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1465                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1466                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1467                                 args.v3.sExtEncoder.ucLaneNum = 8;
1468                         else
1469                                 args.v3.sExtEncoder.ucLaneNum = 4;
1470                         switch (ext_enum) {
1471                         case GRAPH_OBJECT_ENUM_ID1:
1472                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1473                                 break;
1474                         case GRAPH_OBJECT_ENUM_ID2:
1475                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1476                                 break;
1477                         case GRAPH_OBJECT_ENUM_ID3:
1478                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1479                                 break;
1480                         }
1481                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1482                         break;
1483                 default:
1484                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1485                         return;
1486                 }
1487                 break;
1488         default:
1489                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1490                 return;
1491         }
1492         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1493 }
1494
1495 static void
1496 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1497 {
1498         struct drm_device *dev = encoder->dev;
1499         struct radeon_device *rdev = dev->dev_private;
1500         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1501         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1502         ENABLE_YUV_PS_ALLOCATION args;
1503         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1504         uint32_t temp, reg;
1505
1506         memset(&args, 0, sizeof(args));
1507
1508         if (rdev->family >= CHIP_R600)
1509                 reg = R600_BIOS_3_SCRATCH;
1510         else
1511                 reg = RADEON_BIOS_3_SCRATCH;
1512
1513         /* XXX: fix up scratch reg handling */
1514         temp = RREG32(reg);
1515         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1516                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1517                              (radeon_crtc->crtc_id << 18)));
1518         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1519                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1520         else
1521                 WREG32(reg, 0);
1522
1523         if (enable)
1524                 args.ucEnable = ATOM_ENABLE;
1525         args.ucCRTC = radeon_crtc->crtc_id;
1526
1527         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1528
1529         WREG32(reg, temp);
1530 }
1531
1532 static void
1533 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1534 {
1535         struct drm_device *dev = encoder->dev;
1536         struct radeon_device *rdev = dev->dev_private;
1537         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1538         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1539         int index = 0;
1540
1541         memset(&args, 0, sizeof(args));
1542
1543         switch (radeon_encoder->encoder_id) {
1544         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1545         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1546                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1547                 break;
1548         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1549         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1550         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1551                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1552                 break;
1553         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1554                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1555                 break;
1556         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1557                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1558                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1559                 else
1560                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1561                 break;
1562         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1563         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1564                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1565                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1566                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1567                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1568                 else
1569                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1570                 break;
1571         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1572         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1573                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1574                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1575                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1576                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1577                 else
1578                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1579                 break;
1580         default:
1581                 return;
1582         }
1583
1584         switch (mode) {
1585         case DRM_MODE_DPMS_ON:
1586                 args.ucAction = ATOM_ENABLE;
1587                 /* workaround for DVOOutputControl on some RS690 systems */
1588                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1589                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1590                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1591                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1592                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1593                 } else
1594                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1595                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1596                         args.ucAction = ATOM_LCD_BLON;
1597                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1598                 }
1599                 break;
1600         case DRM_MODE_DPMS_STANDBY:
1601         case DRM_MODE_DPMS_SUSPEND:
1602         case DRM_MODE_DPMS_OFF:
1603                 args.ucAction = ATOM_DISABLE;
1604                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1605                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1606                         args.ucAction = ATOM_LCD_BLOFF;
1607                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1608                 }
1609                 break;
1610         }
1611 }
1612
1613 static void
1614 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1615 {
1616         struct drm_device *dev = encoder->dev;
1617         struct radeon_device *rdev = dev->dev_private;
1618         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1619         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1620         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1621         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1622         struct radeon_connector *radeon_connector = NULL;
1623         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1624         bool travis_quirk = false;
1625         int encoder_mode;
1626
1627         if (connector) {
1628                 radeon_connector = to_radeon_connector(connector);
1629                 radeon_dig_connector = radeon_connector->con_priv;
1630                 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1631                      ENCODER_OBJECT_ID_TRAVIS) &&
1632                     (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1633                     !ASIC_IS_DCE5(rdev))
1634                         travis_quirk = true;
1635         }
1636
1637         switch (mode) {
1638         case DRM_MODE_DPMS_ON:
1639                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1640                         if (!connector)
1641                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1642                         else
1643                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1644
1645                         /* setup and enable the encoder */
1646                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1647                         atombios_dig_encoder_setup(encoder,
1648                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1649                                                    dig->panel_mode);
1650                         if (ext_encoder) {
1651                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1652                                         atombios_external_encoder_setup(encoder, ext_encoder,
1653                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1654                         }
1655                 } else if (ASIC_IS_DCE4(rdev)) {
1656                         /* setup and enable the encoder */
1657                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1658                 } else {
1659                         /* setup and enable the encoder and transmitter */
1660                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1661                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1662                 }
1663                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1664                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1665                                 atombios_set_edp_panel_power(connector,
1666                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1667                                 radeon_dig_connector->edp_on = true;
1668                         }
1669                 }
1670                 /* enable the transmitter */
1671                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1672                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1673                         /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1674                         radeon_dp_link_train(encoder, connector);
1675                         if (ASIC_IS_DCE4(rdev))
1676                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1677                 }
1678                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1679                         atombios_dig_transmitter_setup(encoder,
1680                                                        ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1681                 if (ext_encoder)
1682                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1683                 break;
1684         case DRM_MODE_DPMS_STANDBY:
1685         case DRM_MODE_DPMS_SUSPEND:
1686         case DRM_MODE_DPMS_OFF:
1687                 if (ASIC_IS_DCE4(rdev)) {
1688                         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1689                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1690                 }
1691                 if (ext_encoder)
1692                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1693                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1694                         atombios_dig_transmitter_setup(encoder,
1695                                                        ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1696
1697                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1698                     connector && !travis_quirk)
1699                         radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1700                 if (ASIC_IS_DCE4(rdev)) {
1701                         /* disable the transmitter */
1702                         atombios_dig_transmitter_setup(encoder,
1703                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1704                 } else {
1705                         /* disable the encoder and transmitter */
1706                         atombios_dig_transmitter_setup(encoder,
1707                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1708                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1709                 }
1710                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1711                         if (travis_quirk)
1712                                 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1713                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1714                                 atombios_set_edp_panel_power(connector,
1715                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1716                                 radeon_dig_connector->edp_on = false;
1717                         }
1718                 }
1719                 break;
1720         }
1721
1722         encoder_mode = atombios_get_encoder_mode(encoder);
1723         if (radeon_audio != 0 &&
1724                 (encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode)))
1725                 radeon_audio_dpms(encoder, mode);
1726 }
1727
1728 static void
1729 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1730 {
1731         struct drm_device *dev = encoder->dev;
1732         struct radeon_device *rdev = dev->dev_private;
1733         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1734
1735         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1736                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1737                   radeon_encoder->active_device);
1738         switch (radeon_encoder->encoder_id) {
1739         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1740         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1741         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1742         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1743         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1744         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1745         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1746         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1747                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1748                 break;
1749         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1750         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1751         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1752         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1753         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1754                 radeon_atom_encoder_dpms_dig(encoder, mode);
1755                 break;
1756         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1757                 if (ASIC_IS_DCE5(rdev)) {
1758                         switch (mode) {
1759                         case DRM_MODE_DPMS_ON:
1760                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1761                                 break;
1762                         case DRM_MODE_DPMS_STANDBY:
1763                         case DRM_MODE_DPMS_SUSPEND:
1764                         case DRM_MODE_DPMS_OFF:
1765                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1766                                 break;
1767                         }
1768                 } else if (ASIC_IS_DCE3(rdev))
1769                         radeon_atom_encoder_dpms_dig(encoder, mode);
1770                 else
1771                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1772                 break;
1773         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1774         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1775                 if (ASIC_IS_DCE5(rdev)) {
1776                         switch (mode) {
1777                         case DRM_MODE_DPMS_ON:
1778                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1779                                 break;
1780                         case DRM_MODE_DPMS_STANDBY:
1781                         case DRM_MODE_DPMS_SUSPEND:
1782                         case DRM_MODE_DPMS_OFF:
1783                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1784                                 break;
1785                         }
1786                 } else
1787                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1788                 break;
1789         default:
1790                 return;
1791         }
1792
1793         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1794
1795 }
1796
1797 union crtc_source_param {
1798         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1799         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1800 };
1801
1802 static void
1803 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1804 {
1805         struct drm_device *dev = encoder->dev;
1806         struct radeon_device *rdev = dev->dev_private;
1807         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1808         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1809         union crtc_source_param args;
1810         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1811         uint8_t frev, crev;
1812         struct radeon_encoder_atom_dig *dig;
1813
1814         memset(&args, 0, sizeof(args));
1815
1816         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1817                 return;
1818
1819         switch (frev) {
1820         case 1:
1821                 switch (crev) {
1822                 case 1:
1823                 default:
1824                         if (ASIC_IS_AVIVO(rdev))
1825                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1826                         else {
1827                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1828                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1829                                 } else {
1830                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1831                                 }
1832                         }
1833                         switch (radeon_encoder->encoder_id) {
1834                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1835                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1836                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1837                                 break;
1838                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1839                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1840                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1841                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1842                                 else
1843                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1844                                 break;
1845                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1846                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1847                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1848                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1849                                 break;
1850                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1851                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1852                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1853                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1854                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1855                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1856                                 else
1857                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1858                                 break;
1859                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1860                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1861                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1862                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1863                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1864                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1865                                 else
1866                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1867                                 break;
1868                         }
1869                         break;
1870                 case 2:
1871                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1872                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1873                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1874
1875                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1876                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1877                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1878                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1879                                 else
1880                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1881                         } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1882                                 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1883                         } else {
1884                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1885                         }
1886                         switch (radeon_encoder->encoder_id) {
1887                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1888                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1889                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1890                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1891                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1892                                 dig = radeon_encoder->enc_priv;
1893                                 switch (dig->dig_encoder) {
1894                                 case 0:
1895                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1896                                         break;
1897                                 case 1:
1898                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1899                                         break;
1900                                 case 2:
1901                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1902                                         break;
1903                                 case 3:
1904                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1905                                         break;
1906                                 case 4:
1907                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1908                                         break;
1909                                 case 5:
1910                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1911                                         break;
1912                                 case 6:
1913                                         args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1914                                         break;
1915                                 }
1916                                 break;
1917                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1918                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1919                                 break;
1920                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1921                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1922                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1923                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1924                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1925                                 else
1926                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1927                                 break;
1928                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1929                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1930                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1931                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1932                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1933                                 else
1934                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1935                                 break;
1936                         }
1937                         break;
1938                 }
1939                 break;
1940         default:
1941                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1942                 return;
1943         }
1944
1945         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1946
1947         /* update scratch regs with new routing */
1948         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1949 }
1950
1951 static void
1952 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1953                               struct drm_display_mode *mode)
1954 {
1955         struct drm_device *dev = encoder->dev;
1956         struct radeon_device *rdev = dev->dev_private;
1957         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1958         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1959
1960         /* Funky macbooks */
1961         if ((dev->pdev->device == 0x71C5) &&
1962             (dev->pdev->subsystem_vendor == 0x106b) &&
1963             (dev->pdev->subsystem_device == 0x0080)) {
1964                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1965                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1966
1967                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1968                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1969
1970                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1971                 }
1972         }
1973
1974         /* set scaler clears this on some chips */
1975         if (ASIC_IS_AVIVO(rdev) &&
1976             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1977                 if (ASIC_IS_DCE8(rdev)) {
1978                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1979                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1980                                        CIK_INTERLEAVE_EN);
1981                         else
1982                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1983                 } else if (ASIC_IS_DCE4(rdev)) {
1984                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1985                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1986                                        EVERGREEN_INTERLEAVE_EN);
1987                         else
1988                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1989                 } else {
1990                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1991                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1992                                        AVIVO_D1MODE_INTERLEAVE_EN);
1993                         else
1994                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1995                 }
1996         }
1997 }
1998
1999 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
2000 {
2001         struct drm_device *dev = encoder->dev;
2002         struct radeon_device *rdev = dev->dev_private;
2003         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2004         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2005         struct drm_encoder *test_encoder;
2006         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2007         uint32_t dig_enc_in_use = 0;
2008
2009         if (ASIC_IS_DCE6(rdev)) {
2010                 /* DCE6 */
2011                 switch (radeon_encoder->encoder_id) {
2012                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2013                         if (dig->linkb)
2014                                 return 1;
2015                         else
2016                                 return 0;
2017                         break;
2018                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2019                         if (dig->linkb)
2020                                 return 3;
2021                         else
2022                                 return 2;
2023                         break;
2024                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2025                         if (dig->linkb)
2026                                 return 5;
2027                         else
2028                                 return 4;
2029                         break;
2030                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2031                         return 6;
2032                         break;
2033                 }
2034         } else if (ASIC_IS_DCE4(rdev)) {
2035                 /* DCE4/5 */
2036                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2037                         /* ontario follows DCE4 */
2038                         if (rdev->family == CHIP_PALM) {
2039                                 if (dig->linkb)
2040                                         return 1;
2041                                 else
2042                                         return 0;
2043                         } else
2044                                 /* llano follows DCE3.2 */
2045                                 return radeon_crtc->crtc_id;
2046                 } else {
2047                         switch (radeon_encoder->encoder_id) {
2048                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2049                                 if (dig->linkb)
2050                                         return 1;
2051                                 else
2052                                         return 0;
2053                                 break;
2054                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2055                                 if (dig->linkb)
2056                                         return 3;
2057                                 else
2058                                         return 2;
2059                                 break;
2060                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2061                                 if (dig->linkb)
2062                                         return 5;
2063                                 else
2064                                         return 4;
2065                                 break;
2066                         }
2067                 }
2068         }
2069
2070         /* on DCE32 and encoder can driver any block so just crtc id */
2071         if (ASIC_IS_DCE32(rdev)) {
2072                 return radeon_crtc->crtc_id;
2073         }
2074
2075         /* on DCE3 - LVTMA can only be driven by DIGB */
2076         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2077                 struct radeon_encoder *radeon_test_encoder;
2078
2079                 if (encoder == test_encoder)
2080                         continue;
2081
2082                 if (!radeon_encoder_is_digital(test_encoder))
2083                         continue;
2084
2085                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2086                 dig = radeon_test_encoder->enc_priv;
2087
2088                 if (dig->dig_encoder >= 0)
2089                         dig_enc_in_use |= (1 << dig->dig_encoder);
2090         }
2091
2092         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2093                 if (dig_enc_in_use & 0x2)
2094                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2095                 return 1;
2096         }
2097         if (!(dig_enc_in_use & 1))
2098                 return 0;
2099         return 1;
2100 }
2101
2102 /* This only needs to be called once at startup */
2103 void
2104 radeon_atom_encoder_init(struct radeon_device *rdev)
2105 {
2106         struct drm_device *dev = rdev->ddev;
2107         struct drm_encoder *encoder;
2108
2109         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2110                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2111                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2112
2113                 switch (radeon_encoder->encoder_id) {
2114                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2115                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2116                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2117                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2118                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2119                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2120                         break;
2121                 default:
2122                         break;
2123                 }
2124
2125                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2126                         atombios_external_encoder_setup(encoder, ext_encoder,
2127                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2128         }
2129 }
2130
2131 static void
2132 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2133                              struct drm_display_mode *mode,
2134                              struct drm_display_mode *adjusted_mode)
2135 {
2136         struct drm_device *dev = encoder->dev;
2137         struct radeon_device *rdev = dev->dev_private;
2138         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2139         int encoder_mode;
2140
2141         radeon_encoder->pixel_clock = adjusted_mode->clock;
2142
2143         /* need to call this here rather than in prepare() since we need some crtc info */
2144         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2145
2146         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2147                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2148                         atombios_yuv_setup(encoder, true);
2149                 else
2150                         atombios_yuv_setup(encoder, false);
2151         }
2152
2153         switch (radeon_encoder->encoder_id) {
2154         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2155         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2156         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2157         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2158                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2159                 break;
2160         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2161         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2162         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2163         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2164         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2165                 /* handled in dpms */
2166                 encoder_mode = atombios_get_encoder_mode(encoder);
2167                 if (radeon_audio != 0 &&
2168                         (encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode)))
2169                         radeon_audio_mode_set(encoder, adjusted_mode);
2170                 break;
2171         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2172         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2173         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2174                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2175                 break;
2176         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2177         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2178         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2179         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2180                 atombios_dac_setup(encoder, ATOM_ENABLE);
2181                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2182                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2183                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2184                         else
2185                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2186                 }
2187                 break;
2188         }
2189
2190         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2191 }
2192
2193 static bool
2194 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2195 {
2196         struct drm_device *dev = encoder->dev;
2197         struct radeon_device *rdev = dev->dev_private;
2198         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2199         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2200
2201         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2202                                        ATOM_DEVICE_CV_SUPPORT |
2203                                        ATOM_DEVICE_CRT_SUPPORT)) {
2204                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2205                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2206                 uint8_t frev, crev;
2207
2208                 memset(&args, 0, sizeof(args));
2209
2210                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2211                         return false;
2212
2213                 args.sDacload.ucMisc = 0;
2214
2215                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2216                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2217                         args.sDacload.ucDacType = ATOM_DAC_A;
2218                 else
2219                         args.sDacload.ucDacType = ATOM_DAC_B;
2220
2221                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2222                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2223                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2224                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2225                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2226                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2227                         if (crev >= 3)
2228                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2229                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2230                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2231                         if (crev >= 3)
2232                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2233                 }
2234
2235                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2236
2237                 return true;
2238         } else
2239                 return false;
2240 }
2241
2242 static enum drm_connector_status
2243 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2244 {
2245         struct drm_device *dev = encoder->dev;
2246         struct radeon_device *rdev = dev->dev_private;
2247         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2248         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2249         uint32_t bios_0_scratch;
2250
2251         if (!atombios_dac_load_detect(encoder, connector)) {
2252                 DRM_DEBUG_KMS("detect returned false \n");
2253                 return connector_status_unknown;
2254         }
2255
2256         if (rdev->family >= CHIP_R600)
2257                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2258         else
2259                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2260
2261         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2262         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2263                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2264                         return connector_status_connected;
2265         }
2266         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2267                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2268                         return connector_status_connected;
2269         }
2270         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2271                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2272                         return connector_status_connected;
2273         }
2274         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2275                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2276                         return connector_status_connected; /* CTV */
2277                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2278                         return connector_status_connected; /* STV */
2279         }
2280         return connector_status_disconnected;
2281 }
2282
2283 static enum drm_connector_status
2284 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2285 {
2286         struct drm_device *dev = encoder->dev;
2287         struct radeon_device *rdev = dev->dev_private;
2288         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2289         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2290         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2291         u32 bios_0_scratch;
2292
2293         if (!ASIC_IS_DCE4(rdev))
2294                 return connector_status_unknown;
2295
2296         if (!ext_encoder)
2297                 return connector_status_unknown;
2298
2299         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2300                 return connector_status_unknown;
2301
2302         /* load detect on the dp bridge */
2303         atombios_external_encoder_setup(encoder, ext_encoder,
2304                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2305
2306         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2307
2308         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2309         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2310                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2311                         return connector_status_connected;
2312         }
2313         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2314                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2315                         return connector_status_connected;
2316         }
2317         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2318                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2319                         return connector_status_connected;
2320         }
2321         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2322                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2323                         return connector_status_connected; /* CTV */
2324                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2325                         return connector_status_connected; /* STV */
2326         }
2327         return connector_status_disconnected;
2328 }
2329
2330 void
2331 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2332 {
2333         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2334
2335         if (ext_encoder)
2336                 /* ddc_setup on the dp bridge */
2337                 atombios_external_encoder_setup(encoder, ext_encoder,
2338                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2339
2340 }
2341
2342 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2343 {
2344         struct radeon_device *rdev = encoder->dev->dev_private;
2345         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2346         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2347
2348         if ((radeon_encoder->active_device &
2349              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2350             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2351              ENCODER_OBJECT_ID_NONE)) {
2352                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2353                 if (dig) {
2354                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2355                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2356                                 if (rdev->family >= CHIP_R600)
2357                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2358                                 else
2359                                         /* RS600/690/740 have only 1 afmt block */
2360                                         dig->afmt = rdev->mode_info.afmt[0];
2361                         }
2362                 }
2363         }
2364
2365         radeon_atom_output_lock(encoder, true);
2366
2367         if (connector) {
2368                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2369
2370                 /* select the clock/data port if it uses a router */
2371                 if (radeon_connector->router.cd_valid)
2372                         radeon_router_select_cd_port(radeon_connector);
2373
2374                 /* turn eDP panel on for mode set */
2375                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2376                         atombios_set_edp_panel_power(connector,
2377                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2378         }
2379
2380         /* this is needed for the pll/ss setup to work correctly in some cases */
2381         atombios_set_encoder_crtc_source(encoder);
2382         /* set up the FMT blocks */
2383         if (ASIC_IS_DCE8(rdev))
2384                 dce8_program_fmt(encoder);
2385         else if (ASIC_IS_DCE4(rdev))
2386                 dce4_program_fmt(encoder);
2387         else if (ASIC_IS_DCE3(rdev))
2388                 dce3_program_fmt(encoder);
2389         else if (ASIC_IS_AVIVO(rdev))
2390                 avivo_program_fmt(encoder);
2391 }
2392
2393 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2394 {
2395         /* need to call this here as we need the crtc set up */
2396         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2397         radeon_atom_output_lock(encoder, false);
2398 }
2399
2400 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2401 {
2402         struct drm_device *dev = encoder->dev;
2403         struct radeon_device *rdev = dev->dev_private;
2404         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2405         struct radeon_encoder_atom_dig *dig;
2406
2407         /* check for pre-DCE3 cards with shared encoders;
2408          * can't really use the links individually, so don't disable
2409          * the encoder if it's in use by another connector
2410          */
2411         if (!ASIC_IS_DCE3(rdev)) {
2412                 struct drm_encoder *other_encoder;
2413                 struct radeon_encoder *other_radeon_encoder;
2414
2415                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2416                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2417                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2418                             drm_helper_encoder_in_use(other_encoder))
2419                                 goto disable_done;
2420                 }
2421         }
2422
2423         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2424
2425         switch (radeon_encoder->encoder_id) {
2426         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2427         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2428         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2429         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2430                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2431                 break;
2432         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2433         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2434         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2435         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2436         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2437                 /* handled in dpms */
2438                 break;
2439         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2440         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2441         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2442                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2443                 break;
2444         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2445         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2446         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2447         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2448                 atombios_dac_setup(encoder, ATOM_DISABLE);
2449                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2450                         atombios_tv_setup(encoder, ATOM_DISABLE);
2451                 break;
2452         }
2453
2454 disable_done:
2455         if (radeon_encoder_is_digital(encoder)) {
2456                 dig = radeon_encoder->enc_priv;
2457                 dig->dig_encoder = -1;
2458         }
2459         radeon_encoder->active_device = 0;
2460 }
2461
2462 /* these are handled by the primary encoders */
2463 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2464 {
2465
2466 }
2467
2468 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2469 {
2470
2471 }
2472
2473 static void
2474 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2475                          struct drm_display_mode *mode,
2476                          struct drm_display_mode *adjusted_mode)
2477 {
2478
2479 }
2480
2481 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2482 {
2483
2484 }
2485
2486 static void
2487 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2488 {
2489
2490 }
2491
2492 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2493                                        const struct drm_display_mode *mode,
2494                                        struct drm_display_mode *adjusted_mode)
2495 {
2496         return true;
2497 }
2498
2499 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2500         .dpms = radeon_atom_ext_dpms,
2501         .mode_fixup = radeon_atom_ext_mode_fixup,
2502         .prepare = radeon_atom_ext_prepare,
2503         .mode_set = radeon_atom_ext_mode_set,
2504         .commit = radeon_atom_ext_commit,
2505         .disable = radeon_atom_ext_disable,
2506         /* no detect for TMDS/LVDS yet */
2507 };
2508
2509 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2510         .dpms = radeon_atom_encoder_dpms,
2511         .mode_fixup = radeon_atom_mode_fixup,
2512         .prepare = radeon_atom_encoder_prepare,
2513         .mode_set = radeon_atom_encoder_mode_set,
2514         .commit = radeon_atom_encoder_commit,
2515         .disable = radeon_atom_encoder_disable,
2516         .detect = radeon_atom_dig_detect,
2517 };
2518
2519 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2520         .dpms = radeon_atom_encoder_dpms,
2521         .mode_fixup = radeon_atom_mode_fixup,
2522         .prepare = radeon_atom_encoder_prepare,
2523         .mode_set = radeon_atom_encoder_mode_set,
2524         .commit = radeon_atom_encoder_commit,
2525         .detect = radeon_atom_dac_detect,
2526 };
2527
2528 void radeon_enc_destroy(struct drm_encoder *encoder)
2529 {
2530         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2531         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2532                 radeon_atom_backlight_exit(radeon_encoder);
2533         kfree(radeon_encoder->enc_priv);
2534         drm_encoder_cleanup(encoder);
2535         kfree(radeon_encoder);
2536 }
2537
2538 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2539         .destroy = radeon_enc_destroy,
2540 };
2541
2542 static struct radeon_encoder_atom_dac *
2543 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2544 {
2545         struct drm_device *dev = radeon_encoder->base.dev;
2546         struct radeon_device *rdev = dev->dev_private;
2547         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2548
2549         if (!dac)
2550                 return NULL;
2551
2552         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2553         return dac;
2554 }
2555
2556 static struct radeon_encoder_atom_dig *
2557 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2558 {
2559         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2560         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2561
2562         if (!dig)
2563                 return NULL;
2564
2565         /* coherent mode by default */
2566         dig->coherent_mode = true;
2567         dig->dig_encoder = -1;
2568
2569         if (encoder_enum == 2)
2570                 dig->linkb = true;
2571         else
2572                 dig->linkb = false;
2573
2574         return dig;
2575 }
2576
2577 void
2578 radeon_add_atom_encoder(struct drm_device *dev,
2579                         uint32_t encoder_enum,
2580                         uint32_t supported_device,
2581                         u16 caps)
2582 {
2583         struct radeon_device *rdev = dev->dev_private;
2584         struct drm_encoder *encoder;
2585         struct radeon_encoder *radeon_encoder;
2586
2587         /* see if we already added it */
2588         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2589                 radeon_encoder = to_radeon_encoder(encoder);
2590                 if (radeon_encoder->encoder_enum == encoder_enum) {
2591                         radeon_encoder->devices |= supported_device;
2592                         return;
2593                 }
2594
2595         }
2596
2597         /* add a new one */
2598         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2599         if (!radeon_encoder)
2600                 return;
2601
2602         encoder = &radeon_encoder->base;
2603         switch (rdev->num_crtc) {
2604         case 1:
2605                 encoder->possible_crtcs = 0x1;
2606                 break;
2607         case 2:
2608         default:
2609                 encoder->possible_crtcs = 0x3;
2610                 break;
2611         case 4:
2612                 encoder->possible_crtcs = 0xf;
2613                 break;
2614         case 6:
2615                 encoder->possible_crtcs = 0x3f;
2616                 break;
2617         }
2618
2619         radeon_encoder->enc_priv = NULL;
2620
2621         radeon_encoder->encoder_enum = encoder_enum;
2622         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2623         radeon_encoder->devices = supported_device;
2624         radeon_encoder->rmx_type = RMX_OFF;
2625         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2626         radeon_encoder->is_ext_encoder = false;
2627         radeon_encoder->caps = caps;
2628
2629         switch (radeon_encoder->encoder_id) {
2630         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2631         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2632         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2633         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2634                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2635                         radeon_encoder->rmx_type = RMX_FULL;
2636                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2637                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2638                 } else {
2639                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2640                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2641                 }
2642                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2643                 break;
2644         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2645                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2646                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2647                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2648                 break;
2649         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2650         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2651         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2652                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2653                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2654                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2655                 break;
2656         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2657         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2658         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2659         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2660         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2661         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2662         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2663         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2664                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2665                         radeon_encoder->rmx_type = RMX_FULL;
2666                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2667                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2668                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2669                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2670                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2671                 } else {
2672                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2673                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2674                 }
2675                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2676                 break;
2677         case ENCODER_OBJECT_ID_SI170B:
2678         case ENCODER_OBJECT_ID_CH7303:
2679         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2680         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2681         case ENCODER_OBJECT_ID_TITFP513:
2682         case ENCODER_OBJECT_ID_VT1623:
2683         case ENCODER_OBJECT_ID_HDMI_SI1930:
2684         case ENCODER_OBJECT_ID_TRAVIS:
2685         case ENCODER_OBJECT_ID_NUTMEG:
2686                 /* these are handled by the primary encoders */
2687                 radeon_encoder->is_ext_encoder = true;
2688                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2689                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2690                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2691                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2692                 else
2693                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2694                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2695                 break;
2696         }
2697 }