2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <core/client.h>
27 #include <core/engctx.h>
28 #include <core/enum.h>
29 #include <core/handle.h>
30 #include <subdev/bar.h>
31 #include <subdev/fb.h>
32 #include <subdev/mmu.h>
33 #include <subdev/timer.h>
35 #include <nvif/class.h>
36 #include <nvif/unpack.h>
38 #define _(a,b) { (a), ((1ULL << (a)) | (b)) }
43 _(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) |
44 (1ULL << NVDEV_ENGINE_CE2)),
45 _(NVDEV_ENGINE_MSPDEC , 0),
46 _(NVDEV_ENGINE_MSPPP , 0),
47 _(NVDEV_ENGINE_MSVLD , 0),
48 _(NVDEV_ENGINE_CE0 , 0),
49 _(NVDEV_ENGINE_CE1 , 0),
50 _(NVDEV_ENGINE_MSENC , 0),
53 #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
55 struct gk104_fifo_engn {
56 struct nvkm_gpuobj *runlist[2];
58 wait_queue_head_t wait;
61 struct gk104_fifo_priv {
62 struct nvkm_fifo base;
64 struct work_struct fault;
67 struct gk104_fifo_engn engine[FIFO_ENGINE_NR];
69 struct nvkm_gpuobj *mem;
75 struct gk104_fifo_base {
76 struct nvkm_fifo_base base;
77 struct nvkm_gpuobj *pgd;
81 struct gk104_fifo_chan {
82 struct nvkm_fifo_chan base;
91 /*******************************************************************************
92 * FIFO channel objects
93 ******************************************************************************/
96 gk104_fifo_runlist_update(struct gk104_fifo_priv *priv, u32 engine)
98 struct nvkm_bar *bar = nvkm_bar(priv);
99 struct gk104_fifo_engn *engn = &priv->engine[engine];
100 struct nvkm_gpuobj *cur;
103 mutex_lock(&nv_subdev(priv)->mutex);
104 cur = engn->runlist[engn->cur_runlist];
105 engn->cur_runlist = !engn->cur_runlist;
107 for (i = 0, p = 0; i < priv->base.max; i++) {
108 struct gk104_fifo_chan *chan = (void *)priv->base.channel[i];
109 if (chan && chan->state == RUNNING && chan->engine == engine) {
110 nv_wo32(cur, p + 0, i);
111 nv_wo32(cur, p + 4, 0x00000000);
117 nv_wr32(priv, 0x002270, cur->addr >> 12);
118 nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3));
120 if (wait_event_timeout(engn->wait, !(nv_rd32(priv, 0x002284 +
121 (engine * 0x08)) & 0x00100000),
122 msecs_to_jiffies(2000)) == 0)
123 nv_error(priv, "runlist %d update timeout\n", engine);
124 mutex_unlock(&nv_subdev(priv)->mutex);
128 gk104_fifo_context_attach(struct nvkm_object *parent,
129 struct nvkm_object *object)
131 struct nvkm_bar *bar = nvkm_bar(parent);
132 struct gk104_fifo_base *base = (void *)parent->parent;
133 struct nvkm_engctx *ectx = (void *)object;
137 switch (nv_engidx(object->engine)) {
138 case NVDEV_ENGINE_SW :
140 case NVDEV_ENGINE_CE0:
141 case NVDEV_ENGINE_CE1:
142 case NVDEV_ENGINE_CE2:
143 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
145 case NVDEV_ENGINE_GR : addr = 0x0210; break;
146 case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
147 case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
148 case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
153 if (!ectx->vma.node) {
154 ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
155 NV_MEM_ACCESS_RW, &ectx->vma);
159 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
162 nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
163 nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
169 gk104_fifo_chan_kick(struct gk104_fifo_chan *chan)
171 struct nvkm_object *obj = (void *)chan;
172 struct gk104_fifo_priv *priv = (void *)obj->engine;
174 nv_wr32(priv, 0x002634, chan->base.chid);
175 if (!nv_wait(priv, 0x002634, 0x100000, 0x000000)) {
176 nv_error(priv, "channel %d [%s] kick timeout\n",
177 chan->base.chid, nvkm_client_name(chan));
185 gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend,
186 struct nvkm_object *object)
188 struct nvkm_bar *bar = nvkm_bar(parent);
189 struct gk104_fifo_base *base = (void *)parent->parent;
190 struct gk104_fifo_chan *chan = (void *)parent;
194 switch (nv_engidx(object->engine)) {
195 case NVDEV_ENGINE_SW : return 0;
196 case NVDEV_ENGINE_CE0 :
197 case NVDEV_ENGINE_CE1 :
198 case NVDEV_ENGINE_CE2 : addr = 0x0000; break;
199 case NVDEV_ENGINE_GR : addr = 0x0210; break;
200 case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
201 case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
202 case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
207 ret = gk104_fifo_chan_kick(chan);
212 nv_wo32(base, addr + 0x00, 0x00000000);
213 nv_wo32(base, addr + 0x04, 0x00000000);
221 gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
222 struct nvkm_oclass *oclass, void *data, u32 size,
223 struct nvkm_object **pobject)
226 struct kepler_channel_gpfifo_a_v0 v0;
228 struct nvkm_bar *bar = nvkm_bar(parent);
229 struct gk104_fifo_priv *priv = (void *)engine;
230 struct gk104_fifo_base *base = (void *)parent;
231 struct gk104_fifo_chan *chan;
232 u64 usermem, ioffset, ilength;
235 nv_ioctl(parent, "create channel gpfifo size %d\n", size);
236 if (nvif_unpack(args->v0, 0, 0, false)) {
237 nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x "
238 "ioffset %016llx ilength %08x engine %08x\n",
239 args->v0.version, args->v0.pushbuf, args->v0.ioffset,
240 args->v0.ilength, args->v0.engine);
244 for (i = 0; i < FIFO_ENGINE_NR; i++) {
245 if (args->v0.engine & (1 << i)) {
246 if (nvkm_engine(parent, fifo_engine[i].subdev)) {
247 args->v0.engine = (1 << i);
253 if (i == FIFO_ENGINE_NR) {
254 nv_error(priv, "unsupported engines 0x%08x\n", args->v0.engine);
258 ret = nvkm_fifo_channel_create(parent, engine, oclass, 1,
259 priv->user.bar.offset, 0x200,
261 fifo_engine[i].mask, &chan);
262 *pobject = nv_object(chan);
266 args->v0.chid = chan->base.chid;
268 nv_parent(chan)->context_attach = gk104_fifo_context_attach;
269 nv_parent(chan)->context_detach = gk104_fifo_context_detach;
272 usermem = chan->base.chid * 0x200;
273 ioffset = args->v0.ioffset;
274 ilength = order_base_2(args->v0.ilength / 8);
276 for (i = 0; i < 0x200; i += 4)
277 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
279 nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
280 nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
281 nv_wo32(base, 0x10, 0x0000face);
282 nv_wo32(base, 0x30, 0xfffff902);
283 nv_wo32(base, 0x48, lower_32_bits(ioffset));
284 nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
285 nv_wo32(base, 0x84, 0x20400000);
286 nv_wo32(base, 0x94, 0x30000001);
287 nv_wo32(base, 0x9c, 0x00000100);
288 nv_wo32(base, 0xac, 0x0000001f);
289 nv_wo32(base, 0xe8, chan->base.chid);
290 nv_wo32(base, 0xb8, 0xf8000000);
291 nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
292 nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
298 gk104_fifo_chan_init(struct nvkm_object *object)
300 struct nvkm_gpuobj *base = nv_gpuobj(object->parent);
301 struct gk104_fifo_priv *priv = (void *)object->engine;
302 struct gk104_fifo_chan *chan = (void *)object;
303 u32 chid = chan->base.chid;
306 ret = nvkm_fifo_channel_init(&chan->base);
310 nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16);
311 nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12);
313 if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
314 nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
315 gk104_fifo_runlist_update(priv, chan->engine);
316 nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
323 gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend)
325 struct gk104_fifo_priv *priv = (void *)object->engine;
326 struct gk104_fifo_chan *chan = (void *)object;
327 u32 chid = chan->base.chid;
329 if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
330 nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800);
331 gk104_fifo_runlist_update(priv, chan->engine);
334 gk104_fifo_chan_kick(chan);
335 nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000);
336 return nvkm_fifo_channel_fini(&chan->base, suspend);
340 gk104_fifo_chan_ofuncs = {
341 .ctor = gk104_fifo_chan_ctor,
342 .dtor = _nvkm_fifo_channel_dtor,
343 .init = gk104_fifo_chan_init,
344 .fini = gk104_fifo_chan_fini,
345 .map = _nvkm_fifo_channel_map,
346 .rd32 = _nvkm_fifo_channel_rd32,
347 .wr32 = _nvkm_fifo_channel_wr32,
348 .ntfy = _nvkm_fifo_channel_ntfy
351 static struct nvkm_oclass
352 gk104_fifo_sclass[] = {
353 { KEPLER_CHANNEL_GPFIFO_A, &gk104_fifo_chan_ofuncs },
357 /*******************************************************************************
358 * FIFO context - instmem heap and vm setup
359 ******************************************************************************/
362 gk104_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
363 struct nvkm_oclass *oclass, void *data, u32 size,
364 struct nvkm_object **pobject)
366 struct gk104_fifo_base *base;
369 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
370 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base);
371 *pobject = nv_object(base);
375 ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
380 nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
381 nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
382 nv_wo32(base, 0x0208, 0xffffffff);
383 nv_wo32(base, 0x020c, 0x000000ff);
385 ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);
393 gk104_fifo_context_dtor(struct nvkm_object *object)
395 struct gk104_fifo_base *base = (void *)object;
396 nvkm_vm_ref(NULL, &base->vm, base->pgd);
397 nvkm_gpuobj_ref(NULL, &base->pgd);
398 nvkm_fifo_context_destroy(&base->base);
401 static struct nvkm_oclass
402 gk104_fifo_cclass = {
403 .handle = NV_ENGCTX(FIFO, 0xe0),
404 .ofuncs = &(struct nvkm_ofuncs) {
405 .ctor = gk104_fifo_context_ctor,
406 .dtor = gk104_fifo_context_dtor,
407 .init = _nvkm_fifo_context_init,
408 .fini = _nvkm_fifo_context_fini,
409 .rd32 = _nvkm_fifo_context_rd32,
410 .wr32 = _nvkm_fifo_context_wr32,
414 /*******************************************************************************
416 ******************************************************************************/
419 gk104_fifo_engidx(struct gk104_fifo_priv *priv, u32 engn)
422 case NVDEV_ENGINE_GR :
423 case NVDEV_ENGINE_CE2 : engn = 0; break;
424 case NVDEV_ENGINE_MSVLD : engn = 1; break;
425 case NVDEV_ENGINE_MSPPP : engn = 2; break;
426 case NVDEV_ENGINE_MSPDEC: engn = 3; break;
427 case NVDEV_ENGINE_CE0 : engn = 4; break;
428 case NVDEV_ENGINE_CE1 : engn = 5; break;
429 case NVDEV_ENGINE_MSENC : engn = 6; break;
437 static inline struct nvkm_engine *
438 gk104_fifo_engine(struct gk104_fifo_priv *priv, u32 engn)
440 if (engn >= ARRAY_SIZE(fifo_engine))
442 return nvkm_engine(priv, fifo_engine[engn].subdev);
446 gk104_fifo_recover_work(struct work_struct *work)
448 struct gk104_fifo_priv *priv = container_of(work, typeof(*priv), fault);
449 struct nvkm_object *engine;
454 spin_lock_irqsave(&priv->base.lock, flags);
457 spin_unlock_irqrestore(&priv->base.lock, flags);
459 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
460 engm |= 1 << gk104_fifo_engidx(priv, engn);
461 nv_mask(priv, 0x002630, engm, engm);
463 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
464 if ((engine = (void *)nvkm_engine(priv, engn))) {
465 nv_ofuncs(engine)->fini(engine, false);
466 WARN_ON(nv_ofuncs(engine)->init(engine));
468 gk104_fifo_runlist_update(priv, gk104_fifo_engidx(priv, engn));
471 nv_wr32(priv, 0x00262c, engm);
472 nv_mask(priv, 0x002630, engm, 0x00000000);
476 gk104_fifo_recover(struct gk104_fifo_priv *priv, struct nvkm_engine *engine,
477 struct gk104_fifo_chan *chan)
479 u32 chid = chan->base.chid;
482 nv_error(priv, "%s engine fault on channel %d, recovering...\n",
483 nv_subdev(engine)->name, chid);
485 nv_mask(priv, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800);
486 chan->state = KILLED;
488 spin_lock_irqsave(&priv->base.lock, flags);
489 priv->mask |= 1ULL << nv_engidx(engine);
490 spin_unlock_irqrestore(&priv->base.lock, flags);
491 schedule_work(&priv->fault);
495 gk104_fifo_swmthd(struct gk104_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
497 struct gk104_fifo_chan *chan = NULL;
498 struct nvkm_handle *bind;
502 spin_lock_irqsave(&priv->base.lock, flags);
503 if (likely(chid >= priv->base.min && chid <= priv->base.max))
504 chan = (void *)priv->base.channel[chid];
508 bind = nvkm_namedb_get_class(nv_namedb(chan), 0x906e);
510 if (!mthd || !nv_call(bind->object, mthd, data))
512 nvkm_namedb_put(bind);
516 spin_unlock_irqrestore(&priv->base.lock, flags);
520 static const struct nvkm_enum
521 gk104_fifo_bind_reason[] = {
522 { 0x01, "BIND_NOT_UNBOUND" },
523 { 0x02, "SNOOP_WITHOUT_BAR1" },
524 { 0x03, "UNBIND_WHILE_RUNNING" },
525 { 0x05, "INVALID_RUNLIST" },
526 { 0x06, "INVALID_CTX_TGT" },
527 { 0x0b, "UNBIND_WHILE_PARKED" },
532 gk104_fifo_intr_bind(struct gk104_fifo_priv *priv)
534 u32 intr = nv_rd32(priv, 0x00252c);
535 u32 code = intr & 0x000000ff;
536 const struct nvkm_enum *en;
539 en = nvkm_enum_find(gk104_fifo_bind_reason, code);
541 snprintf(enunk, sizeof(enunk), "UNK%02x", code);
543 nv_error(priv, "BIND_ERROR [ %s ]\n", en ? en->name : enunk);
546 static const struct nvkm_enum
547 gk104_fifo_sched_reason[] = {
548 { 0x0a, "CTXSW_TIMEOUT" },
553 gk104_fifo_intr_sched_ctxsw(struct gk104_fifo_priv *priv)
555 struct nvkm_engine *engine;
556 struct gk104_fifo_chan *chan;
559 for (engn = 0; engn < ARRAY_SIZE(fifo_engine); engn++) {
560 u32 stat = nv_rd32(priv, 0x002640 + (engn * 0x04));
561 u32 busy = (stat & 0x80000000);
562 u32 next = (stat & 0x07ff0000) >> 16;
563 u32 chsw = (stat & 0x00008000);
564 u32 save = (stat & 0x00004000);
565 u32 load = (stat & 0x00002000);
566 u32 prev = (stat & 0x000007ff);
567 u32 chid = load ? next : prev;
571 if (!(chan = (void *)priv->base.channel[chid]))
573 if (!(engine = gk104_fifo_engine(priv, engn)))
575 gk104_fifo_recover(priv, engine, chan);
581 gk104_fifo_intr_sched(struct gk104_fifo_priv *priv)
583 u32 intr = nv_rd32(priv, 0x00254c);
584 u32 code = intr & 0x000000ff;
585 const struct nvkm_enum *en;
588 en = nvkm_enum_find(gk104_fifo_sched_reason, code);
590 snprintf(enunk, sizeof(enunk), "UNK%02x", code);
592 nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk);
596 gk104_fifo_intr_sched_ctxsw(priv);
604 gk104_fifo_intr_chsw(struct gk104_fifo_priv *priv)
606 u32 stat = nv_rd32(priv, 0x00256c);
607 nv_error(priv, "CHSW_ERROR 0x%08x\n", stat);
608 nv_wr32(priv, 0x00256c, stat);
612 gk104_fifo_intr_dropped_fault(struct gk104_fifo_priv *priv)
614 u32 stat = nv_rd32(priv, 0x00259c);
615 nv_error(priv, "DROPPED_MMU_FAULT 0x%08x\n", stat);
618 static const struct nvkm_enum
619 gk104_fifo_fault_engine[] = {
620 { 0x00, "GR", NULL, NVDEV_ENGINE_GR },
621 { 0x03, "IFB", NULL, NVDEV_ENGINE_IFB },
622 { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
623 { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
624 { 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO },
625 { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO },
626 { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO },
627 { 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD },
628 { 0x11, "MSPPP", NULL, NVDEV_ENGINE_MSPPP },
630 { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_MSPDEC },
631 { 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },
632 { 0x16, "CE1", NULL, NVDEV_ENGINE_CE1 },
634 { 0x19, "MSENC", NULL, NVDEV_ENGINE_MSENC },
635 { 0x1b, "CE2", NULL, NVDEV_ENGINE_CE2 },
639 static const struct nvkm_enum
640 gk104_fifo_fault_reason[] = {
642 { 0x01, "PDE_SIZE" },
644 { 0x03, "VA_LIMIT_VIOLATION" },
645 { 0x04, "UNBOUND_INST_BLOCK" },
646 { 0x05, "PRIV_VIOLATION" },
647 { 0x06, "RO_VIOLATION" },
648 { 0x07, "WO_VIOLATION" },
649 { 0x08, "PITCH_MASK_VIOLATION" },
650 { 0x09, "WORK_CREATION" },
651 { 0x0a, "UNSUPPORTED_APERTURE" },
652 { 0x0b, "COMPRESSION_FAILURE" },
653 { 0x0c, "UNSUPPORTED_KIND" },
654 { 0x0d, "REGION_VIOLATION" },
655 { 0x0e, "BOTH_PTES_VALID" },
656 { 0x0f, "INFO_TYPE_POISONED" },
660 static const struct nvkm_enum
661 gk104_fifo_fault_hubclient[] = {
669 { 0x07, "HOST_CPU" },
670 { 0x08, "HOST_CPU_NB" },
681 { 0x13, "RASTERTWOD" },
697 static const struct nvkm_enum
698 gk104_fifo_fault_gpcclient[] = {
699 { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" },
700 { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" },
701 { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" },
702 { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" },
710 { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" },
711 { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" },
712 { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" },
713 { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" },
715 { 0x20, "LTP_UTLB_0" },
716 { 0x21, "LTP_UTLB_1" },
717 { 0x22, "LTP_UTLB_2" },
718 { 0x23, "LTP_UTLB_3" },
719 { 0x24, "GPC_RGG_UTLB" },
724 gk104_fifo_intr_fault(struct gk104_fifo_priv *priv, int unit)
726 u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
727 u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
728 u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
729 u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
730 u32 gpc = (stat & 0x1f000000) >> 24;
731 u32 client = (stat & 0x00001f00) >> 8;
732 u32 write = (stat & 0x00000080);
733 u32 hub = (stat & 0x00000040);
734 u32 reason = (stat & 0x0000000f);
735 struct nvkm_object *engctx = NULL, *object;
736 struct nvkm_engine *engine = NULL;
737 const struct nvkm_enum *er, *eu, *ec;
743 er = nvkm_enum_find(gk104_fifo_fault_reason, reason);
745 snprintf(erunk, sizeof(erunk), "UNK%02X", reason);
747 eu = nvkm_enum_find(gk104_fifo_fault_engine, unit);
750 case NVDEV_SUBDEV_BAR:
751 nv_mask(priv, 0x001704, 0x00000000, 0x00000000);
753 case NVDEV_SUBDEV_INSTMEM:
754 nv_mask(priv, 0x001714, 0x00000000, 0x00000000);
756 case NVDEV_ENGINE_IFB:
757 nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
760 engine = nvkm_engine(priv, eu->data2);
762 engctx = nvkm_engctx_get(engine, inst);
766 snprintf(euunk, sizeof(euunk), "UNK%02x", unit);
770 ec = nvkm_enum_find(gk104_fifo_fault_hubclient, client);
772 ec = nvkm_enum_find(gk104_fifo_fault_gpcclient, client);
773 snprintf(gpcid, sizeof(gpcid), "%d", gpc);
777 snprintf(ecunk, sizeof(ecunk), "UNK%02x", client);
779 nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on "
780 "channel 0x%010llx [%s]\n", write ? "write" : "read",
781 (u64)vahi << 32 | valo, er ? er->name : erunk,
782 eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/",
783 ec ? ec->name : ecunk, (u64)inst << 12,
784 nvkm_client_name(engctx));
788 switch (nv_mclass(object)) {
789 case KEPLER_CHANNEL_GPFIFO_A:
790 case MAXWELL_CHANNEL_GPFIFO_A:
791 gk104_fifo_recover(priv, engine, (void *)object);
794 object = object->parent;
797 nvkm_engctx_put(engctx);
800 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = {
801 { 0x00000001, "MEMREQ" },
802 { 0x00000002, "MEMACK_TIMEOUT" },
803 { 0x00000004, "MEMACK_EXTRA" },
804 { 0x00000008, "MEMDAT_TIMEOUT" },
805 { 0x00000010, "MEMDAT_EXTRA" },
806 { 0x00000020, "MEMFLUSH" },
807 { 0x00000040, "MEMOP" },
808 { 0x00000080, "LBCONNECT" },
809 { 0x00000100, "LBREQ" },
810 { 0x00000200, "LBACK_TIMEOUT" },
811 { 0x00000400, "LBACK_EXTRA" },
812 { 0x00000800, "LBDAT_TIMEOUT" },
813 { 0x00001000, "LBDAT_EXTRA" },
814 { 0x00002000, "GPFIFO" },
815 { 0x00004000, "GPPTR" },
816 { 0x00008000, "GPENTRY" },
817 { 0x00010000, "GPCRC" },
818 { 0x00020000, "PBPTR" },
819 { 0x00040000, "PBENTRY" },
820 { 0x00080000, "PBCRC" },
821 { 0x00100000, "XBARCONNECT" },
822 { 0x00200000, "METHOD" },
823 { 0x00400000, "METHODCRC" },
824 { 0x00800000, "DEVICE" },
825 { 0x02000000, "SEMAPHORE" },
826 { 0x04000000, "ACQUIRE" },
827 { 0x08000000, "PRI" },
828 { 0x20000000, "NO_CTXSW_SEG" },
829 { 0x40000000, "PBSEG" },
830 { 0x80000000, "SIGNATURE" },
835 gk104_fifo_intr_pbdma_0(struct gk104_fifo_priv *priv, int unit)
837 u32 mask = nv_rd32(priv, 0x04010c + (unit * 0x2000));
838 u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)) & mask;
839 u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
840 u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
841 u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff;
842 u32 subc = (addr & 0x00070000) >> 16;
843 u32 mthd = (addr & 0x00003ffc);
846 if (stat & 0x00800000) {
847 if (!gk104_fifo_swmthd(priv, chid, mthd, data))
849 nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
853 nv_error(priv, "PBDMA%d:", unit);
854 nvkm_bitfield_print(gk104_fifo_pbdma_intr_0, show);
857 "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
859 nvkm_client_name_for_fifo_chid(&priv->base, chid),
863 nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
866 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = {
867 { 0x00000001, "HCE_RE_ILLEGAL_OP" },
868 { 0x00000002, "HCE_RE_ALIGNB" },
869 { 0x00000004, "HCE_PRIV" },
870 { 0x00000008, "HCE_ILLEGAL_MTHD" },
871 { 0x00000010, "HCE_ILLEGAL_CLASS" },
876 gk104_fifo_intr_pbdma_1(struct gk104_fifo_priv *priv, int unit)
878 u32 mask = nv_rd32(priv, 0x04014c + (unit * 0x2000));
879 u32 stat = nv_rd32(priv, 0x040148 + (unit * 0x2000)) & mask;
880 u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff;
883 nv_error(priv, "PBDMA%d:", unit);
884 nvkm_bitfield_print(gk104_fifo_pbdma_intr_1, stat);
886 nv_error(priv, "PBDMA%d: ch %d %08x %08x\n", unit, chid,
887 nv_rd32(priv, 0x040150 + (unit * 0x2000)),
888 nv_rd32(priv, 0x040154 + (unit * 0x2000)));
891 nv_wr32(priv, 0x040148 + (unit * 0x2000), stat);
895 gk104_fifo_intr_runlist(struct gk104_fifo_priv *priv)
897 u32 mask = nv_rd32(priv, 0x002a00);
899 u32 engn = __ffs(mask);
900 wake_up(&priv->engine[engn].wait);
901 nv_wr32(priv, 0x002a00, 1 << engn);
902 mask &= ~(1 << engn);
907 gk104_fifo_intr_engine(struct gk104_fifo_priv *priv)
909 nvkm_fifo_uevent(&priv->base);
913 gk104_fifo_intr(struct nvkm_subdev *subdev)
915 struct gk104_fifo_priv *priv = (void *)subdev;
916 u32 mask = nv_rd32(priv, 0x002140);
917 u32 stat = nv_rd32(priv, 0x002100) & mask;
919 if (stat & 0x00000001) {
920 gk104_fifo_intr_bind(priv);
921 nv_wr32(priv, 0x002100, 0x00000001);
925 if (stat & 0x00000010) {
926 nv_error(priv, "PIO_ERROR\n");
927 nv_wr32(priv, 0x002100, 0x00000010);
931 if (stat & 0x00000100) {
932 gk104_fifo_intr_sched(priv);
933 nv_wr32(priv, 0x002100, 0x00000100);
937 if (stat & 0x00010000) {
938 gk104_fifo_intr_chsw(priv);
939 nv_wr32(priv, 0x002100, 0x00010000);
943 if (stat & 0x00800000) {
944 nv_error(priv, "FB_FLUSH_TIMEOUT\n");
945 nv_wr32(priv, 0x002100, 0x00800000);
949 if (stat & 0x01000000) {
950 nv_error(priv, "LB_ERROR\n");
951 nv_wr32(priv, 0x002100, 0x01000000);
955 if (stat & 0x08000000) {
956 gk104_fifo_intr_dropped_fault(priv);
957 nv_wr32(priv, 0x002100, 0x08000000);
961 if (stat & 0x10000000) {
962 u32 mask = nv_rd32(priv, 0x00259c);
964 u32 unit = __ffs(mask);
965 gk104_fifo_intr_fault(priv, unit);
966 nv_wr32(priv, 0x00259c, (1 << unit));
967 mask &= ~(1 << unit);
972 if (stat & 0x20000000) {
973 u32 mask = nv_rd32(priv, 0x0025a0);
975 u32 unit = __ffs(mask);
976 gk104_fifo_intr_pbdma_0(priv, unit);
977 gk104_fifo_intr_pbdma_1(priv, unit);
978 nv_wr32(priv, 0x0025a0, (1 << unit));
979 mask &= ~(1 << unit);
984 if (stat & 0x40000000) {
985 gk104_fifo_intr_runlist(priv);
989 if (stat & 0x80000000) {
990 nv_wr32(priv, 0x002100, 0x80000000);
991 gk104_fifo_intr_engine(priv);
996 nv_error(priv, "INTR 0x%08x\n", stat);
997 nv_mask(priv, 0x002140, stat, 0x00000000);
998 nv_wr32(priv, 0x002100, stat);
1003 gk104_fifo_uevent_init(struct nvkm_event *event, int type, int index)
1005 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
1006 nv_mask(fifo, 0x002140, 0x80000000, 0x80000000);
1010 gk104_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
1012 struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
1013 nv_mask(fifo, 0x002140, 0x80000000, 0x00000000);
1016 static const struct nvkm_event_func
1017 gk104_fifo_uevent_func = {
1018 .ctor = nvkm_fifo_uevent_ctor,
1019 .init = gk104_fifo_uevent_init,
1020 .fini = gk104_fifo_uevent_fini,
1024 gk104_fifo_fini(struct nvkm_object *object, bool suspend)
1026 struct gk104_fifo_priv *priv = (void *)object;
1029 ret = nvkm_fifo_fini(&priv->base, suspend);
1033 /* allow mmu fault interrupts, even when we're not using fifo */
1034 nv_mask(priv, 0x002140, 0x10000000, 0x10000000);
1039 gk104_fifo_init(struct nvkm_object *object)
1041 struct gk104_fifo_priv *priv = (void *)object;
1044 ret = nvkm_fifo_init(&priv->base);
1048 /* enable all available PBDMA units */
1049 nv_wr32(priv, 0x000204, 0xffffffff);
1050 priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204));
1051 nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr);
1054 for (i = 0; i < priv->spoon_nr; i++) {
1055 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
1056 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
1057 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
1061 for (i = 0; i < priv->spoon_nr; i++) {
1062 nv_wr32(priv, 0x040148 + (i * 0x2000), 0xffffffff); /* INTR */
1063 nv_wr32(priv, 0x04014c + (i * 0x2000), 0xffffffff); /* INTREN */
1066 nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
1068 nv_wr32(priv, 0x002100, 0xffffffff);
1069 nv_wr32(priv, 0x002140, 0x7fffffff);
1074 gk104_fifo_dtor(struct nvkm_object *object)
1076 struct gk104_fifo_priv *priv = (void *)object;
1079 nvkm_gpuobj_unmap(&priv->user.bar);
1080 nvkm_gpuobj_ref(NULL, &priv->user.mem);
1082 for (i = 0; i < FIFO_ENGINE_NR; i++) {
1083 nvkm_gpuobj_ref(NULL, &priv->engine[i].runlist[1]);
1084 nvkm_gpuobj_ref(NULL, &priv->engine[i].runlist[0]);
1087 nvkm_fifo_destroy(&priv->base);
1091 gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
1092 struct nvkm_oclass *oclass, void *data, u32 size,
1093 struct nvkm_object **pobject)
1095 struct gk104_fifo_impl *impl = (void *)oclass;
1096 struct gk104_fifo_priv *priv;
1099 ret = nvkm_fifo_create(parent, engine, oclass, 0,
1100 impl->channels - 1, &priv);
1101 *pobject = nv_object(priv);
1105 INIT_WORK(&priv->fault, gk104_fifo_recover_work);
1107 for (i = 0; i < FIFO_ENGINE_NR; i++) {
1108 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
1109 0, &priv->engine[i].runlist[0]);
1113 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
1114 0, &priv->engine[i].runlist[1]);
1118 init_waitqueue_head(&priv->engine[i].wait);
1121 ret = nvkm_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200,
1122 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem);
1126 ret = nvkm_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
1131 ret = nvkm_event_init(&gk104_fifo_uevent_func, 1, 1, &priv->base.uevent);
1135 nv_subdev(priv)->unit = 0x00000100;
1136 nv_subdev(priv)->intr = gk104_fifo_intr;
1137 nv_engine(priv)->cclass = &gk104_fifo_cclass;
1138 nv_engine(priv)->sclass = gk104_fifo_sclass;
1142 struct nvkm_oclass *
1143 gk104_fifo_oclass = &(struct gk104_fifo_impl) {
1144 .base.handle = NV_ENGINE(FIFO, 0xe0),
1145 .base.ofuncs = &(struct nvkm_ofuncs) {
1146 .ctor = gk104_fifo_ctor,
1147 .dtor = gk104_fifo_dtor,
1148 .init = gk104_fifo_init,
1149 .fini = gk104_fifo_fini,