drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c

   1 /*
   2  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "mdp5_kms.h"
  20
  21 #include <linux/sort.h>
  22 #include <drm/drm_mode.h>
  23 #include "drm_crtc.h"
  24 #include "drm_crtc_helper.h"
  25 #include "drm_flip_work.h"
  26
  27 #define CURSOR_WIDTH    64
  28 #define CURSOR_HEIGHT   64
  29
  30 struct mdp5_crtc {
  31         struct drm_crtc base;
  32         int id;
  33         bool enabled;
  34
  35         /* layer mixer used for this CRTC (+ its lock): */
  36 #define GET_LM_ID(crtc_id)      ((crtc_id == 3) ? 5 : crtc_id)
  37         int lm;
  38         spinlock_t lm_lock;     /* protect REG_MDP5_LM_* registers */
  39
  40         /* CTL used for this CRTC: */
  41         struct mdp5_ctl *ctl;
  42
  43         /* if there is a pending flip, these will be non-null: */
  44         struct drm_pending_vblank_event *event;
  45
  46         /* Bits have been flushed at the last commit,
  47          * used to decide if a vsync has happened since last commit.
  48          */
  49         u32 flushed_mask;
  50
  51 #define PENDING_CURSOR 0x1
  52 #define PENDING_FLIP   0x2
  53         atomic_t pending;
  54
  55         /* for unref'ing cursor bo's after scanout completes: */
  56         struct drm_flip_work unref_cursor_work;
  57
  58         struct mdp_irq vblank;
  59         struct mdp_irq err;
  60         struct mdp_irq pp_done;
  61
  62         struct completion pp_completion;
  63
  64         bool cmd_mode;
  65
  66         struct {
  67                 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
  68                 spinlock_t lock;
  69
  70                 /* current cursor being scanned out: */
  71                 struct drm_gem_object *scanout_bo;
  72                 uint32_t width, height;
  73                 uint32_t x, y;
  74         } cursor;
  75 };
  76 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
  77
  78 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
  79 {
  80         struct msm_drm_private *priv = crtc->dev->dev_private;
  81         return to_mdp5_kms(to_mdp_kms(priv->kms));
  82 }
  83
  84 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
  85 {
  86         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  87
  88         atomic_or(pending, &mdp5_crtc->pending);
  89         mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
  90 }
  91
  92 static void request_pp_done_pending(struct drm_crtc *crtc)
  93 {
  94         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  95         reinit_completion(&mdp5_crtc->pp_completion);
  96 }
  97
  98 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
  99 {
 100         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 101
 102         DBG("%s: flush=%08x", crtc->name, flush_mask);
 103         return mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask);
 104 }
 105
 106 /*
 107  * flush updates, to make sure hw is updated to new scanout fb,
 108  * so that we can safely queue unref to current fb (ie. next
 109  * vblank we know hw is done w/ previous scanout_fb).
 110  */
 111 static u32 crtc_flush_all(struct drm_crtc *crtc)
 112 {
 113         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 114         struct drm_plane *plane;
 115         uint32_t flush_mask = 0;
 116
 117         /* this should not happen: */
 118         if (WARN_ON(!mdp5_crtc->ctl))
 119                 return 0;
 120
 121         drm_atomic_crtc_for_each_plane(plane, crtc) {
 122                 flush_mask |= mdp5_plane_get_flush(plane);
 123         }
 124
 125         flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm);
 126
 127         return crtc_flush(crtc, flush_mask);
 128 }
 129
 130 /* if file!=NULL, this is preclose potential cancel-flip path */
 131 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
 132 {
 133         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 134         struct drm_device *dev = crtc->dev;
 135         struct drm_pending_vblank_event *event;
 136         unsigned long flags;
 137
 138         spin_lock_irqsave(&dev->event_lock, flags);
 139         event = mdp5_crtc->event;
 140         if (event) {
 141                 /* if regular vblank case (!file) or if cancel-flip from
 142                  * preclose on file that requested flip, then send the
 143                  * event:
 144                  */
 145                 if (!file || (event->base.file_priv == file)) {
 146                         mdp5_crtc->event = NULL;
 147                         DBG("%s: send event: %p", crtc->name, event);
 148                         drm_crtc_send_vblank_event(crtc, event);
 149                 }
 150         }
 151         spin_unlock_irqrestore(&dev->event_lock, flags);
 152
 153         if (mdp5_crtc->ctl && !crtc->state->enable) {
 154                 /* set STAGE_UNUSED for all layers */
 155                 mdp5_ctl_blend(mdp5_crtc->ctl, NULL, 0, 0);
 156                 mdp5_crtc->ctl = NULL;
 157         }
 158 }
 159
 160 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
 161 {
 162         struct mdp5_crtc *mdp5_crtc =
 163                 container_of(work, struct mdp5_crtc, unref_cursor_work);
 164         struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
 165
 166         msm_gem_put_iova(val, mdp5_kms->id);
 167         drm_gem_object_unreference_unlocked(val);
 168 }
 169
 170 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
 171 {
 172         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 173
 174         drm_crtc_cleanup(crtc);
 175         drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
 176
 177         kfree(mdp5_crtc);
 178 }
 179
 180 /*
 181  * blend_setup() - blend all the planes of a CRTC
 182  *
 183  * If no base layer is available, border will be enabled as the base layer.
 184  * Otherwise all layers will be blended based on their stage calculated
 185  * in mdp5_crtc_atomic_check.
 186  */
 187 static void blend_setup(struct drm_crtc *crtc)
 188 {
 189         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 190         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 191         struct drm_plane *plane;
 192         const struct mdp5_cfg_hw *hw_cfg;
 193         struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
 194         const struct mdp_format *format;
 195         uint32_t lm = mdp5_crtc->lm;
 196         uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
 197         unsigned long flags;
 198         uint8_t stage[STAGE_MAX + 1];
 199         int i, plane_cnt = 0;
 200 #define blender(stage)  ((stage) - STAGE0)
 201
 202         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 203
 204         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 205
 206         /* ctl could be released already when we are shutting down: */
 207         if (!mdp5_crtc->ctl)
 208                 goto out;
 209
 210         /* Collect all plane information */
 211         drm_atomic_crtc_for_each_plane(plane, crtc) {
 212                 pstate = to_mdp5_plane_state(plane->state);
 213                 pstates[pstate->stage] = pstate;
 214                 stage[pstate->stage] = mdp5_plane_pipe(plane);
 215                 plane_cnt++;
 216         }
 217
 218         if (!pstates[STAGE_BASE]) {
 219                 ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
 220                 DBG("Border Color is enabled");
 221         }
 222
 223         /* The reset for blending */
 224         for (i = STAGE0; i <= STAGE_MAX; i++) {
 225                 if (!pstates[i])
 226                         continue;
 227
 228                 format = to_mdp_format(
 229                         msm_framebuffer_format(pstates[i]->base.fb));
 230                 plane = pstates[i]->base.plane;
 231                 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 232                         MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
 233                 fg_alpha = pstates[i]->alpha;
 234                 bg_alpha = 0xFF - pstates[i]->alpha;
 235                 DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
 236
 237                 if (format->alpha_enable && pstates[i]->premultiplied) {
 238                         blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 239                                 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 240                         if (fg_alpha != 0xff) {
 241                                 bg_alpha = fg_alpha;
 242                                 blend_op |=
 243                                         MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
 244                                         MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
 245                         } else {
 246                                 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 247                         }
 248                 } else if (format->alpha_enable) {
 249                         blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
 250                                 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 251                         if (fg_alpha != 0xff) {
 252                                 bg_alpha = fg_alpha;
 253                                 blend_op |=
 254                                        MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
 255                                        MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
 256                                        MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
 257                                        MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
 258                         } else {
 259                                 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 260                         }
 261                 }
 262
 263                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
 264                                 blender(i)), blend_op);
 265                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
 266                                 blender(i)), fg_alpha);
 267                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
 268                                 blender(i)), bg_alpha);
 269         }
 270
 271         mdp5_ctl_blend(mdp5_crtc->ctl, stage, plane_cnt, ctl_blend_flags);
 272
 273 out:
 274         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 275 }
 276
 277 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
 278 {
 279         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 280         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 281         unsigned long flags;
 282         struct drm_display_mode *mode;
 283
 284         if (WARN_ON(!crtc->state))
 285                 return;
 286
 287         mode = &crtc->state->adjusted_mode;
 288
 289         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 290                         crtc->name, mode->base.id, mode->name,
 291                         mode->vrefresh, mode->clock,
 292                         mode->hdisplay, mode->hsync_start,
 293                         mode->hsync_end, mode->htotal,
 294                         mode->vdisplay, mode->vsync_start,
 295                         mode->vsync_end, mode->vtotal,
 296                         mode->type, mode->flags);
 297
 298         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 299         mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(mdp5_crtc->lm),
 300                         MDP5_LM_OUT_SIZE_WIDTH(mode->hdisplay) |
 301                         MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
 302         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 303 }
 304
 305 static void mdp5_crtc_disable(struct drm_crtc *crtc)
 306 {
 307         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 308         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 309
 310         DBG("%s", crtc->name);
 311
 312         if (WARN_ON(!mdp5_crtc->enabled))
 313                 return;
 314
 315         if (mdp5_crtc->cmd_mode)
 316                 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
 317
 318         mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
 319         mdp5_disable(mdp5_kms);
 320
 321         mdp5_crtc->enabled = false;
 322 }
 323
 324 static void mdp5_crtc_enable(struct drm_crtc *crtc)
 325 {
 326         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 327         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 328
 329         DBG("%s", crtc->name);
 330
 331         if (WARN_ON(mdp5_crtc->enabled))
 332                 return;
 333
 334         mdp5_enable(mdp5_kms);
 335         mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
 336
 337         if (mdp5_crtc->cmd_mode)
 338                 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
 339
 340         mdp5_crtc->enabled = true;
 341 }
 342
 343 struct plane_state {
 344         struct drm_plane *plane;
 345         struct mdp5_plane_state *state;
 346 };
 347
 348 static int pstate_cmp(const void *a, const void *b)
 349 {
 350         struct plane_state *pa = (struct plane_state *)a;
 351         struct plane_state *pb = (struct plane_state *)b;
 352         return pa->state->zpos - pb->state->zpos;
 353 }
 354
 355 /* is there a helper for this? */
 356 static bool is_fullscreen(struct drm_crtc_state *cstate,
 357                 struct drm_plane_state *pstate)
 358 {
 359         return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) &&
 360                 ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) &&
 361                 ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay);
 362 }
 363
 364 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
 365                 struct drm_crtc_state *state)
 366 {
 367         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 368         struct drm_plane *plane;
 369         struct drm_device *dev = crtc->dev;
 370         struct plane_state pstates[STAGE_MAX + 1];
 371         const struct mdp5_cfg_hw *hw_cfg;
 372         const struct drm_plane_state *pstate;
 373         int cnt = 0, base = 0, i;
 374
 375         DBG("%s: check", crtc->name);
 376
 377         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 378                 pstates[cnt].plane = plane;
 379                 pstates[cnt].state = to_mdp5_plane_state(pstate);
 380
 381                 cnt++;
 382         }
 383
 384         /* assign a stage based on sorted zpos property */
 385         sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
 386
 387         /* if the bottom-most layer is not fullscreen, we need to use
 388          * it for solid-color:
 389          */
 390         if ((cnt > 0) && !is_fullscreen(state, &pstates[0].state->base))
 391                 base++;
 392
 393         /* verify that there are not too many planes attached to crtc
 394          * and that we don't have conflicting mixer stages:
 395          */
 396         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 397
 398         if ((cnt + base) >= hw_cfg->lm.nb_stages) {
 399                 dev_err(dev->dev, "too many planes! cnt=%d, base=%d\n", cnt, base);
 400                 return -EINVAL;
 401         }
 402
 403         for (i = 0; i < cnt; i++) {
 404                 pstates[i].state->stage = STAGE_BASE + i + base;
 405                 DBG("%s: assign pipe %s on stage=%d", crtc->name,
 406                                 pstates[i].plane->name,
 407                                 pstates[i].state->stage);
 408         }
 409
 410         return 0;
 411 }
 412
 413 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,
 414                                    struct drm_crtc_state *old_crtc_state)
 415 {
 416         DBG("%s: begin", crtc->name);
 417 }
 418
 419 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
 420                                    struct drm_crtc_state *old_crtc_state)
 421 {
 422         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 423         struct drm_device *dev = crtc->dev;
 424         unsigned long flags;
 425
 426         DBG("%s: event: %p", crtc->name, crtc->state->event);
 427
 428         WARN_ON(mdp5_crtc->event);
 429
 430         spin_lock_irqsave(&dev->event_lock, flags);
 431         mdp5_crtc->event = crtc->state->event;
 432         spin_unlock_irqrestore(&dev->event_lock, flags);
 433
 434         /*
 435          * If no CTL has been allocated in mdp5_crtc_atomic_check(),
 436          * it means we are trying to flush a CRTC whose state is disabled:
 437          * nothing else needs to be done.
 438          */
 439         if (unlikely(!mdp5_crtc->ctl))
 440                 return;
 441
 442         blend_setup(crtc);
 443
 444         /* PP_DONE irq is only used by command mode for now.
 445          * It is better to request pending before FLUSH and START trigger
 446          * to make sure no pp_done irq missed.
 447          * This is safe because no pp_done will happen before SW trigger
 448          * in command mode.
 449          */
 450         if (mdp5_crtc->cmd_mode)
 451                 request_pp_done_pending(crtc);
 452
 453         mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
 454
 455         request_pending(crtc, PENDING_FLIP);
 456 }
 457
 458 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
 459 {
 460         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 461         uint32_t xres = crtc->mode.hdisplay;
 462         uint32_t yres = crtc->mode.vdisplay;
 463
 464         /*
 465          * Cursor Region Of Interest (ROI) is a plane read from cursor
 466          * buffer to render. The ROI region is determined by the visibility of
 467          * the cursor point. In the default Cursor image the cursor point will
 468          * be at the top left of the cursor image, unless it is specified
 469          * otherwise using hotspot feature.
 470          *
 471          * If the cursor point reaches the right (xres - x < cursor.width) or
 472          * bottom (yres - y < cursor.height) boundary of the screen, then ROI
 473          * width and ROI height need to be evaluated to crop the cursor image
 474          * accordingly.
 475          * (xres-x) will be new cursor width when x > (xres - cursor.width)
 476          * (yres-y) will be new cursor height when y > (yres - cursor.height)
 477          */
 478         *roi_w = min(mdp5_crtc->cursor.width, xres -
 479                         mdp5_crtc->cursor.x);
 480         *roi_h = min(mdp5_crtc->cursor.height, yres -
 481                         mdp5_crtc->cursor.y);
 482 }
 483
 484 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
 485                 struct drm_file *file, uint32_t handle,
 486                 uint32_t width, uint32_t height)
 487 {
 488         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 489         struct drm_device *dev = crtc->dev;
 490         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 491         struct drm_gem_object *cursor_bo, *old_bo = NULL;
 492         uint32_t blendcfg, stride;
 493         uint64_t cursor_addr;
 494         int ret, lm;
 495         enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
 496         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 497         uint32_t roi_w, roi_h;
 498         bool cursor_enable = true;
 499         unsigned long flags;
 500
 501         if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
 502                 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
 503                 return -EINVAL;
 504         }
 505
 506         if (NULL == mdp5_crtc->ctl)
 507                 return -EINVAL;
 508
 509         if (!handle) {
 510                 DBG("Cursor off");
 511                 cursor_enable = false;
 512                 goto set_cursor;
 513         }
 514
 515         cursor_bo = drm_gem_object_lookup(file, handle);
 516         if (!cursor_bo)
 517                 return -ENOENT;
 518
 519         ret = msm_gem_get_iova(cursor_bo, mdp5_kms->id, &cursor_addr);
 520         if (ret)
 521                 return -EINVAL;
 522
 523         lm = mdp5_crtc->lm;
 524         stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB8888, 0);
 525
 526         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 527         old_bo = mdp5_crtc->cursor.scanout_bo;
 528
 529         mdp5_crtc->cursor.scanout_bo = cursor_bo;
 530         mdp5_crtc->cursor.width = width;
 531         mdp5_crtc->cursor.height = height;
 532
 533         get_roi(crtc, &roi_w, &roi_h);
 534
 535         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
 536         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
 537                         MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
 538         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
 539                         MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
 540                         MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
 541         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
 542                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 543                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 544         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr);
 545
 546         blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
 547         blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
 548         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
 549
 550         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 551
 552 set_cursor:
 553         ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, 0, cursor_enable);
 554         if (ret) {
 555                 dev_err(dev->dev, "failed to %sable cursor: %d\n",
 556                                 cursor_enable ? "en" : "dis", ret);
 557                 goto end;
 558         }
 559
 560         crtc_flush(crtc, flush_mask);
 561
 562 end:
 563         if (old_bo) {
 564                 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
 565                 /* enable vblank to complete cursor work: */
 566                 request_pending(crtc, PENDING_CURSOR);
 567         }
 568         return ret;
 569 }
 570
 571 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 572 {
 573         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 574         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 575         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 576         uint32_t roi_w;
 577         uint32_t roi_h;
 578         unsigned long flags;
 579
 580         /* In case the CRTC is disabled, just drop the cursor update */
 581         if (unlikely(!crtc->state->enable))
 582                 return 0;
 583
 584         mdp5_crtc->cursor.x = x = max(x, 0);
 585         mdp5_crtc->cursor.y = y = max(y, 0);
 586
 587         get_roi(crtc, &roi_w, &roi_h);
 588
 589         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 590         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(mdp5_crtc->lm),
 591                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 592                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 593         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(mdp5_crtc->lm),
 594                         MDP5_LM_CURSOR_START_XY_Y_START(y) |
 595                         MDP5_LM_CURSOR_START_XY_X_START(x));
 596         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 597
 598         crtc_flush(crtc, flush_mask);
 599
 600         return 0;
 601 }
 602
 603 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
 604         .set_config = drm_atomic_helper_set_config,
 605         .destroy = mdp5_crtc_destroy,
 606         .page_flip = drm_atomic_helper_page_flip,
 607         .set_property = drm_atomic_helper_crtc_set_property,
 608         .reset = drm_atomic_helper_crtc_reset,
 609         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 610         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 611         .cursor_set = mdp5_crtc_cursor_set,
 612         .cursor_move = mdp5_crtc_cursor_move,
 613 };
 614
 615 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
 616         .mode_set_nofb = mdp5_crtc_mode_set_nofb,
 617         .disable = mdp5_crtc_disable,
 618         .enable = mdp5_crtc_enable,
 619         .atomic_check = mdp5_crtc_atomic_check,
 620         .atomic_begin = mdp5_crtc_atomic_begin,
 621         .atomic_flush = mdp5_crtc_atomic_flush,
 622 };
 623
 624 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
 625 {
 626         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
 627         struct drm_crtc *crtc = &mdp5_crtc->base;
 628         struct msm_drm_private *priv = crtc->dev->dev_private;
 629         unsigned pending;
 630
 631         mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
 632
 633         pending = atomic_xchg(&mdp5_crtc->pending, 0);
 634
 635         if (pending & PENDING_FLIP) {
 636                 complete_flip(crtc, NULL);
 637         }
 638
 639         if (pending & PENDING_CURSOR)
 640                 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
 641 }
 642
 643 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
 644 {
 645         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
 646
 647         DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus);
 648 }
 649
 650 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
 651 {
 652         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
 653                                                                 pp_done);
 654
 655         complete(&mdp5_crtc->pp_completion);
 656 }
 657
 658 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
 659 {
 660         struct drm_device *dev = crtc->dev;
 661         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 662         int ret;
 663
 664         ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
 665                                                 msecs_to_jiffies(50));
 666         if (ret == 0)
 667                 dev_warn(dev->dev, "pp done time out, lm=%d\n", mdp5_crtc->lm);
 668 }
 669
 670 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
 671 {
 672         struct drm_device *dev = crtc->dev;
 673         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 674         int ret;
 675
 676         /* Should not call this function if crtc is disabled. */
 677         if (!mdp5_crtc->ctl)
 678                 return;
 679
 680         ret = drm_crtc_vblank_get(crtc);
 681         if (ret)
 682                 return;
 683
 684         ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
 685                 ((mdp5_ctl_get_commit_status(mdp5_crtc->ctl) &
 686                 mdp5_crtc->flushed_mask) == 0),
 687                 msecs_to_jiffies(50));
 688         if (ret <= 0)
 689                 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
 690
 691         mdp5_crtc->flushed_mask = 0;
 692
 693         drm_crtc_vblank_put(crtc);
 694 }
 695
 696 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
 697 {
 698         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 699         return mdp5_crtc->vblank.irqmask;
 700 }
 701
 702 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
 703                 struct mdp5_interface *intf, struct mdp5_ctl *ctl)
 704 {
 705         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 706         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 707         int lm = mdp5_crtc_get_lm(crtc);
 708
 709         /* now that we know what irq's we want: */
 710         mdp5_crtc->err.irqmask = intf2err(intf->num);
 711         mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf);
 712
 713         if ((intf->type == INTF_DSI) &&
 714                 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
 715                 mdp5_crtc->pp_done.irqmask = lm2ppdone(lm);
 716                 mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
 717                 mdp5_crtc->cmd_mode = true;
 718         } else {
 719                 mdp5_crtc->pp_done.irqmask = 0;
 720                 mdp5_crtc->pp_done.irq = NULL;
 721                 mdp5_crtc->cmd_mode = false;
 722         }
 723
 724         mdp_irq_update(&mdp5_kms->base);
 725
 726         mdp5_crtc->ctl = ctl;
 727         mdp5_ctl_set_pipeline(ctl, intf, lm);
 728 }
 729
 730 int mdp5_crtc_get_lm(struct drm_crtc *crtc)
 731 {
 732         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 733         return WARN_ON(!crtc) ? -EINVAL : mdp5_crtc->lm;
 734 }
 735
 736 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
 737 {
 738         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 739
 740         if (mdp5_crtc->cmd_mode)
 741                 mdp5_crtc_wait_for_pp_done(crtc);
 742         else
 743                 mdp5_crtc_wait_for_flush_done(crtc);
 744 }
 745
 746 /* initialize crtc */
 747 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
 748                 struct drm_plane *plane, int id)
 749 {
 750         struct drm_crtc *crtc = NULL;
 751         struct mdp5_crtc *mdp5_crtc;
 752
 753         mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
 754         if (!mdp5_crtc)
 755                 return ERR_PTR(-ENOMEM);
 756
 757         crtc = &mdp5_crtc->base;
 758
 759         mdp5_crtc->id = id;
 760         mdp5_crtc->lm = GET_LM_ID(id);
 761
 762         spin_lock_init(&mdp5_crtc->lm_lock);
 763         spin_lock_init(&mdp5_crtc->cursor.lock);
 764         init_completion(&mdp5_crtc->pp_completion);
 765
 766         mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
 767         mdp5_crtc->err.irq = mdp5_crtc_err_irq;
 768
 769         drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp5_crtc_funcs,
 770                                   NULL);
 771
 772         drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
 773                         "unref cursor", unref_cursor_worker);
 774
 775         drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);
 776         plane->crtc = crtc;
 777
 778         return crtc;
 779 }