2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
194 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
195 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
196 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
199 #define ASSIGN_CTX_PML4(ppgtt, reg_state) { \
200 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
201 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
205 ADVANCED_CONTEXT = 0,
210 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
211 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
212 LEGACY_64B_CONTEXT :\
216 FAULT_AND_HALT, /* Debug only */
218 FAULT_AND_CONTINUE /* Unsupported */
220 #define GEN8_CTX_ID_SHIFT 32
221 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
223 static int intel_lr_context_pin(struct drm_i915_gem_request *rq);
224 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
225 struct drm_i915_gem_object *default_ctx_obj);
229 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
231 * @enable_execlists: value of i915.enable_execlists module parameter.
233 * Only certain platforms support Execlists (the prerequisites being
234 * support for Logical Ring Contexts and Aliasing PPGTT or better).
236 * Return: 1 if Execlists is supported and has to be enabled.
238 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
240 WARN_ON(i915.enable_ppgtt == -1);
242 /* On platforms with execlist available, vGPU will only
243 * support execlist mode, no ring buffer mode.
245 if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
248 if (INTEL_INFO(dev)->gen >= 9)
251 if (enable_execlists == 0)
254 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
255 i915.use_mmio_flip >= 0)
262 * intel_execlists_ctx_id() - get the Execlists Context ID
263 * @ctx_obj: Logical Ring Context backing object.
265 * Do not confuse with ctx->id! Unfortunately we have a name overload
266 * here: the old context ID we pass to userspace as a handler so that
267 * they can refer to a context, and the new context ID we pass to the
268 * ELSP so that the GPU can inform us of the context status via
271 * Return: 20-bits globally unique context ID.
273 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
275 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj) +
276 LRC_PPHWSP_PN * PAGE_SIZE;
278 /* LRCA is required to be 4K aligned so the more significant 20 bits
279 * are globally unique */
283 static bool disable_lite_restore_wa(struct intel_engine_cs *ring)
285 struct drm_device *dev = ring->dev;
287 return ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
288 (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) &&
289 (ring->id == VCS || ring->id == VCS2);
292 uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
293 struct intel_engine_cs *ring)
295 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
297 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj) +
298 LRC_PPHWSP_PN * PAGE_SIZE;
300 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
302 desc = GEN8_CTX_VALID;
303 desc |= GEN8_CTX_ADDRESSING_MODE(dev) << GEN8_CTX_ADDRESSING_MODE_SHIFT;
304 if (IS_GEN8(ctx_obj->base.dev))
305 desc |= GEN8_CTX_L3LLC_COHERENT;
306 desc |= GEN8_CTX_PRIVILEGE;
308 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
310 /* TODO: WaDisableLiteRestore when we start using semaphore
311 * signalling between Command Streamers */
312 /* desc |= GEN8_CTX_FORCE_RESTORE; */
314 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
315 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
316 if (disable_lite_restore_wa(ring))
317 desc |= GEN8_CTX_FORCE_RESTORE;
322 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
323 struct drm_i915_gem_request *rq1)
326 struct intel_engine_cs *ring = rq0->ring;
327 struct drm_device *dev = ring->dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
332 desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring);
333 rq1->elsp_submitted++;
338 desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring);
339 rq0->elsp_submitted++;
341 /* You must always write both descriptors in the order below. */
342 spin_lock(&dev_priv->uncore.lock);
343 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
344 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
345 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
347 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0]));
348 /* The context is automatically loaded after the following */
349 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
351 /* ELSP is a wo register, use another nearby reg for posting */
352 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring));
353 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
354 spin_unlock(&dev_priv->uncore.lock);
357 static int execlists_update_context(struct drm_i915_gem_request *rq)
359 struct intel_engine_cs *ring = rq->ring;
360 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
361 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
362 struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
367 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj));
368 WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
370 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
371 reg_state = kmap_atomic(page);
373 reg_state[CTX_RING_TAIL+1] = rq->tail;
374 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
376 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
377 /* True 32b PPGTT with dynamic page allocation: update PDP
378 * registers and point the unallocated PDPs to scratch page.
379 * PML4 is allocated during ppgtt init, so this is not needed
382 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
383 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
384 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
385 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
388 kunmap_atomic(reg_state);
393 static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
394 struct drm_i915_gem_request *rq1)
396 execlists_update_context(rq0);
399 execlists_update_context(rq1);
401 execlists_elsp_write(rq0, rq1);
404 static void execlists_context_unqueue(struct intel_engine_cs *ring)
406 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
407 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
409 assert_spin_locked(&ring->execlist_lock);
412 * If irqs are not active generate a warning as batches that finish
413 * without the irqs may get lost and a GPU Hang may occur.
415 WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
417 if (list_empty(&ring->execlist_queue))
420 /* Try to read in pairs */
421 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
425 } else if (req0->ctx == cursor->ctx) {
426 /* Same ctx: ignore first request, as second request
427 * will update tail past first request's workload */
428 cursor->elsp_submitted = req0->elsp_submitted;
429 list_del(&req0->execlist_link);
430 list_add_tail(&req0->execlist_link,
431 &ring->execlist_retired_req_list);
439 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
441 * WaIdleLiteRestore: make sure we never cause a lite
442 * restore with HEAD==TAIL
444 if (req0->elsp_submitted) {
446 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
447 * as we resubmit the request. See gen8_emit_request()
448 * for where we prepare the padding after the end of the
451 struct intel_ringbuffer *ringbuf;
453 ringbuf = req0->ctx->engine[ring->id].ringbuf;
455 req0->tail &= ringbuf->size - 1;
459 WARN_ON(req1 && req1->elsp_submitted);
461 execlists_submit_requests(req0, req1);
464 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
467 struct drm_i915_gem_request *head_req;
469 assert_spin_locked(&ring->execlist_lock);
471 head_req = list_first_entry_or_null(&ring->execlist_queue,
472 struct drm_i915_gem_request,
475 if (head_req != NULL) {
476 struct drm_i915_gem_object *ctx_obj =
477 head_req->ctx->engine[ring->id].state;
478 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
479 WARN(head_req->elsp_submitted == 0,
480 "Never submitted head request\n");
482 if (--head_req->elsp_submitted <= 0) {
483 list_del(&head_req->execlist_link);
484 list_add_tail(&head_req->execlist_link,
485 &ring->execlist_retired_req_list);
495 * intel_lrc_irq_handler() - handle Context Switch interrupts
496 * @ring: Engine Command Streamer to handle.
498 * Check the unread Context Status Buffers and manage the submission of new
499 * contexts to the ELSP accordingly.
501 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
503 struct drm_i915_private *dev_priv = ring->dev->dev_private;
509 u32 submit_contexts = 0;
511 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
513 read_pointer = ring->next_context_status_buffer;
514 write_pointer = status_pointer & 0x07;
515 if (read_pointer > write_pointer)
518 spin_lock(&ring->execlist_lock);
520 while (read_pointer < write_pointer) {
522 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer % 6));
523 status_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer % 6));
525 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
528 if (status & GEN8_CTX_STATUS_PREEMPTED) {
529 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
530 if (execlists_check_remove_request(ring, status_id))
531 WARN(1, "Lite Restored request removed from queue\n");
533 WARN(1, "Preemption without Lite Restore\n");
536 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
537 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
538 if (execlists_check_remove_request(ring, status_id))
543 if (disable_lite_restore_wa(ring)) {
544 /* Prevent a ctx to preempt itself */
545 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) &&
546 (submit_contexts != 0))
547 execlists_context_unqueue(ring);
548 } else if (submit_contexts != 0) {
549 execlists_context_unqueue(ring);
552 spin_unlock(&ring->execlist_lock);
554 WARN(submit_contexts > 2, "More than two context complete events?\n");
555 ring->next_context_status_buffer = write_pointer % 6;
557 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
558 _MASKED_FIELD(0x07 << 8, ((u32)ring->next_context_status_buffer & 0x07) << 8));
561 static int execlists_context_queue(struct drm_i915_gem_request *request)
563 struct intel_engine_cs *ring = request->ring;
564 struct drm_i915_gem_request *cursor;
565 int num_elements = 0;
567 if (request->ctx != ring->default_context)
568 intel_lr_context_pin(request);
570 i915_gem_request_reference(request);
572 spin_lock_irq(&ring->execlist_lock);
574 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
575 if (++num_elements > 2)
578 if (num_elements > 2) {
579 struct drm_i915_gem_request *tail_req;
581 tail_req = list_last_entry(&ring->execlist_queue,
582 struct drm_i915_gem_request,
585 if (request->ctx == tail_req->ctx) {
586 WARN(tail_req->elsp_submitted != 0,
587 "More than 2 already-submitted reqs queued\n");
588 list_del(&tail_req->execlist_link);
589 list_add_tail(&tail_req->execlist_link,
590 &ring->execlist_retired_req_list);
594 list_add_tail(&request->execlist_link, &ring->execlist_queue);
595 if (num_elements == 0)
596 execlists_context_unqueue(ring);
598 spin_unlock_irq(&ring->execlist_lock);
603 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
605 struct intel_engine_cs *ring = req->ring;
606 uint32_t flush_domains;
610 if (ring->gpu_caches_dirty)
611 flush_domains = I915_GEM_GPU_DOMAINS;
613 ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
617 ring->gpu_caches_dirty = false;
621 static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
622 struct list_head *vmas)
624 const unsigned other_rings = ~intel_ring_flag(req->ring);
625 struct i915_vma *vma;
626 uint32_t flush_domains = 0;
627 bool flush_chipset = false;
630 list_for_each_entry(vma, vmas, exec_list) {
631 struct drm_i915_gem_object *obj = vma->obj;
633 if (obj->active & other_rings) {
634 ret = i915_gem_object_sync(obj, req->ring, &req);
639 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
640 flush_chipset |= i915_gem_clflush_object(obj, false);
642 flush_domains |= obj->base.write_domain;
645 if (flush_domains & I915_GEM_DOMAIN_GTT)
648 /* Unconditionally invalidate gpu caches and ensure that we do flush
649 * any residual writes from the previous batch.
651 return logical_ring_invalidate_all_caches(req);
654 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
658 request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;
660 if (request->ctx != request->ring->default_context) {
661 ret = intel_lr_context_pin(request);
669 static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
672 struct intel_ringbuffer *ringbuf = req->ringbuf;
673 struct intel_engine_cs *ring = req->ring;
674 struct drm_i915_gem_request *target;
678 if (intel_ring_space(ringbuf) >= bytes)
681 /* The whole point of reserving space is to not wait! */
682 WARN_ON(ringbuf->reserved_in_use);
684 list_for_each_entry(target, &ring->request_list, list) {
686 * The request queue is per-engine, so can contain requests
687 * from multiple ringbuffers. Here, we must ignore any that
688 * aren't from the ringbuffer we're considering.
690 if (target->ringbuf != ringbuf)
693 /* Would completion of this request free enough space? */
694 space = __intel_ring_space(target->postfix, ringbuf->tail,
700 if (WARN_ON(&target->list == &ring->request_list))
703 ret = i915_wait_request(target);
707 ringbuf->space = space;
712 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
713 * @request: Request to advance the logical ringbuffer of.
715 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
716 * really happens during submission is that the context and current tail will be placed
717 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
718 * point, the tail *inside* the context is updated and the ELSP written to.
721 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
723 struct intel_engine_cs *ring = request->ring;
724 struct drm_i915_private *dev_priv = request->i915;
726 intel_logical_ring_advance(request->ringbuf);
728 request->tail = request->ringbuf->tail;
730 if (intel_ring_stopped(ring))
733 if (dev_priv->guc.execbuf_client)
734 i915_guc_submit(dev_priv->guc.execbuf_client, request);
736 execlists_context_queue(request);
739 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
741 uint32_t __iomem *virt;
742 int rem = ringbuf->size - ringbuf->tail;
744 virt = ringbuf->virtual_start + ringbuf->tail;
747 iowrite32(MI_NOOP, virt++);
750 intel_ring_update_space(ringbuf);
753 static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
755 struct intel_ringbuffer *ringbuf = req->ringbuf;
756 int remain_usable = ringbuf->effective_size - ringbuf->tail;
757 int remain_actual = ringbuf->size - ringbuf->tail;
758 int ret, total_bytes, wait_bytes = 0;
759 bool need_wrap = false;
761 if (ringbuf->reserved_in_use)
764 total_bytes = bytes + ringbuf->reserved_size;
766 if (unlikely(bytes > remain_usable)) {
768 * Not enough space for the basic request. So need to flush
769 * out the remainder and then wait for base + reserved.
771 wait_bytes = remain_actual + total_bytes;
774 if (unlikely(total_bytes > remain_usable)) {
776 * The base request will fit but the reserved space
777 * falls off the end. So only need to to wait for the
778 * reserved size after flushing out the remainder.
780 wait_bytes = remain_actual + ringbuf->reserved_size;
782 } else if (total_bytes > ringbuf->space) {
783 /* No wrapping required, just waiting. */
784 wait_bytes = total_bytes;
789 ret = logical_ring_wait_for_space(req, wait_bytes);
794 __wrap_ring_buffer(ringbuf);
801 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
803 * @req: The request to start some new work for
804 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
806 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
807 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
808 * and also preallocates a request (every workload submission is still mediated through
809 * requests, same as it did with legacy ringbuffer submission).
811 * Return: non-zero if the ringbuffer is not ready to be written to.
813 int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
815 struct drm_i915_private *dev_priv;
818 WARN_ON(req == NULL);
819 dev_priv = req->ring->dev->dev_private;
821 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
822 dev_priv->mm.interruptible);
826 ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
830 req->ringbuf->space -= num_dwords * sizeof(uint32_t);
834 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
837 * The first call merely notes the reserve request and is common for
838 * all back ends. The subsequent localised _begin() call actually
839 * ensures that the reservation is available. Without the begin, if
840 * the request creator immediately submitted the request without
841 * adding any commands to it then there might not actually be
842 * sufficient room for the submission commands.
844 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
846 return intel_logical_ring_begin(request, 0);
850 * execlists_submission() - submit a batchbuffer for execution, Execlists style
853 * @ring: Engine Command Streamer to submit to.
854 * @ctx: Context to employ for this submission.
855 * @args: execbuffer call arguments.
856 * @vmas: list of vmas.
857 * @batch_obj: the batchbuffer to submit.
858 * @exec_start: batchbuffer start virtual address pointer.
859 * @dispatch_flags: translated execbuffer call flags.
861 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
862 * away the submission details of the execbuffer ioctl call.
864 * Return: non-zero if the submission fails.
866 int intel_execlists_submission(struct i915_execbuffer_params *params,
867 struct drm_i915_gem_execbuffer2 *args,
868 struct list_head *vmas)
870 struct drm_device *dev = params->dev;
871 struct intel_engine_cs *ring = params->ring;
872 struct drm_i915_private *dev_priv = dev->dev_private;
873 struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
879 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
880 instp_mask = I915_EXEC_CONSTANTS_MASK;
881 switch (instp_mode) {
882 case I915_EXEC_CONSTANTS_REL_GENERAL:
883 case I915_EXEC_CONSTANTS_ABSOLUTE:
884 case I915_EXEC_CONSTANTS_REL_SURFACE:
885 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
886 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
890 if (instp_mode != dev_priv->relative_constants_mode) {
891 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
892 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
896 /* The HW changed the meaning on this bit on gen6 */
897 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
901 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
905 if (args->num_cliprects != 0) {
906 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
909 if (args->DR4 == 0xffffffff) {
910 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
914 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
915 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
920 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
921 DRM_DEBUG("sol reset is gen7 only\n");
925 ret = execlists_move_to_gpu(params->request, vmas);
929 if (ring == &dev_priv->ring[RCS] &&
930 instp_mode != dev_priv->relative_constants_mode) {
931 ret = intel_logical_ring_begin(params->request, 4);
935 intel_logical_ring_emit(ringbuf, MI_NOOP);
936 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
937 intel_logical_ring_emit(ringbuf, INSTPM);
938 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
939 intel_logical_ring_advance(ringbuf);
941 dev_priv->relative_constants_mode = instp_mode;
944 exec_start = params->batch_obj_vm_offset +
945 args->batch_start_offset;
947 ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags);
951 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
953 i915_gem_execbuffer_move_to_active(vmas, params->request);
954 i915_gem_execbuffer_retire_commands(params);
959 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
961 struct drm_i915_gem_request *req, *tmp;
962 struct list_head retired_list;
964 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
965 if (list_empty(&ring->execlist_retired_req_list))
968 INIT_LIST_HEAD(&retired_list);
969 spin_lock_irq(&ring->execlist_lock);
970 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
971 spin_unlock_irq(&ring->execlist_lock);
973 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
974 struct intel_context *ctx = req->ctx;
975 struct drm_i915_gem_object *ctx_obj =
976 ctx->engine[ring->id].state;
978 if (ctx_obj && (ctx != ring->default_context))
979 intel_lr_context_unpin(req);
980 list_del(&req->execlist_link);
981 i915_gem_request_unreference(req);
985 void intel_logical_ring_stop(struct intel_engine_cs *ring)
987 struct drm_i915_private *dev_priv = ring->dev->dev_private;
990 if (!intel_ring_initialized(ring))
993 ret = intel_ring_idle(ring);
994 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
995 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
998 /* TODO: Is this correct with Execlists enabled? */
999 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
1000 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
1001 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
1004 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
1007 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
1009 struct intel_engine_cs *ring = req->ring;
1012 if (!ring->gpu_caches_dirty)
1015 ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
1019 ring->gpu_caches_dirty = false;
1023 static int intel_lr_context_do_pin(struct intel_engine_cs *ring,
1024 struct drm_i915_gem_object *ctx_obj,
1025 struct intel_ringbuffer *ringbuf)
1027 struct drm_device *dev = ring->dev;
1028 struct drm_i915_private *dev_priv = dev->dev_private;
1031 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1032 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
1033 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
1037 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
1041 ctx_obj->dirty = true;
1043 /* Invalidate GuC TLB. */
1044 if (i915.enable_guc_submission)
1045 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
1050 i915_gem_object_ggtt_unpin(ctx_obj);
1055 static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
1058 struct intel_engine_cs *ring = rq->ring;
1059 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
1060 struct intel_ringbuffer *ringbuf = rq->ringbuf;
1062 if (rq->ctx->engine[ring->id].pin_count++ == 0) {
1063 ret = intel_lr_context_do_pin(ring, ctx_obj, ringbuf);
1065 goto reset_pin_count;
1070 rq->ctx->engine[ring->id].pin_count = 0;
1074 void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
1076 struct intel_engine_cs *ring = rq->ring;
1077 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
1078 struct intel_ringbuffer *ringbuf = rq->ringbuf;
1081 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1082 if (--rq->ctx->engine[ring->id].pin_count == 0) {
1083 intel_unpin_ringbuffer_obj(ringbuf);
1084 i915_gem_object_ggtt_unpin(ctx_obj);
1089 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1092 struct intel_engine_cs *ring = req->ring;
1093 struct intel_ringbuffer *ringbuf = req->ringbuf;
1094 struct drm_device *dev = ring->dev;
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 struct i915_workarounds *w = &dev_priv->workarounds;
1098 if (WARN_ON_ONCE(w->count == 0))
1101 ring->gpu_caches_dirty = true;
1102 ret = logical_ring_flush_all_caches(req);
1106 ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1110 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1111 for (i = 0; i < w->count; i++) {
1112 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1113 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1115 intel_logical_ring_emit(ringbuf, MI_NOOP);
1117 intel_logical_ring_advance(ringbuf);
1119 ring->gpu_caches_dirty = true;
1120 ret = logical_ring_flush_all_caches(req);
1127 #define wa_ctx_emit(batch, index, cmd) \
1129 int __index = (index)++; \
1130 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1133 batch[__index] = (cmd); \
1138 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1139 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1140 * but there is a slight complication as this is applied in WA batch where the
1141 * values are only initialized once so we cannot take register value at the
1142 * beginning and reuse it further; hence we save its value to memory, upload a
1143 * constant value with bit21 set and then we restore it back with the saved value.
1144 * To simplify the WA, a constant value is formed by using the default value
1145 * of this register. This shouldn't be a problem because we are only modifying
1146 * it for a short period and this batch in non-premptible. We can ofcourse
1147 * use additional instructions that read the actual value of the register
1148 * at that time and set our bit of interest but it makes the WA complicated.
1150 * This WA is also required for Gen9 so extracting as a function avoids
1153 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
1154 uint32_t *const batch,
1157 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
1160 * WaDisableLSQCROPERFforOCL:skl
1161 * This WA is implemented in skl_init_clock_gating() but since
1162 * this batch updates GEN8_L3SQCREG4 with default value we need to
1163 * set this bit here to retain the WA during flush.
1165 if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0)
1166 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
1168 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1169 MI_SRM_LRM_GLOBAL_GTT));
1170 wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
1171 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1172 wa_ctx_emit(batch, index, 0);
1174 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1175 wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
1176 wa_ctx_emit(batch, index, l3sqc4_flush);
1178 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1179 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
1180 PIPE_CONTROL_DC_FLUSH_ENABLE));
1181 wa_ctx_emit(batch, index, 0);
1182 wa_ctx_emit(batch, index, 0);
1183 wa_ctx_emit(batch, index, 0);
1184 wa_ctx_emit(batch, index, 0);
1186 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1187 MI_SRM_LRM_GLOBAL_GTT));
1188 wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
1189 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1190 wa_ctx_emit(batch, index, 0);
1195 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1197 uint32_t start_alignment)
1199 return wa_ctx->offset = ALIGN(offset, start_alignment);
1202 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1204 uint32_t size_alignment)
1206 wa_ctx->size = offset - wa_ctx->offset;
1208 WARN(wa_ctx->size % size_alignment,
1209 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1210 wa_ctx->size, size_alignment);
1215 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1217 * @ring: only applicable for RCS
1218 * @wa_ctx: structure representing wa_ctx
1219 * offset: specifies start of the batch, should be cache-aligned. This is updated
1220 * with the offset value received as input.
1221 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1222 * @batch: page in which WA are loaded
1223 * @offset: This field specifies the start of the batch, it should be
1224 * cache-aligned otherwise it is adjusted accordingly.
1225 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1226 * initialized at the beginning and shared across all contexts but this field
1227 * helps us to have multiple batches at different offsets and select them based
1228 * on a criteria. At the moment this batch always start at the beginning of the page
1229 * and at this point we don't have multiple wa_ctx batch buffers.
1231 * The number of WA applied are not known at the beginning; we use this field
1232 * to return the no of DWORDS written.
1234 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1235 * so it adds NOOPs as padding to make it cacheline aligned.
1236 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1237 * makes a complete batch buffer.
1239 * Return: non-zero if we exceed the PAGE_SIZE limit.
1242 static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
1243 struct i915_wa_ctx_bb *wa_ctx,
1244 uint32_t *const batch,
1247 uint32_t scratch_addr;
1248 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1250 /* WaDisableCtxRestoreArbitration:bdw,chv */
1251 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1253 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1254 if (IS_BROADWELL(ring->dev)) {
1255 int rc = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1261 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1262 /* Actual scratch location is at 128 bytes offset */
1263 scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES;
1265 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1266 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1267 PIPE_CONTROL_GLOBAL_GTT_IVB |
1268 PIPE_CONTROL_CS_STALL |
1269 PIPE_CONTROL_QW_WRITE));
1270 wa_ctx_emit(batch, index, scratch_addr);
1271 wa_ctx_emit(batch, index, 0);
1272 wa_ctx_emit(batch, index, 0);
1273 wa_ctx_emit(batch, index, 0);
1275 /* Pad to end of cacheline */
1276 while (index % CACHELINE_DWORDS)
1277 wa_ctx_emit(batch, index, MI_NOOP);
1280 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1281 * execution depends on the length specified in terms of cache lines
1282 * in the register CTX_RCS_INDIRECT_CTX
1285 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1289 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1291 * @ring: only applicable for RCS
1292 * @wa_ctx: structure representing wa_ctx
1293 * offset: specifies start of the batch, should be cache-aligned.
1294 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1295 * @batch: page in which WA are loaded
1296 * @offset: This field specifies the start of this batch.
1297 * This batch is started immediately after indirect_ctx batch. Since we ensure
1298 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1300 * The number of DWORDS written are returned using this field.
1302 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1303 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1305 static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
1306 struct i915_wa_ctx_bb *wa_ctx,
1307 uint32_t *const batch,
1310 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1312 /* WaDisableCtxRestoreArbitration:bdw,chv */
1313 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1315 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1317 return wa_ctx_end(wa_ctx, *offset = index, 1);
1320 static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
1321 struct i915_wa_ctx_bb *wa_ctx,
1322 uint32_t *const batch,
1326 struct drm_device *dev = ring->dev;
1327 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1329 /* WaDisableCtxRestoreArbitration:skl,bxt */
1330 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
1331 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
1332 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1334 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1335 ret = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1340 /* Pad to end of cacheline */
1341 while (index % CACHELINE_DWORDS)
1342 wa_ctx_emit(batch, index, MI_NOOP);
1344 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1347 static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
1348 struct i915_wa_ctx_bb *wa_ctx,
1349 uint32_t *const batch,
1352 struct drm_device *dev = ring->dev;
1353 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1355 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1356 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
1357 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
1358 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1359 wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1360 wa_ctx_emit(batch, index,
1361 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1362 wa_ctx_emit(batch, index, MI_NOOP);
1365 /* WaDisableCtxRestoreArbitration:skl,bxt */
1366 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
1367 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
1368 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1370 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1372 return wa_ctx_end(wa_ctx, *offset = index, 1);
1375 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
1379 ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size));
1380 if (!ring->wa_ctx.obj) {
1381 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1385 ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0);
1387 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1389 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1396 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring)
1398 if (ring->wa_ctx.obj) {
1399 i915_gem_object_ggtt_unpin(ring->wa_ctx.obj);
1400 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1401 ring->wa_ctx.obj = NULL;
1405 static int intel_init_workaround_bb(struct intel_engine_cs *ring)
1411 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
1413 WARN_ON(ring->id != RCS);
1415 /* update this when WA for higher Gen are added */
1416 if (INTEL_INFO(ring->dev)->gen > 9) {
1417 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1418 INTEL_INFO(ring->dev)->gen);
1422 /* some WA perform writes to scratch page, ensure it is valid */
1423 if (ring->scratch.obj == NULL) {
1424 DRM_ERROR("scratch page not allocated for %s\n", ring->name);
1428 ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE);
1430 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1434 page = i915_gem_object_get_page(wa_ctx->obj, 0);
1435 batch = kmap_atomic(page);
1438 if (INTEL_INFO(ring->dev)->gen == 8) {
1439 ret = gen8_init_indirectctx_bb(ring,
1440 &wa_ctx->indirect_ctx,
1446 ret = gen8_init_perctx_bb(ring,
1452 } else if (INTEL_INFO(ring->dev)->gen == 9) {
1453 ret = gen9_init_indirectctx_bb(ring,
1454 &wa_ctx->indirect_ctx,
1460 ret = gen9_init_perctx_bb(ring,
1469 kunmap_atomic(batch);
1471 lrc_destroy_wa_ctx_obj(ring);
1476 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1478 struct drm_device *dev = ring->dev;
1479 struct drm_i915_private *dev_priv = dev->dev_private;
1481 lrc_setup_hardware_status_page(ring,
1482 ring->default_context->engine[ring->id].state);
1484 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1485 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1487 if (ring->status_page.obj) {
1488 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1489 (u32)ring->status_page.gfx_addr);
1490 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1493 I915_WRITE(RING_MODE_GEN7(ring),
1494 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1495 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1496 POSTING_READ(RING_MODE_GEN7(ring));
1497 ring->next_context_status_buffer = 0;
1498 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1500 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1505 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1507 struct drm_device *dev = ring->dev;
1508 struct drm_i915_private *dev_priv = dev->dev_private;
1511 ret = gen8_init_common_ring(ring);
1515 /* We need to disable the AsyncFlip performance optimisations in order
1516 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1517 * programmed to '1' on all products.
1519 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1521 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1523 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1525 return init_workarounds_ring(ring);
1528 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1532 ret = gen8_init_common_ring(ring);
1536 return init_workarounds_ring(ring);
1539 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1541 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1542 struct intel_engine_cs *ring = req->ring;
1543 struct intel_ringbuffer *ringbuf = req->ringbuf;
1544 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1547 ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
1551 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1552 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1553 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1555 intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
1556 intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1557 intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
1558 intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
1561 intel_logical_ring_emit(ringbuf, MI_NOOP);
1562 intel_logical_ring_advance(ringbuf);
1567 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1568 u64 offset, unsigned dispatch_flags)
1570 struct intel_ringbuffer *ringbuf = req->ringbuf;
1571 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1574 /* Don't rely in hw updating PDPs, specially in lite-restore.
1575 * Ideally, we should set Force PD Restore in ctx descriptor,
1576 * but we can't. Force Restore would be a second option, but
1577 * it is unsafe in case of lite-restore (because the ctx is
1578 * not idle). PML4 is allocated during ppgtt init so this is
1579 * not needed in 48-bit.*/
1580 if (req->ctx->ppgtt &&
1581 (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {
1582 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1583 !intel_vgpu_active(req->i915->dev)) {
1584 ret = intel_logical_ring_emit_pdps(req);
1589 req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
1592 ret = intel_logical_ring_begin(req, 4);
1596 /* FIXME(BDW): Address space and security selectors. */
1597 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
1599 (dispatch_flags & I915_DISPATCH_RS ?
1600 MI_BATCH_RESOURCE_STREAMER : 0));
1601 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1602 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1603 intel_logical_ring_emit(ringbuf, MI_NOOP);
1604 intel_logical_ring_advance(ringbuf);
1609 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1611 struct drm_device *dev = ring->dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 unsigned long flags;
1615 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1618 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1619 if (ring->irq_refcount++ == 0) {
1620 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1621 POSTING_READ(RING_IMR(ring->mmio_base));
1623 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1628 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1630 struct drm_device *dev = ring->dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 unsigned long flags;
1634 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1635 if (--ring->irq_refcount == 0) {
1636 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1637 POSTING_READ(RING_IMR(ring->mmio_base));
1639 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1642 static int gen8_emit_flush(struct drm_i915_gem_request *request,
1643 u32 invalidate_domains,
1646 struct intel_ringbuffer *ringbuf = request->ringbuf;
1647 struct intel_engine_cs *ring = ringbuf->ring;
1648 struct drm_device *dev = ring->dev;
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1653 ret = intel_logical_ring_begin(request, 4);
1657 cmd = MI_FLUSH_DW + 1;
1659 /* We always require a command barrier so that subsequent
1660 * commands, such as breadcrumb interrupts, are strictly ordered
1661 * wrt the contents of the write cache being flushed to memory
1662 * (and thus being coherent from the CPU).
1664 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1666 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1667 cmd |= MI_INVALIDATE_TLB;
1668 if (ring == &dev_priv->ring[VCS])
1669 cmd |= MI_INVALIDATE_BSD;
1672 intel_logical_ring_emit(ringbuf, cmd);
1673 intel_logical_ring_emit(ringbuf,
1674 I915_GEM_HWS_SCRATCH_ADDR |
1675 MI_FLUSH_DW_USE_GTT);
1676 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1677 intel_logical_ring_emit(ringbuf, 0); /* value */
1678 intel_logical_ring_advance(ringbuf);
1683 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1684 u32 invalidate_domains,
1687 struct intel_ringbuffer *ringbuf = request->ringbuf;
1688 struct intel_engine_cs *ring = ringbuf->ring;
1689 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1694 flags |= PIPE_CONTROL_CS_STALL;
1696 if (flush_domains) {
1697 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1698 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1701 if (invalidate_domains) {
1702 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1703 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1704 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1705 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1706 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1707 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1708 flags |= PIPE_CONTROL_QW_WRITE;
1709 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1713 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1716 vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
1717 flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
1719 ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1724 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1725 intel_logical_ring_emit(ringbuf, 0);
1726 intel_logical_ring_emit(ringbuf, 0);
1727 intel_logical_ring_emit(ringbuf, 0);
1728 intel_logical_ring_emit(ringbuf, 0);
1729 intel_logical_ring_emit(ringbuf, 0);
1732 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1733 intel_logical_ring_emit(ringbuf, flags);
1734 intel_logical_ring_emit(ringbuf, scratch_addr);
1735 intel_logical_ring_emit(ringbuf, 0);
1736 intel_logical_ring_emit(ringbuf, 0);
1737 intel_logical_ring_emit(ringbuf, 0);
1738 intel_logical_ring_advance(ringbuf);
1743 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1745 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1748 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1750 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1753 static u32 bxt_a_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1757 * On BXT A steppings there is a HW coherency issue whereby the
1758 * MI_STORE_DATA_IMM storing the completed request's seqno
1759 * occasionally doesn't invalidate the CPU cache. Work around this by
1760 * clflushing the corresponding cacheline whenever the caller wants
1761 * the coherency to be guaranteed. Note that this cacheline is known
1762 * to be clean at this point, since we only write it in
1763 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1764 * this clflush in practice becomes an invalidate operation.
1767 if (!lazy_coherency)
1768 intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
1770 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1773 static void bxt_a_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1775 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1777 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1778 intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
1781 static int gen8_emit_request(struct drm_i915_gem_request *request)
1783 struct intel_ringbuffer *ringbuf = request->ringbuf;
1784 struct intel_engine_cs *ring = ringbuf->ring;
1789 * Reserve space for 2 NOOPs at the end of each request to be
1790 * used as a workaround for not being allowed to do lite
1791 * restore with HEAD==TAIL (WaIdleLiteRestore).
1793 ret = intel_logical_ring_begin(request, 8);
1797 cmd = MI_STORE_DWORD_IMM_GEN4;
1798 cmd |= MI_GLOBAL_GTT;
1800 intel_logical_ring_emit(ringbuf, cmd);
1801 intel_logical_ring_emit(ringbuf,
1802 (ring->status_page.gfx_addr +
1803 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1804 intel_logical_ring_emit(ringbuf, 0);
1805 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1806 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1807 intel_logical_ring_emit(ringbuf, MI_NOOP);
1808 intel_logical_ring_advance_and_submit(request);
1811 * Here we add two extra NOOPs as padding to avoid
1812 * lite restore of a context with HEAD==TAIL.
1814 intel_logical_ring_emit(ringbuf, MI_NOOP);
1815 intel_logical_ring_emit(ringbuf, MI_NOOP);
1816 intel_logical_ring_advance(ringbuf);
1821 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1823 struct render_state so;
1826 ret = i915_gem_render_state_prepare(req->ring, &so);
1830 if (so.rodata == NULL)
1833 ret = req->ring->emit_bb_start(req, so.ggtt_offset,
1834 I915_DISPATCH_SECURE);
1838 ret = req->ring->emit_bb_start(req,
1839 (so.ggtt_offset + so.aux_batch_offset),
1840 I915_DISPATCH_SECURE);
1844 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1847 i915_gem_render_state_fini(&so);
1851 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1855 ret = intel_logical_ring_workarounds_emit(req);
1859 ret = intel_rcs_context_init_mocs(req);
1861 * Failing to program the MOCS is non-fatal.The system will not
1862 * run at peak performance. So generate an error and carry on.
1865 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1867 return intel_lr_context_render_state_init(req);
1871 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1873 * @ring: Engine Command Streamer.
1876 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1878 struct drm_i915_private *dev_priv;
1880 if (!intel_ring_initialized(ring))
1883 dev_priv = ring->dev->dev_private;
1885 intel_logical_ring_stop(ring);
1886 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1889 ring->cleanup(ring);
1891 i915_cmd_parser_fini_ring(ring);
1892 i915_gem_batch_pool_fini(&ring->batch_pool);
1894 if (ring->status_page.obj) {
1895 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1896 ring->status_page.obj = NULL;
1899 lrc_destroy_wa_ctx_obj(ring);
1902 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1906 /* Intentionally left blank. */
1907 ring->buffer = NULL;
1910 INIT_LIST_HEAD(&ring->active_list);
1911 INIT_LIST_HEAD(&ring->request_list);
1912 i915_gem_batch_pool_init(dev, &ring->batch_pool);
1913 init_waitqueue_head(&ring->irq_queue);
1915 INIT_LIST_HEAD(&ring->execlist_queue);
1916 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1917 spin_lock_init(&ring->execlist_lock);
1919 ret = i915_cmd_parser_init_ring(ring);
1923 ret = intel_lr_context_deferred_alloc(ring->default_context, ring);
1927 /* As this is the default context, always pin it */
1928 ret = intel_lr_context_do_pin(
1930 ring->default_context->engine[ring->id].state,
1931 ring->default_context->engine[ring->id].ringbuf);
1934 "Failed to pin and map ringbuffer %s: %d\n",
1942 static int logical_render_ring_init(struct drm_device *dev)
1944 struct drm_i915_private *dev_priv = dev->dev_private;
1945 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1948 ring->name = "render ring";
1950 ring->mmio_base = RENDER_RING_BASE;
1951 ring->irq_enable_mask =
1952 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1953 ring->irq_keep_mask =
1954 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1955 if (HAS_L3_DPF(dev))
1956 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1958 if (INTEL_INFO(dev)->gen >= 9)
1959 ring->init_hw = gen9_init_render_ring;
1961 ring->init_hw = gen8_init_render_ring;
1962 ring->init_context = gen8_init_rcs_context;
1963 ring->cleanup = intel_fini_pipe_control;
1964 if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
1965 ring->get_seqno = bxt_a_get_seqno;
1966 ring->set_seqno = bxt_a_set_seqno;
1968 ring->get_seqno = gen8_get_seqno;
1969 ring->set_seqno = gen8_set_seqno;
1971 ring->emit_request = gen8_emit_request;
1972 ring->emit_flush = gen8_emit_flush_render;
1973 ring->irq_get = gen8_logical_ring_get_irq;
1974 ring->irq_put = gen8_logical_ring_put_irq;
1975 ring->emit_bb_start = gen8_emit_bb_start;
1979 ret = intel_init_pipe_control(ring);
1983 ret = intel_init_workaround_bb(ring);
1986 * We continue even if we fail to initialize WA batch
1987 * because we only expect rare glitches but nothing
1988 * critical to prevent us from using GPU
1990 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1994 ret = logical_ring_init(dev, ring);
1996 lrc_destroy_wa_ctx_obj(ring);
2002 static int logical_bsd_ring_init(struct drm_device *dev)
2004 struct drm_i915_private *dev_priv = dev->dev_private;
2005 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2007 ring->name = "bsd ring";
2009 ring->mmio_base = GEN6_BSD_RING_BASE;
2010 ring->irq_enable_mask =
2011 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2012 ring->irq_keep_mask =
2013 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2015 ring->init_hw = gen8_init_common_ring;
2016 if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
2017 ring->get_seqno = bxt_a_get_seqno;
2018 ring->set_seqno = bxt_a_set_seqno;
2020 ring->get_seqno = gen8_get_seqno;
2021 ring->set_seqno = gen8_set_seqno;
2023 ring->emit_request = gen8_emit_request;
2024 ring->emit_flush = gen8_emit_flush;
2025 ring->irq_get = gen8_logical_ring_get_irq;
2026 ring->irq_put = gen8_logical_ring_put_irq;
2027 ring->emit_bb_start = gen8_emit_bb_start;
2029 return logical_ring_init(dev, ring);
2032 static int logical_bsd2_ring_init(struct drm_device *dev)
2034 struct drm_i915_private *dev_priv = dev->dev_private;
2035 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2037 ring->name = "bds2 ring";
2039 ring->mmio_base = GEN8_BSD2_RING_BASE;
2040 ring->irq_enable_mask =
2041 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2042 ring->irq_keep_mask =
2043 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2045 ring->init_hw = gen8_init_common_ring;
2046 ring->get_seqno = gen8_get_seqno;
2047 ring->set_seqno = gen8_set_seqno;
2048 ring->emit_request = gen8_emit_request;
2049 ring->emit_flush = gen8_emit_flush;
2050 ring->irq_get = gen8_logical_ring_get_irq;
2051 ring->irq_put = gen8_logical_ring_put_irq;
2052 ring->emit_bb_start = gen8_emit_bb_start;
2054 return logical_ring_init(dev, ring);
2057 static int logical_blt_ring_init(struct drm_device *dev)
2059 struct drm_i915_private *dev_priv = dev->dev_private;
2060 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2062 ring->name = "blitter ring";
2064 ring->mmio_base = BLT_RING_BASE;
2065 ring->irq_enable_mask =
2066 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2067 ring->irq_keep_mask =
2068 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2070 ring->init_hw = gen8_init_common_ring;
2071 if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
2072 ring->get_seqno = bxt_a_get_seqno;
2073 ring->set_seqno = bxt_a_set_seqno;
2075 ring->get_seqno = gen8_get_seqno;
2076 ring->set_seqno = gen8_set_seqno;
2078 ring->emit_request = gen8_emit_request;
2079 ring->emit_flush = gen8_emit_flush;
2080 ring->irq_get = gen8_logical_ring_get_irq;
2081 ring->irq_put = gen8_logical_ring_put_irq;
2082 ring->emit_bb_start = gen8_emit_bb_start;
2084 return logical_ring_init(dev, ring);
2087 static int logical_vebox_ring_init(struct drm_device *dev)
2089 struct drm_i915_private *dev_priv = dev->dev_private;
2090 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2092 ring->name = "video enhancement ring";
2094 ring->mmio_base = VEBOX_RING_BASE;
2095 ring->irq_enable_mask =
2096 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2097 ring->irq_keep_mask =
2098 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2100 ring->init_hw = gen8_init_common_ring;
2101 if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
2102 ring->get_seqno = bxt_a_get_seqno;
2103 ring->set_seqno = bxt_a_set_seqno;
2105 ring->get_seqno = gen8_get_seqno;
2106 ring->set_seqno = gen8_set_seqno;
2108 ring->emit_request = gen8_emit_request;
2109 ring->emit_flush = gen8_emit_flush;
2110 ring->irq_get = gen8_logical_ring_get_irq;
2111 ring->irq_put = gen8_logical_ring_put_irq;
2112 ring->emit_bb_start = gen8_emit_bb_start;
2114 return logical_ring_init(dev, ring);
2118 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2121 * This function inits the engines for an Execlists submission style (the equivalent in the
2122 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
2123 * those engines that are present in the hardware.
2125 * Return: non-zero if the initialization failed.
2127 int intel_logical_rings_init(struct drm_device *dev)
2129 struct drm_i915_private *dev_priv = dev->dev_private;
2132 ret = logical_render_ring_init(dev);
2137 ret = logical_bsd_ring_init(dev);
2139 goto cleanup_render_ring;
2143 ret = logical_blt_ring_init(dev);
2145 goto cleanup_bsd_ring;
2148 if (HAS_VEBOX(dev)) {
2149 ret = logical_vebox_ring_init(dev);
2151 goto cleanup_blt_ring;
2154 if (HAS_BSD2(dev)) {
2155 ret = logical_bsd2_ring_init(dev);
2157 goto cleanup_vebox_ring;
2163 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
2165 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
2167 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
2168 cleanup_render_ring:
2169 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
2175 make_rpcs(struct drm_device *dev)
2180 * No explicit RPCS request is needed to ensure full
2181 * slice/subslice/EU enablement prior to Gen9.
2183 if (INTEL_INFO(dev)->gen < 9)
2187 * Starting in Gen9, render power gating can leave
2188 * slice/subslice/EU in a partially enabled state. We
2189 * must make an explicit request through RPCS for full
2192 if (INTEL_INFO(dev)->has_slice_pg) {
2193 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2194 rpcs |= INTEL_INFO(dev)->slice_total <<
2195 GEN8_RPCS_S_CNT_SHIFT;
2196 rpcs |= GEN8_RPCS_ENABLE;
2199 if (INTEL_INFO(dev)->has_subslice_pg) {
2200 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2201 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
2202 GEN8_RPCS_SS_CNT_SHIFT;
2203 rpcs |= GEN8_RPCS_ENABLE;
2206 if (INTEL_INFO(dev)->has_eu_pg) {
2207 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2208 GEN8_RPCS_EU_MIN_SHIFT;
2209 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2210 GEN8_RPCS_EU_MAX_SHIFT;
2211 rpcs |= GEN8_RPCS_ENABLE;
2218 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
2219 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
2221 struct drm_device *dev = ring->dev;
2222 struct drm_i915_private *dev_priv = dev->dev_private;
2223 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2225 uint32_t *reg_state;
2229 ppgtt = dev_priv->mm.aliasing_ppgtt;
2231 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2233 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2237 ret = i915_gem_object_get_pages(ctx_obj);
2239 DRM_DEBUG_DRIVER("Could not get object pages\n");
2243 i915_gem_object_pin_pages(ctx_obj);
2245 /* The second page of the context object contains some fields which must
2246 * be set up prior to the first execution. */
2247 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2248 reg_state = kmap_atomic(page);
2250 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2251 * commands followed by (reg, value) pairs. The values we are setting here are
2252 * only for the first context restore: on a subsequent save, the GPU will
2253 * recreate this batchbuffer with new values (including all the missing
2254 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2255 if (ring->id == RCS)
2256 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
2258 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
2259 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
2260 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
2261 reg_state[CTX_CONTEXT_CONTROL+1] =
2262 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2263 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2264 CTX_CTRL_RS_CTX_ENABLE);
2265 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
2266 reg_state[CTX_RING_HEAD+1] = 0;
2267 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
2268 reg_state[CTX_RING_TAIL+1] = 0;
2269 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
2270 /* Ring buffer start address is not known until the buffer is pinned.
2271 * It is written to the context image in execlists_update_context()
2273 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
2274 reg_state[CTX_RING_BUFFER_CONTROL+1] =
2275 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
2276 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
2277 reg_state[CTX_BB_HEAD_U+1] = 0;
2278 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
2279 reg_state[CTX_BB_HEAD_L+1] = 0;
2280 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
2281 reg_state[CTX_BB_STATE+1] = (1<<5);
2282 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
2283 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
2284 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
2285 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
2286 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
2287 reg_state[CTX_SECOND_BB_STATE+1] = 0;
2288 if (ring->id == RCS) {
2289 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
2290 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
2291 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
2292 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
2293 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
2294 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
2295 if (ring->wa_ctx.obj) {
2296 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
2297 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2299 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2300 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2301 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2303 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2304 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
2306 reg_state[CTX_BB_PER_CTX_PTR+1] =
2307 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2311 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
2312 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
2313 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
2314 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
2315 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
2316 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
2317 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
2318 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
2319 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
2320 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
2321 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
2322 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
2324 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2325 /* 64b PPGTT (48bit canonical)
2326 * PDP0_DESCRIPTOR contains the base address to PML4 and
2327 * other PDP Descriptors are ignored.
2329 ASSIGN_CTX_PML4(ppgtt, reg_state);
2332 * PDP*_DESCRIPTOR contains the base address of space supported.
2333 * With dynamic page allocation, PDPs may not be allocated at
2334 * this point. Point the unallocated PDPs to the scratch page
2336 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
2337 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
2338 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
2339 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
2342 if (ring->id == RCS) {
2343 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2344 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
2345 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
2348 kunmap_atomic(reg_state);
2351 set_page_dirty(page);
2352 i915_gem_object_unpin_pages(ctx_obj);
2358 * intel_lr_context_free() - free the LRC specific bits of a context
2359 * @ctx: the LR context to free.
2361 * The real context freeing is done in i915_gem_context_free: this only
2362 * takes care of the bits that are LRC related: the per-engine backing
2363 * objects and the logical ringbuffer.
2365 void intel_lr_context_free(struct intel_context *ctx)
2369 for (i = 0; i < I915_NUM_RINGS; i++) {
2370 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2373 struct intel_ringbuffer *ringbuf =
2374 ctx->engine[i].ringbuf;
2375 struct intel_engine_cs *ring = ringbuf->ring;
2377 if (ctx == ring->default_context) {
2378 intel_unpin_ringbuffer_obj(ringbuf);
2379 i915_gem_object_ggtt_unpin(ctx_obj);
2381 WARN_ON(ctx->engine[ring->id].pin_count);
2382 intel_ringbuffer_free(ringbuf);
2383 drm_gem_object_unreference(&ctx_obj->base);
2388 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
2392 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
2396 if (INTEL_INFO(ring->dev)->gen >= 9)
2397 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2399 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2405 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2412 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
2413 struct drm_i915_gem_object *default_ctx_obj)
2415 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2418 /* The HWSP is part of the default context object in LRC mode. */
2419 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj)
2420 + LRC_PPHWSP_PN * PAGE_SIZE;
2421 page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN);
2422 ring->status_page.page_addr = kmap(page);
2423 ring->status_page.obj = default_ctx_obj;
2425 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
2426 (u32)ring->status_page.gfx_addr);
2427 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
2431 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2432 * @ctx: LR context to create.
2433 * @ring: engine to be used with the context.
2435 * This function can be called more than once, with different engines, if we plan
2436 * to use the context with them. The context backing objects and the ringbuffers
2437 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2438 * the creation is a deferred call: it's better to make sure first that we need to use
2439 * a given ring with the context.
2441 * Return: non-zero on error.
2444 int intel_lr_context_deferred_alloc(struct intel_context *ctx,
2445 struct intel_engine_cs *ring)
2447 struct drm_device *dev = ring->dev;
2448 struct drm_i915_gem_object *ctx_obj;
2449 uint32_t context_size;
2450 struct intel_ringbuffer *ringbuf;
2453 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2454 WARN_ON(ctx->engine[ring->id].state);
2456 context_size = round_up(get_lr_context_size(ring), 4096);
2458 /* One extra page as the sharing data between driver and GuC */
2459 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2461 ctx_obj = i915_gem_alloc_object(dev, context_size);
2463 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2467 ringbuf = intel_engine_create_ringbuffer(ring, 4 * PAGE_SIZE);
2468 if (IS_ERR(ringbuf)) {
2469 ret = PTR_ERR(ringbuf);
2470 goto error_deref_obj;
2473 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
2475 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2479 ctx->engine[ring->id].ringbuf = ringbuf;
2480 ctx->engine[ring->id].state = ctx_obj;
2482 if (ctx != ring->default_context && ring->init_context) {
2483 struct drm_i915_gem_request *req;
2485 ret = i915_gem_request_alloc(ring,
2488 DRM_ERROR("ring create req: %d\n",
2493 ret = ring->init_context(req);
2495 DRM_ERROR("ring init context: %d\n",
2497 i915_gem_request_cancel(req);
2500 i915_add_request_no_flush(req);
2505 intel_ringbuffer_free(ringbuf);
2507 drm_gem_object_unreference(&ctx_obj->base);
2508 ctx->engine[ring->id].ringbuf = NULL;
2509 ctx->engine[ring->id].state = NULL;
2513 void intel_lr_context_reset(struct drm_device *dev,
2514 struct intel_context *ctx)
2516 struct drm_i915_private *dev_priv = dev->dev_private;
2517 struct intel_engine_cs *ring;
2520 for_each_ring(ring, dev_priv, i) {
2521 struct drm_i915_gem_object *ctx_obj =
2522 ctx->engine[ring->id].state;
2523 struct intel_ringbuffer *ringbuf =
2524 ctx->engine[ring->id].ringbuf;
2525 uint32_t *reg_state;
2531 if (i915_gem_object_get_pages(ctx_obj)) {
2532 WARN(1, "Failed get_pages for context obj\n");
2535 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2536 reg_state = kmap_atomic(page);
2538 reg_state[CTX_RING_HEAD+1] = 0;
2539 reg_state[CTX_RING_TAIL+1] = 0;
2541 kunmap_atomic(reg_state);