drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  42 {
  43         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  44 }
  45
  46 static void
  47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  48 {
  49         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  50         struct drm_i915_private *dev_priv = dev->dev_private;
  51         uint32_t enabled_bits;
  52
  53         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  54
  55         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  56              "HDMI port enabled, expecting disabled\n");
  57 }
  58
  59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  60 {
  61         struct intel_digital_port *intel_dig_port =
  62                 container_of(encoder, struct intel_digital_port, base.base);
  63         return &intel_dig_port->hdmi;
  64 }
  65
  66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  67 {
  68         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  69 }
  70
  71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  72 {
  73         switch (type) {
  74         case HDMI_INFOFRAME_TYPE_AVI:
  75                 return VIDEO_DIP_SELECT_AVI;
  76         case HDMI_INFOFRAME_TYPE_SPD:
  77                 return VIDEO_DIP_SELECT_SPD;
  78         case HDMI_INFOFRAME_TYPE_VENDOR:
  79                 return VIDEO_DIP_SELECT_VENDOR;
  80         default:
  81                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  82                 return 0;
  83         }
  84 }
  85
  86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  87 {
  88         switch (type) {
  89         case HDMI_INFOFRAME_TYPE_AVI:
  90                 return VIDEO_DIP_ENABLE_AVI;
  91         case HDMI_INFOFRAME_TYPE_SPD:
  92                 return VIDEO_DIP_ENABLE_SPD;
  93         case HDMI_INFOFRAME_TYPE_VENDOR:
  94                 return VIDEO_DIP_ENABLE_VENDOR;
  95         default:
  96                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  97                 return 0;
  98         }
  99 }
 100
 101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 102 {
 103         switch (type) {
 104         case HDMI_INFOFRAME_TYPE_AVI:
 105                 return VIDEO_DIP_ENABLE_AVI_HSW;
 106         case HDMI_INFOFRAME_TYPE_SPD:
 107                 return VIDEO_DIP_ENABLE_SPD_HSW;
 108         case HDMI_INFOFRAME_TYPE_VENDOR:
 109                 return VIDEO_DIP_ENABLE_VS_HSW;
 110         default:
 111                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 112                 return 0;
 113         }
 114 }
 115
 116 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 117                                   enum transcoder cpu_transcoder,
 118                                   struct drm_i915_private *dev_priv)
 119 {
 120         switch (type) {
 121         case HDMI_INFOFRAME_TYPE_AVI:
 122                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 123         case HDMI_INFOFRAME_TYPE_SPD:
 124                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 125         case HDMI_INFOFRAME_TYPE_VENDOR:
 126                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 127         default:
 128                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 129                 return 0;
 130         }
 131 }
 132
 133 static void g4x_write_infoframe(struct drm_encoder *encoder,
 134                                 enum hdmi_infoframe_type type,
 135                                 const void *frame, ssize_t len)
 136 {
 137         const uint32_t *data = frame;
 138         struct drm_device *dev = encoder->dev;
 139         struct drm_i915_private *dev_priv = dev->dev_private;
 140         u32 val = I915_READ(VIDEO_DIP_CTL);
 141         int i;
 142
 143         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 144
 145         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 146         val |= g4x_infoframe_index(type);
 147
 148         val &= ~g4x_infoframe_enable(type);
 149
 150         I915_WRITE(VIDEO_DIP_CTL, val);
 151
 152         mmiowb();
 153         for (i = 0; i < len; i += 4) {
 154                 I915_WRITE(VIDEO_DIP_DATA, *data);
 155                 data++;
 156         }
 157         /* Write every possible data byte to force correct ECC calculation. */
 158         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 159                 I915_WRITE(VIDEO_DIP_DATA, 0);
 160         mmiowb();
 161
 162         val |= g4x_infoframe_enable(type);
 163         val &= ~VIDEO_DIP_FREQ_MASK;
 164         val |= VIDEO_DIP_FREQ_VSYNC;
 165
 166         I915_WRITE(VIDEO_DIP_CTL, val);
 167         POSTING_READ(VIDEO_DIP_CTL);
 168 }
 169
 170 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
 171 {
 172         struct drm_device *dev = encoder->dev;
 173         struct drm_i915_private *dev_priv = dev->dev_private;
 174         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 175         u32 val = I915_READ(VIDEO_DIP_CTL);
 176
 177         if ((val & VIDEO_DIP_ENABLE) == 0)
 178                 return false;
 179
 180         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 181                 return false;
 182
 183         return val & (VIDEO_DIP_ENABLE_AVI |
 184                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 185 }
 186
 187 static void ibx_write_infoframe(struct drm_encoder *encoder,
 188                                 enum hdmi_infoframe_type type,
 189                                 const void *frame, ssize_t len)
 190 {
 191         const uint32_t *data = frame;
 192         struct drm_device *dev = encoder->dev;
 193         struct drm_i915_private *dev_priv = dev->dev_private;
 194         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 195         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 196         u32 val = I915_READ(reg);
 197
 198         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 199
 200         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 201         val |= g4x_infoframe_index(type);
 202
 203         val &= ~g4x_infoframe_enable(type);
 204
 205         I915_WRITE(reg, val);
 206
 207         mmiowb();
 208         for (i = 0; i < len; i += 4) {
 209                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 210                 data++;
 211         }
 212         /* Write every possible data byte to force correct ECC calculation. */
 213         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 214                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 215         mmiowb();
 216
 217         val |= g4x_infoframe_enable(type);
 218         val &= ~VIDEO_DIP_FREQ_MASK;
 219         val |= VIDEO_DIP_FREQ_VSYNC;
 220
 221         I915_WRITE(reg, val);
 222         POSTING_READ(reg);
 223 }
 224
 225 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
 226 {
 227         struct drm_device *dev = encoder->dev;
 228         struct drm_i915_private *dev_priv = dev->dev_private;
 229         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 230         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 231         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 232         u32 val = I915_READ(reg);
 233
 234         if ((val & VIDEO_DIP_ENABLE) == 0)
 235                 return false;
 236
 237         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 238                 return false;
 239
 240         return val & (VIDEO_DIP_ENABLE_AVI |
 241                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 242                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 243 }
 244
 245 static void cpt_write_infoframe(struct drm_encoder *encoder,
 246                                 enum hdmi_infoframe_type type,
 247                                 const void *frame, ssize_t len)
 248 {
 249         const uint32_t *data = frame;
 250         struct drm_device *dev = encoder->dev;
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 253         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 254         u32 val = I915_READ(reg);
 255
 256         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 257
 258         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 259         val |= g4x_infoframe_index(type);
 260
 261         /* The DIP control register spec says that we need to update the AVI
 262          * infoframe without clearing its enable bit */
 263         if (type != HDMI_INFOFRAME_TYPE_AVI)
 264                 val &= ~g4x_infoframe_enable(type);
 265
 266         I915_WRITE(reg, val);
 267
 268         mmiowb();
 269         for (i = 0; i < len; i += 4) {
 270                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 271                 data++;
 272         }
 273         /* Write every possible data byte to force correct ECC calculation. */
 274         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 275                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 276         mmiowb();
 277
 278         val |= g4x_infoframe_enable(type);
 279         val &= ~VIDEO_DIP_FREQ_MASK;
 280         val |= VIDEO_DIP_FREQ_VSYNC;
 281
 282         I915_WRITE(reg, val);
 283         POSTING_READ(reg);
 284 }
 285
 286 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
 287 {
 288         struct drm_device *dev = encoder->dev;
 289         struct drm_i915_private *dev_priv = dev->dev_private;
 290         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 291         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 292         u32 val = I915_READ(reg);
 293
 294         if ((val & VIDEO_DIP_ENABLE) == 0)
 295                 return false;
 296
 297         return val & (VIDEO_DIP_ENABLE_AVI |
 298                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 299                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 300 }
 301
 302 static void vlv_write_infoframe(struct drm_encoder *encoder,
 303                                 enum hdmi_infoframe_type type,
 304                                 const void *frame, ssize_t len)
 305 {
 306         const uint32_t *data = frame;
 307         struct drm_device *dev = encoder->dev;
 308         struct drm_i915_private *dev_priv = dev->dev_private;
 309         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 310         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 311         u32 val = I915_READ(reg);
 312
 313         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 314
 315         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 316         val |= g4x_infoframe_index(type);
 317
 318         val &= ~g4x_infoframe_enable(type);
 319
 320         I915_WRITE(reg, val);
 321
 322         mmiowb();
 323         for (i = 0; i < len; i += 4) {
 324                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 325                 data++;
 326         }
 327         /* Write every possible data byte to force correct ECC calculation. */
 328         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 329                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 330         mmiowb();
 331
 332         val |= g4x_infoframe_enable(type);
 333         val &= ~VIDEO_DIP_FREQ_MASK;
 334         val |= VIDEO_DIP_FREQ_VSYNC;
 335
 336         I915_WRITE(reg, val);
 337         POSTING_READ(reg);
 338 }
 339
 340 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
 341 {
 342         struct drm_device *dev = encoder->dev;
 343         struct drm_i915_private *dev_priv = dev->dev_private;
 344         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 345         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 346         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 347         u32 val = I915_READ(reg);
 348
 349         if ((val & VIDEO_DIP_ENABLE) == 0)
 350                 return false;
 351
 352         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 353                 return false;
 354
 355         return val & (VIDEO_DIP_ENABLE_AVI |
 356                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 357                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 358 }
 359
 360 static void hsw_write_infoframe(struct drm_encoder *encoder,
 361                                 enum hdmi_infoframe_type type,
 362                                 const void *frame, ssize_t len)
 363 {
 364         const uint32_t *data = frame;
 365         struct drm_device *dev = encoder->dev;
 366         struct drm_i915_private *dev_priv = dev->dev_private;
 367         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 368         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 369         u32 data_reg;
 370         int i;
 371         u32 val = I915_READ(ctl_reg);
 372
 373         data_reg = hsw_infoframe_data_reg(type,
 374                                           intel_crtc->config->cpu_transcoder,
 375                                           dev_priv);
 376         if (data_reg == 0)
 377                 return;
 378
 379         val &= ~hsw_infoframe_enable(type);
 380         I915_WRITE(ctl_reg, val);
 381
 382         mmiowb();
 383         for (i = 0; i < len; i += 4) {
 384                 I915_WRITE(data_reg + i, *data);
 385                 data++;
 386         }
 387         /* Write every possible data byte to force correct ECC calculation. */
 388         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 389                 I915_WRITE(data_reg + i, 0);
 390         mmiowb();
 391
 392         val |= hsw_infoframe_enable(type);
 393         I915_WRITE(ctl_reg, val);
 394         POSTING_READ(ctl_reg);
 395 }
 396
 397 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
 398 {
 399         struct drm_device *dev = encoder->dev;
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 402         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 403         u32 val = I915_READ(ctl_reg);
 404
 405         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 406                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 407                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 408 }
 409
 410 /*
 411  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 412  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 413  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 414  * used for both technologies.
 415  *
 416  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 417  * DW1:       DB3       | DB2 | DB1 | DB0
 418  * DW2:       DB7       | DB6 | DB5 | DB4
 419  * DW3: ...
 420  *
 421  * (HB is Header Byte, DB is Data Byte)
 422  *
 423  * The hdmi pack() functions don't know about that hardware specific hole so we
 424  * trick them by giving an offset into the buffer and moving back the header
 425  * bytes by one.
 426  */
 427 static void intel_write_infoframe(struct drm_encoder *encoder,
 428                                   union hdmi_infoframe *frame)
 429 {
 430         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 431         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 432         ssize_t len;
 433
 434         /* see comment above for the reason for this offset */
 435         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 436         if (len < 0)
 437                 return;
 438
 439         /* Insert the 'hole' (see big comment above) at position 3 */
 440         buffer[0] = buffer[1];
 441         buffer[1] = buffer[2];
 442         buffer[2] = buffer[3];
 443         buffer[3] = 0;
 444         len++;
 445
 446         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 447 }
 448
 449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 450                                          const struct drm_display_mode *adjusted_mode)
 451 {
 452         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 453         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 454         union hdmi_infoframe frame;
 455         int ret;
 456
 457         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 458                                                        adjusted_mode);
 459         if (ret < 0) {
 460                 DRM_ERROR("couldn't fill AVI infoframe\n");
 461                 return;
 462         }
 463
 464         if (intel_hdmi->rgb_quant_range_selectable) {
 465                 if (intel_crtc->config->limited_color_range)
 466                         frame.avi.quantization_range =
 467                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 468                 else
 469                         frame.avi.quantization_range =
 470                                 HDMI_QUANTIZATION_RANGE_FULL;
 471         }
 472
 473         intel_write_infoframe(encoder, &frame);
 474 }
 475
 476 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 477 {
 478         union hdmi_infoframe frame;
 479         int ret;
 480
 481         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 482         if (ret < 0) {
 483                 DRM_ERROR("couldn't fill SPD infoframe\n");
 484                 return;
 485         }
 486
 487         frame.spd.sdi = HDMI_SPD_SDI_PC;
 488
 489         intel_write_infoframe(encoder, &frame);
 490 }
 491
 492 static void
 493 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 494                               const struct drm_display_mode *adjusted_mode)
 495 {
 496         union hdmi_infoframe frame;
 497         int ret;
 498
 499         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 500                                                           adjusted_mode);
 501         if (ret < 0)
 502                 return;
 503
 504         intel_write_infoframe(encoder, &frame);
 505 }
 506
 507 static void g4x_set_infoframes(struct drm_encoder *encoder,
 508                                bool enable,
 509                                const struct drm_display_mode *adjusted_mode)
 510 {
 511         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 512         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 513         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 514         u32 reg = VIDEO_DIP_CTL;
 515         u32 val = I915_READ(reg);
 516         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 517
 518         assert_hdmi_port_disabled(intel_hdmi);
 519
 520         /* If the registers were not initialized yet, they might be zeroes,
 521          * which means we're selecting the AVI DIP and we're setting its
 522          * frequency to once. This seems to really confuse the HW and make
 523          * things stop working (the register spec says the AVI always needs to
 524          * be sent every VSync). So here we avoid writing to the register more
 525          * than we need and also explicitly select the AVI DIP and explicitly
 526          * set its frequency to every VSync. Avoiding to write it twice seems to
 527          * be enough to solve the problem, but being defensive shouldn't hurt us
 528          * either. */
 529         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 530
 531         if (!enable) {
 532                 if (!(val & VIDEO_DIP_ENABLE))
 533                         return;
 534                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 535                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 536                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 537                         return;
 538                 }
 539                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 540                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 541                 I915_WRITE(reg, val);
 542                 POSTING_READ(reg);
 543                 return;
 544         }
 545
 546         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 547                 if (val & VIDEO_DIP_ENABLE) {
 548                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 549                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 550                         return;
 551                 }
 552                 val &= ~VIDEO_DIP_PORT_MASK;
 553                 val |= port;
 554         }
 555
 556         val |= VIDEO_DIP_ENABLE;
 557         val &= ~(VIDEO_DIP_ENABLE_AVI |
 558                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 559
 560         I915_WRITE(reg, val);
 561         POSTING_READ(reg);
 562
 563         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 564         intel_hdmi_set_spd_infoframe(encoder);
 565         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 566 }
 567
 568 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
 569 {
 570         struct drm_device *dev = encoder->dev;
 571         struct drm_connector *connector;
 572
 573         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 574
 575         /*
 576          * HDMI cloning is only supported on g4x which doesn't
 577          * support deep color or GCP infoframes anyway so no
 578          * need to worry about multiple HDMI sinks here.
 579          */
 580         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 581                 if (connector->encoder == encoder)
 582                         return connector->display_info.bpc > 8;
 583
 584         return false;
 585 }
 586
 587 /*
 588  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 589  *
 590  * From HDMI specification 1.4a:
 591  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 592  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 593  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 594  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 595  *   phase of 0
 596  */
 597 static bool gcp_default_phase_possible(int pipe_bpp,
 598                                        const struct drm_display_mode *mode)
 599 {
 600         unsigned int pixels_per_group;
 601
 602         switch (pipe_bpp) {
 603         case 30:
 604                 /* 4 pixels in 5 clocks */
 605                 pixels_per_group = 4;
 606                 break;
 607         case 36:
 608                 /* 2 pixels in 3 clocks */
 609                 pixels_per_group = 2;
 610                 break;
 611         case 48:
 612                 /* 1 pixel in 2 clocks */
 613                 pixels_per_group = 1;
 614                 break;
 615         default:
 616                 /* phase information not relevant for 8bpc */
 617                 return false;
 618         }
 619
 620         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 621                 mode->crtc_htotal % pixels_per_group == 0 &&
 622                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 623                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 624                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 625                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 626                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 627                  mode->crtc_htotal/2 % pixels_per_group == 0);
 628 }
 629
 630 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
 631 {
 632         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 633         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 634         u32 reg, val = 0;
 635
 636         if (HAS_DDI(dev_priv))
 637                 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
 638         else if (IS_VALLEYVIEW(dev_priv))
 639                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 640         else if (HAS_PCH_SPLIT(dev_priv->dev))
 641                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 642         else
 643                 return false;
 644
 645         /* Indicate color depth whenever the sink supports deep color */
 646         if (hdmi_sink_is_deep_color(encoder))
 647                 val |= GCP_COLOR_INDICATION;
 648
 649         /* Enable default_phase whenever the display mode is suitably aligned */
 650         if (gcp_default_phase_possible(crtc->config->pipe_bpp,
 651                                        &crtc->config->base.adjusted_mode))
 652                 val |= GCP_DEFAULT_PHASE_ENABLE;
 653
 654         I915_WRITE(reg, val);
 655
 656         return val != 0;
 657 }
 658
 659 static void ibx_set_infoframes(struct drm_encoder *encoder,
 660                                bool enable,
 661                                const struct drm_display_mode *adjusted_mode)
 662 {
 663         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 664         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 665         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 666         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 667         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 668         u32 val = I915_READ(reg);
 669         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 670
 671         assert_hdmi_port_disabled(intel_hdmi);
 672
 673         /* See the big comment in g4x_set_infoframes() */
 674         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 675
 676         if (!enable) {
 677                 if (!(val & VIDEO_DIP_ENABLE))
 678                         return;
 679                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 680                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 681                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 682                 I915_WRITE(reg, val);
 683                 POSTING_READ(reg);
 684                 return;
 685         }
 686
 687         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 688                 WARN(val & VIDEO_DIP_ENABLE,
 689                      "DIP already enabled on port %c\n",
 690                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 691                 val &= ~VIDEO_DIP_PORT_MASK;
 692                 val |= port;
 693         }
 694
 695         val |= VIDEO_DIP_ENABLE;
 696         val &= ~(VIDEO_DIP_ENABLE_AVI |
 697                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 698                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 699
 700         if (intel_hdmi_set_gcp_infoframe(encoder))
 701                 val |= VIDEO_DIP_ENABLE_GCP;
 702
 703         I915_WRITE(reg, val);
 704         POSTING_READ(reg);
 705
 706         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 707         intel_hdmi_set_spd_infoframe(encoder);
 708         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 709 }
 710
 711 static void cpt_set_infoframes(struct drm_encoder *encoder,
 712                                bool enable,
 713                                const struct drm_display_mode *adjusted_mode)
 714 {
 715         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 716         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 717         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 718         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 719         u32 val = I915_READ(reg);
 720
 721         assert_hdmi_port_disabled(intel_hdmi);
 722
 723         /* See the big comment in g4x_set_infoframes() */
 724         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 725
 726         if (!enable) {
 727                 if (!(val & VIDEO_DIP_ENABLE))
 728                         return;
 729                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 730                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 731                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 732                 I915_WRITE(reg, val);
 733                 POSTING_READ(reg);
 734                 return;
 735         }
 736
 737         /* Set both together, unset both together: see the spec. */
 738         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 739         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 740                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 741
 742         if (intel_hdmi_set_gcp_infoframe(encoder))
 743                 val |= VIDEO_DIP_ENABLE_GCP;
 744
 745         I915_WRITE(reg, val);
 746         POSTING_READ(reg);
 747
 748         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 749         intel_hdmi_set_spd_infoframe(encoder);
 750         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 751 }
 752
 753 static void vlv_set_infoframes(struct drm_encoder *encoder,
 754                                bool enable,
 755                                const struct drm_display_mode *adjusted_mode)
 756 {
 757         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 758         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 759         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 760         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 761         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 762         u32 val = I915_READ(reg);
 763         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 764
 765         assert_hdmi_port_disabled(intel_hdmi);
 766
 767         /* See the big comment in g4x_set_infoframes() */
 768         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 769
 770         if (!enable) {
 771                 if (!(val & VIDEO_DIP_ENABLE))
 772                         return;
 773                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 774                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 775                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 776                 I915_WRITE(reg, val);
 777                 POSTING_READ(reg);
 778                 return;
 779         }
 780
 781         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 782                 WARN(val & VIDEO_DIP_ENABLE,
 783                      "DIP already enabled on port %c\n",
 784                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 785                 val &= ~VIDEO_DIP_PORT_MASK;
 786                 val |= port;
 787         }
 788
 789         val |= VIDEO_DIP_ENABLE;
 790         val &= ~(VIDEO_DIP_ENABLE_AVI |
 791                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 792                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 793
 794         if (intel_hdmi_set_gcp_infoframe(encoder))
 795                 val |= VIDEO_DIP_ENABLE_GCP;
 796
 797         I915_WRITE(reg, val);
 798         POSTING_READ(reg);
 799
 800         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 801         intel_hdmi_set_spd_infoframe(encoder);
 802         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 803 }
 804
 805 static void hsw_set_infoframes(struct drm_encoder *encoder,
 806                                bool enable,
 807                                const struct drm_display_mode *adjusted_mode)
 808 {
 809         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 810         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 811         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 812         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 813         u32 val = I915_READ(reg);
 814
 815         assert_hdmi_port_disabled(intel_hdmi);
 816
 817         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 818                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 819                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 820
 821         if (!enable) {
 822                 I915_WRITE(reg, val);
 823                 POSTING_READ(reg);
 824                 return;
 825         }
 826
 827         if (intel_hdmi_set_gcp_infoframe(encoder))
 828                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 829
 830         I915_WRITE(reg, val);
 831         POSTING_READ(reg);
 832
 833         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 834         intel_hdmi_set_spd_infoframe(encoder);
 835         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 836 }
 837
 838 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 839 {
 840         struct drm_device *dev = encoder->base.dev;
 841         struct drm_i915_private *dev_priv = dev->dev_private;
 842         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 843         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 844         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 845         u32 hdmi_val;
 846
 847         hdmi_val = SDVO_ENCODING_HDMI;
 848         if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
 849                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
 850         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 851                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 852         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 853                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 854
 855         if (crtc->config->pipe_bpp > 24)
 856                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 857         else
 858                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 859
 860         if (crtc->config->has_hdmi_sink)
 861                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 862
 863         if (HAS_PCH_CPT(dev))
 864                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 865         else if (IS_CHERRYVIEW(dev))
 866                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 867         else
 868                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 869
 870         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 871         POSTING_READ(intel_hdmi->hdmi_reg);
 872 }
 873
 874 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 875                                     enum pipe *pipe)
 876 {
 877         struct drm_device *dev = encoder->base.dev;
 878         struct drm_i915_private *dev_priv = dev->dev_private;
 879         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 880         enum intel_display_power_domain power_domain;
 881         u32 tmp;
 882
 883         power_domain = intel_display_port_power_domain(encoder);
 884         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 885                 return false;
 886
 887         tmp = I915_READ(intel_hdmi->hdmi_reg);
 888
 889         if (!(tmp & SDVO_ENABLE))
 890                 return false;
 891
 892         if (HAS_PCH_CPT(dev))
 893                 *pipe = PORT_TO_PIPE_CPT(tmp);
 894         else if (IS_CHERRYVIEW(dev))
 895                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 896         else
 897                 *pipe = PORT_TO_PIPE(tmp);
 898
 899         return true;
 900 }
 901
 902 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 903                                   struct intel_crtc_state *pipe_config)
 904 {
 905         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 906         struct drm_device *dev = encoder->base.dev;
 907         struct drm_i915_private *dev_priv = dev->dev_private;
 908         u32 tmp, flags = 0;
 909         int dotclock;
 910
 911         tmp = I915_READ(intel_hdmi->hdmi_reg);
 912
 913         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 914                 flags |= DRM_MODE_FLAG_PHSYNC;
 915         else
 916                 flags |= DRM_MODE_FLAG_NHSYNC;
 917
 918         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 919                 flags |= DRM_MODE_FLAG_PVSYNC;
 920         else
 921                 flags |= DRM_MODE_FLAG_NVSYNC;
 922
 923         if (tmp & HDMI_MODE_SELECT_HDMI)
 924                 pipe_config->has_hdmi_sink = true;
 925
 926         if (intel_hdmi->infoframe_enabled(&encoder->base))
 927                 pipe_config->has_infoframe = true;
 928
 929         if (tmp & SDVO_AUDIO_ENABLE)
 930                 pipe_config->has_audio = true;
 931
 932         if (!HAS_PCH_SPLIT(dev) &&
 933             tmp & HDMI_COLOR_RANGE_16_235)
 934                 pipe_config->limited_color_range = true;
 935
 936         pipe_config->base.adjusted_mode.flags |= flags;
 937
 938         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 939                 dotclock = pipe_config->port_clock * 2 / 3;
 940         else
 941                 dotclock = pipe_config->port_clock;
 942
 943         if (pipe_config->pixel_multiplier)
 944                 dotclock /= pipe_config->pixel_multiplier;
 945
 946         if (HAS_PCH_SPLIT(dev_priv->dev))
 947                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 948
 949         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 950 }
 951
 952 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
 953 {
 954         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 955
 956         WARN_ON(!crtc->config->has_hdmi_sink);
 957         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 958                          pipe_name(crtc->pipe));
 959         intel_audio_codec_enable(encoder);
 960 }
 961
 962 static void g4x_enable_hdmi(struct intel_encoder *encoder)
 963 {
 964         struct drm_device *dev = encoder->base.dev;
 965         struct drm_i915_private *dev_priv = dev->dev_private;
 966         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 967         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 968         u32 temp;
 969
 970         temp = I915_READ(intel_hdmi->hdmi_reg);
 971
 972         temp |= SDVO_ENABLE;
 973         if (crtc->config->has_audio)
 974                 temp |= SDVO_AUDIO_ENABLE;
 975
 976         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 977         POSTING_READ(intel_hdmi->hdmi_reg);
 978
 979         if (crtc->config->has_audio)
 980                 intel_enable_hdmi_audio(encoder);
 981 }
 982
 983 static void ibx_enable_hdmi(struct intel_encoder *encoder)
 984 {
 985         struct drm_device *dev = encoder->base.dev;
 986         struct drm_i915_private *dev_priv = dev->dev_private;
 987         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 988         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 989         u32 temp;
 990
 991         temp = I915_READ(intel_hdmi->hdmi_reg);
 992
 993         temp |= SDVO_ENABLE;
 994         if (crtc->config->has_audio)
 995                 temp |= SDVO_AUDIO_ENABLE;
 996
 997         /*
 998          * HW workaround, need to write this twice for issue
 999          * that may result in first write getting masked.
1000          */
1001         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1002         POSTING_READ(intel_hdmi->hdmi_reg);
1003         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1004         POSTING_READ(intel_hdmi->hdmi_reg);
1005
1006         /*
1007          * HW workaround, need to toggle enable bit off and on
1008          * for 12bpc with pixel repeat.
1009          *
1010          * FIXME: BSpec says this should be done at the end of
1011          * of the modeset sequence, so not sure if this isn't too soon.
1012          */
1013         if (crtc->config->pipe_bpp > 24 &&
1014             crtc->config->pixel_multiplier > 1) {
1015                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1016                 POSTING_READ(intel_hdmi->hdmi_reg);
1017
1018                 /*
1019                  * HW workaround, need to write this twice for issue
1020                  * that may result in first write getting masked.
1021                  */
1022                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1023                 POSTING_READ(intel_hdmi->hdmi_reg);
1024                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1025                 POSTING_READ(intel_hdmi->hdmi_reg);
1026         }
1027
1028         if (crtc->config->has_audio)
1029                 intel_enable_hdmi_audio(encoder);
1030 }
1031
1032 static void cpt_enable_hdmi(struct intel_encoder *encoder)
1033 {
1034         struct drm_device *dev = encoder->base.dev;
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1037         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1038         enum pipe pipe = crtc->pipe;
1039         u32 temp;
1040
1041         temp = I915_READ(intel_hdmi->hdmi_reg);
1042
1043         temp |= SDVO_ENABLE;
1044         if (crtc->config->has_audio)
1045                 temp |= SDVO_AUDIO_ENABLE;
1046
1047         /*
1048          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1049          *
1050          * The procedure for 12bpc is as follows:
1051          * 1. disable HDMI clock gating
1052          * 2. enable HDMI with 8bpc
1053          * 3. enable HDMI with 12bpc
1054          * 4. enable HDMI clock gating
1055          */
1056
1057         if (crtc->config->pipe_bpp > 24) {
1058                 I915_WRITE(TRANS_CHICKEN1(pipe),
1059                            I915_READ(TRANS_CHICKEN1(pipe)) |
1060                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1061
1062                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1063                 temp |= SDVO_COLOR_FORMAT_8bpc;
1064         }
1065
1066         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1067         POSTING_READ(intel_hdmi->hdmi_reg);
1068
1069         if (crtc->config->pipe_bpp > 24) {
1070                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1071                 temp |= HDMI_COLOR_FORMAT_12bpc;
1072
1073                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1074                 POSTING_READ(intel_hdmi->hdmi_reg);
1075
1076                 I915_WRITE(TRANS_CHICKEN1(pipe),
1077                            I915_READ(TRANS_CHICKEN1(pipe)) &
1078                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1079         }
1080
1081         if (crtc->config->has_audio)
1082                 intel_enable_hdmi_audio(encoder);
1083 }
1084
1085 static void vlv_enable_hdmi(struct intel_encoder *encoder)
1086 {
1087 }
1088
1089 static void intel_disable_hdmi(struct intel_encoder *encoder)
1090 {
1091         struct drm_device *dev = encoder->base.dev;
1092         struct drm_i915_private *dev_priv = dev->dev_private;
1093         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1094         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1095         u32 temp;
1096
1097         temp = I915_READ(intel_hdmi->hdmi_reg);
1098
1099         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1100         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1101         POSTING_READ(intel_hdmi->hdmi_reg);
1102
1103         /*
1104          * HW workaround for IBX, we need to move the port
1105          * to transcoder A after disabling it to allow the
1106          * matching DP port to be enabled on transcoder A.
1107          */
1108         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1109                 temp &= ~SDVO_PIPE_B_SELECT;
1110                 temp |= SDVO_ENABLE;
1111                 /*
1112                  * HW workaround, need to write this twice for issue
1113                  * that may result in first write getting masked.
1114                  */
1115                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1116                 POSTING_READ(intel_hdmi->hdmi_reg);
1117                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1118                 POSTING_READ(intel_hdmi->hdmi_reg);
1119
1120                 temp &= ~SDVO_ENABLE;
1121                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1122                 POSTING_READ(intel_hdmi->hdmi_reg);
1123         }
1124
1125         intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1126 }
1127
1128 static void g4x_disable_hdmi(struct intel_encoder *encoder)
1129 {
1130         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1131
1132         if (crtc->config->has_audio)
1133                 intel_audio_codec_disable(encoder);
1134
1135         intel_disable_hdmi(encoder);
1136 }
1137
1138 static void pch_disable_hdmi(struct intel_encoder *encoder)
1139 {
1140         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1141
1142         if (crtc->config->has_audio)
1143                 intel_audio_codec_disable(encoder);
1144 }
1145
1146 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1147 {
1148         intel_disable_hdmi(encoder);
1149 }
1150
1151 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1152 {
1153         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1154
1155         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1156                 return 165000;
1157         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1158                 return 300000;
1159         else
1160                 return 225000;
1161 }
1162
1163 static enum drm_mode_status
1164 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1165                       int clock, bool respect_dvi_limit)
1166 {
1167         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1168
1169         if (clock < 25000)
1170                 return MODE_CLOCK_LOW;
1171         if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1172                 return MODE_CLOCK_HIGH;
1173
1174         /* BXT DPLL can't generate 223-240 MHz */
1175         if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1176                 return MODE_CLOCK_RANGE;
1177
1178         /* CHV DPLL can't generate 216-240 MHz */
1179         if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1180                 return MODE_CLOCK_RANGE;
1181
1182         return MODE_OK;
1183 }
1184
1185 static enum drm_mode_status
1186 intel_hdmi_mode_valid(struct drm_connector *connector,
1187                       struct drm_display_mode *mode)
1188 {
1189         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1190         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1191         enum drm_mode_status status;
1192         int clock;
1193
1194         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1195                 return MODE_NO_DBLESCAN;
1196
1197         clock = mode->clock;
1198         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1199                 clock *= 2;
1200
1201         /* check if we can do 8bpc */
1202         status = hdmi_port_clock_valid(hdmi, clock, true);
1203
1204         /* if we can't do 8bpc we may still be able to do 12bpc */
1205         if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1206                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1207
1208         return status;
1209 }
1210
1211 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1212 {
1213         struct drm_device *dev = crtc_state->base.crtc->dev;
1214         struct drm_atomic_state *state;
1215         struct intel_encoder *encoder;
1216         struct drm_connector *connector;
1217         struct drm_connector_state *connector_state;
1218         int count = 0, count_hdmi = 0;
1219         int i;
1220
1221         if (HAS_GMCH_DISPLAY(dev))
1222                 return false;
1223
1224         state = crtc_state->base.state;
1225
1226         for_each_connector_in_state(state, connector, connector_state, i) {
1227                 if (connector_state->crtc != crtc_state->base.crtc)
1228                         continue;
1229
1230                 encoder = to_intel_encoder(connector_state->best_encoder);
1231
1232                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1233                 count++;
1234         }
1235
1236         /*
1237          * HDMI 12bpc affects the clocks, so it's only possible
1238          * when not cloning with other encoder types.
1239          */
1240         return count_hdmi > 0 && count_hdmi == count;
1241 }
1242
1243 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1244                                struct intel_crtc_state *pipe_config)
1245 {
1246         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1247         struct drm_device *dev = encoder->base.dev;
1248         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1249         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1250         int clock_12bpc = clock_8bpc * 3 / 2;
1251         int desired_bpp;
1252
1253         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1254
1255         if (pipe_config->has_hdmi_sink)
1256                 pipe_config->has_infoframe = true;
1257
1258         if (intel_hdmi->color_range_auto) {
1259                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1260                 pipe_config->limited_color_range =
1261                         pipe_config->has_hdmi_sink &&
1262                         drm_match_cea_mode(adjusted_mode) > 1;
1263         } else {
1264                 pipe_config->limited_color_range =
1265                         intel_hdmi->limited_color_range;
1266         }
1267
1268         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1269                 pipe_config->pixel_multiplier = 2;
1270                 clock_8bpc *= 2;
1271                 clock_12bpc *= 2;
1272         }
1273
1274         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1275                 pipe_config->has_pch_encoder = true;
1276
1277         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1278                 pipe_config->has_audio = true;
1279
1280         /*
1281          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1282          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1283          * outputs. We also need to check that the higher clock still fits
1284          * within limits.
1285          */
1286         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1287             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
1288             hdmi_12bpc_possible(pipe_config)) {
1289                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1290                 desired_bpp = 12*3;
1291
1292                 /* Need to adjust the port link by 1.5x for 12bpc. */
1293                 pipe_config->port_clock = clock_12bpc;
1294         } else {
1295                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1296                 desired_bpp = 8*3;
1297
1298                 pipe_config->port_clock = clock_8bpc;
1299         }
1300
1301         if (!pipe_config->bw_constrained) {
1302                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1303                 pipe_config->pipe_bpp = desired_bpp;
1304         }
1305
1306         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1307                                   false) != MODE_OK) {
1308                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1309                 return false;
1310         }
1311
1312         /* Set user selected PAR to incoming mode's member */
1313         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1314
1315         return true;
1316 }
1317
1318 static void
1319 intel_hdmi_unset_edid(struct drm_connector *connector)
1320 {
1321         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1322
1323         intel_hdmi->has_hdmi_sink = false;
1324         intel_hdmi->has_audio = false;
1325         intel_hdmi->rgb_quant_range_selectable = false;
1326
1327         kfree(to_intel_connector(connector)->detect_edid);
1328         to_intel_connector(connector)->detect_edid = NULL;
1329 }
1330
1331 static bool
1332 intel_hdmi_set_edid(struct drm_connector *connector, bool force)
1333 {
1334         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1335         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1336         struct intel_encoder *intel_encoder =
1337                 &hdmi_to_dig_port(intel_hdmi)->base;
1338         enum intel_display_power_domain power_domain;
1339         struct edid *edid = NULL;
1340         bool connected = false;
1341
1342         power_domain = intel_display_port_power_domain(intel_encoder);
1343         intel_display_power_get(dev_priv, power_domain);
1344
1345         if (force)
1346                 edid = drm_get_edid(connector,
1347                                     intel_gmbus_get_adapter(dev_priv,
1348                                     intel_hdmi->ddc_bus));
1349
1350         intel_display_power_put(dev_priv, power_domain);
1351
1352         to_intel_connector(connector)->detect_edid = edid;
1353         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1354                 intel_hdmi->rgb_quant_range_selectable =
1355                         drm_rgb_quant_range_selectable(edid);
1356
1357                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1358                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1359                         intel_hdmi->has_audio =
1360                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1361
1362                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1363                         intel_hdmi->has_hdmi_sink =
1364                                 drm_detect_hdmi_monitor(edid);
1365
1366                 connected = true;
1367         }
1368
1369         return connected;
1370 }
1371
1372 static enum drm_connector_status
1373 intel_hdmi_detect(struct drm_connector *connector, bool force)
1374 {
1375         enum drm_connector_status status;
1376         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1377         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1378         bool live_status = false;
1379         unsigned int retry = 3;
1380
1381         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1382                       connector->base.id, connector->name);
1383
1384         while (!live_status && --retry) {
1385                 live_status = intel_digital_port_connected(dev_priv,
1386                                 hdmi_to_dig_port(intel_hdmi));
1387                 mdelay(10);
1388         }
1389
1390         if (!live_status)
1391                 DRM_DEBUG_KMS("Live status not up!");
1392
1393         intel_hdmi_unset_edid(connector);
1394
1395         if (intel_hdmi_set_edid(connector, live_status)) {
1396                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1397
1398                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1399                 status = connector_status_connected;
1400         } else
1401                 status = connector_status_disconnected;
1402
1403         return status;
1404 }
1405
1406 static void
1407 intel_hdmi_force(struct drm_connector *connector)
1408 {
1409         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1410
1411         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1412                       connector->base.id, connector->name);
1413
1414         intel_hdmi_unset_edid(connector);
1415
1416         if (connector->status != connector_status_connected)
1417                 return;
1418
1419         intel_hdmi_set_edid(connector, true);
1420         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1421 }
1422
1423 static int intel_hdmi_get_modes(struct drm_connector *connector)
1424 {
1425         struct edid *edid;
1426
1427         edid = to_intel_connector(connector)->detect_edid;
1428         if (edid == NULL)
1429                 return 0;
1430
1431         return intel_connector_update_modes(connector, edid);
1432 }
1433
1434 static bool
1435 intel_hdmi_detect_audio(struct drm_connector *connector)
1436 {
1437         bool has_audio = false;
1438         struct edid *edid;
1439
1440         edid = to_intel_connector(connector)->detect_edid;
1441         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1442                 has_audio = drm_detect_monitor_audio(edid);
1443
1444         return has_audio;
1445 }
1446
1447 static int
1448 intel_hdmi_set_property(struct drm_connector *connector,
1449                         struct drm_property *property,
1450                         uint64_t val)
1451 {
1452         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1453         struct intel_digital_port *intel_dig_port =
1454                 hdmi_to_dig_port(intel_hdmi);
1455         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1456         int ret;
1457
1458         ret = drm_object_property_set_value(&connector->base, property, val);
1459         if (ret)
1460                 return ret;
1461
1462         if (property == dev_priv->force_audio_property) {
1463                 enum hdmi_force_audio i = val;
1464                 bool has_audio;
1465
1466                 if (i == intel_hdmi->force_audio)
1467                         return 0;
1468
1469                 intel_hdmi->force_audio = i;
1470
1471                 if (i == HDMI_AUDIO_AUTO)
1472                         has_audio = intel_hdmi_detect_audio(connector);
1473                 else
1474                         has_audio = (i == HDMI_AUDIO_ON);
1475
1476                 if (i == HDMI_AUDIO_OFF_DVI)
1477                         intel_hdmi->has_hdmi_sink = 0;
1478
1479                 intel_hdmi->has_audio = has_audio;
1480                 goto done;
1481         }
1482
1483         if (property == dev_priv->broadcast_rgb_property) {
1484                 bool old_auto = intel_hdmi->color_range_auto;
1485                 bool old_range = intel_hdmi->limited_color_range;
1486
1487                 switch (val) {
1488                 case INTEL_BROADCAST_RGB_AUTO:
1489                         intel_hdmi->color_range_auto = true;
1490                         break;
1491                 case INTEL_BROADCAST_RGB_FULL:
1492                         intel_hdmi->color_range_auto = false;
1493                         intel_hdmi->limited_color_range = false;
1494                         break;
1495                 case INTEL_BROADCAST_RGB_LIMITED:
1496                         intel_hdmi->color_range_auto = false;
1497                         intel_hdmi->limited_color_range = true;
1498                         break;
1499                 default:
1500                         return -EINVAL;
1501                 }
1502
1503                 if (old_auto == intel_hdmi->color_range_auto &&
1504                     old_range == intel_hdmi->limited_color_range)
1505                         return 0;
1506
1507                 goto done;
1508         }
1509
1510         if (property == connector->dev->mode_config.aspect_ratio_property) {
1511                 switch (val) {
1512                 case DRM_MODE_PICTURE_ASPECT_NONE:
1513                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1514                         break;
1515                 case DRM_MODE_PICTURE_ASPECT_4_3:
1516                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1517                         break;
1518                 case DRM_MODE_PICTURE_ASPECT_16_9:
1519                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1520                         break;
1521                 default:
1522                         return -EINVAL;
1523                 }
1524                 goto done;
1525         }
1526
1527         return -EINVAL;
1528
1529 done:
1530         if (intel_dig_port->base.base.crtc)
1531                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1532
1533         return 0;
1534 }
1535
1536 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1537 {
1538         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1539         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1540         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1541
1542         intel_hdmi_prepare(encoder);
1543
1544         intel_hdmi->set_infoframes(&encoder->base,
1545                                    intel_crtc->config->has_hdmi_sink,
1546                                    adjusted_mode);
1547 }
1548
1549 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1550 {
1551         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1552         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1553         struct drm_device *dev = encoder->base.dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct intel_crtc *intel_crtc =
1556                 to_intel_crtc(encoder->base.crtc);
1557         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1558         enum dpio_channel port = vlv_dport_to_channel(dport);
1559         int pipe = intel_crtc->pipe;
1560         u32 val;
1561
1562         /* Enable clock channels for this port */
1563         mutex_lock(&dev_priv->sb_lock);
1564         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1565         val = 0;
1566         if (pipe)
1567                 val |= (1<<21);
1568         else
1569                 val &= ~(1<<21);
1570         val |= 0x001000c4;
1571         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1572
1573         /* HDMI 1.0V-2dB */
1574         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1575         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1576         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1577         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1578         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1579         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1580         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1581         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1582
1583         /* Program lane clock */
1584         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1585         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1586         mutex_unlock(&dev_priv->sb_lock);
1587
1588         intel_hdmi->set_infoframes(&encoder->base,
1589                                    intel_crtc->config->has_hdmi_sink,
1590                                    adjusted_mode);
1591
1592         g4x_enable_hdmi(encoder);
1593
1594         vlv_wait_port_ready(dev_priv, dport, 0x0);
1595 }
1596
1597 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1598 {
1599         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1600         struct drm_device *dev = encoder->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         struct intel_crtc *intel_crtc =
1603                 to_intel_crtc(encoder->base.crtc);
1604         enum dpio_channel port = vlv_dport_to_channel(dport);
1605         int pipe = intel_crtc->pipe;
1606
1607         intel_hdmi_prepare(encoder);
1608
1609         /* Program Tx lane resets to default */
1610         mutex_lock(&dev_priv->sb_lock);
1611         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1612                          DPIO_PCS_TX_LANE2_RESET |
1613                          DPIO_PCS_TX_LANE1_RESET);
1614         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1615                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1616                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1617                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1618                          DPIO_PCS_CLK_SOFT_RESET);
1619
1620         /* Fix up inter-pair skew failure */
1621         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1622         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1623         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1624
1625         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1626         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1627         mutex_unlock(&dev_priv->sb_lock);
1628 }
1629
1630 static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
1631                                      bool reset)
1632 {
1633         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1634         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1635         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1636         enum pipe pipe = crtc->pipe;
1637         uint32_t val;
1638
1639         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1640         if (reset)
1641                 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1642         else
1643                 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1644         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1645
1646         if (crtc->config->lane_count > 2) {
1647                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1648                 if (reset)
1649                         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1650                 else
1651                         val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1652                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1653         }
1654
1655         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1656         val |= CHV_PCS_REQ_SOFTRESET_EN;
1657         if (reset)
1658                 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1659         else
1660                 val |= DPIO_PCS_CLK_SOFT_RESET;
1661         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1662
1663         if (crtc->config->lane_count > 2) {
1664                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1665                 val |= CHV_PCS_REQ_SOFTRESET_EN;
1666                 if (reset)
1667                         val &= ~DPIO_PCS_CLK_SOFT_RESET;
1668                 else
1669                         val |= DPIO_PCS_CLK_SOFT_RESET;
1670                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1671         }
1672 }
1673
1674 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1675 {
1676         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1677         struct drm_device *dev = encoder->base.dev;
1678         struct drm_i915_private *dev_priv = dev->dev_private;
1679         struct intel_crtc *intel_crtc =
1680                 to_intel_crtc(encoder->base.crtc);
1681         enum dpio_channel ch = vlv_dport_to_channel(dport);
1682         enum pipe pipe = intel_crtc->pipe;
1683         u32 val;
1684
1685         intel_hdmi_prepare(encoder);
1686
1687         /*
1688          * Must trick the second common lane into life.
1689          * Otherwise we can't even access the PLL.
1690          */
1691         if (ch == DPIO_CH0 && pipe == PIPE_B)
1692                 dport->release_cl2_override =
1693                         !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
1694
1695         chv_phy_powergate_lanes(encoder, true, 0x0);
1696
1697         mutex_lock(&dev_priv->sb_lock);
1698
1699         /* Assert data lane reset */
1700         chv_data_lane_soft_reset(encoder, true);
1701
1702         /* program left/right clock distribution */
1703         if (pipe != PIPE_B) {
1704                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1705                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1706                 if (ch == DPIO_CH0)
1707                         val |= CHV_BUFLEFTENA1_FORCE;
1708                 if (ch == DPIO_CH1)
1709                         val |= CHV_BUFRIGHTENA1_FORCE;
1710                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1711         } else {
1712                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1713                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1714                 if (ch == DPIO_CH0)
1715                         val |= CHV_BUFLEFTENA2_FORCE;
1716                 if (ch == DPIO_CH1)
1717                         val |= CHV_BUFRIGHTENA2_FORCE;
1718                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1719         }
1720
1721         /* program clock channel usage */
1722         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1723         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1724         if (pipe != PIPE_B)
1725                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1726         else
1727                 val |= CHV_PCS_USEDCLKCHANNEL;
1728         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1729
1730         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1731         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1732         if (pipe != PIPE_B)
1733                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1734         else
1735                 val |= CHV_PCS_USEDCLKCHANNEL;
1736         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1737
1738         /*
1739          * This a a bit weird since generally CL
1740          * matches the pipe, but here we need to
1741          * pick the CL based on the port.
1742          */
1743         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1744         if (pipe != PIPE_B)
1745                 val &= ~CHV_CMN_USEDCLKCHANNEL;
1746         else
1747                 val |= CHV_CMN_USEDCLKCHANNEL;
1748         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1749
1750         mutex_unlock(&dev_priv->sb_lock);
1751 }
1752
1753 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1754 {
1755         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1756         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1757         u32 val;
1758
1759         mutex_lock(&dev_priv->sb_lock);
1760
1761         /* disable left/right clock distribution */
1762         if (pipe != PIPE_B) {
1763                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1764                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1765                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1766         } else {
1767                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1768                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1769                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1770         }
1771
1772         mutex_unlock(&dev_priv->sb_lock);
1773
1774         /*
1775          * Leave the power down bit cleared for at least one
1776          * lane so that chv_powergate_phy_ch() will power
1777          * on something when the channel is otherwise unused.
1778          * When the port is off and the override is removed
1779          * the lanes power down anyway, so otherwise it doesn't
1780          * really matter what the state of power down bits is
1781          * after this.
1782          */
1783         chv_phy_powergate_lanes(encoder, false, 0x0);
1784 }
1785
1786 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1787 {
1788         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1789         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1790         struct intel_crtc *intel_crtc =
1791                 to_intel_crtc(encoder->base.crtc);
1792         enum dpio_channel port = vlv_dport_to_channel(dport);
1793         int pipe = intel_crtc->pipe;
1794
1795         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1796         mutex_lock(&dev_priv->sb_lock);
1797         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1798         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1799         mutex_unlock(&dev_priv->sb_lock);
1800 }
1801
1802 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1803 {
1804         struct drm_device *dev = encoder->base.dev;
1805         struct drm_i915_private *dev_priv = dev->dev_private;
1806
1807         mutex_lock(&dev_priv->sb_lock);
1808
1809         /* Assert data lane reset */
1810         chv_data_lane_soft_reset(encoder, true);
1811
1812         mutex_unlock(&dev_priv->sb_lock);
1813 }
1814
1815 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1816 {
1817         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1818         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1819         struct drm_device *dev = encoder->base.dev;
1820         struct drm_i915_private *dev_priv = dev->dev_private;
1821         struct intel_crtc *intel_crtc =
1822                 to_intel_crtc(encoder->base.crtc);
1823         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1824         enum dpio_channel ch = vlv_dport_to_channel(dport);
1825         int pipe = intel_crtc->pipe;
1826         int data, i, stagger;
1827         u32 val;
1828
1829         mutex_lock(&dev_priv->sb_lock);
1830
1831         /* allow hardware to manage TX FIFO reset source */
1832         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1833         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1834         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1835
1836         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1837         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1838         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1839
1840         /* Program Tx latency optimal setting */
1841         for (i = 0; i < 4; i++) {
1842                 /* Set the upar bit */
1843                 data = (i == 1) ? 0x0 : 0x1;
1844                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1845                                 data << DPIO_UPAR_SHIFT);
1846         }
1847
1848         /* Data lane stagger programming */
1849         if (intel_crtc->config->port_clock > 270000)
1850                 stagger = 0x18;
1851         else if (intel_crtc->config->port_clock > 135000)
1852                 stagger = 0xd;
1853         else if (intel_crtc->config->port_clock > 67500)
1854                 stagger = 0x7;
1855         else if (intel_crtc->config->port_clock > 33750)
1856                 stagger = 0x4;
1857         else
1858                 stagger = 0x2;
1859
1860         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1861         val |= DPIO_TX2_STAGGER_MASK(0x1f);
1862         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1863
1864         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1865         val |= DPIO_TX2_STAGGER_MASK(0x1f);
1866         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1867
1868         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1869                        DPIO_LANESTAGGER_STRAP(stagger) |
1870                        DPIO_LANESTAGGER_STRAP_OVRD |
1871                        DPIO_TX1_STAGGER_MASK(0x1f) |
1872                        DPIO_TX1_STAGGER_MULT(6) |
1873                        DPIO_TX2_STAGGER_MULT(0));
1874
1875         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1876                        DPIO_LANESTAGGER_STRAP(stagger) |
1877                        DPIO_LANESTAGGER_STRAP_OVRD |
1878                        DPIO_TX1_STAGGER_MASK(0x1f) |
1879                        DPIO_TX1_STAGGER_MULT(7) |
1880                        DPIO_TX2_STAGGER_MULT(5));
1881
1882         /* Deassert data lane reset */
1883         chv_data_lane_soft_reset(encoder, false);
1884
1885         /* Clear calc init */
1886         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1887         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1888         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1889         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1890         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1891
1892         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1893         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1894         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1895         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1896         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1897
1898         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1899         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1900         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1901         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1902
1903         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1904         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1905         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1906         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1907
1908         /* FIXME: Program the support xxx V-dB */
1909         /* Use 800mV-0dB */
1910         for (i = 0; i < 4; i++) {
1911                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1912                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1913                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1914                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1915         }
1916
1917         for (i = 0; i < 4; i++) {
1918                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1919
1920                 val &= ~DPIO_SWING_MARGIN000_MASK;
1921                 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1922
1923                 /*
1924                  * Supposedly this value shouldn't matter when unique transition
1925                  * scale is disabled, but in fact it does matter. Let's just
1926                  * always program the same value and hope it's OK.
1927                  */
1928                 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
1929                 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
1930
1931                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1932         }
1933
1934         /*
1935          * The document said it needs to set bit 27 for ch0 and bit 26
1936          * for ch1. Might be a typo in the doc.
1937          * For now, for this unique transition scale selection, set bit
1938          * 27 for ch0 and ch1.
1939          */
1940         for (i = 0; i < 4; i++) {
1941                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1942                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1943                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1944         }
1945
1946         /* Start swing calculation */
1947         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1948         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1949         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1950
1951         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1952         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1953         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1954
1955         mutex_unlock(&dev_priv->sb_lock);
1956
1957         intel_hdmi->set_infoframes(&encoder->base,
1958                                    intel_crtc->config->has_hdmi_sink,
1959                                    adjusted_mode);
1960
1961         g4x_enable_hdmi(encoder);
1962
1963         vlv_wait_port_ready(dev_priv, dport, 0x0);
1964
1965         /* Second common lane will stay alive on its own now */
1966         if (dport->release_cl2_override) {
1967                 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
1968                 dport->release_cl2_override = false;
1969         }
1970 }
1971
1972 static void intel_hdmi_destroy(struct drm_connector *connector)
1973 {
1974         kfree(to_intel_connector(connector)->detect_edid);
1975         drm_connector_cleanup(connector);
1976         kfree(connector);
1977 }
1978
1979 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1980         .dpms = drm_atomic_helper_connector_dpms,
1981         .detect = intel_hdmi_detect,
1982         .force = intel_hdmi_force,
1983         .fill_modes = drm_helper_probe_single_connector_modes,
1984         .set_property = intel_hdmi_set_property,
1985         .atomic_get_property = intel_connector_atomic_get_property,
1986         .destroy = intel_hdmi_destroy,
1987         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1988         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1989 };
1990
1991 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1992         .get_modes = intel_hdmi_get_modes,
1993         .mode_valid = intel_hdmi_mode_valid,
1994         .best_encoder = intel_best_encoder,
1995 };
1996
1997 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1998         .destroy = intel_encoder_destroy,
1999 };
2000
2001 static void
2002 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2003 {
2004         intel_attach_force_audio_property(connector);
2005         intel_attach_broadcast_rgb_property(connector);
2006         intel_hdmi->color_range_auto = true;
2007         intel_attach_aspect_ratio_property(connector);
2008         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2009 }
2010
2011 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2012                                struct intel_connector *intel_connector)
2013 {
2014         struct drm_connector *connector = &intel_connector->base;
2015         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2016         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2017         struct drm_device *dev = intel_encoder->base.dev;
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         enum port port = intel_dig_port->port;
2020         uint8_t alternate_ddc_pin;
2021
2022         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2023                            DRM_MODE_CONNECTOR_HDMIA);
2024         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2025
2026         connector->interlace_allowed = 1;
2027         connector->doublescan_allowed = 0;
2028         connector->stereo_allowed = 1;
2029
2030         switch (port) {
2031         case PORT_B:
2032                 if (IS_BROXTON(dev_priv))
2033                         intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
2034                 else
2035                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2036                 /*
2037                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2038                  * interrupts to check the external panel connection.
2039                  */
2040                 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))
2041                         intel_encoder->hpd_pin = HPD_PORT_A;
2042                 else
2043                         intel_encoder->hpd_pin = HPD_PORT_B;
2044                 break;
2045         case PORT_C:
2046                 if (IS_BROXTON(dev_priv))
2047                         intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
2048                 else
2049                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2050                 intel_encoder->hpd_pin = HPD_PORT_C;
2051                 break;
2052         case PORT_D:
2053                 if (WARN_ON(IS_BROXTON(dev_priv)))
2054                         intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
2055                 else if (IS_CHERRYVIEW(dev_priv))
2056                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
2057                 else
2058                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2059                 intel_encoder->hpd_pin = HPD_PORT_D;
2060                 break;
2061         case PORT_E:
2062                 /* On SKL PORT E doesn't have seperate GMBUS pin
2063                  *  We rely on VBT to set a proper alternate GMBUS pin. */
2064                 alternate_ddc_pin =
2065                         dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
2066                 switch (alternate_ddc_pin) {
2067                 case DDC_PIN_B:
2068                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2069                         break;
2070                 case DDC_PIN_C:
2071                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2072                         break;
2073                 case DDC_PIN_D:
2074                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2075                         break;
2076                 default:
2077                         MISSING_CASE(alternate_ddc_pin);
2078                 }
2079                 intel_encoder->hpd_pin = HPD_PORT_E;
2080                 break;
2081         case PORT_A:
2082                 intel_encoder->hpd_pin = HPD_PORT_A;
2083                 /* Internal port only for eDP. */
2084         default:
2085                 BUG();
2086         }
2087
2088         if (IS_VALLEYVIEW(dev)) {
2089                 intel_hdmi->write_infoframe = vlv_write_infoframe;
2090                 intel_hdmi->set_infoframes = vlv_set_infoframes;
2091                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2092         } else if (IS_G4X(dev)) {
2093                 intel_hdmi->write_infoframe = g4x_write_infoframe;
2094                 intel_hdmi->set_infoframes = g4x_set_infoframes;
2095                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2096         } else if (HAS_DDI(dev)) {
2097                 intel_hdmi->write_infoframe = hsw_write_infoframe;
2098                 intel_hdmi->set_infoframes = hsw_set_infoframes;
2099                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2100         } else if (HAS_PCH_IBX(dev)) {
2101                 intel_hdmi->write_infoframe = ibx_write_infoframe;
2102                 intel_hdmi->set_infoframes = ibx_set_infoframes;
2103                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2104         } else {
2105                 intel_hdmi->write_infoframe = cpt_write_infoframe;
2106                 intel_hdmi->set_infoframes = cpt_set_infoframes;
2107                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2108         }
2109
2110         if (HAS_DDI(dev))
2111                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2112         else
2113                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2114         intel_connector->unregister = intel_connector_unregister;
2115
2116         intel_hdmi_add_properties(intel_hdmi, connector);
2117
2118         intel_connector_attach_encoder(intel_connector, intel_encoder);
2119         drm_connector_register(connector);
2120         intel_hdmi->attached_connector = intel_connector;
2121
2122         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2123          * 0xd.  Failure to do so will result in spurious interrupts being
2124          * generated on the port when a cable is not attached.
2125          */
2126         if (IS_G4X(dev) && !IS_GM45(dev)) {
2127                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2128                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2129         }
2130 }
2131
2132 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
2133 {
2134         struct intel_digital_port *intel_dig_port;
2135         struct intel_encoder *intel_encoder;
2136         struct intel_connector *intel_connector;
2137
2138         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2139         if (!intel_dig_port)
2140                 return;
2141
2142         intel_connector = intel_connector_alloc();
2143         if (!intel_connector) {
2144                 kfree(intel_dig_port);
2145                 return;
2146         }
2147
2148         intel_encoder = &intel_dig_port->base;
2149
2150         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2151                          DRM_MODE_ENCODER_TMDS);
2152
2153         intel_encoder->compute_config = intel_hdmi_compute_config;
2154         if (HAS_PCH_SPLIT(dev)) {
2155                 intel_encoder->disable = pch_disable_hdmi;
2156                 intel_encoder->post_disable = pch_post_disable_hdmi;
2157         } else {
2158                 intel_encoder->disable = g4x_disable_hdmi;
2159         }
2160         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2161         intel_encoder->get_config = intel_hdmi_get_config;
2162         if (IS_CHERRYVIEW(dev)) {
2163                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2164                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2165                 intel_encoder->enable = vlv_enable_hdmi;
2166                 intel_encoder->post_disable = chv_hdmi_post_disable;
2167                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2168         } else if (IS_VALLEYVIEW(dev)) {
2169                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2170                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2171                 intel_encoder->enable = vlv_enable_hdmi;
2172                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2173         } else {
2174                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2175                 if (HAS_PCH_CPT(dev))
2176                         intel_encoder->enable = cpt_enable_hdmi;
2177                 else if (HAS_PCH_IBX(dev))
2178                         intel_encoder->enable = ibx_enable_hdmi;
2179                 else
2180                         intel_encoder->enable = g4x_enable_hdmi;
2181         }
2182
2183         intel_encoder->type = INTEL_OUTPUT_HDMI;
2184         if (IS_CHERRYVIEW(dev)) {
2185                 if (port == PORT_D)
2186                         intel_encoder->crtc_mask = 1 << 2;
2187                 else
2188                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2189         } else {
2190                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2191         }
2192         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2193         /*
2194          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2195          * to work on real hardware. And since g4x can send infoframes to
2196          * only one port anyway, nothing is lost by allowing it.
2197          */
2198         if (IS_G4X(dev))
2199                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2200
2201         intel_dig_port->port = port;
2202         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2203         intel_dig_port->dp.output_reg = 0;
2204
2205         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2206 }