drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  42 {
  43         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  44 }
  45
  46 static void
  47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  48 {
  49         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  50         struct drm_i915_private *dev_priv = dev->dev_private;
  51         uint32_t enabled_bits;
  52
  53         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  54
  55         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  56              "HDMI port enabled, expecting disabled\n");
  57 }
  58
  59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  60 {
  61         struct intel_digital_port *intel_dig_port =
  62                 container_of(encoder, struct intel_digital_port, base.base);
  63         return &intel_dig_port->hdmi;
  64 }
  65
  66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  67 {
  68         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  69 }
  70
  71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  72 {
  73         switch (type) {
  74         case HDMI_INFOFRAME_TYPE_AVI:
  75                 return VIDEO_DIP_SELECT_AVI;
  76         case HDMI_INFOFRAME_TYPE_SPD:
  77                 return VIDEO_DIP_SELECT_SPD;
  78         case HDMI_INFOFRAME_TYPE_VENDOR:
  79                 return VIDEO_DIP_SELECT_VENDOR;
  80         default:
  81                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  82                 return 0;
  83         }
  84 }
  85
  86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  87 {
  88         switch (type) {
  89         case HDMI_INFOFRAME_TYPE_AVI:
  90                 return VIDEO_DIP_ENABLE_AVI;
  91         case HDMI_INFOFRAME_TYPE_SPD:
  92                 return VIDEO_DIP_ENABLE_SPD;
  93         case HDMI_INFOFRAME_TYPE_VENDOR:
  94                 return VIDEO_DIP_ENABLE_VENDOR;
  95         default:
  96                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  97                 return 0;
  98         }
  99 }
 100
 101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 102 {
 103         switch (type) {
 104         case HDMI_INFOFRAME_TYPE_AVI:
 105                 return VIDEO_DIP_ENABLE_AVI_HSW;
 106         case HDMI_INFOFRAME_TYPE_SPD:
 107                 return VIDEO_DIP_ENABLE_SPD_HSW;
 108         case HDMI_INFOFRAME_TYPE_VENDOR:
 109                 return VIDEO_DIP_ENABLE_VS_HSW;
 110         default:
 111                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 112                 return 0;
 113         }
 114 }
 115
 116 static i915_reg_t
 117 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 118                  enum transcoder cpu_transcoder,
 119                  enum hdmi_infoframe_type type,
 120                  int i)
 121 {
 122         switch (type) {
 123         case HDMI_INFOFRAME_TYPE_AVI:
 124                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 125         case HDMI_INFOFRAME_TYPE_SPD:
 126                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 127         case HDMI_INFOFRAME_TYPE_VENDOR:
 128                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 129         default:
 130                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 131                 return INVALID_MMIO_REG;
 132         }
 133 }
 134
 135 static void g4x_write_infoframe(struct drm_encoder *encoder,
 136                                 enum hdmi_infoframe_type type,
 137                                 const void *frame, ssize_t len)
 138 {
 139         const uint32_t *data = frame;
 140         struct drm_device *dev = encoder->dev;
 141         struct drm_i915_private *dev_priv = dev->dev_private;
 142         u32 val = I915_READ(VIDEO_DIP_CTL);
 143         int i;
 144
 145         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 146
 147         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 148         val |= g4x_infoframe_index(type);
 149
 150         val &= ~g4x_infoframe_enable(type);
 151
 152         I915_WRITE(VIDEO_DIP_CTL, val);
 153
 154         mmiowb();
 155         for (i = 0; i < len; i += 4) {
 156                 I915_WRITE(VIDEO_DIP_DATA, *data);
 157                 data++;
 158         }
 159         /* Write every possible data byte to force correct ECC calculation. */
 160         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 161                 I915_WRITE(VIDEO_DIP_DATA, 0);
 162         mmiowb();
 163
 164         val |= g4x_infoframe_enable(type);
 165         val &= ~VIDEO_DIP_FREQ_MASK;
 166         val |= VIDEO_DIP_FREQ_VSYNC;
 167
 168         I915_WRITE(VIDEO_DIP_CTL, val);
 169         POSTING_READ(VIDEO_DIP_CTL);
 170 }
 171
 172 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
 173                                   const struct intel_crtc_state *pipe_config)
 174 {
 175         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 176         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 177         u32 val = I915_READ(VIDEO_DIP_CTL);
 178
 179         if ((val & VIDEO_DIP_ENABLE) == 0)
 180                 return false;
 181
 182         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 183                 return false;
 184
 185         return val & (VIDEO_DIP_ENABLE_AVI |
 186                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 187 }
 188
 189 static void ibx_write_infoframe(struct drm_encoder *encoder,
 190                                 enum hdmi_infoframe_type type,
 191                                 const void *frame, ssize_t len)
 192 {
 193         const uint32_t *data = frame;
 194         struct drm_device *dev = encoder->dev;
 195         struct drm_i915_private *dev_priv = dev->dev_private;
 196         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 197         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 198         u32 val = I915_READ(reg);
 199         int i;
 200
 201         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 202
 203         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 204         val |= g4x_infoframe_index(type);
 205
 206         val &= ~g4x_infoframe_enable(type);
 207
 208         I915_WRITE(reg, val);
 209
 210         mmiowb();
 211         for (i = 0; i < len; i += 4) {
 212                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 213                 data++;
 214         }
 215         /* Write every possible data byte to force correct ECC calculation. */
 216         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 217                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 218         mmiowb();
 219
 220         val |= g4x_infoframe_enable(type);
 221         val &= ~VIDEO_DIP_FREQ_MASK;
 222         val |= VIDEO_DIP_FREQ_VSYNC;
 223
 224         I915_WRITE(reg, val);
 225         POSTING_READ(reg);
 226 }
 227
 228 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
 229                                   const struct intel_crtc_state *pipe_config)
 230 {
 231         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 232         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 233         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 234         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 235         u32 val = I915_READ(reg);
 236
 237         if ((val & VIDEO_DIP_ENABLE) == 0)
 238                 return false;
 239
 240         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 241                 return false;
 242
 243         return val & (VIDEO_DIP_ENABLE_AVI |
 244                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 245                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 246 }
 247
 248 static void cpt_write_infoframe(struct drm_encoder *encoder,
 249                                 enum hdmi_infoframe_type type,
 250                                 const void *frame, ssize_t len)
 251 {
 252         const uint32_t *data = frame;
 253         struct drm_device *dev = encoder->dev;
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 256         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 257         u32 val = I915_READ(reg);
 258         int i;
 259
 260         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 261
 262         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 263         val |= g4x_infoframe_index(type);
 264
 265         /* The DIP control register spec says that we need to update the AVI
 266          * infoframe without clearing its enable bit */
 267         if (type != HDMI_INFOFRAME_TYPE_AVI)
 268                 val &= ~g4x_infoframe_enable(type);
 269
 270         I915_WRITE(reg, val);
 271
 272         mmiowb();
 273         for (i = 0; i < len; i += 4) {
 274                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 275                 data++;
 276         }
 277         /* Write every possible data byte to force correct ECC calculation. */
 278         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 279                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 280         mmiowb();
 281
 282         val |= g4x_infoframe_enable(type);
 283         val &= ~VIDEO_DIP_FREQ_MASK;
 284         val |= VIDEO_DIP_FREQ_VSYNC;
 285
 286         I915_WRITE(reg, val);
 287         POSTING_READ(reg);
 288 }
 289
 290 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
 291                                   const struct intel_crtc_state *pipe_config)
 292 {
 293         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 294         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 295         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 296
 297         if ((val & VIDEO_DIP_ENABLE) == 0)
 298                 return false;
 299
 300         return val & (VIDEO_DIP_ENABLE_AVI |
 301                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 302                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 303 }
 304
 305 static void vlv_write_infoframe(struct drm_encoder *encoder,
 306                                 enum hdmi_infoframe_type type,
 307                                 const void *frame, ssize_t len)
 308 {
 309         const uint32_t *data = frame;
 310         struct drm_device *dev = encoder->dev;
 311         struct drm_i915_private *dev_priv = dev->dev_private;
 312         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 313         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 314         u32 val = I915_READ(reg);
 315         int i;
 316
 317         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 318
 319         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 320         val |= g4x_infoframe_index(type);
 321
 322         val &= ~g4x_infoframe_enable(type);
 323
 324         I915_WRITE(reg, val);
 325
 326         mmiowb();
 327         for (i = 0; i < len; i += 4) {
 328                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 329                 data++;
 330         }
 331         /* Write every possible data byte to force correct ECC calculation. */
 332         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 333                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 334         mmiowb();
 335
 336         val |= g4x_infoframe_enable(type);
 337         val &= ~VIDEO_DIP_FREQ_MASK;
 338         val |= VIDEO_DIP_FREQ_VSYNC;
 339
 340         I915_WRITE(reg, val);
 341         POSTING_READ(reg);
 342 }
 343
 344 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
 345                                   const struct intel_crtc_state *pipe_config)
 346 {
 347         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 348         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 349         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 350         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 351
 352         if ((val & VIDEO_DIP_ENABLE) == 0)
 353                 return false;
 354
 355         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 356                 return false;
 357
 358         return val & (VIDEO_DIP_ENABLE_AVI |
 359                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 360                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 361 }
 362
 363 static void hsw_write_infoframe(struct drm_encoder *encoder,
 364                                 enum hdmi_infoframe_type type,
 365                                 const void *frame, ssize_t len)
 366 {
 367         const uint32_t *data = frame;
 368         struct drm_device *dev = encoder->dev;
 369         struct drm_i915_private *dev_priv = dev->dev_private;
 370         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 371         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
 372         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 373         i915_reg_t data_reg;
 374         int i;
 375         u32 val = I915_READ(ctl_reg);
 376
 377         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
 378         if (i915_mmio_reg_valid(data_reg))
 379                 return;
 380
 381         val &= ~hsw_infoframe_enable(type);
 382         I915_WRITE(ctl_reg, val);
 383
 384         mmiowb();
 385         for (i = 0; i < len; i += 4) {
 386                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 387                                             type, i >> 2), *data);
 388                 data++;
 389         }
 390         /* Write every possible data byte to force correct ECC calculation. */
 391         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 392                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 393                                             type, i >> 2), 0);
 394         mmiowb();
 395
 396         val |= hsw_infoframe_enable(type);
 397         I915_WRITE(ctl_reg, val);
 398         POSTING_READ(ctl_reg);
 399 }
 400
 401 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
 402                                   const struct intel_crtc_state *pipe_config)
 403 {
 404         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 405         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 406
 407         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 408                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 409                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 410 }
 411
 412 /*
 413  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 414  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 415  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 416  * used for both technologies.
 417  *
 418  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 419  * DW1:       DB3       | DB2 | DB1 | DB0
 420  * DW2:       DB7       | DB6 | DB5 | DB4
 421  * DW3: ...
 422  *
 423  * (HB is Header Byte, DB is Data Byte)
 424  *
 425  * The hdmi pack() functions don't know about that hardware specific hole so we
 426  * trick them by giving an offset into the buffer and moving back the header
 427  * bytes by one.
 428  */
 429 static void intel_write_infoframe(struct drm_encoder *encoder,
 430                                   union hdmi_infoframe *frame)
 431 {
 432         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 433         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 434         ssize_t len;
 435
 436         /* see comment above for the reason for this offset */
 437         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 438         if (len < 0)
 439                 return;
 440
 441         /* Insert the 'hole' (see big comment above) at position 3 */
 442         buffer[0] = buffer[1];
 443         buffer[1] = buffer[2];
 444         buffer[2] = buffer[3];
 445         buffer[3] = 0;
 446         len++;
 447
 448         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 449 }
 450
 451 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 452                                          const struct drm_display_mode *adjusted_mode)
 453 {
 454         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 455         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 456         union hdmi_infoframe frame;
 457         int ret;
 458
 459         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 460                                                        adjusted_mode);
 461         if (ret < 0) {
 462                 DRM_ERROR("couldn't fill AVI infoframe\n");
 463                 return;
 464         }
 465
 466         if (intel_hdmi->rgb_quant_range_selectable) {
 467                 if (intel_crtc->config->limited_color_range)
 468                         frame.avi.quantization_range =
 469                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 470                 else
 471                         frame.avi.quantization_range =
 472                                 HDMI_QUANTIZATION_RANGE_FULL;
 473         }
 474
 475         intel_write_infoframe(encoder, &frame);
 476 }
 477
 478 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 479 {
 480         union hdmi_infoframe frame;
 481         int ret;
 482
 483         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 484         if (ret < 0) {
 485                 DRM_ERROR("couldn't fill SPD infoframe\n");
 486                 return;
 487         }
 488
 489         frame.spd.sdi = HDMI_SPD_SDI_PC;
 490
 491         intel_write_infoframe(encoder, &frame);
 492 }
 493
 494 static void
 495 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 496                               const struct drm_display_mode *adjusted_mode)
 497 {
 498         union hdmi_infoframe frame;
 499         int ret;
 500
 501         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 502                                                           adjusted_mode);
 503         if (ret < 0)
 504                 return;
 505
 506         intel_write_infoframe(encoder, &frame);
 507 }
 508
 509 static void g4x_set_infoframes(struct drm_encoder *encoder,
 510                                bool enable,
 511                                const struct drm_display_mode *adjusted_mode)
 512 {
 513         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 514         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 515         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 516         i915_reg_t reg = VIDEO_DIP_CTL;
 517         u32 val = I915_READ(reg);
 518         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 519
 520         assert_hdmi_port_disabled(intel_hdmi);
 521
 522         /* If the registers were not initialized yet, they might be zeroes,
 523          * which means we're selecting the AVI DIP and we're setting its
 524          * frequency to once. This seems to really confuse the HW and make
 525          * things stop working (the register spec says the AVI always needs to
 526          * be sent every VSync). So here we avoid writing to the register more
 527          * than we need and also explicitly select the AVI DIP and explicitly
 528          * set its frequency to every VSync. Avoiding to write it twice seems to
 529          * be enough to solve the problem, but being defensive shouldn't hurt us
 530          * either. */
 531         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 532
 533         if (!enable) {
 534                 if (!(val & VIDEO_DIP_ENABLE))
 535                         return;
 536                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 537                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 538                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 539                         return;
 540                 }
 541                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 542                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 543                 I915_WRITE(reg, val);
 544                 POSTING_READ(reg);
 545                 return;
 546         }
 547
 548         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 549                 if (val & VIDEO_DIP_ENABLE) {
 550                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 551                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 552                         return;
 553                 }
 554                 val &= ~VIDEO_DIP_PORT_MASK;
 555                 val |= port;
 556         }
 557
 558         val |= VIDEO_DIP_ENABLE;
 559         val &= ~(VIDEO_DIP_ENABLE_AVI |
 560                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 561
 562         I915_WRITE(reg, val);
 563         POSTING_READ(reg);
 564
 565         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 566         intel_hdmi_set_spd_infoframe(encoder);
 567         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 568 }
 569
 570 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
 571 {
 572         struct drm_device *dev = encoder->dev;
 573         struct drm_connector *connector;
 574
 575         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 576
 577         /*
 578          * HDMI cloning is only supported on g4x which doesn't
 579          * support deep color or GCP infoframes anyway so no
 580          * need to worry about multiple HDMI sinks here.
 581          */
 582         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 583                 if (connector->encoder == encoder)
 584                         return connector->display_info.bpc > 8;
 585
 586         return false;
 587 }
 588
 589 /*
 590  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 591  *
 592  * From HDMI specification 1.4a:
 593  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 594  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 595  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 596  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 597  *   phase of 0
 598  */
 599 static bool gcp_default_phase_possible(int pipe_bpp,
 600                                        const struct drm_display_mode *mode)
 601 {
 602         unsigned int pixels_per_group;
 603
 604         switch (pipe_bpp) {
 605         case 30:
 606                 /* 4 pixels in 5 clocks */
 607                 pixels_per_group = 4;
 608                 break;
 609         case 36:
 610                 /* 2 pixels in 3 clocks */
 611                 pixels_per_group = 2;
 612                 break;
 613         case 48:
 614                 /* 1 pixel in 2 clocks */
 615                 pixels_per_group = 1;
 616                 break;
 617         default:
 618                 /* phase information not relevant for 8bpc */
 619                 return false;
 620         }
 621
 622         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 623                 mode->crtc_htotal % pixels_per_group == 0 &&
 624                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 625                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 626                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 627                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 628                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 629                  mode->crtc_htotal/2 % pixels_per_group == 0);
 630 }
 631
 632 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
 633 {
 634         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 635         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 636         i915_reg_t reg;
 637         u32 val = 0;
 638
 639         if (HAS_DDI(dev_priv))
 640                 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
 641         else if (IS_VALLEYVIEW(dev_priv))
 642                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 643         else if (HAS_PCH_SPLIT(dev_priv->dev))
 644                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 645         else
 646                 return false;
 647
 648         /* Indicate color depth whenever the sink supports deep color */
 649         if (hdmi_sink_is_deep_color(encoder))
 650                 val |= GCP_COLOR_INDICATION;
 651
 652         /* Enable default_phase whenever the display mode is suitably aligned */
 653         if (gcp_default_phase_possible(crtc->config->pipe_bpp,
 654                                        &crtc->config->base.adjusted_mode))
 655                 val |= GCP_DEFAULT_PHASE_ENABLE;
 656
 657         I915_WRITE(reg, val);
 658
 659         return val != 0;
 660 }
 661
 662 static void ibx_set_infoframes(struct drm_encoder *encoder,
 663                                bool enable,
 664                                const struct drm_display_mode *adjusted_mode)
 665 {
 666         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 667         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 668         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 669         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 670         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 671         u32 val = I915_READ(reg);
 672         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 673
 674         assert_hdmi_port_disabled(intel_hdmi);
 675
 676         /* See the big comment in g4x_set_infoframes() */
 677         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 678
 679         if (!enable) {
 680                 if (!(val & VIDEO_DIP_ENABLE))
 681                         return;
 682                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 683                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 684                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 685                 I915_WRITE(reg, val);
 686                 POSTING_READ(reg);
 687                 return;
 688         }
 689
 690         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 691                 WARN(val & VIDEO_DIP_ENABLE,
 692                      "DIP already enabled on port %c\n",
 693                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 694                 val &= ~VIDEO_DIP_PORT_MASK;
 695                 val |= port;
 696         }
 697
 698         val |= VIDEO_DIP_ENABLE;
 699         val &= ~(VIDEO_DIP_ENABLE_AVI |
 700                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 701                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 702
 703         if (intel_hdmi_set_gcp_infoframe(encoder))
 704                 val |= VIDEO_DIP_ENABLE_GCP;
 705
 706         I915_WRITE(reg, val);
 707         POSTING_READ(reg);
 708
 709         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 710         intel_hdmi_set_spd_infoframe(encoder);
 711         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 712 }
 713
 714 static void cpt_set_infoframes(struct drm_encoder *encoder,
 715                                bool enable,
 716                                const struct drm_display_mode *adjusted_mode)
 717 {
 718         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 719         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 720         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 721         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 722         u32 val = I915_READ(reg);
 723
 724         assert_hdmi_port_disabled(intel_hdmi);
 725
 726         /* See the big comment in g4x_set_infoframes() */
 727         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 728
 729         if (!enable) {
 730                 if (!(val & VIDEO_DIP_ENABLE))
 731                         return;
 732                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 733                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 734                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 735                 I915_WRITE(reg, val);
 736                 POSTING_READ(reg);
 737                 return;
 738         }
 739
 740         /* Set both together, unset both together: see the spec. */
 741         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 742         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 743                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 744
 745         if (intel_hdmi_set_gcp_infoframe(encoder))
 746                 val |= VIDEO_DIP_ENABLE_GCP;
 747
 748         I915_WRITE(reg, val);
 749         POSTING_READ(reg);
 750
 751         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 752         intel_hdmi_set_spd_infoframe(encoder);
 753         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 754 }
 755
 756 static void vlv_set_infoframes(struct drm_encoder *encoder,
 757                                bool enable,
 758                                const struct drm_display_mode *adjusted_mode)
 759 {
 760         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 761         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 762         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 763         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 764         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 765         u32 val = I915_READ(reg);
 766         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 767
 768         assert_hdmi_port_disabled(intel_hdmi);
 769
 770         /* See the big comment in g4x_set_infoframes() */
 771         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 772
 773         if (!enable) {
 774                 if (!(val & VIDEO_DIP_ENABLE))
 775                         return;
 776                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 777                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 778                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 779                 I915_WRITE(reg, val);
 780                 POSTING_READ(reg);
 781                 return;
 782         }
 783
 784         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 785                 WARN(val & VIDEO_DIP_ENABLE,
 786                      "DIP already enabled on port %c\n",
 787                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 788                 val &= ~VIDEO_DIP_PORT_MASK;
 789                 val |= port;
 790         }
 791
 792         val |= VIDEO_DIP_ENABLE;
 793         val &= ~(VIDEO_DIP_ENABLE_AVI |
 794                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 795                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 796
 797         if (intel_hdmi_set_gcp_infoframe(encoder))
 798                 val |= VIDEO_DIP_ENABLE_GCP;
 799
 800         I915_WRITE(reg, val);
 801         POSTING_READ(reg);
 802
 803         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 804         intel_hdmi_set_spd_infoframe(encoder);
 805         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 806 }
 807
 808 static void hsw_set_infoframes(struct drm_encoder *encoder,
 809                                bool enable,
 810                                const struct drm_display_mode *adjusted_mode)
 811 {
 812         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 813         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 814         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 815         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 816         u32 val = I915_READ(reg);
 817
 818         assert_hdmi_port_disabled(intel_hdmi);
 819
 820         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 821                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 822                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 823
 824         if (!enable) {
 825                 I915_WRITE(reg, val);
 826                 POSTING_READ(reg);
 827                 return;
 828         }
 829
 830         if (intel_hdmi_set_gcp_infoframe(encoder))
 831                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 832
 833         I915_WRITE(reg, val);
 834         POSTING_READ(reg);
 835
 836         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 837         intel_hdmi_set_spd_infoframe(encoder);
 838         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 839 }
 840
 841 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 842 {
 843         struct drm_device *dev = encoder->base.dev;
 844         struct drm_i915_private *dev_priv = dev->dev_private;
 845         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 846         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 847         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 848         u32 hdmi_val;
 849
 850         hdmi_val = SDVO_ENCODING_HDMI;
 851         if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
 852                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
 853         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 854                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 855         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 856                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 857
 858         if (crtc->config->pipe_bpp > 24)
 859                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 860         else
 861                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 862
 863         if (crtc->config->has_hdmi_sink)
 864                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 865
 866         if (HAS_PCH_CPT(dev))
 867                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 868         else if (IS_CHERRYVIEW(dev))
 869                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 870         else
 871                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 872
 873         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 874         POSTING_READ(intel_hdmi->hdmi_reg);
 875 }
 876
 877 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 878                                     enum pipe *pipe)
 879 {
 880         struct drm_device *dev = encoder->base.dev;
 881         struct drm_i915_private *dev_priv = dev->dev_private;
 882         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 883         enum intel_display_power_domain power_domain;
 884         u32 tmp;
 885
 886         power_domain = intel_display_port_power_domain(encoder);
 887         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 888                 return false;
 889
 890         tmp = I915_READ(intel_hdmi->hdmi_reg);
 891
 892         if (!(tmp & SDVO_ENABLE))
 893                 return false;
 894
 895         if (HAS_PCH_CPT(dev))
 896                 *pipe = PORT_TO_PIPE_CPT(tmp);
 897         else if (IS_CHERRYVIEW(dev))
 898                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 899         else
 900                 *pipe = PORT_TO_PIPE(tmp);
 901
 902         return true;
 903 }
 904
 905 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 906                                   struct intel_crtc_state *pipe_config)
 907 {
 908         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 909         struct drm_device *dev = encoder->base.dev;
 910         struct drm_i915_private *dev_priv = dev->dev_private;
 911         u32 tmp, flags = 0;
 912         int dotclock;
 913
 914         tmp = I915_READ(intel_hdmi->hdmi_reg);
 915
 916         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 917                 flags |= DRM_MODE_FLAG_PHSYNC;
 918         else
 919                 flags |= DRM_MODE_FLAG_NHSYNC;
 920
 921         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 922                 flags |= DRM_MODE_FLAG_PVSYNC;
 923         else
 924                 flags |= DRM_MODE_FLAG_NVSYNC;
 925
 926         if (tmp & HDMI_MODE_SELECT_HDMI)
 927                 pipe_config->has_hdmi_sink = true;
 928
 929         if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
 930                 pipe_config->has_infoframe = true;
 931
 932         if (tmp & SDVO_AUDIO_ENABLE)
 933                 pipe_config->has_audio = true;
 934
 935         if (!HAS_PCH_SPLIT(dev) &&
 936             tmp & HDMI_COLOR_RANGE_16_235)
 937                 pipe_config->limited_color_range = true;
 938
 939         pipe_config->base.adjusted_mode.flags |= flags;
 940
 941         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 942                 dotclock = pipe_config->port_clock * 2 / 3;
 943         else
 944                 dotclock = pipe_config->port_clock;
 945
 946         if (pipe_config->pixel_multiplier)
 947                 dotclock /= pipe_config->pixel_multiplier;
 948
 949         if (HAS_PCH_SPLIT(dev_priv->dev))
 950                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 951
 952         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 953 }
 954
 955 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
 956 {
 957         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 958
 959         WARN_ON(!crtc->config->has_hdmi_sink);
 960         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 961                          pipe_name(crtc->pipe));
 962         intel_audio_codec_enable(encoder);
 963 }
 964
 965 static void g4x_enable_hdmi(struct intel_encoder *encoder)
 966 {
 967         struct drm_device *dev = encoder->base.dev;
 968         struct drm_i915_private *dev_priv = dev->dev_private;
 969         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 970         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 971         u32 temp;
 972
 973         temp = I915_READ(intel_hdmi->hdmi_reg);
 974
 975         temp |= SDVO_ENABLE;
 976         if (crtc->config->has_audio)
 977                 temp |= SDVO_AUDIO_ENABLE;
 978
 979         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 980         POSTING_READ(intel_hdmi->hdmi_reg);
 981
 982         if (crtc->config->has_audio)
 983                 intel_enable_hdmi_audio(encoder);
 984 }
 985
 986 static void ibx_enable_hdmi(struct intel_encoder *encoder)
 987 {
 988         struct drm_device *dev = encoder->base.dev;
 989         struct drm_i915_private *dev_priv = dev->dev_private;
 990         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 991         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 992         u32 temp;
 993
 994         temp = I915_READ(intel_hdmi->hdmi_reg);
 995
 996         temp |= SDVO_ENABLE;
 997         if (crtc->config->has_audio)
 998                 temp |= SDVO_AUDIO_ENABLE;
 999
1000         /*
1001          * HW workaround, need to write this twice for issue
1002          * that may result in first write getting masked.
1003          */
1004         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1005         POSTING_READ(intel_hdmi->hdmi_reg);
1006         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1007         POSTING_READ(intel_hdmi->hdmi_reg);
1008
1009         /*
1010          * HW workaround, need to toggle enable bit off and on
1011          * for 12bpc with pixel repeat.
1012          *
1013          * FIXME: BSpec says this should be done at the end of
1014          * of the modeset sequence, so not sure if this isn't too soon.
1015          */
1016         if (crtc->config->pipe_bpp > 24 &&
1017             crtc->config->pixel_multiplier > 1) {
1018                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1019                 POSTING_READ(intel_hdmi->hdmi_reg);
1020
1021                 /*
1022                  * HW workaround, need to write this twice for issue
1023                  * that may result in first write getting masked.
1024                  */
1025                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1026                 POSTING_READ(intel_hdmi->hdmi_reg);
1027                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1028                 POSTING_READ(intel_hdmi->hdmi_reg);
1029         }
1030
1031         if (crtc->config->has_audio)
1032                 intel_enable_hdmi_audio(encoder);
1033 }
1034
1035 static void cpt_enable_hdmi(struct intel_encoder *encoder)
1036 {
1037         struct drm_device *dev = encoder->base.dev;
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1040         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1041         enum pipe pipe = crtc->pipe;
1042         u32 temp;
1043
1044         temp = I915_READ(intel_hdmi->hdmi_reg);
1045
1046         temp |= SDVO_ENABLE;
1047         if (crtc->config->has_audio)
1048                 temp |= SDVO_AUDIO_ENABLE;
1049
1050         /*
1051          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1052          *
1053          * The procedure for 12bpc is as follows:
1054          * 1. disable HDMI clock gating
1055          * 2. enable HDMI with 8bpc
1056          * 3. enable HDMI with 12bpc
1057          * 4. enable HDMI clock gating
1058          */
1059
1060         if (crtc->config->pipe_bpp > 24) {
1061                 I915_WRITE(TRANS_CHICKEN1(pipe),
1062                            I915_READ(TRANS_CHICKEN1(pipe)) |
1063                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1064
1065                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1066                 temp |= SDVO_COLOR_FORMAT_8bpc;
1067         }
1068
1069         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1070         POSTING_READ(intel_hdmi->hdmi_reg);
1071
1072         if (crtc->config->pipe_bpp > 24) {
1073                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1074                 temp |= HDMI_COLOR_FORMAT_12bpc;
1075
1076                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1077                 POSTING_READ(intel_hdmi->hdmi_reg);
1078
1079                 I915_WRITE(TRANS_CHICKEN1(pipe),
1080                            I915_READ(TRANS_CHICKEN1(pipe)) &
1081                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1082         }
1083
1084         if (crtc->config->has_audio)
1085                 intel_enable_hdmi_audio(encoder);
1086 }
1087
1088 static void vlv_enable_hdmi(struct intel_encoder *encoder)
1089 {
1090 }
1091
1092 static void intel_disable_hdmi(struct intel_encoder *encoder)
1093 {
1094         struct drm_device *dev = encoder->base.dev;
1095         struct drm_i915_private *dev_priv = dev->dev_private;
1096         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1097         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1098         u32 temp;
1099
1100         temp = I915_READ(intel_hdmi->hdmi_reg);
1101
1102         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1103         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1104         POSTING_READ(intel_hdmi->hdmi_reg);
1105
1106         /*
1107          * HW workaround for IBX, we need to move the port
1108          * to transcoder A after disabling it to allow the
1109          * matching DP port to be enabled on transcoder A.
1110          */
1111         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1112                 /*
1113                  * We get CPU/PCH FIFO underruns on the other pipe when
1114                  * doing the workaround. Sweep them under the rug.
1115                  */
1116                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1117                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1118
1119                 temp &= ~SDVO_PIPE_B_SELECT;
1120                 temp |= SDVO_ENABLE;
1121                 /*
1122                  * HW workaround, need to write this twice for issue
1123                  * that may result in first write getting masked.
1124                  */
1125                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1126                 POSTING_READ(intel_hdmi->hdmi_reg);
1127                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1128                 POSTING_READ(intel_hdmi->hdmi_reg);
1129
1130                 temp &= ~SDVO_ENABLE;
1131                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1132                 POSTING_READ(intel_hdmi->hdmi_reg);
1133
1134                 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
1135                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1136                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1137         }
1138
1139         intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1140 }
1141
1142 static void g4x_disable_hdmi(struct intel_encoder *encoder)
1143 {
1144         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1145
1146         if (crtc->config->has_audio)
1147                 intel_audio_codec_disable(encoder);
1148
1149         intel_disable_hdmi(encoder);
1150 }
1151
1152 static void pch_disable_hdmi(struct intel_encoder *encoder)
1153 {
1154         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1155
1156         if (crtc->config->has_audio)
1157                 intel_audio_codec_disable(encoder);
1158 }
1159
1160 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1161 {
1162         intel_disable_hdmi(encoder);
1163 }
1164
1165 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1166 {
1167         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1168
1169         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1170                 return 165000;
1171         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1172                 return 300000;
1173         else
1174                 return 225000;
1175 }
1176
1177 static enum drm_mode_status
1178 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1179                       int clock, bool respect_dvi_limit)
1180 {
1181         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1182
1183         if (clock < 25000)
1184                 return MODE_CLOCK_LOW;
1185         if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1186                 return MODE_CLOCK_HIGH;
1187
1188         /* BXT DPLL can't generate 223-240 MHz */
1189         if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1190                 return MODE_CLOCK_RANGE;
1191
1192         /* CHV DPLL can't generate 216-240 MHz */
1193         if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1194                 return MODE_CLOCK_RANGE;
1195
1196         return MODE_OK;
1197 }
1198
1199 static enum drm_mode_status
1200 intel_hdmi_mode_valid(struct drm_connector *connector,
1201                       struct drm_display_mode *mode)
1202 {
1203         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1204         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1205         enum drm_mode_status status;
1206         int clock;
1207
1208         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1209                 return MODE_NO_DBLESCAN;
1210
1211         clock = mode->clock;
1212         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1213                 clock *= 2;
1214
1215         /* check if we can do 8bpc */
1216         status = hdmi_port_clock_valid(hdmi, clock, true);
1217
1218         /* if we can't do 8bpc we may still be able to do 12bpc */
1219         if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1220                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1221
1222         return status;
1223 }
1224
1225 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1226 {
1227         struct drm_device *dev = crtc_state->base.crtc->dev;
1228         struct drm_atomic_state *state;
1229         struct intel_encoder *encoder;
1230         struct drm_connector *connector;
1231         struct drm_connector_state *connector_state;
1232         int count = 0, count_hdmi = 0;
1233         int i;
1234
1235         if (HAS_GMCH_DISPLAY(dev))
1236                 return false;
1237
1238         state = crtc_state->base.state;
1239
1240         for_each_connector_in_state(state, connector, connector_state, i) {
1241                 if (connector_state->crtc != crtc_state->base.crtc)
1242                         continue;
1243
1244                 encoder = to_intel_encoder(connector_state->best_encoder);
1245
1246                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1247                 count++;
1248         }
1249
1250         /*
1251          * HDMI 12bpc affects the clocks, so it's only possible
1252          * when not cloning with other encoder types.
1253          */
1254         return count_hdmi > 0 && count_hdmi == count;
1255 }
1256
1257 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1258                                struct intel_crtc_state *pipe_config)
1259 {
1260         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1261         struct drm_device *dev = encoder->base.dev;
1262         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1263         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1264         int clock_12bpc = clock_8bpc * 3 / 2;
1265         int desired_bpp;
1266
1267         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1268
1269         if (pipe_config->has_hdmi_sink)
1270                 pipe_config->has_infoframe = true;
1271
1272         if (intel_hdmi->color_range_auto) {
1273                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1274                 pipe_config->limited_color_range =
1275                         pipe_config->has_hdmi_sink &&
1276                         drm_match_cea_mode(adjusted_mode) > 1;
1277         } else {
1278                 pipe_config->limited_color_range =
1279                         intel_hdmi->limited_color_range;
1280         }
1281
1282         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1283                 pipe_config->pixel_multiplier = 2;
1284                 clock_8bpc *= 2;
1285                 clock_12bpc *= 2;
1286         }
1287
1288         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1289                 pipe_config->has_pch_encoder = true;
1290
1291         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1292                 pipe_config->has_audio = true;
1293
1294         /*
1295          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1296          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1297          * outputs. We also need to check that the higher clock still fits
1298          * within limits.
1299          */
1300         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1301             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
1302             hdmi_12bpc_possible(pipe_config)) {
1303                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1304                 desired_bpp = 12*3;
1305
1306                 /* Need to adjust the port link by 1.5x for 12bpc. */
1307                 pipe_config->port_clock = clock_12bpc;
1308         } else {
1309                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1310                 desired_bpp = 8*3;
1311
1312                 pipe_config->port_clock = clock_8bpc;
1313         }
1314
1315         if (!pipe_config->bw_constrained) {
1316                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1317                 pipe_config->pipe_bpp = desired_bpp;
1318         }
1319
1320         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1321                                   false) != MODE_OK) {
1322                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1323                 return false;
1324         }
1325
1326         /* Set user selected PAR to incoming mode's member */
1327         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1328
1329         return true;
1330 }
1331
1332 static void
1333 intel_hdmi_unset_edid(struct drm_connector *connector)
1334 {
1335         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1336
1337         intel_hdmi->has_hdmi_sink = false;
1338         intel_hdmi->has_audio = false;
1339         intel_hdmi->rgb_quant_range_selectable = false;
1340
1341         kfree(to_intel_connector(connector)->detect_edid);
1342         to_intel_connector(connector)->detect_edid = NULL;
1343 }
1344
1345 static bool
1346 intel_hdmi_set_edid(struct drm_connector *connector, bool force)
1347 {
1348         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1349         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1350         struct edid *edid = NULL;
1351         bool connected = false;
1352
1353         if (force) {
1354                 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1355
1356                 edid = drm_get_edid(connector,
1357                                     intel_gmbus_get_adapter(dev_priv,
1358                                     intel_hdmi->ddc_bus));
1359
1360                 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1361         }
1362
1363         to_intel_connector(connector)->detect_edid = edid;
1364         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1365                 intel_hdmi->rgb_quant_range_selectable =
1366                         drm_rgb_quant_range_selectable(edid);
1367
1368                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1369                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1370                         intel_hdmi->has_audio =
1371                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1372
1373                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1374                         intel_hdmi->has_hdmi_sink =
1375                                 drm_detect_hdmi_monitor(edid);
1376
1377                 connected = true;
1378         }
1379
1380         return connected;
1381 }
1382
1383 static enum drm_connector_status
1384 intel_hdmi_detect(struct drm_connector *connector, bool force)
1385 {
1386         enum drm_connector_status status;
1387         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1388         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1389         bool live_status = false;
1390         unsigned int retry = 3;
1391
1392         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1393                       connector->base.id, connector->name);
1394
1395         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1396
1397         while (!live_status && --retry) {
1398                 live_status = intel_digital_port_connected(dev_priv,
1399                                 hdmi_to_dig_port(intel_hdmi));
1400                 mdelay(10);
1401         }
1402
1403         if (!live_status)
1404                 DRM_DEBUG_KMS("Live status not up!");
1405
1406         intel_hdmi_unset_edid(connector);
1407
1408         if (intel_hdmi_set_edid(connector, live_status)) {
1409                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1410
1411                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1412                 status = connector_status_connected;
1413         } else
1414                 status = connector_status_disconnected;
1415
1416         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1417
1418         return status;
1419 }
1420
1421 static void
1422 intel_hdmi_force(struct drm_connector *connector)
1423 {
1424         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1425
1426         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1427                       connector->base.id, connector->name);
1428
1429         intel_hdmi_unset_edid(connector);
1430
1431         if (connector->status != connector_status_connected)
1432                 return;
1433
1434         intel_hdmi_set_edid(connector, true);
1435         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1436 }
1437
1438 static int intel_hdmi_get_modes(struct drm_connector *connector)
1439 {
1440         struct edid *edid;
1441
1442         edid = to_intel_connector(connector)->detect_edid;
1443         if (edid == NULL)
1444                 return 0;
1445
1446         return intel_connector_update_modes(connector, edid);
1447 }
1448
1449 static bool
1450 intel_hdmi_detect_audio(struct drm_connector *connector)
1451 {
1452         bool has_audio = false;
1453         struct edid *edid;
1454
1455         edid = to_intel_connector(connector)->detect_edid;
1456         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1457                 has_audio = drm_detect_monitor_audio(edid);
1458
1459         return has_audio;
1460 }
1461
1462 static int
1463 intel_hdmi_set_property(struct drm_connector *connector,
1464                         struct drm_property *property,
1465                         uint64_t val)
1466 {
1467         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1468         struct intel_digital_port *intel_dig_port =
1469                 hdmi_to_dig_port(intel_hdmi);
1470         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1471         int ret;
1472
1473         ret = drm_object_property_set_value(&connector->base, property, val);
1474         if (ret)
1475                 return ret;
1476
1477         if (property == dev_priv->force_audio_property) {
1478                 enum hdmi_force_audio i = val;
1479                 bool has_audio;
1480
1481                 if (i == intel_hdmi->force_audio)
1482                         return 0;
1483
1484                 intel_hdmi->force_audio = i;
1485
1486                 if (i == HDMI_AUDIO_AUTO)
1487                         has_audio = intel_hdmi_detect_audio(connector);
1488                 else
1489                         has_audio = (i == HDMI_AUDIO_ON);
1490
1491                 if (i == HDMI_AUDIO_OFF_DVI)
1492                         intel_hdmi->has_hdmi_sink = 0;
1493
1494                 intel_hdmi->has_audio = has_audio;
1495                 goto done;
1496         }
1497
1498         if (property == dev_priv->broadcast_rgb_property) {
1499                 bool old_auto = intel_hdmi->color_range_auto;
1500                 bool old_range = intel_hdmi->limited_color_range;
1501
1502                 switch (val) {
1503                 case INTEL_BROADCAST_RGB_AUTO:
1504                         intel_hdmi->color_range_auto = true;
1505                         break;
1506                 case INTEL_BROADCAST_RGB_FULL:
1507                         intel_hdmi->color_range_auto = false;
1508                         intel_hdmi->limited_color_range = false;
1509                         break;
1510                 case INTEL_BROADCAST_RGB_LIMITED:
1511                         intel_hdmi->color_range_auto = false;
1512                         intel_hdmi->limited_color_range = true;
1513                         break;
1514                 default:
1515                         return -EINVAL;
1516                 }
1517
1518                 if (old_auto == intel_hdmi->color_range_auto &&
1519                     old_range == intel_hdmi->limited_color_range)
1520                         return 0;
1521
1522                 goto done;
1523         }
1524
1525         if (property == connector->dev->mode_config.aspect_ratio_property) {
1526                 switch (val) {
1527                 case DRM_MODE_PICTURE_ASPECT_NONE:
1528                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1529                         break;
1530                 case DRM_MODE_PICTURE_ASPECT_4_3:
1531                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1532                         break;
1533                 case DRM_MODE_PICTURE_ASPECT_16_9:
1534                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1535                         break;
1536                 default:
1537                         return -EINVAL;
1538                 }
1539                 goto done;
1540         }
1541
1542         return -EINVAL;
1543
1544 done:
1545         if (intel_dig_port->base.base.crtc)
1546                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1547
1548         return 0;
1549 }
1550
1551 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1552 {
1553         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1554         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1555         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1556
1557         intel_hdmi_prepare(encoder);
1558
1559         intel_hdmi->set_infoframes(&encoder->base,
1560                                    intel_crtc->config->has_hdmi_sink,
1561                                    adjusted_mode);
1562 }
1563
1564 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1565 {
1566         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1567         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1568         struct drm_device *dev = encoder->base.dev;
1569         struct drm_i915_private *dev_priv = dev->dev_private;
1570         struct intel_crtc *intel_crtc =
1571                 to_intel_crtc(encoder->base.crtc);
1572         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1573         enum dpio_channel port = vlv_dport_to_channel(dport);
1574         int pipe = intel_crtc->pipe;
1575         u32 val;
1576
1577         /* Enable clock channels for this port */
1578         mutex_lock(&dev_priv->sb_lock);
1579         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1580         val = 0;
1581         if (pipe)
1582                 val |= (1<<21);
1583         else
1584                 val &= ~(1<<21);
1585         val |= 0x001000c4;
1586         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1587
1588         /* HDMI 1.0V-2dB */
1589         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1590         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1591         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1592         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1593         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1594         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1595         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1596         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1597
1598         /* Program lane clock */
1599         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1600         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1601         mutex_unlock(&dev_priv->sb_lock);
1602
1603         intel_hdmi->set_infoframes(&encoder->base,
1604                                    intel_crtc->config->has_hdmi_sink,
1605                                    adjusted_mode);
1606
1607         g4x_enable_hdmi(encoder);
1608
1609         vlv_wait_port_ready(dev_priv, dport, 0x0);
1610 }
1611
1612 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1613 {
1614         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1615         struct drm_device *dev = encoder->base.dev;
1616         struct drm_i915_private *dev_priv = dev->dev_private;
1617         struct intel_crtc *intel_crtc =
1618                 to_intel_crtc(encoder->base.crtc);
1619         enum dpio_channel port = vlv_dport_to_channel(dport);
1620         int pipe = intel_crtc->pipe;
1621
1622         intel_hdmi_prepare(encoder);
1623
1624         /* Program Tx lane resets to default */
1625         mutex_lock(&dev_priv->sb_lock);
1626         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1627                          DPIO_PCS_TX_LANE2_RESET |
1628                          DPIO_PCS_TX_LANE1_RESET);
1629         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1630                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1631                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1632                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1633                          DPIO_PCS_CLK_SOFT_RESET);
1634
1635         /* Fix up inter-pair skew failure */
1636         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1637         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1638         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1639
1640         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1641         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1642         mutex_unlock(&dev_priv->sb_lock);
1643 }
1644
1645 static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
1646                                      bool reset)
1647 {
1648         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1649         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1650         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1651         enum pipe pipe = crtc->pipe;
1652         uint32_t val;
1653
1654         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1655         if (reset)
1656                 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1657         else
1658                 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1659         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1660
1661         if (crtc->config->lane_count > 2) {
1662                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1663                 if (reset)
1664                         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1665                 else
1666                         val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1667                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1668         }
1669
1670         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1671         val |= CHV_PCS_REQ_SOFTRESET_EN;
1672         if (reset)
1673                 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1674         else
1675                 val |= DPIO_PCS_CLK_SOFT_RESET;
1676         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1677
1678         if (crtc->config->lane_count > 2) {
1679                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1680                 val |= CHV_PCS_REQ_SOFTRESET_EN;
1681                 if (reset)
1682                         val &= ~DPIO_PCS_CLK_SOFT_RESET;
1683                 else
1684                         val |= DPIO_PCS_CLK_SOFT_RESET;
1685                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1686         }
1687 }
1688
1689 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1690 {
1691         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1692         struct drm_device *dev = encoder->base.dev;
1693         struct drm_i915_private *dev_priv = dev->dev_private;
1694         struct intel_crtc *intel_crtc =
1695                 to_intel_crtc(encoder->base.crtc);
1696         enum dpio_channel ch = vlv_dport_to_channel(dport);
1697         enum pipe pipe = intel_crtc->pipe;
1698         u32 val;
1699
1700         intel_hdmi_prepare(encoder);
1701
1702         /*
1703          * Must trick the second common lane into life.
1704          * Otherwise we can't even access the PLL.
1705          */
1706         if (ch == DPIO_CH0 && pipe == PIPE_B)
1707                 dport->release_cl2_override =
1708                         !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
1709
1710         chv_phy_powergate_lanes(encoder, true, 0x0);
1711
1712         mutex_lock(&dev_priv->sb_lock);
1713
1714         /* Assert data lane reset */
1715         chv_data_lane_soft_reset(encoder, true);
1716
1717         /* program left/right clock distribution */
1718         if (pipe != PIPE_B) {
1719                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1720                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1721                 if (ch == DPIO_CH0)
1722                         val |= CHV_BUFLEFTENA1_FORCE;
1723                 if (ch == DPIO_CH1)
1724                         val |= CHV_BUFRIGHTENA1_FORCE;
1725                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1726         } else {
1727                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1728                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1729                 if (ch == DPIO_CH0)
1730                         val |= CHV_BUFLEFTENA2_FORCE;
1731                 if (ch == DPIO_CH1)
1732                         val |= CHV_BUFRIGHTENA2_FORCE;
1733                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1734         }
1735
1736         /* program clock channel usage */
1737         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1738         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1739         if (pipe != PIPE_B)
1740                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1741         else
1742                 val |= CHV_PCS_USEDCLKCHANNEL;
1743         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1744
1745         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1746         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1747         if (pipe != PIPE_B)
1748                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1749         else
1750                 val |= CHV_PCS_USEDCLKCHANNEL;
1751         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1752
1753         /*
1754          * This a a bit weird since generally CL
1755          * matches the pipe, but here we need to
1756          * pick the CL based on the port.
1757          */
1758         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1759         if (pipe != PIPE_B)
1760                 val &= ~CHV_CMN_USEDCLKCHANNEL;
1761         else
1762                 val |= CHV_CMN_USEDCLKCHANNEL;
1763         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1764
1765         mutex_unlock(&dev_priv->sb_lock);
1766 }
1767
1768 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1769 {
1770         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1771         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1772         u32 val;
1773
1774         mutex_lock(&dev_priv->sb_lock);
1775
1776         /* disable left/right clock distribution */
1777         if (pipe != PIPE_B) {
1778                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1779                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1780                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1781         } else {
1782                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1783                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1784                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1785         }
1786
1787         mutex_unlock(&dev_priv->sb_lock);
1788
1789         /*
1790          * Leave the power down bit cleared for at least one
1791          * lane so that chv_powergate_phy_ch() will power
1792          * on something when the channel is otherwise unused.
1793          * When the port is off and the override is removed
1794          * the lanes power down anyway, so otherwise it doesn't
1795          * really matter what the state of power down bits is
1796          * after this.
1797          */
1798         chv_phy_powergate_lanes(encoder, false, 0x0);
1799 }
1800
1801 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1802 {
1803         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1804         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1805         struct intel_crtc *intel_crtc =
1806                 to_intel_crtc(encoder->base.crtc);
1807         enum dpio_channel port = vlv_dport_to_channel(dport);
1808         int pipe = intel_crtc->pipe;
1809
1810         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1811         mutex_lock(&dev_priv->sb_lock);
1812         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1813         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1814         mutex_unlock(&dev_priv->sb_lock);
1815 }
1816
1817 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1818 {
1819         struct drm_device *dev = encoder->base.dev;
1820         struct drm_i915_private *dev_priv = dev->dev_private;
1821
1822         mutex_lock(&dev_priv->sb_lock);
1823
1824         /* Assert data lane reset */
1825         chv_data_lane_soft_reset(encoder, true);
1826
1827         mutex_unlock(&dev_priv->sb_lock);
1828 }
1829
1830 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1831 {
1832         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1833         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1834         struct drm_device *dev = encoder->base.dev;
1835         struct drm_i915_private *dev_priv = dev->dev_private;
1836         struct intel_crtc *intel_crtc =
1837                 to_intel_crtc(encoder->base.crtc);
1838         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1839         enum dpio_channel ch = vlv_dport_to_channel(dport);
1840         int pipe = intel_crtc->pipe;
1841         int data, i, stagger;
1842         u32 val;
1843
1844         mutex_lock(&dev_priv->sb_lock);
1845
1846         /* allow hardware to manage TX FIFO reset source */
1847         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1848         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1849         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1850
1851         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1852         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1853         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1854
1855         /* Program Tx latency optimal setting */
1856         for (i = 0; i < 4; i++) {
1857                 /* Set the upar bit */
1858                 data = (i == 1) ? 0x0 : 0x1;
1859                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1860                                 data << DPIO_UPAR_SHIFT);
1861         }
1862
1863         /* Data lane stagger programming */
1864         if (intel_crtc->config->port_clock > 270000)
1865                 stagger = 0x18;
1866         else if (intel_crtc->config->port_clock > 135000)
1867                 stagger = 0xd;
1868         else if (intel_crtc->config->port_clock > 67500)
1869                 stagger = 0x7;
1870         else if (intel_crtc->config->port_clock > 33750)
1871                 stagger = 0x4;
1872         else
1873                 stagger = 0x2;
1874
1875         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1876         val |= DPIO_TX2_STAGGER_MASK(0x1f);
1877         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1878
1879         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1880         val |= DPIO_TX2_STAGGER_MASK(0x1f);
1881         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1882
1883         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1884                        DPIO_LANESTAGGER_STRAP(stagger) |
1885                        DPIO_LANESTAGGER_STRAP_OVRD |
1886                        DPIO_TX1_STAGGER_MASK(0x1f) |
1887                        DPIO_TX1_STAGGER_MULT(6) |
1888                        DPIO_TX2_STAGGER_MULT(0));
1889
1890         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1891                        DPIO_LANESTAGGER_STRAP(stagger) |
1892                        DPIO_LANESTAGGER_STRAP_OVRD |
1893                        DPIO_TX1_STAGGER_MASK(0x1f) |
1894                        DPIO_TX1_STAGGER_MULT(7) |
1895                        DPIO_TX2_STAGGER_MULT(5));
1896
1897         /* Deassert data lane reset */
1898         chv_data_lane_soft_reset(encoder, false);
1899
1900         /* Clear calc init */
1901         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1902         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1903         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1904         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1905         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1906
1907         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1908         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1909         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1910         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1911         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1912
1913         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1914         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1915         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1916         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1917
1918         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1919         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1920         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1921         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1922
1923         /* FIXME: Program the support xxx V-dB */
1924         /* Use 800mV-0dB */
1925         for (i = 0; i < 4; i++) {
1926                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1927                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1928                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1929                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1930         }
1931
1932         for (i = 0; i < 4; i++) {
1933                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1934
1935                 val &= ~DPIO_SWING_MARGIN000_MASK;
1936                 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1937
1938                 /*
1939                  * Supposedly this value shouldn't matter when unique transition
1940                  * scale is disabled, but in fact it does matter. Let's just
1941                  * always program the same value and hope it's OK.
1942                  */
1943                 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
1944                 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
1945
1946                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1947         }
1948
1949         /*
1950          * The document said it needs to set bit 27 for ch0 and bit 26
1951          * for ch1. Might be a typo in the doc.
1952          * For now, for this unique transition scale selection, set bit
1953          * 27 for ch0 and ch1.
1954          */
1955         for (i = 0; i < 4; i++) {
1956                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1957                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1958                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1959         }
1960
1961         /* Start swing calculation */
1962         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1963         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1964         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1965
1966         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1967         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1968         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1969
1970         mutex_unlock(&dev_priv->sb_lock);
1971
1972         intel_hdmi->set_infoframes(&encoder->base,
1973                                    intel_crtc->config->has_hdmi_sink,
1974                                    adjusted_mode);
1975
1976         g4x_enable_hdmi(encoder);
1977
1978         vlv_wait_port_ready(dev_priv, dport, 0x0);
1979
1980         /* Second common lane will stay alive on its own now */
1981         if (dport->release_cl2_override) {
1982                 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
1983                 dport->release_cl2_override = false;
1984         }
1985 }
1986
1987 static void intel_hdmi_destroy(struct drm_connector *connector)
1988 {
1989         kfree(to_intel_connector(connector)->detect_edid);
1990         drm_connector_cleanup(connector);
1991         kfree(connector);
1992 }
1993
1994 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1995         .dpms = drm_atomic_helper_connector_dpms,
1996         .detect = intel_hdmi_detect,
1997         .force = intel_hdmi_force,
1998         .fill_modes = drm_helper_probe_single_connector_modes,
1999         .set_property = intel_hdmi_set_property,
2000         .atomic_get_property = intel_connector_atomic_get_property,
2001         .destroy = intel_hdmi_destroy,
2002         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2003         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2004 };
2005
2006 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2007         .get_modes = intel_hdmi_get_modes,
2008         .mode_valid = intel_hdmi_mode_valid,
2009         .best_encoder = intel_best_encoder,
2010 };
2011
2012 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2013         .destroy = intel_encoder_destroy,
2014 };
2015
2016 static void
2017 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2018 {
2019         intel_attach_force_audio_property(connector);
2020         intel_attach_broadcast_rgb_property(connector);
2021         intel_hdmi->color_range_auto = true;
2022         intel_attach_aspect_ratio_property(connector);
2023         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2024 }
2025
2026 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2027                                struct intel_connector *intel_connector)
2028 {
2029         struct drm_connector *connector = &intel_connector->base;
2030         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2031         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2032         struct drm_device *dev = intel_encoder->base.dev;
2033         struct drm_i915_private *dev_priv = dev->dev_private;
2034         enum port port = intel_dig_port->port;
2035         uint8_t alternate_ddc_pin;
2036
2037         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2038                            DRM_MODE_CONNECTOR_HDMIA);
2039         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2040
2041         connector->interlace_allowed = 1;
2042         connector->doublescan_allowed = 0;
2043         connector->stereo_allowed = 1;
2044
2045         switch (port) {
2046         case PORT_B:
2047                 if (IS_BROXTON(dev_priv))
2048                         intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
2049                 else
2050                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2051                 /*
2052                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2053                  * interrupts to check the external panel connection.
2054                  */
2055                 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
2056                         intel_encoder->hpd_pin = HPD_PORT_A;
2057                 else
2058                         intel_encoder->hpd_pin = HPD_PORT_B;
2059                 break;
2060         case PORT_C:
2061                 if (IS_BROXTON(dev_priv))
2062                         intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
2063                 else
2064                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2065                 intel_encoder->hpd_pin = HPD_PORT_C;
2066                 break;
2067         case PORT_D:
2068                 if (WARN_ON(IS_BROXTON(dev_priv)))
2069                         intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
2070                 else if (IS_CHERRYVIEW(dev_priv))
2071                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
2072                 else
2073                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2074                 intel_encoder->hpd_pin = HPD_PORT_D;
2075                 break;
2076         case PORT_E:
2077                 /* On SKL PORT E doesn't have seperate GMBUS pin
2078                  *  We rely on VBT to set a proper alternate GMBUS pin. */
2079                 alternate_ddc_pin =
2080                         dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
2081                 switch (alternate_ddc_pin) {
2082                 case DDC_PIN_B:
2083                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2084                         break;
2085                 case DDC_PIN_C:
2086                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2087                         break;
2088                 case DDC_PIN_D:
2089                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2090                         break;
2091                 default:
2092                         MISSING_CASE(alternate_ddc_pin);
2093                 }
2094                 intel_encoder->hpd_pin = HPD_PORT_E;
2095                 break;
2096         case PORT_A:
2097                 intel_encoder->hpd_pin = HPD_PORT_A;
2098                 /* Internal port only for eDP. */
2099         default:
2100                 BUG();
2101         }
2102
2103         if (IS_VALLEYVIEW(dev)) {
2104                 intel_hdmi->write_infoframe = vlv_write_infoframe;
2105                 intel_hdmi->set_infoframes = vlv_set_infoframes;
2106                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2107         } else if (IS_G4X(dev)) {
2108                 intel_hdmi->write_infoframe = g4x_write_infoframe;
2109                 intel_hdmi->set_infoframes = g4x_set_infoframes;
2110                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2111         } else if (HAS_DDI(dev)) {
2112                 intel_hdmi->write_infoframe = hsw_write_infoframe;
2113                 intel_hdmi->set_infoframes = hsw_set_infoframes;
2114                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2115         } else if (HAS_PCH_IBX(dev)) {
2116                 intel_hdmi->write_infoframe = ibx_write_infoframe;
2117                 intel_hdmi->set_infoframes = ibx_set_infoframes;
2118                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2119         } else {
2120                 intel_hdmi->write_infoframe = cpt_write_infoframe;
2121                 intel_hdmi->set_infoframes = cpt_set_infoframes;
2122                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2123         }
2124
2125         if (HAS_DDI(dev))
2126                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2127         else
2128                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2129         intel_connector->unregister = intel_connector_unregister;
2130
2131         intel_hdmi_add_properties(intel_hdmi, connector);
2132
2133         intel_connector_attach_encoder(intel_connector, intel_encoder);
2134         drm_connector_register(connector);
2135         intel_hdmi->attached_connector = intel_connector;
2136
2137         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2138          * 0xd.  Failure to do so will result in spurious interrupts being
2139          * generated on the port when a cable is not attached.
2140          */
2141         if (IS_G4X(dev) && !IS_GM45(dev)) {
2142                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2143                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2144         }
2145 }
2146
2147 void intel_hdmi_init(struct drm_device *dev,
2148                      i915_reg_t hdmi_reg, enum port port)
2149 {
2150         struct intel_digital_port *intel_dig_port;
2151         struct intel_encoder *intel_encoder;
2152         struct intel_connector *intel_connector;
2153
2154         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2155         if (!intel_dig_port)
2156                 return;
2157
2158         intel_connector = intel_connector_alloc();
2159         if (!intel_connector) {
2160                 kfree(intel_dig_port);
2161                 return;
2162         }
2163
2164         intel_encoder = &intel_dig_port->base;
2165
2166         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2167                          DRM_MODE_ENCODER_TMDS, NULL);
2168
2169         intel_encoder->compute_config = intel_hdmi_compute_config;
2170         if (HAS_PCH_SPLIT(dev)) {
2171                 intel_encoder->disable = pch_disable_hdmi;
2172                 intel_encoder->post_disable = pch_post_disable_hdmi;
2173         } else {
2174                 intel_encoder->disable = g4x_disable_hdmi;
2175         }
2176         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2177         intel_encoder->get_config = intel_hdmi_get_config;
2178         if (IS_CHERRYVIEW(dev)) {
2179                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2180                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2181                 intel_encoder->enable = vlv_enable_hdmi;
2182                 intel_encoder->post_disable = chv_hdmi_post_disable;
2183                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2184         } else if (IS_VALLEYVIEW(dev)) {
2185                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2186                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2187                 intel_encoder->enable = vlv_enable_hdmi;
2188                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2189         } else {
2190                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2191                 if (HAS_PCH_CPT(dev))
2192                         intel_encoder->enable = cpt_enable_hdmi;
2193                 else if (HAS_PCH_IBX(dev))
2194                         intel_encoder->enable = ibx_enable_hdmi;
2195                 else
2196                         intel_encoder->enable = g4x_enable_hdmi;
2197         }
2198
2199         intel_encoder->type = INTEL_OUTPUT_HDMI;
2200         if (IS_CHERRYVIEW(dev)) {
2201                 if (port == PORT_D)
2202                         intel_encoder->crtc_mask = 1 << 2;
2203                 else
2204                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2205         } else {
2206                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2207         }
2208         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2209         /*
2210          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2211          * to work on real hardware. And since g4x can send infoframes to
2212          * only one port anyway, nothing is lost by allowing it.
2213          */
2214         if (IS_G4X(dev))
2215                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2216
2217         intel_dig_port->port = port;
2218         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2219         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2220
2221         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2222 }