drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_set_mode(struct drm_atomic_state *state);
  90 static int intel_framebuffer_init(struct drm_device *dev,
  91                                   struct intel_framebuffer *ifb,
  92                                   struct drm_mode_fb_cmd2 *mode_cmd,
  93                                   struct drm_i915_gem_object *obj);
  94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  97                                          struct intel_link_m_n *m_n,
  98                                          struct intel_link_m_n *m2_n2);
  99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 102 static void vlv_prepare_pll(struct intel_crtc *crtc,
 103                             const struct intel_crtc_state *pipe_config);
 104 static void chv_prepare_pll(struct intel_crtc *crtc,
 105                             const struct intel_crtc_state *pipe_config);
 106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 109         struct intel_crtc_state *crtc_state);
 110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 111                            int num_connectors);
 112 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 113
 114 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 115 {
 116         if (!connector->mst_port)
 117                 return connector->encoder;
 118         else
 119                 return &connector->mst_port->mst_encoders[pipe]->base;
 120 }
 121
 122 typedef struct {
 123         int     min, max;
 124 } intel_range_t;
 125
 126 typedef struct {
 127         int     dot_limit;
 128         int     p2_slow, p2_fast;
 129 } intel_p2_t;
 130
 131 typedef struct intel_limit intel_limit_t;
 132 struct intel_limit {
 133         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 134         intel_p2_t          p2;
 135 };
 136
 137 int
 138 intel_pch_rawclk(struct drm_device *dev)
 139 {
 140         struct drm_i915_private *dev_priv = dev->dev_private;
 141
 142         WARN_ON(!HAS_PCH_SPLIT(dev));
 143
 144         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 145 }
 146
 147 static inline u32 /* units of 100MHz */
 148 intel_fdi_link_freq(struct drm_device *dev)
 149 {
 150         if (IS_GEN5(dev)) {
 151                 struct drm_i915_private *dev_priv = dev->dev_private;
 152                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 153         } else
 154                 return 27;
 155 }
 156
 157 static const intel_limit_t intel_limits_i8xx_dac = {
 158         .dot = { .min = 25000, .max = 350000 },
 159         .vco = { .min = 908000, .max = 1512000 },
 160         .n = { .min = 2, .max = 16 },
 161         .m = { .min = 96, .max = 140 },
 162         .m1 = { .min = 18, .max = 26 },
 163         .m2 = { .min = 6, .max = 16 },
 164         .p = { .min = 4, .max = 128 },
 165         .p1 = { .min = 2, .max = 33 },
 166         .p2 = { .dot_limit = 165000,
 167                 .p2_slow = 4, .p2_fast = 2 },
 168 };
 169
 170 static const intel_limit_t intel_limits_i8xx_dvo = {
 171         .dot = { .min = 25000, .max = 350000 },
 172         .vco = { .min = 908000, .max = 1512000 },
 173         .n = { .min = 2, .max = 16 },
 174         .m = { .min = 96, .max = 140 },
 175         .m1 = { .min = 18, .max = 26 },
 176         .m2 = { .min = 6, .max = 16 },
 177         .p = { .min = 4, .max = 128 },
 178         .p1 = { .min = 2, .max = 33 },
 179         .p2 = { .dot_limit = 165000,
 180                 .p2_slow = 4, .p2_fast = 4 },
 181 };
 182
 183 static const intel_limit_t intel_limits_i8xx_lvds = {
 184         .dot = { .min = 25000, .max = 350000 },
 185         .vco = { .min = 908000, .max = 1512000 },
 186         .n = { .min = 2, .max = 16 },
 187         .m = { .min = 96, .max = 140 },
 188         .m1 = { .min = 18, .max = 26 },
 189         .m2 = { .min = 6, .max = 16 },
 190         .p = { .min = 4, .max = 128 },
 191         .p1 = { .min = 1, .max = 6 },
 192         .p2 = { .dot_limit = 165000,
 193                 .p2_slow = 14, .p2_fast = 7 },
 194 };
 195
 196 static const intel_limit_t intel_limits_i9xx_sdvo = {
 197         .dot = { .min = 20000, .max = 400000 },
 198         .vco = { .min = 1400000, .max = 2800000 },
 199         .n = { .min = 1, .max = 6 },
 200         .m = { .min = 70, .max = 120 },
 201         .m1 = { .min = 8, .max = 18 },
 202         .m2 = { .min = 3, .max = 7 },
 203         .p = { .min = 5, .max = 80 },
 204         .p1 = { .min = 1, .max = 8 },
 205         .p2 = { .dot_limit = 200000,
 206                 .p2_slow = 10, .p2_fast = 5 },
 207 };
 208
 209 static const intel_limit_t intel_limits_i9xx_lvds = {
 210         .dot = { .min = 20000, .max = 400000 },
 211         .vco = { .min = 1400000, .max = 2800000 },
 212         .n = { .min = 1, .max = 6 },
 213         .m = { .min = 70, .max = 120 },
 214         .m1 = { .min = 8, .max = 18 },
 215         .m2 = { .min = 3, .max = 7 },
 216         .p = { .min = 7, .max = 98 },
 217         .p1 = { .min = 1, .max = 8 },
 218         .p2 = { .dot_limit = 112000,
 219                 .p2_slow = 14, .p2_fast = 7 },
 220 };
 221
 222
 223 static const intel_limit_t intel_limits_g4x_sdvo = {
 224         .dot = { .min = 25000, .max = 270000 },
 225         .vco = { .min = 1750000, .max = 3500000},
 226         .n = { .min = 1, .max = 4 },
 227         .m = { .min = 104, .max = 138 },
 228         .m1 = { .min = 17, .max = 23 },
 229         .m2 = { .min = 5, .max = 11 },
 230         .p = { .min = 10, .max = 30 },
 231         .p1 = { .min = 1, .max = 3},
 232         .p2 = { .dot_limit = 270000,
 233                 .p2_slow = 10,
 234                 .p2_fast = 10
 235         },
 236 };
 237
 238 static const intel_limit_t intel_limits_g4x_hdmi = {
 239         .dot = { .min = 22000, .max = 400000 },
 240         .vco = { .min = 1750000, .max = 3500000},
 241         .n = { .min = 1, .max = 4 },
 242         .m = { .min = 104, .max = 138 },
 243         .m1 = { .min = 16, .max = 23 },
 244         .m2 = { .min = 5, .max = 11 },
 245         .p = { .min = 5, .max = 80 },
 246         .p1 = { .min = 1, .max = 8},
 247         .p2 = { .dot_limit = 165000,
 248                 .p2_slow = 10, .p2_fast = 5 },
 249 };
 250
 251 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 252         .dot = { .min = 20000, .max = 115000 },
 253         .vco = { .min = 1750000, .max = 3500000 },
 254         .n = { .min = 1, .max = 3 },
 255         .m = { .min = 104, .max = 138 },
 256         .m1 = { .min = 17, .max = 23 },
 257         .m2 = { .min = 5, .max = 11 },
 258         .p = { .min = 28, .max = 112 },
 259         .p1 = { .min = 2, .max = 8 },
 260         .p2 = { .dot_limit = 0,
 261                 .p2_slow = 14, .p2_fast = 14
 262         },
 263 };
 264
 265 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 266         .dot = { .min = 80000, .max = 224000 },
 267         .vco = { .min = 1750000, .max = 3500000 },
 268         .n = { .min = 1, .max = 3 },
 269         .m = { .min = 104, .max = 138 },
 270         .m1 = { .min = 17, .max = 23 },
 271         .m2 = { .min = 5, .max = 11 },
 272         .p = { .min = 14, .max = 42 },
 273         .p1 = { .min = 2, .max = 6 },
 274         .p2 = { .dot_limit = 0,
 275                 .p2_slow = 7, .p2_fast = 7
 276         },
 277 };
 278
 279 static const intel_limit_t intel_limits_pineview_sdvo = {
 280         .dot = { .min = 20000, .max = 400000},
 281         .vco = { .min = 1700000, .max = 3500000 },
 282         /* Pineview's Ncounter is a ring counter */
 283         .n = { .min = 3, .max = 6 },
 284         .m = { .min = 2, .max = 256 },
 285         /* Pineview only has one combined m divider, which we treat as m2. */
 286         .m1 = { .min = 0, .max = 0 },
 287         .m2 = { .min = 0, .max = 254 },
 288         .p = { .min = 5, .max = 80 },
 289         .p1 = { .min = 1, .max = 8 },
 290         .p2 = { .dot_limit = 200000,
 291                 .p2_slow = 10, .p2_fast = 5 },
 292 };
 293
 294 static const intel_limit_t intel_limits_pineview_lvds = {
 295         .dot = { .min = 20000, .max = 400000 },
 296         .vco = { .min = 1700000, .max = 3500000 },
 297         .n = { .min = 3, .max = 6 },
 298         .m = { .min = 2, .max = 256 },
 299         .m1 = { .min = 0, .max = 0 },
 300         .m2 = { .min = 0, .max = 254 },
 301         .p = { .min = 7, .max = 112 },
 302         .p1 = { .min = 1, .max = 8 },
 303         .p2 = { .dot_limit = 112000,
 304                 .p2_slow = 14, .p2_fast = 14 },
 305 };
 306
 307 /* Ironlake / Sandybridge
 308  *
 309  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 310  * the range value for them is (actual_value - 2).
 311  */
 312 static const intel_limit_t intel_limits_ironlake_dac = {
 313         .dot = { .min = 25000, .max = 350000 },
 314         .vco = { .min = 1760000, .max = 3510000 },
 315         .n = { .min = 1, .max = 5 },
 316         .m = { .min = 79, .max = 127 },
 317         .m1 = { .min = 12, .max = 22 },
 318         .m2 = { .min = 5, .max = 9 },
 319         .p = { .min = 5, .max = 80 },
 320         .p1 = { .min = 1, .max = 8 },
 321         .p2 = { .dot_limit = 225000,
 322                 .p2_slow = 10, .p2_fast = 5 },
 323 };
 324
 325 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 326         .dot = { .min = 25000, .max = 350000 },
 327         .vco = { .min = 1760000, .max = 3510000 },
 328         .n = { .min = 1, .max = 3 },
 329         .m = { .min = 79, .max = 118 },
 330         .m1 = { .min = 12, .max = 22 },
 331         .m2 = { .min = 5, .max = 9 },
 332         .p = { .min = 28, .max = 112 },
 333         .p1 = { .min = 2, .max = 8 },
 334         .p2 = { .dot_limit = 225000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336 };
 337
 338 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 339         .dot = { .min = 25000, .max = 350000 },
 340         .vco = { .min = 1760000, .max = 3510000 },
 341         .n = { .min = 1, .max = 3 },
 342         .m = { .min = 79, .max = 127 },
 343         .m1 = { .min = 12, .max = 22 },
 344         .m2 = { .min = 5, .max = 9 },
 345         .p = { .min = 14, .max = 56 },
 346         .p1 = { .min = 2, .max = 8 },
 347         .p2 = { .dot_limit = 225000,
 348                 .p2_slow = 7, .p2_fast = 7 },
 349 };
 350
 351 /* LVDS 100mhz refclk limits. */
 352 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 353         .dot = { .min = 25000, .max = 350000 },
 354         .vco = { .min = 1760000, .max = 3510000 },
 355         .n = { .min = 1, .max = 2 },
 356         .m = { .min = 79, .max = 126 },
 357         .m1 = { .min = 12, .max = 22 },
 358         .m2 = { .min = 5, .max = 9 },
 359         .p = { .min = 28, .max = 112 },
 360         .p1 = { .min = 2, .max = 8 },
 361         .p2 = { .dot_limit = 225000,
 362                 .p2_slow = 14, .p2_fast = 14 },
 363 };
 364
 365 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 366         .dot = { .min = 25000, .max = 350000 },
 367         .vco = { .min = 1760000, .max = 3510000 },
 368         .n = { .min = 1, .max = 3 },
 369         .m = { .min = 79, .max = 126 },
 370         .m1 = { .min = 12, .max = 22 },
 371         .m2 = { .min = 5, .max = 9 },
 372         .p = { .min = 14, .max = 42 },
 373         .p1 = { .min = 2, .max = 6 },
 374         .p2 = { .dot_limit = 225000,
 375                 .p2_slow = 7, .p2_fast = 7 },
 376 };
 377
 378 static const intel_limit_t intel_limits_vlv = {
 379          /*
 380           * These are the data rate limits (measured in fast clocks)
 381           * since those are the strictest limits we have. The fast
 382           * clock and actual rate limits are more relaxed, so checking
 383           * them would make no difference.
 384           */
 385         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 386         .vco = { .min = 4000000, .max = 6000000 },
 387         .n = { .min = 1, .max = 7 },
 388         .m1 = { .min = 2, .max = 3 },
 389         .m2 = { .min = 11, .max = 156 },
 390         .p1 = { .min = 2, .max = 3 },
 391         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 392 };
 393
 394 static const intel_limit_t intel_limits_chv = {
 395         /*
 396          * These are the data rate limits (measured in fast clocks)
 397          * since those are the strictest limits we have.  The fast
 398          * clock and actual rate limits are more relaxed, so checking
 399          * them would make no difference.
 400          */
 401         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 402         .vco = { .min = 4800000, .max = 6480000 },
 403         .n = { .min = 1, .max = 1 },
 404         .m1 = { .min = 2, .max = 2 },
 405         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 406         .p1 = { .min = 2, .max = 4 },
 407         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 408 };
 409
 410 static const intel_limit_t intel_limits_bxt = {
 411         /* FIXME: find real dot limits */
 412         .dot = { .min = 0, .max = INT_MAX },
 413         .vco = { .min = 4800000, .max = 6700000 },
 414         .n = { .min = 1, .max = 1 },
 415         .m1 = { .min = 2, .max = 2 },
 416         /* FIXME: find real m2 limits */
 417         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 418         .p1 = { .min = 2, .max = 4 },
 419         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 420 };
 421
 422 static bool
 423 needs_modeset(struct drm_crtc_state *state)
 424 {
 425         return state->mode_changed || state->active_changed;
 426 }
 427
 428 /**
 429  * Returns whether any output on the specified pipe is of the specified type
 430  */
 431 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 432 {
 433         struct drm_device *dev = crtc->base.dev;
 434         struct intel_encoder *encoder;
 435
 436         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 437                 if (encoder->type == type)
 438                         return true;
 439
 440         return false;
 441 }
 442
 443 /**
 444  * Returns whether any output on the specified pipe will have the specified
 445  * type after a staged modeset is complete, i.e., the same as
 446  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 447  * encoder->crtc.
 448  */
 449 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 450                                       int type)
 451 {
 452         struct drm_atomic_state *state = crtc_state->base.state;
 453         struct drm_connector *connector;
 454         struct drm_connector_state *connector_state;
 455         struct intel_encoder *encoder;
 456         int i, num_connectors = 0;
 457
 458         for_each_connector_in_state(state, connector, connector_state, i) {
 459                 if (connector_state->crtc != crtc_state->base.crtc)
 460                         continue;
 461
 462                 num_connectors++;
 463
 464                 encoder = to_intel_encoder(connector_state->best_encoder);
 465                 if (encoder->type == type)
 466                         return true;
 467         }
 468
 469         WARN_ON(num_connectors == 0);
 470
 471         return false;
 472 }
 473
 474 static const intel_limit_t *
 475 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 476 {
 477         struct drm_device *dev = crtc_state->base.crtc->dev;
 478         const intel_limit_t *limit;
 479
 480         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 481                 if (intel_is_dual_link_lvds(dev)) {
 482                         if (refclk == 100000)
 483                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 484                         else
 485                                 limit = &intel_limits_ironlake_dual_lvds;
 486                 } else {
 487                         if (refclk == 100000)
 488                                 limit = &intel_limits_ironlake_single_lvds_100m;
 489                         else
 490                                 limit = &intel_limits_ironlake_single_lvds;
 491                 }
 492         } else
 493                 limit = &intel_limits_ironlake_dac;
 494
 495         return limit;
 496 }
 497
 498 static const intel_limit_t *
 499 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 500 {
 501         struct drm_device *dev = crtc_state->base.crtc->dev;
 502         const intel_limit_t *limit;
 503
 504         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 505                 if (intel_is_dual_link_lvds(dev))
 506                         limit = &intel_limits_g4x_dual_channel_lvds;
 507                 else
 508                         limit = &intel_limits_g4x_single_channel_lvds;
 509         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 510                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 511                 limit = &intel_limits_g4x_hdmi;
 512         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 513                 limit = &intel_limits_g4x_sdvo;
 514         } else /* The option is for other outputs */
 515                 limit = &intel_limits_i9xx_sdvo;
 516
 517         return limit;
 518 }
 519
 520 static const intel_limit_t *
 521 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 522 {
 523         struct drm_device *dev = crtc_state->base.crtc->dev;
 524         const intel_limit_t *limit;
 525
 526         if (IS_BROXTON(dev))
 527                 limit = &intel_limits_bxt;
 528         else if (HAS_PCH_SPLIT(dev))
 529                 limit = intel_ironlake_limit(crtc_state, refclk);
 530         else if (IS_G4X(dev)) {
 531                 limit = intel_g4x_limit(crtc_state);
 532         } else if (IS_PINEVIEW(dev)) {
 533                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 534                         limit = &intel_limits_pineview_lvds;
 535                 else
 536                         limit = &intel_limits_pineview_sdvo;
 537         } else if (IS_CHERRYVIEW(dev)) {
 538                 limit = &intel_limits_chv;
 539         } else if (IS_VALLEYVIEW(dev)) {
 540                 limit = &intel_limits_vlv;
 541         } else if (!IS_GEN2(dev)) {
 542                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 543                         limit = &intel_limits_i9xx_lvds;
 544                 else
 545                         limit = &intel_limits_i9xx_sdvo;
 546         } else {
 547                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 548                         limit = &intel_limits_i8xx_lvds;
 549                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 550                         limit = &intel_limits_i8xx_dvo;
 551                 else
 552                         limit = &intel_limits_i8xx_dac;
 553         }
 554         return limit;
 555 }
 556
 557 /*
 558  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 559  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 560  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 561  * The helpers' return value is the rate of the clock that is fed to the
 562  * display engine's pipe which can be the above fast dot clock rate or a
 563  * divided-down version of it.
 564  */
 565 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 566 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 567 {
 568         clock->m = clock->m2 + 2;
 569         clock->p = clock->p1 * clock->p2;
 570         if (WARN_ON(clock->n == 0 || clock->p == 0))
 571                 return 0;
 572         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 573         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 574
 575         return clock->dot;
 576 }
 577
 578 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 579 {
 580         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 581 }
 582
 583 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 584 {
 585         clock->m = i9xx_dpll_compute_m(clock);
 586         clock->p = clock->p1 * clock->p2;
 587         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 588                 return 0;
 589         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 590         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 591
 592         return clock->dot;
 593 }
 594
 595 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 596 {
 597         clock->m = clock->m1 * clock->m2;
 598         clock->p = clock->p1 * clock->p2;
 599         if (WARN_ON(clock->n == 0 || clock->p == 0))
 600                 return 0;
 601         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 602         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 603
 604         return clock->dot / 5;
 605 }
 606
 607 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 608 {
 609         clock->m = clock->m1 * clock->m2;
 610         clock->p = clock->p1 * clock->p2;
 611         if (WARN_ON(clock->n == 0 || clock->p == 0))
 612                 return 0;
 613         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 614                         clock->n << 22);
 615         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 616
 617         return clock->dot / 5;
 618 }
 619
 620 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 621 /**
 622  * Returns whether the given set of divisors are valid for a given refclk with
 623  * the given connectors.
 624  */
 625
 626 static bool intel_PLL_is_valid(struct drm_device *dev,
 627                                const intel_limit_t *limit,
 628                                const intel_clock_t *clock)
 629 {
 630         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 631                 INTELPllInvalid("n out of range\n");
 632         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 633                 INTELPllInvalid("p1 out of range\n");
 634         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 635                 INTELPllInvalid("m2 out of range\n");
 636         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 637                 INTELPllInvalid("m1 out of range\n");
 638
 639         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 640                 if (clock->m1 <= clock->m2)
 641                         INTELPllInvalid("m1 <= m2\n");
 642
 643         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 644                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 645                         INTELPllInvalid("p out of range\n");
 646                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 647                         INTELPllInvalid("m out of range\n");
 648         }
 649
 650         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 651                 INTELPllInvalid("vco out of range\n");
 652         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 653          * connector, etc., rather than just a single range.
 654          */
 655         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 656                 INTELPllInvalid("dot out of range\n");
 657
 658         return true;
 659 }
 660
 661 static int
 662 i9xx_select_p2_div(const intel_limit_t *limit,
 663                    const struct intel_crtc_state *crtc_state,
 664                    int target)
 665 {
 666         struct drm_device *dev = crtc_state->base.crtc->dev;
 667
 668         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 669                 /*
 670                  * For LVDS just rely on its current settings for dual-channel.
 671                  * We haven't figured out how to reliably set up different
 672                  * single/dual channel state, if we even can.
 673                  */
 674                 if (intel_is_dual_link_lvds(dev))
 675                         return limit->p2.p2_fast;
 676                 else
 677                         return limit->p2.p2_slow;
 678         } else {
 679                 if (target < limit->p2.dot_limit)
 680                         return limit->p2.p2_slow;
 681                 else
 682                         return limit->p2.p2_fast;
 683         }
 684 }
 685
 686 static bool
 687 i9xx_find_best_dpll(const intel_limit_t *limit,
 688                     struct intel_crtc_state *crtc_state,
 689                     int target, int refclk, intel_clock_t *match_clock,
 690                     intel_clock_t *best_clock)
 691 {
 692         struct drm_device *dev = crtc_state->base.crtc->dev;
 693         intel_clock_t clock;
 694         int err = target;
 695
 696         memset(best_clock, 0, sizeof(*best_clock));
 697
 698         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 699
 700         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 701              clock.m1++) {
 702                 for (clock.m2 = limit->m2.min;
 703                      clock.m2 <= limit->m2.max; clock.m2++) {
 704                         if (clock.m2 >= clock.m1)
 705                                 break;
 706                         for (clock.n = limit->n.min;
 707                              clock.n <= limit->n.max; clock.n++) {
 708                                 for (clock.p1 = limit->p1.min;
 709                                         clock.p1 <= limit->p1.max; clock.p1++) {
 710                                         int this_err;
 711
 712                                         i9xx_calc_dpll_params(refclk, &clock);
 713                                         if (!intel_PLL_is_valid(dev, limit,
 714                                                                 &clock))
 715                                                 continue;
 716                                         if (match_clock &&
 717                                             clock.p != match_clock->p)
 718                                                 continue;
 719
 720                                         this_err = abs(clock.dot - target);
 721                                         if (this_err < err) {
 722                                                 *best_clock = clock;
 723                                                 err = this_err;
 724                                         }
 725                                 }
 726                         }
 727                 }
 728         }
 729
 730         return (err != target);
 731 }
 732
 733 static bool
 734 pnv_find_best_dpll(const intel_limit_t *limit,
 735                    struct intel_crtc_state *crtc_state,
 736                    int target, int refclk, intel_clock_t *match_clock,
 737                    intel_clock_t *best_clock)
 738 {
 739         struct drm_device *dev = crtc_state->base.crtc->dev;
 740         intel_clock_t clock;
 741         int err = target;
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744
 745         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 746
 747         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 748              clock.m1++) {
 749                 for (clock.m2 = limit->m2.min;
 750                      clock.m2 <= limit->m2.max; clock.m2++) {
 751                         for (clock.n = limit->n.min;
 752                              clock.n <= limit->n.max; clock.n++) {
 753                                 for (clock.p1 = limit->p1.min;
 754                                         clock.p1 <= limit->p1.max; clock.p1++) {
 755                                         int this_err;
 756
 757                                         pnv_calc_dpll_params(refclk, &clock);
 758                                         if (!intel_PLL_is_valid(dev, limit,
 759                                                                 &clock))
 760                                                 continue;
 761                                         if (match_clock &&
 762                                             clock.p != match_clock->p)
 763                                                 continue;
 764
 765                                         this_err = abs(clock.dot - target);
 766                                         if (this_err < err) {
 767                                                 *best_clock = clock;
 768                                                 err = this_err;
 769                                         }
 770                                 }
 771                         }
 772                 }
 773         }
 774
 775         return (err != target);
 776 }
 777
 778 static bool
 779 g4x_find_best_dpll(const intel_limit_t *limit,
 780                    struct intel_crtc_state *crtc_state,
 781                    int target, int refclk, intel_clock_t *match_clock,
 782                    intel_clock_t *best_clock)
 783 {
 784         struct drm_device *dev = crtc_state->base.crtc->dev;
 785         intel_clock_t clock;
 786         int max_n;
 787         bool found = false;
 788         /* approximately equals target * 0.00585 */
 789         int err_most = (target >> 8) + (target >> 9);
 790
 791         memset(best_clock, 0, sizeof(*best_clock));
 792
 793         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 794
 795         max_n = limit->n.max;
 796         /* based on hardware requirement, prefer smaller n to precision */
 797         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 798                 /* based on hardware requirement, prefere larger m1,m2 */
 799                 for (clock.m1 = limit->m1.max;
 800                      clock.m1 >= limit->m1.min; clock.m1--) {
 801                         for (clock.m2 = limit->m2.max;
 802                              clock.m2 >= limit->m2.min; clock.m2--) {
 803                                 for (clock.p1 = limit->p1.max;
 804                                      clock.p1 >= limit->p1.min; clock.p1--) {
 805                                         int this_err;
 806
 807                                         i9xx_calc_dpll_params(refclk, &clock);
 808                                         if (!intel_PLL_is_valid(dev, limit,
 809                                                                 &clock))
 810                                                 continue;
 811
 812                                         this_err = abs(clock.dot - target);
 813                                         if (this_err < err_most) {
 814                                                 *best_clock = clock;
 815                                                 err_most = this_err;
 816                                                 max_n = clock.n;
 817                                                 found = true;
 818                                         }
 819                                 }
 820                         }
 821                 }
 822         }
 823         return found;
 824 }
 825
 826 /*
 827  * Check if the calculated PLL configuration is more optimal compared to the
 828  * best configuration and error found so far. Return the calculated error.
 829  */
 830 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 831                                const intel_clock_t *calculated_clock,
 832                                const intel_clock_t *best_clock,
 833                                unsigned int best_error_ppm,
 834                                unsigned int *error_ppm)
 835 {
 836         /*
 837          * For CHV ignore the error and consider only the P value.
 838          * Prefer a bigger P value based on HW requirements.
 839          */
 840         if (IS_CHERRYVIEW(dev)) {
 841                 *error_ppm = 0;
 842
 843                 return calculated_clock->p > best_clock->p;
 844         }
 845
 846         if (WARN_ON_ONCE(!target_freq))
 847                 return false;
 848
 849         *error_ppm = div_u64(1000000ULL *
 850                                 abs(target_freq - calculated_clock->dot),
 851                              target_freq);
 852         /*
 853          * Prefer a better P value over a better (smaller) error if the error
 854          * is small. Ensure this preference for future configurations too by
 855          * setting the error to 0.
 856          */
 857         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 858                 *error_ppm = 0;
 859
 860                 return true;
 861         }
 862
 863         return *error_ppm + 10 < best_error_ppm;
 864 }
 865
 866 static bool
 867 vlv_find_best_dpll(const intel_limit_t *limit,
 868                    struct intel_crtc_state *crtc_state,
 869                    int target, int refclk, intel_clock_t *match_clock,
 870                    intel_clock_t *best_clock)
 871 {
 872         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 873         struct drm_device *dev = crtc->base.dev;
 874         intel_clock_t clock;
 875         unsigned int bestppm = 1000000;
 876         /* min update 19.2 MHz */
 877         int max_n = min(limit->n.max, refclk / 19200);
 878         bool found = false;
 879
 880         target *= 5; /* fast clock */
 881
 882         memset(best_clock, 0, sizeof(*best_clock));
 883
 884         /* based on hardware requirement, prefer smaller n to precision */
 885         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 886                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 887                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 888                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 889                                 clock.p = clock.p1 * clock.p2;
 890                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 891                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 892                                         unsigned int ppm;
 893
 894                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 895                                                                      refclk * clock.m1);
 896
 897                                         vlv_calc_dpll_params(refclk, &clock);
 898
 899                                         if (!intel_PLL_is_valid(dev, limit,
 900                                                                 &clock))
 901                                                 continue;
 902
 903                                         if (!vlv_PLL_is_optimal(dev, target,
 904                                                                 &clock,
 905                                                                 best_clock,
 906                                                                 bestppm, &ppm))
 907                                                 continue;
 908
 909                                         *best_clock = clock;
 910                                         bestppm = ppm;
 911                                         found = true;
 912                                 }
 913                         }
 914                 }
 915         }
 916
 917         return found;
 918 }
 919
 920 static bool
 921 chv_find_best_dpll(const intel_limit_t *limit,
 922                    struct intel_crtc_state *crtc_state,
 923                    int target, int refclk, intel_clock_t *match_clock,
 924                    intel_clock_t *best_clock)
 925 {
 926         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 927         struct drm_device *dev = crtc->base.dev;
 928         unsigned int best_error_ppm;
 929         intel_clock_t clock;
 930         uint64_t m2;
 931         int found = false;
 932
 933         memset(best_clock, 0, sizeof(*best_clock));
 934         best_error_ppm = 1000000;
 935
 936         /*
 937          * Based on hardware doc, the n always set to 1, and m1 always
 938          * set to 2.  If requires to support 200Mhz refclk, we need to
 939          * revisit this because n may not 1 anymore.
 940          */
 941         clock.n = 1, clock.m1 = 2;
 942         target *= 5;    /* fast clock */
 943
 944         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 945                 for (clock.p2 = limit->p2.p2_fast;
 946                                 clock.p2 >= limit->p2.p2_slow;
 947                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 948                         unsigned int error_ppm;
 949
 950                         clock.p = clock.p1 * clock.p2;
 951
 952                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 953                                         clock.n) << 22, refclk * clock.m1);
 954
 955                         if (m2 > INT_MAX/clock.m1)
 956                                 continue;
 957
 958                         clock.m2 = m2;
 959
 960                         chv_calc_dpll_params(refclk, &clock);
 961
 962                         if (!intel_PLL_is_valid(dev, limit, &clock))
 963                                 continue;
 964
 965                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 966                                                 best_error_ppm, &error_ppm))
 967                                 continue;
 968
 969                         *best_clock = clock;
 970                         best_error_ppm = error_ppm;
 971                         found = true;
 972                 }
 973         }
 974
 975         return found;
 976 }
 977
 978 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 979                         intel_clock_t *best_clock)
 980 {
 981         int refclk = i9xx_get_refclk(crtc_state, 0);
 982
 983         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 984                                   target_clock, refclk, NULL, best_clock);
 985 }
 986
 987 bool intel_crtc_active(struct drm_crtc *crtc)
 988 {
 989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 990
 991         /* Be paranoid as we can arrive here with only partial
 992          * state retrieved from the hardware during setup.
 993          *
 994          * We can ditch the adjusted_mode.crtc_clock check as soon
 995          * as Haswell has gained clock readout/fastboot support.
 996          *
 997          * We can ditch the crtc->primary->fb check as soon as we can
 998          * properly reconstruct framebuffers.
 999          *
1000          * FIXME: The intel_crtc->active here should be switched to
1001          * crtc->state->active once we have proper CRTC states wired up
1002          * for atomic.
1003          */
1004         return intel_crtc->active && crtc->primary->state->fb &&
1005                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1006 }
1007
1008 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1009                                              enum pipe pipe)
1010 {
1011         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1013
1014         return intel_crtc->config->cpu_transcoder;
1015 }
1016
1017 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1018 {
1019         struct drm_i915_private *dev_priv = dev->dev_private;
1020         u32 reg = PIPEDSL(pipe);
1021         u32 line1, line2;
1022         u32 line_mask;
1023
1024         if (IS_GEN2(dev))
1025                 line_mask = DSL_LINEMASK_GEN2;
1026         else
1027                 line_mask = DSL_LINEMASK_GEN3;
1028
1029         line1 = I915_READ(reg) & line_mask;
1030         msleep(5);
1031         line2 = I915_READ(reg) & line_mask;
1032
1033         return line1 == line2;
1034 }
1035
1036 /*
1037  * intel_wait_for_pipe_off - wait for pipe to turn off
1038  * @crtc: crtc whose pipe to wait for
1039  *
1040  * After disabling a pipe, we can't wait for vblank in the usual way,
1041  * spinning on the vblank interrupt status bit, since we won't actually
1042  * see an interrupt when the pipe is disabled.
1043  *
1044  * On Gen4 and above:
1045  *   wait for the pipe register state bit to turn off
1046  *
1047  * Otherwise:
1048  *   wait for the display line value to settle (it usually
1049  *   ends up stopping at the start of the next frame).
1050  *
1051  */
1052 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1053 {
1054         struct drm_device *dev = crtc->base.dev;
1055         struct drm_i915_private *dev_priv = dev->dev_private;
1056         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1057         enum pipe pipe = crtc->pipe;
1058
1059         if (INTEL_INFO(dev)->gen >= 4) {
1060                 int reg = PIPECONF(cpu_transcoder);
1061
1062                 /* Wait for the Pipe State to go off */
1063                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1064                              100))
1065                         WARN(1, "pipe_off wait timed out\n");
1066         } else {
1067                 /* Wait for the display line to settle */
1068                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1069                         WARN(1, "pipe_off wait timed out\n");
1070         }
1071 }
1072
1073 /*
1074  * ibx_digital_port_connected - is the specified port connected?
1075  * @dev_priv: i915 private structure
1076  * @port: the port to test
1077  *
1078  * Returns true if @port is connected, false otherwise.
1079  */
1080 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1081                                 struct intel_digital_port *port)
1082 {
1083         u32 bit;
1084
1085         if (HAS_PCH_IBX(dev_priv->dev)) {
1086                 switch (port->port) {
1087                 case PORT_B:
1088                         bit = SDE_PORTB_HOTPLUG;
1089                         break;
1090                 case PORT_C:
1091                         bit = SDE_PORTC_HOTPLUG;
1092                         break;
1093                 case PORT_D:
1094                         bit = SDE_PORTD_HOTPLUG;
1095                         break;
1096                 default:
1097                         return true;
1098                 }
1099         } else {
1100                 switch (port->port) {
1101                 case PORT_B:
1102                         bit = SDE_PORTB_HOTPLUG_CPT;
1103                         break;
1104                 case PORT_C:
1105                         bit = SDE_PORTC_HOTPLUG_CPT;
1106                         break;
1107                 case PORT_D:
1108                         bit = SDE_PORTD_HOTPLUG_CPT;
1109                         break;
1110                 default:
1111                         return true;
1112                 }
1113         }
1114
1115         return I915_READ(SDEISR) & bit;
1116 }
1117
1118 static const char *state_string(bool enabled)
1119 {
1120         return enabled ? "on" : "off";
1121 }
1122
1123 /* Only for pre-ILK configs */
1124 void assert_pll(struct drm_i915_private *dev_priv,
1125                 enum pipe pipe, bool state)
1126 {
1127         int reg;
1128         u32 val;
1129         bool cur_state;
1130
1131         reg = DPLL(pipe);
1132         val = I915_READ(reg);
1133         cur_state = !!(val & DPLL_VCO_ENABLE);
1134         I915_STATE_WARN(cur_state != state,
1135              "PLL state assertion failure (expected %s, current %s)\n",
1136              state_string(state), state_string(cur_state));
1137 }
1138
1139 /* XXX: the dsi pll is shared between MIPI DSI ports */
1140 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1141 {
1142         u32 val;
1143         bool cur_state;
1144
1145         mutex_lock(&dev_priv->sb_lock);
1146         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1147         mutex_unlock(&dev_priv->sb_lock);
1148
1149         cur_state = val & DSI_PLL_VCO_EN;
1150         I915_STATE_WARN(cur_state != state,
1151              "DSI PLL state assertion failure (expected %s, current %s)\n",
1152              state_string(state), state_string(cur_state));
1153 }
1154 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1155 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1156
1157 struct intel_shared_dpll *
1158 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1159 {
1160         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1161
1162         if (crtc->config->shared_dpll < 0)
1163                 return NULL;
1164
1165         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1166 }
1167
1168 /* For ILK+ */
1169 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1170                         struct intel_shared_dpll *pll,
1171                         bool state)
1172 {
1173         bool cur_state;
1174         struct intel_dpll_hw_state hw_state;
1175
1176         if (WARN (!pll,
1177                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1178                 return;
1179
1180         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1181         I915_STATE_WARN(cur_state != state,
1182              "%s assertion failure (expected %s, current %s)\n",
1183              pll->name, state_string(state), state_string(cur_state));
1184 }
1185
1186 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1187                           enum pipe pipe, bool state)
1188 {
1189         int reg;
1190         u32 val;
1191         bool cur_state;
1192         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1193                                                                       pipe);
1194
1195         if (HAS_DDI(dev_priv->dev)) {
1196                 /* DDI does not have a specific FDI_TX register */
1197                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1198                 val = I915_READ(reg);
1199                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1200         } else {
1201                 reg = FDI_TX_CTL(pipe);
1202                 val = I915_READ(reg);
1203                 cur_state = !!(val & FDI_TX_ENABLE);
1204         }
1205         I915_STATE_WARN(cur_state != state,
1206              "FDI TX state assertion failure (expected %s, current %s)\n",
1207              state_string(state), state_string(cur_state));
1208 }
1209 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1210 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1211
1212 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1213                           enum pipe pipe, bool state)
1214 {
1215         int reg;
1216         u32 val;
1217         bool cur_state;
1218
1219         reg = FDI_RX_CTL(pipe);
1220         val = I915_READ(reg);
1221         cur_state = !!(val & FDI_RX_ENABLE);
1222         I915_STATE_WARN(cur_state != state,
1223              "FDI RX state assertion failure (expected %s, current %s)\n",
1224              state_string(state), state_string(cur_state));
1225 }
1226 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1227 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1228
1229 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1230                                       enum pipe pipe)
1231 {
1232         int reg;
1233         u32 val;
1234
1235         /* ILK FDI PLL is always enabled */
1236         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1237                 return;
1238
1239         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1240         if (HAS_DDI(dev_priv->dev))
1241                 return;
1242
1243         reg = FDI_TX_CTL(pipe);
1244         val = I915_READ(reg);
1245         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1246 }
1247
1248 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1249                        enum pipe pipe, bool state)
1250 {
1251         int reg;
1252         u32 val;
1253         bool cur_state;
1254
1255         reg = FDI_RX_CTL(pipe);
1256         val = I915_READ(reg);
1257         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1258         I915_STATE_WARN(cur_state != state,
1259              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1260              state_string(state), state_string(cur_state));
1261 }
1262
1263 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1264                            enum pipe pipe)
1265 {
1266         struct drm_device *dev = dev_priv->dev;
1267         int pp_reg;
1268         u32 val;
1269         enum pipe panel_pipe = PIPE_A;
1270         bool locked = true;
1271
1272         if (WARN_ON(HAS_DDI(dev)))
1273                 return;
1274
1275         if (HAS_PCH_SPLIT(dev)) {
1276                 u32 port_sel;
1277
1278                 pp_reg = PCH_PP_CONTROL;
1279                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1280
1281                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1282                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1283                         panel_pipe = PIPE_B;
1284                 /* XXX: else fix for eDP */
1285         } else if (IS_VALLEYVIEW(dev)) {
1286                 /* presumably write lock depends on pipe, not port select */
1287                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1288                 panel_pipe = pipe;
1289         } else {
1290                 pp_reg = PP_CONTROL;
1291                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1292                         panel_pipe = PIPE_B;
1293         }
1294
1295         val = I915_READ(pp_reg);
1296         if (!(val & PANEL_POWER_ON) ||
1297             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1298                 locked = false;
1299
1300         I915_STATE_WARN(panel_pipe == pipe && locked,
1301              "panel assertion failure, pipe %c regs locked\n",
1302              pipe_name(pipe));
1303 }
1304
1305 static void assert_cursor(struct drm_i915_private *dev_priv,
1306                           enum pipe pipe, bool state)
1307 {
1308         struct drm_device *dev = dev_priv->dev;
1309         bool cur_state;
1310
1311         if (IS_845G(dev) || IS_I865G(dev))
1312                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1313         else
1314                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1315
1316         I915_STATE_WARN(cur_state != state,
1317              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1318              pipe_name(pipe), state_string(state), state_string(cur_state));
1319 }
1320 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1321 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1322
1323 void assert_pipe(struct drm_i915_private *dev_priv,
1324                  enum pipe pipe, bool state)
1325 {
1326         int reg;
1327         u32 val;
1328         bool cur_state;
1329         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1330                                                                       pipe);
1331
1332         /* if we need the pipe quirk it must be always on */
1333         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1334             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1335                 state = true;
1336
1337         if (!intel_display_power_is_enabled(dev_priv,
1338                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1339                 cur_state = false;
1340         } else {
1341                 reg = PIPECONF(cpu_transcoder);
1342                 val = I915_READ(reg);
1343                 cur_state = !!(val & PIPECONF_ENABLE);
1344         }
1345
1346         I915_STATE_WARN(cur_state != state,
1347              "pipe %c assertion failure (expected %s, current %s)\n",
1348              pipe_name(pipe), state_string(state), state_string(cur_state));
1349 }
1350
1351 static void assert_plane(struct drm_i915_private *dev_priv,
1352                          enum plane plane, bool state)
1353 {
1354         int reg;
1355         u32 val;
1356         bool cur_state;
1357
1358         reg = DSPCNTR(plane);
1359         val = I915_READ(reg);
1360         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1361         I915_STATE_WARN(cur_state != state,
1362              "plane %c assertion failure (expected %s, current %s)\n",
1363              plane_name(plane), state_string(state), state_string(cur_state));
1364 }
1365
1366 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1367 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1368
1369 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1370                                    enum pipe pipe)
1371 {
1372         struct drm_device *dev = dev_priv->dev;
1373         int reg, i;
1374         u32 val;
1375         int cur_pipe;
1376
1377         /* Primary planes are fixed to pipes on gen4+ */
1378         if (INTEL_INFO(dev)->gen >= 4) {
1379                 reg = DSPCNTR(pipe);
1380                 val = I915_READ(reg);
1381                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1382                      "plane %c assertion failure, should be disabled but not\n",
1383                      plane_name(pipe));
1384                 return;
1385         }
1386
1387         /* Need to check both planes against the pipe */
1388         for_each_pipe(dev_priv, i) {
1389                 reg = DSPCNTR(i);
1390                 val = I915_READ(reg);
1391                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1392                         DISPPLANE_SEL_PIPE_SHIFT;
1393                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1394                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1395                      plane_name(i), pipe_name(pipe));
1396         }
1397 }
1398
1399 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1400                                     enum pipe pipe)
1401 {
1402         struct drm_device *dev = dev_priv->dev;
1403         int reg, sprite;
1404         u32 val;
1405
1406         if (INTEL_INFO(dev)->gen >= 9) {
1407                 for_each_sprite(dev_priv, pipe, sprite) {
1408                         val = I915_READ(PLANE_CTL(pipe, sprite));
1409                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1410                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1411                              sprite, pipe_name(pipe));
1412                 }
1413         } else if (IS_VALLEYVIEW(dev)) {
1414                 for_each_sprite(dev_priv, pipe, sprite) {
1415                         reg = SPCNTR(pipe, sprite);
1416                         val = I915_READ(reg);
1417                         I915_STATE_WARN(val & SP_ENABLE,
1418                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1419                              sprite_name(pipe, sprite), pipe_name(pipe));
1420                 }
1421         } else if (INTEL_INFO(dev)->gen >= 7) {
1422                 reg = SPRCTL(pipe);
1423                 val = I915_READ(reg);
1424                 I915_STATE_WARN(val & SPRITE_ENABLE,
1425                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426                      plane_name(pipe), pipe_name(pipe));
1427         } else if (INTEL_INFO(dev)->gen >= 5) {
1428                 reg = DVSCNTR(pipe);
1429                 val = I915_READ(reg);
1430                 I915_STATE_WARN(val & DVS_ENABLE,
1431                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1432                      plane_name(pipe), pipe_name(pipe));
1433         }
1434 }
1435
1436 static void assert_vblank_disabled(struct drm_crtc *crtc)
1437 {
1438         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1439                 drm_crtc_vblank_put(crtc);
1440 }
1441
1442 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1443 {
1444         u32 val;
1445         bool enabled;
1446
1447         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1448
1449         val = I915_READ(PCH_DREF_CONTROL);
1450         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1451                             DREF_SUPERSPREAD_SOURCE_MASK));
1452         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1453 }
1454
1455 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1456                                            enum pipe pipe)
1457 {
1458         int reg;
1459         u32 val;
1460         bool enabled;
1461
1462         reg = PCH_TRANSCONF(pipe);
1463         val = I915_READ(reg);
1464         enabled = !!(val & TRANS_ENABLE);
1465         I915_STATE_WARN(enabled,
1466              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1467              pipe_name(pipe));
1468 }
1469
1470 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1471                             enum pipe pipe, u32 port_sel, u32 val)
1472 {
1473         if ((val & DP_PORT_EN) == 0)
1474                 return false;
1475
1476         if (HAS_PCH_CPT(dev_priv->dev)) {
1477                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1478                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1479                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1480                         return false;
1481         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1482                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1483                         return false;
1484         } else {
1485                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1486                         return false;
1487         }
1488         return true;
1489 }
1490
1491 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1492                               enum pipe pipe, u32 val)
1493 {
1494         if ((val & SDVO_ENABLE) == 0)
1495                 return false;
1496
1497         if (HAS_PCH_CPT(dev_priv->dev)) {
1498                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1499                         return false;
1500         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1501                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1502                         return false;
1503         } else {
1504                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1505                         return false;
1506         }
1507         return true;
1508 }
1509
1510 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1511                               enum pipe pipe, u32 val)
1512 {
1513         if ((val & LVDS_PORT_EN) == 0)
1514                 return false;
1515
1516         if (HAS_PCH_CPT(dev_priv->dev)) {
1517                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1518                         return false;
1519         } else {
1520                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1521                         return false;
1522         }
1523         return true;
1524 }
1525
1526 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1527                               enum pipe pipe, u32 val)
1528 {
1529         if ((val & ADPA_DAC_ENABLE) == 0)
1530                 return false;
1531         if (HAS_PCH_CPT(dev_priv->dev)) {
1532                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1533                         return false;
1534         } else {
1535                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1536                         return false;
1537         }
1538         return true;
1539 }
1540
1541 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1542                                    enum pipe pipe, int reg, u32 port_sel)
1543 {
1544         u32 val = I915_READ(reg);
1545         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1546              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1547              reg, pipe_name(pipe));
1548
1549         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1550              && (val & DP_PIPEB_SELECT),
1551              "IBX PCH dp port still using transcoder B\n");
1552 }
1553
1554 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1555                                      enum pipe pipe, int reg)
1556 {
1557         u32 val = I915_READ(reg);
1558         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1559              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1560              reg, pipe_name(pipe));
1561
1562         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1563              && (val & SDVO_PIPE_B_SELECT),
1564              "IBX PCH hdmi port still using transcoder B\n");
1565 }
1566
1567 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1568                                       enum pipe pipe)
1569 {
1570         int reg;
1571         u32 val;
1572
1573         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1574         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1575         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1576
1577         reg = PCH_ADPA;
1578         val = I915_READ(reg);
1579         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1580              "PCH VGA enabled on transcoder %c, should be disabled\n",
1581              pipe_name(pipe));
1582
1583         reg = PCH_LVDS;
1584         val = I915_READ(reg);
1585         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1586              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1587              pipe_name(pipe));
1588
1589         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1590         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1591         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1592 }
1593
1594 static void intel_init_dpio(struct drm_device *dev)
1595 {
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597
1598         if (!IS_VALLEYVIEW(dev))
1599                 return;
1600
1601         /*
1602          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1603          * CHV x1 PHY (DP/HDMI D)
1604          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1605          */
1606         if (IS_CHERRYVIEW(dev)) {
1607                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1608                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1609         } else {
1610                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1611         }
1612 }
1613
1614 static void vlv_enable_pll(struct intel_crtc *crtc,
1615                            const struct intel_crtc_state *pipe_config)
1616 {
1617         struct drm_device *dev = crtc->base.dev;
1618         struct drm_i915_private *dev_priv = dev->dev_private;
1619         int reg = DPLL(crtc->pipe);
1620         u32 dpll = pipe_config->dpll_hw_state.dpll;
1621
1622         assert_pipe_disabled(dev_priv, crtc->pipe);
1623
1624         /* No really, not for ILK+ */
1625         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1626
1627         /* PLL is protected by panel, make sure we can write it */
1628         if (IS_MOBILE(dev_priv->dev))
1629                 assert_panel_unlocked(dev_priv, crtc->pipe);
1630
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150);
1634
1635         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1636                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1637
1638         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1639         POSTING_READ(DPLL_MD(crtc->pipe));
1640
1641         /* We do this three times for luck */
1642         I915_WRITE(reg, dpll);
1643         POSTING_READ(reg);
1644         udelay(150); /* wait for warmup */
1645         I915_WRITE(reg, dpll);
1646         POSTING_READ(reg);
1647         udelay(150); /* wait for warmup */
1648         I915_WRITE(reg, dpll);
1649         POSTING_READ(reg);
1650         udelay(150); /* wait for warmup */
1651 }
1652
1653 static void chv_enable_pll(struct intel_crtc *crtc,
1654                            const struct intel_crtc_state *pipe_config)
1655 {
1656         struct drm_device *dev = crtc->base.dev;
1657         struct drm_i915_private *dev_priv = dev->dev_private;
1658         int pipe = crtc->pipe;
1659         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1660         u32 tmp;
1661
1662         assert_pipe_disabled(dev_priv, crtc->pipe);
1663
1664         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1665
1666         mutex_lock(&dev_priv->sb_lock);
1667
1668         /* Enable back the 10bit clock to display controller */
1669         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1670         tmp |= DPIO_DCLKP_EN;
1671         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1672
1673         mutex_unlock(&dev_priv->sb_lock);
1674
1675         /*
1676          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1677          */
1678         udelay(1);
1679
1680         /* Enable PLL */
1681         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1682
1683         /* Check PLL is locked */
1684         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1685                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1686
1687         /* not sure when this should be written */
1688         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1689         POSTING_READ(DPLL_MD(pipe));
1690 }
1691
1692 static int intel_num_dvo_pipes(struct drm_device *dev)
1693 {
1694         struct intel_crtc *crtc;
1695         int count = 0;
1696
1697         for_each_intel_crtc(dev, crtc)
1698                 count += crtc->base.state->active &&
1699                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1700
1701         return count;
1702 }
1703
1704 static void i9xx_enable_pll(struct intel_crtc *crtc)
1705 {
1706         struct drm_device *dev = crtc->base.dev;
1707         struct drm_i915_private *dev_priv = dev->dev_private;
1708         int reg = DPLL(crtc->pipe);
1709         u32 dpll = crtc->config->dpll_hw_state.dpll;
1710
1711         assert_pipe_disabled(dev_priv, crtc->pipe);
1712
1713         /* No really, not for ILK+ */
1714         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1715
1716         /* PLL is protected by panel, make sure we can write it */
1717         if (IS_MOBILE(dev) && !IS_I830(dev))
1718                 assert_panel_unlocked(dev_priv, crtc->pipe);
1719
1720         /* Enable DVO 2x clock on both PLLs if necessary */
1721         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1722                 /*
1723                  * It appears to be important that we don't enable this
1724                  * for the current pipe before otherwise configuring the
1725                  * PLL. No idea how this should be handled if multiple
1726                  * DVO outputs are enabled simultaneosly.
1727                  */
1728                 dpll |= DPLL_DVO_2X_MODE;
1729                 I915_WRITE(DPLL(!crtc->pipe),
1730                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1731         }
1732
1733         /* Wait for the clocks to stabilize. */
1734         POSTING_READ(reg);
1735         udelay(150);
1736
1737         if (INTEL_INFO(dev)->gen >= 4) {
1738                 I915_WRITE(DPLL_MD(crtc->pipe),
1739                            crtc->config->dpll_hw_state.dpll_md);
1740         } else {
1741                 /* The pixel multiplier can only be updated once the
1742                  * DPLL is enabled and the clocks are stable.
1743                  *
1744                  * So write it again.
1745                  */
1746                 I915_WRITE(reg, dpll);
1747         }
1748
1749         /* We do this three times for luck */
1750         I915_WRITE(reg, dpll);
1751         POSTING_READ(reg);
1752         udelay(150); /* wait for warmup */
1753         I915_WRITE(reg, dpll);
1754         POSTING_READ(reg);
1755         udelay(150); /* wait for warmup */
1756         I915_WRITE(reg, dpll);
1757         POSTING_READ(reg);
1758         udelay(150); /* wait for warmup */
1759 }
1760
1761 /**
1762  * i9xx_disable_pll - disable a PLL
1763  * @dev_priv: i915 private structure
1764  * @pipe: pipe PLL to disable
1765  *
1766  * Disable the PLL for @pipe, making sure the pipe is off first.
1767  *
1768  * Note!  This is for pre-ILK only.
1769  */
1770 static void i9xx_disable_pll(struct intel_crtc *crtc)
1771 {
1772         struct drm_device *dev = crtc->base.dev;
1773         struct drm_i915_private *dev_priv = dev->dev_private;
1774         enum pipe pipe = crtc->pipe;
1775
1776         /* Disable DVO 2x clock on both PLLs if necessary */
1777         if (IS_I830(dev) &&
1778             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1779             !intel_num_dvo_pipes(dev)) {
1780                 I915_WRITE(DPLL(PIPE_B),
1781                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1782                 I915_WRITE(DPLL(PIPE_A),
1783                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1784         }
1785
1786         /* Don't disable pipe or pipe PLLs if needed */
1787         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1788             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1789                 return;
1790
1791         /* Make sure the pipe isn't still relying on us */
1792         assert_pipe_disabled(dev_priv, pipe);
1793
1794         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1795         POSTING_READ(DPLL(pipe));
1796 }
1797
1798 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1799 {
1800         u32 val;
1801
1802         /* Make sure the pipe isn't still relying on us */
1803         assert_pipe_disabled(dev_priv, pipe);
1804
1805         /*
1806          * Leave integrated clock source and reference clock enabled for pipe B.
1807          * The latter is needed for VGA hotplug / manual detection.
1808          */
1809         val = DPLL_VGA_MODE_DIS;
1810         if (pipe == PIPE_B)
1811                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1812         I915_WRITE(DPLL(pipe), val);
1813         POSTING_READ(DPLL(pipe));
1814
1815 }
1816
1817 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1818 {
1819         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1820         u32 val;
1821
1822         /* Make sure the pipe isn't still relying on us */
1823         assert_pipe_disabled(dev_priv, pipe);
1824
1825         /* Set PLL en = 0 */
1826         val = DPLL_SSC_REF_CLK_CHV |
1827                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1828         if (pipe != PIPE_A)
1829                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1830         I915_WRITE(DPLL(pipe), val);
1831         POSTING_READ(DPLL(pipe));
1832
1833         mutex_lock(&dev_priv->sb_lock);
1834
1835         /* Disable 10bit clock to display controller */
1836         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1837         val &= ~DPIO_DCLKP_EN;
1838         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1839
1840         /* disable left/right clock distribution */
1841         if (pipe != PIPE_B) {
1842                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1843                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1844                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1845         } else {
1846                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1847                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1848                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1849         }
1850
1851         mutex_unlock(&dev_priv->sb_lock);
1852 }
1853
1854 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1855                          struct intel_digital_port *dport,
1856                          unsigned int expected_mask)
1857 {
1858         u32 port_mask;
1859         int dpll_reg;
1860
1861         switch (dport->port) {
1862         case PORT_B:
1863                 port_mask = DPLL_PORTB_READY_MASK;
1864                 dpll_reg = DPLL(0);
1865                 break;
1866         case PORT_C:
1867                 port_mask = DPLL_PORTC_READY_MASK;
1868                 dpll_reg = DPLL(0);
1869                 expected_mask <<= 4;
1870                 break;
1871         case PORT_D:
1872                 port_mask = DPLL_PORTD_READY_MASK;
1873                 dpll_reg = DPIO_PHY_STATUS;
1874                 break;
1875         default:
1876                 BUG();
1877         }
1878
1879         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1880                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1881                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1882 }
1883
1884 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1885 {
1886         struct drm_device *dev = crtc->base.dev;
1887         struct drm_i915_private *dev_priv = dev->dev_private;
1888         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1889
1890         if (WARN_ON(pll == NULL))
1891                 return;
1892
1893         WARN_ON(!pll->config.crtc_mask);
1894         if (pll->active == 0) {
1895                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1896                 WARN_ON(pll->on);
1897                 assert_shared_dpll_disabled(dev_priv, pll);
1898
1899                 pll->mode_set(dev_priv, pll);
1900         }
1901 }
1902
1903 /**
1904  * intel_enable_shared_dpll - enable PCH PLL
1905  * @dev_priv: i915 private structure
1906  * @pipe: pipe PLL to enable
1907  *
1908  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1909  * drives the transcoder clock.
1910  */
1911 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1912 {
1913         struct drm_device *dev = crtc->base.dev;
1914         struct drm_i915_private *dev_priv = dev->dev_private;
1915         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1916
1917         if (WARN_ON(pll == NULL))
1918                 return;
1919
1920         if (WARN_ON(pll->config.crtc_mask == 0))
1921                 return;
1922
1923         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1924                       pll->name, pll->active, pll->on,
1925                       crtc->base.base.id);
1926
1927         if (pll->active++) {
1928                 WARN_ON(!pll->on);
1929                 assert_shared_dpll_enabled(dev_priv, pll);
1930                 return;
1931         }
1932         WARN_ON(pll->on);
1933
1934         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1935
1936         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1937         pll->enable(dev_priv, pll);
1938         pll->on = true;
1939 }
1940
1941 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1942 {
1943         struct drm_device *dev = crtc->base.dev;
1944         struct drm_i915_private *dev_priv = dev->dev_private;
1945         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1946
1947         /* PCH only available on ILK+ */
1948         BUG_ON(INTEL_INFO(dev)->gen < 5);
1949         if (pll == NULL)
1950                 return;
1951
1952         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1953                 return;
1954
1955         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1956                       pll->name, pll->active, pll->on,
1957                       crtc->base.base.id);
1958
1959         if (WARN_ON(pll->active == 0)) {
1960                 assert_shared_dpll_disabled(dev_priv, pll);
1961                 return;
1962         }
1963
1964         assert_shared_dpll_enabled(dev_priv, pll);
1965         WARN_ON(!pll->on);
1966         if (--pll->active)
1967                 return;
1968
1969         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1970         pll->disable(dev_priv, pll);
1971         pll->on = false;
1972
1973         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1974 }
1975
1976 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1977                                            enum pipe pipe)
1978 {
1979         struct drm_device *dev = dev_priv->dev;
1980         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1982         uint32_t reg, val, pipeconf_val;
1983
1984         /* PCH only available on ILK+ */
1985         BUG_ON(!HAS_PCH_SPLIT(dev));
1986
1987         /* Make sure PCH DPLL is enabled */
1988         assert_shared_dpll_enabled(dev_priv,
1989                                    intel_crtc_to_shared_dpll(intel_crtc));
1990
1991         /* FDI must be feeding us bits for PCH ports */
1992         assert_fdi_tx_enabled(dev_priv, pipe);
1993         assert_fdi_rx_enabled(dev_priv, pipe);
1994
1995         if (HAS_PCH_CPT(dev)) {
1996                 /* Workaround: Set the timing override bit before enabling the
1997                  * pch transcoder. */
1998                 reg = TRANS_CHICKEN2(pipe);
1999                 val = I915_READ(reg);
2000                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2001                 I915_WRITE(reg, val);
2002         }
2003
2004         reg = PCH_TRANSCONF(pipe);
2005         val = I915_READ(reg);
2006         pipeconf_val = I915_READ(PIPECONF(pipe));
2007
2008         if (HAS_PCH_IBX(dev_priv->dev)) {
2009                 /*
2010                  * Make the BPC in transcoder be consistent with
2011                  * that in pipeconf reg. For HDMI we must use 8bpc
2012                  * here for both 8bpc and 12bpc.
2013                  */
2014                 val &= ~PIPECONF_BPC_MASK;
2015                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2016                         val |= PIPECONF_8BPC;
2017                 else
2018                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2019         }
2020
2021         val &= ~TRANS_INTERLACE_MASK;
2022         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2023                 if (HAS_PCH_IBX(dev_priv->dev) &&
2024                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2025                         val |= TRANS_LEGACY_INTERLACED_ILK;
2026                 else
2027                         val |= TRANS_INTERLACED;
2028         else
2029                 val |= TRANS_PROGRESSIVE;
2030
2031         I915_WRITE(reg, val | TRANS_ENABLE);
2032         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2033                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2034 }
2035
2036 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2037                                       enum transcoder cpu_transcoder)
2038 {
2039         u32 val, pipeconf_val;
2040
2041         /* PCH only available on ILK+ */
2042         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2043
2044         /* FDI must be feeding us bits for PCH ports */
2045         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2046         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2047
2048         /* Workaround: set timing override bit. */
2049         val = I915_READ(_TRANSA_CHICKEN2);
2050         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2051         I915_WRITE(_TRANSA_CHICKEN2, val);
2052
2053         val = TRANS_ENABLE;
2054         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2055
2056         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2057             PIPECONF_INTERLACED_ILK)
2058                 val |= TRANS_INTERLACED;
2059         else
2060                 val |= TRANS_PROGRESSIVE;
2061
2062         I915_WRITE(LPT_TRANSCONF, val);
2063         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2064                 DRM_ERROR("Failed to enable PCH transcoder\n");
2065 }
2066
2067 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2068                                             enum pipe pipe)
2069 {
2070         struct drm_device *dev = dev_priv->dev;
2071         uint32_t reg, val;
2072
2073         /* FDI relies on the transcoder */
2074         assert_fdi_tx_disabled(dev_priv, pipe);
2075         assert_fdi_rx_disabled(dev_priv, pipe);
2076
2077         /* Ports must be off as well */
2078         assert_pch_ports_disabled(dev_priv, pipe);
2079
2080         reg = PCH_TRANSCONF(pipe);
2081         val = I915_READ(reg);
2082         val &= ~TRANS_ENABLE;
2083         I915_WRITE(reg, val);
2084         /* wait for PCH transcoder off, transcoder state */
2085         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2086                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2087
2088         if (!HAS_PCH_IBX(dev)) {
2089                 /* Workaround: Clear the timing override chicken bit again. */
2090                 reg = TRANS_CHICKEN2(pipe);
2091                 val = I915_READ(reg);
2092                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2093                 I915_WRITE(reg, val);
2094         }
2095 }
2096
2097 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2098 {
2099         u32 val;
2100
2101         val = I915_READ(LPT_TRANSCONF);
2102         val &= ~TRANS_ENABLE;
2103         I915_WRITE(LPT_TRANSCONF, val);
2104         /* wait for PCH transcoder off, transcoder state */
2105         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2106                 DRM_ERROR("Failed to disable PCH transcoder\n");
2107
2108         /* Workaround: clear timing override bit. */
2109         val = I915_READ(_TRANSA_CHICKEN2);
2110         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2111         I915_WRITE(_TRANSA_CHICKEN2, val);
2112 }
2113
2114 /**
2115  * intel_enable_pipe - enable a pipe, asserting requirements
2116  * @crtc: crtc responsible for the pipe
2117  *
2118  * Enable @crtc's pipe, making sure that various hardware specific requirements
2119  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2120  */
2121 static void intel_enable_pipe(struct intel_crtc *crtc)
2122 {
2123         struct drm_device *dev = crtc->base.dev;
2124         struct drm_i915_private *dev_priv = dev->dev_private;
2125         enum pipe pipe = crtc->pipe;
2126         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2127                                                                       pipe);
2128         enum pipe pch_transcoder;
2129         int reg;
2130         u32 val;
2131
2132         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2133
2134         assert_planes_disabled(dev_priv, pipe);
2135         assert_cursor_disabled(dev_priv, pipe);
2136         assert_sprites_disabled(dev_priv, pipe);
2137
2138         if (HAS_PCH_LPT(dev_priv->dev))
2139                 pch_transcoder = TRANSCODER_A;
2140         else
2141                 pch_transcoder = pipe;
2142
2143         /*
2144          * A pipe without a PLL won't actually be able to drive bits from
2145          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2146          * need the check.
2147          */
2148         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2149                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2150                         assert_dsi_pll_enabled(dev_priv);
2151                 else
2152                         assert_pll_enabled(dev_priv, pipe);
2153         else {
2154                 if (crtc->config->has_pch_encoder) {
2155                         /* if driving the PCH, we need FDI enabled */
2156                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2157                         assert_fdi_tx_pll_enabled(dev_priv,
2158                                                   (enum pipe) cpu_transcoder);
2159                 }
2160                 /* FIXME: assert CPU port conditions for SNB+ */
2161         }
2162
2163         reg = PIPECONF(cpu_transcoder);
2164         val = I915_READ(reg);
2165         if (val & PIPECONF_ENABLE) {
2166                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2167                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2168                 return;
2169         }
2170
2171         I915_WRITE(reg, val | PIPECONF_ENABLE);
2172         POSTING_READ(reg);
2173 }
2174
2175 /**
2176  * intel_disable_pipe - disable a pipe, asserting requirements
2177  * @crtc: crtc whose pipes is to be disabled
2178  *
2179  * Disable the pipe of @crtc, making sure that various hardware
2180  * specific requirements are met, if applicable, e.g. plane
2181  * disabled, panel fitter off, etc.
2182  *
2183  * Will wait until the pipe has shut down before returning.
2184  */
2185 static void intel_disable_pipe(struct intel_crtc *crtc)
2186 {
2187         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2188         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2189         enum pipe pipe = crtc->pipe;
2190         int reg;
2191         u32 val;
2192
2193         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2194
2195         /*
2196          * Make sure planes won't keep trying to pump pixels to us,
2197          * or we might hang the display.
2198          */
2199         assert_planes_disabled(dev_priv, pipe);
2200         assert_cursor_disabled(dev_priv, pipe);
2201         assert_sprites_disabled(dev_priv, pipe);
2202
2203         reg = PIPECONF(cpu_transcoder);
2204         val = I915_READ(reg);
2205         if ((val & PIPECONF_ENABLE) == 0)
2206                 return;
2207
2208         /*
2209          * Double wide has implications for planes
2210          * so best keep it disabled when not needed.
2211          */
2212         if (crtc->config->double_wide)
2213                 val &= ~PIPECONF_DOUBLE_WIDE;
2214
2215         /* Don't disable pipe or pipe PLLs if needed */
2216         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2217             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2218                 val &= ~PIPECONF_ENABLE;
2219
2220         I915_WRITE(reg, val);
2221         if ((val & PIPECONF_ENABLE) == 0)
2222                 intel_wait_for_pipe_off(crtc);
2223 }
2224
2225 static bool need_vtd_wa(struct drm_device *dev)
2226 {
2227 #ifdef CONFIG_INTEL_IOMMU
2228         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2229                 return true;
2230 #endif
2231         return false;
2232 }
2233
2234 unsigned int
2235 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2236                   uint64_t fb_format_modifier)
2237 {
2238         unsigned int tile_height;
2239         uint32_t pixel_bytes;
2240
2241         switch (fb_format_modifier) {
2242         case DRM_FORMAT_MOD_NONE:
2243                 tile_height = 1;
2244                 break;
2245         case I915_FORMAT_MOD_X_TILED:
2246                 tile_height = IS_GEN2(dev) ? 16 : 8;
2247                 break;
2248         case I915_FORMAT_MOD_Y_TILED:
2249                 tile_height = 32;
2250                 break;
2251         case I915_FORMAT_MOD_Yf_TILED:
2252                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2253                 switch (pixel_bytes) {
2254                 default:
2255                 case 1:
2256                         tile_height = 64;
2257                         break;
2258                 case 2:
2259                 case 4:
2260                         tile_height = 32;
2261                         break;
2262                 case 8:
2263                         tile_height = 16;
2264                         break;
2265                 case 16:
2266                         WARN_ONCE(1,
2267                                   "128-bit pixels are not supported for display!");
2268                         tile_height = 16;
2269                         break;
2270                 }
2271                 break;
2272         default:
2273                 MISSING_CASE(fb_format_modifier);
2274                 tile_height = 1;
2275                 break;
2276         }
2277
2278         return tile_height;
2279 }
2280
2281 unsigned int
2282 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2283                       uint32_t pixel_format, uint64_t fb_format_modifier)
2284 {
2285         return ALIGN(height, intel_tile_height(dev, pixel_format,
2286                                                fb_format_modifier));
2287 }
2288
2289 static int
2290 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2291                         const struct drm_plane_state *plane_state)
2292 {
2293         struct intel_rotation_info *info = &view->rotation_info;
2294         unsigned int tile_height, tile_pitch;
2295
2296         *view = i915_ggtt_view_normal;
2297
2298         if (!plane_state)
2299                 return 0;
2300
2301         if (!intel_rotation_90_or_270(plane_state->rotation))
2302                 return 0;
2303
2304         *view = i915_ggtt_view_rotated;
2305
2306         info->height = fb->height;
2307         info->pixel_format = fb->pixel_format;
2308         info->pitch = fb->pitches[0];
2309         info->fb_modifier = fb->modifier[0];
2310
2311         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2312                                         fb->modifier[0]);
2313         tile_pitch = PAGE_SIZE / tile_height;
2314         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2315         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2316         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2317
2318         return 0;
2319 }
2320
2321 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2322 {
2323         if (INTEL_INFO(dev_priv)->gen >= 9)
2324                 return 256 * 1024;
2325         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2326                  IS_VALLEYVIEW(dev_priv))
2327                 return 128 * 1024;
2328         else if (INTEL_INFO(dev_priv)->gen >= 4)
2329                 return 4 * 1024;
2330         else
2331                 return 0;
2332 }
2333
2334 int
2335 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2336                            struct drm_framebuffer *fb,
2337                            const struct drm_plane_state *plane_state,
2338                            struct intel_engine_cs *pipelined,
2339                            struct drm_i915_gem_request **pipelined_request)
2340 {
2341         struct drm_device *dev = fb->dev;
2342         struct drm_i915_private *dev_priv = dev->dev_private;
2343         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2344         struct i915_ggtt_view view;
2345         u32 alignment;
2346         int ret;
2347
2348         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2349
2350         switch (fb->modifier[0]) {
2351         case DRM_FORMAT_MOD_NONE:
2352                 alignment = intel_linear_alignment(dev_priv);
2353                 break;
2354         case I915_FORMAT_MOD_X_TILED:
2355                 if (INTEL_INFO(dev)->gen >= 9)
2356                         alignment = 256 * 1024;
2357                 else {
2358                         /* pin() will align the object as required by fence */
2359                         alignment = 0;
2360                 }
2361                 break;
2362         case I915_FORMAT_MOD_Y_TILED:
2363         case I915_FORMAT_MOD_Yf_TILED:
2364                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2365                           "Y tiling bo slipped through, driver bug!\n"))
2366                         return -EINVAL;
2367                 alignment = 1 * 1024 * 1024;
2368                 break;
2369         default:
2370                 MISSING_CASE(fb->modifier[0]);
2371                 return -EINVAL;
2372         }
2373
2374         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2375         if (ret)
2376                 return ret;
2377
2378         /* Note that the w/a also requires 64 PTE of padding following the
2379          * bo. We currently fill all unused PTE with the shadow page and so
2380          * we should always have valid PTE following the scanout preventing
2381          * the VT-d warning.
2382          */
2383         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2384                 alignment = 256 * 1024;
2385
2386         /*
2387          * Global gtt pte registers are special registers which actually forward
2388          * writes to a chunk of system memory. Which means that there is no risk
2389          * that the register values disappear as soon as we call
2390          * intel_runtime_pm_put(), so it is correct to wrap only the
2391          * pin/unpin/fence and not more.
2392          */
2393         intel_runtime_pm_get(dev_priv);
2394
2395         dev_priv->mm.interruptible = false;
2396         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2397                                                    pipelined_request, &view);
2398         if (ret)
2399                 goto err_interruptible;
2400
2401         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2402          * fence, whereas 965+ only requires a fence if using
2403          * framebuffer compression.  For simplicity, we always install
2404          * a fence as the cost is not that onerous.
2405          */
2406         ret = i915_gem_object_get_fence(obj);
2407         if (ret)
2408                 goto err_unpin;
2409
2410         i915_gem_object_pin_fence(obj);
2411
2412         dev_priv->mm.interruptible = true;
2413         intel_runtime_pm_put(dev_priv);
2414         return 0;
2415
2416 err_unpin:
2417         i915_gem_object_unpin_from_display_plane(obj, &view);
2418 err_interruptible:
2419         dev_priv->mm.interruptible = true;
2420         intel_runtime_pm_put(dev_priv);
2421         return ret;
2422 }
2423
2424 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2425                                const struct drm_plane_state *plane_state)
2426 {
2427         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2428         struct i915_ggtt_view view;
2429         int ret;
2430
2431         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2432
2433         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2434         WARN_ONCE(ret, "Couldn't get view from plane state!");
2435
2436         i915_gem_object_unpin_fence(obj);
2437         i915_gem_object_unpin_from_display_plane(obj, &view);
2438 }
2439
2440 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2441  * is assumed to be a power-of-two. */
2442 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2443                                              int *x, int *y,
2444                                              unsigned int tiling_mode,
2445                                              unsigned int cpp,
2446                                              unsigned int pitch)
2447 {
2448         if (tiling_mode != I915_TILING_NONE) {
2449                 unsigned int tile_rows, tiles;
2450
2451                 tile_rows = *y / 8;
2452                 *y %= 8;
2453
2454                 tiles = *x / (512/cpp);
2455                 *x %= 512/cpp;
2456
2457                 return tile_rows * pitch * 8 + tiles * 4096;
2458         } else {
2459                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2460                 unsigned int offset;
2461
2462                 offset = *y * pitch + *x * cpp;
2463                 *y = (offset & alignment) / pitch;
2464                 *x = ((offset & alignment) - *y * pitch) / cpp;
2465                 return offset & ~alignment;
2466         }
2467 }
2468
2469 static int i9xx_format_to_fourcc(int format)
2470 {
2471         switch (format) {
2472         case DISPPLANE_8BPP:
2473                 return DRM_FORMAT_C8;
2474         case DISPPLANE_BGRX555:
2475                 return DRM_FORMAT_XRGB1555;
2476         case DISPPLANE_BGRX565:
2477                 return DRM_FORMAT_RGB565;
2478         default:
2479         case DISPPLANE_BGRX888:
2480                 return DRM_FORMAT_XRGB8888;
2481         case DISPPLANE_RGBX888:
2482                 return DRM_FORMAT_XBGR8888;
2483         case DISPPLANE_BGRX101010:
2484                 return DRM_FORMAT_XRGB2101010;
2485         case DISPPLANE_RGBX101010:
2486                 return DRM_FORMAT_XBGR2101010;
2487         }
2488 }
2489
2490 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2491 {
2492         switch (format) {
2493         case PLANE_CTL_FORMAT_RGB_565:
2494                 return DRM_FORMAT_RGB565;
2495         default:
2496         case PLANE_CTL_FORMAT_XRGB_8888:
2497                 if (rgb_order) {
2498                         if (alpha)
2499                                 return DRM_FORMAT_ABGR8888;
2500                         else
2501                                 return DRM_FORMAT_XBGR8888;
2502                 } else {
2503                         if (alpha)
2504                                 return DRM_FORMAT_ARGB8888;
2505                         else
2506                                 return DRM_FORMAT_XRGB8888;
2507                 }
2508         case PLANE_CTL_FORMAT_XRGB_2101010:
2509                 if (rgb_order)
2510                         return DRM_FORMAT_XBGR2101010;
2511                 else
2512                         return DRM_FORMAT_XRGB2101010;
2513         }
2514 }
2515
2516 static bool
2517 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2518                               struct intel_initial_plane_config *plane_config)
2519 {
2520         struct drm_device *dev = crtc->base.dev;
2521         struct drm_i915_gem_object *obj = NULL;
2522         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2523         struct drm_framebuffer *fb = &plane_config->fb->base;
2524         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2525         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2526                                     PAGE_SIZE);
2527
2528         size_aligned -= base_aligned;
2529
2530         if (plane_config->size == 0)
2531                 return false;
2532
2533         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2534                                                              base_aligned,
2535                                                              base_aligned,
2536                                                              size_aligned);
2537         if (!obj)
2538                 return false;
2539
2540         obj->tiling_mode = plane_config->tiling;
2541         if (obj->tiling_mode == I915_TILING_X)
2542                 obj->stride = fb->pitches[0];
2543
2544         mode_cmd.pixel_format = fb->pixel_format;
2545         mode_cmd.width = fb->width;
2546         mode_cmd.height = fb->height;
2547         mode_cmd.pitches[0] = fb->pitches[0];
2548         mode_cmd.modifier[0] = fb->modifier[0];
2549         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2550
2551         mutex_lock(&dev->struct_mutex);
2552         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2553                                    &mode_cmd, obj)) {
2554                 DRM_DEBUG_KMS("intel fb init failed\n");
2555                 goto out_unref_obj;
2556         }
2557         mutex_unlock(&dev->struct_mutex);
2558
2559         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2560         return true;
2561
2562 out_unref_obj:
2563         drm_gem_object_unreference(&obj->base);
2564         mutex_unlock(&dev->struct_mutex);
2565         return false;
2566 }
2567
2568 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2569 static void
2570 update_state_fb(struct drm_plane *plane)
2571 {
2572         if (plane->fb == plane->state->fb)
2573                 return;
2574
2575         if (plane->state->fb)
2576                 drm_framebuffer_unreference(plane->state->fb);
2577         plane->state->fb = plane->fb;
2578         if (plane->state->fb)
2579                 drm_framebuffer_reference(plane->state->fb);
2580 }
2581
2582 static void
2583 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2584                              struct intel_initial_plane_config *plane_config)
2585 {
2586         struct drm_device *dev = intel_crtc->base.dev;
2587         struct drm_i915_private *dev_priv = dev->dev_private;
2588         struct drm_crtc *c;
2589         struct intel_crtc *i;
2590         struct drm_i915_gem_object *obj;
2591         struct drm_plane *primary = intel_crtc->base.primary;
2592         struct drm_plane_state *plane_state = primary->state;
2593         struct drm_framebuffer *fb;
2594
2595         if (!plane_config->fb)
2596                 return;
2597
2598         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2599                 fb = &plane_config->fb->base;
2600                 goto valid_fb;
2601         }
2602
2603         kfree(plane_config->fb);
2604
2605         /*
2606          * Failed to alloc the obj, check to see if we should share
2607          * an fb with another CRTC instead
2608          */
2609         for_each_crtc(dev, c) {
2610                 i = to_intel_crtc(c);
2611
2612                 if (c == &intel_crtc->base)
2613                         continue;
2614
2615                 if (!i->active)
2616                         continue;
2617
2618                 fb = c->primary->fb;
2619                 if (!fb)
2620                         continue;
2621
2622                 obj = intel_fb_obj(fb);
2623                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2624                         drm_framebuffer_reference(fb);
2625                         goto valid_fb;
2626                 }
2627         }
2628
2629         return;
2630
2631 valid_fb:
2632         plane_state->src_x = plane_state->src_y = 0;
2633         plane_state->src_w = fb->width << 16;
2634         plane_state->src_h = fb->height << 16;
2635
2636         plane_state->crtc_x = plane_state->src_y = 0;
2637         plane_state->crtc_w = fb->width;
2638         plane_state->crtc_h = fb->height;
2639
2640         obj = intel_fb_obj(fb);
2641         if (obj->tiling_mode != I915_TILING_NONE)
2642                 dev_priv->preserve_bios_swizzle = true;
2643
2644         drm_framebuffer_reference(fb);
2645         primary->fb = primary->state->fb = fb;
2646         primary->crtc = primary->state->crtc = &intel_crtc->base;
2647         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2648         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2649 }
2650
2651 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2652                                       struct drm_framebuffer *fb,
2653                                       int x, int y)
2654 {
2655         struct drm_device *dev = crtc->dev;
2656         struct drm_i915_private *dev_priv = dev->dev_private;
2657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2658         struct drm_plane *primary = crtc->primary;
2659         bool visible = to_intel_plane_state(primary->state)->visible;
2660         struct drm_i915_gem_object *obj;
2661         int plane = intel_crtc->plane;
2662         unsigned long linear_offset;
2663         u32 dspcntr;
2664         u32 reg = DSPCNTR(plane);
2665         int pixel_size;
2666
2667         if (!visible || !fb) {
2668                 I915_WRITE(reg, 0);
2669                 if (INTEL_INFO(dev)->gen >= 4)
2670                         I915_WRITE(DSPSURF(plane), 0);
2671                 else
2672                         I915_WRITE(DSPADDR(plane), 0);
2673                 POSTING_READ(reg);
2674                 return;
2675         }
2676
2677         obj = intel_fb_obj(fb);
2678         if (WARN_ON(obj == NULL))
2679                 return;
2680
2681         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2682
2683         dspcntr = DISPPLANE_GAMMA_ENABLE;
2684
2685         dspcntr |= DISPLAY_PLANE_ENABLE;
2686
2687         if (INTEL_INFO(dev)->gen < 4) {
2688                 if (intel_crtc->pipe == PIPE_B)
2689                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2690
2691                 /* pipesrc and dspsize control the size that is scaled from,
2692                  * which should always be the user's requested size.
2693                  */
2694                 I915_WRITE(DSPSIZE(plane),
2695                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2696                            (intel_crtc->config->pipe_src_w - 1));
2697                 I915_WRITE(DSPPOS(plane), 0);
2698         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2699                 I915_WRITE(PRIMSIZE(plane),
2700                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2701                            (intel_crtc->config->pipe_src_w - 1));
2702                 I915_WRITE(PRIMPOS(plane), 0);
2703                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2704         }
2705
2706         switch (fb->pixel_format) {
2707         case DRM_FORMAT_C8:
2708                 dspcntr |= DISPPLANE_8BPP;
2709                 break;
2710         case DRM_FORMAT_XRGB1555:
2711                 dspcntr |= DISPPLANE_BGRX555;
2712                 break;
2713         case DRM_FORMAT_RGB565:
2714                 dspcntr |= DISPPLANE_BGRX565;
2715                 break;
2716         case DRM_FORMAT_XRGB8888:
2717                 dspcntr |= DISPPLANE_BGRX888;
2718                 break;
2719         case DRM_FORMAT_XBGR8888:
2720                 dspcntr |= DISPPLANE_RGBX888;
2721                 break;
2722         case DRM_FORMAT_XRGB2101010:
2723                 dspcntr |= DISPPLANE_BGRX101010;
2724                 break;
2725         case DRM_FORMAT_XBGR2101010:
2726                 dspcntr |= DISPPLANE_RGBX101010;
2727                 break;
2728         default:
2729                 BUG();
2730         }
2731
2732         if (INTEL_INFO(dev)->gen >= 4 &&
2733             obj->tiling_mode != I915_TILING_NONE)
2734                 dspcntr |= DISPPLANE_TILED;
2735
2736         if (IS_G4X(dev))
2737                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2738
2739         linear_offset = y * fb->pitches[0] + x * pixel_size;
2740
2741         if (INTEL_INFO(dev)->gen >= 4) {
2742                 intel_crtc->dspaddr_offset =
2743                         intel_gen4_compute_page_offset(dev_priv,
2744                                                        &x, &y, obj->tiling_mode,
2745                                                        pixel_size,
2746                                                        fb->pitches[0]);
2747                 linear_offset -= intel_crtc->dspaddr_offset;
2748         } else {
2749                 intel_crtc->dspaddr_offset = linear_offset;
2750         }
2751
2752         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2753                 dspcntr |= DISPPLANE_ROTATE_180;
2754
2755                 x += (intel_crtc->config->pipe_src_w - 1);
2756                 y += (intel_crtc->config->pipe_src_h - 1);
2757
2758                 /* Finding the last pixel of the last line of the display
2759                 data and adding to linear_offset*/
2760                 linear_offset +=
2761                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2762                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2763         }
2764
2765         I915_WRITE(reg, dspcntr);
2766
2767         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2768         if (INTEL_INFO(dev)->gen >= 4) {
2769                 I915_WRITE(DSPSURF(plane),
2770                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2771                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2772                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2773         } else
2774                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2775         POSTING_READ(reg);
2776 }
2777
2778 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2779                                           struct drm_framebuffer *fb,
2780                                           int x, int y)
2781 {
2782         struct drm_device *dev = crtc->dev;
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2785         struct drm_plane *primary = crtc->primary;
2786         bool visible = to_intel_plane_state(primary->state)->visible;
2787         struct drm_i915_gem_object *obj;
2788         int plane = intel_crtc->plane;
2789         unsigned long linear_offset;
2790         u32 dspcntr;
2791         u32 reg = DSPCNTR(plane);
2792         int pixel_size;
2793
2794         if (!visible || !fb) {
2795                 I915_WRITE(reg, 0);
2796                 I915_WRITE(DSPSURF(plane), 0);
2797                 POSTING_READ(reg);
2798                 return;
2799         }
2800
2801         obj = intel_fb_obj(fb);
2802         if (WARN_ON(obj == NULL))
2803                 return;
2804
2805         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2806
2807         dspcntr = DISPPLANE_GAMMA_ENABLE;
2808
2809         dspcntr |= DISPLAY_PLANE_ENABLE;
2810
2811         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2812                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2813
2814         switch (fb->pixel_format) {
2815         case DRM_FORMAT_C8:
2816                 dspcntr |= DISPPLANE_8BPP;
2817                 break;
2818         case DRM_FORMAT_RGB565:
2819                 dspcntr |= DISPPLANE_BGRX565;
2820                 break;
2821         case DRM_FORMAT_XRGB8888:
2822                 dspcntr |= DISPPLANE_BGRX888;
2823                 break;
2824         case DRM_FORMAT_XBGR8888:
2825                 dspcntr |= DISPPLANE_RGBX888;
2826                 break;
2827         case DRM_FORMAT_XRGB2101010:
2828                 dspcntr |= DISPPLANE_BGRX101010;
2829                 break;
2830         case DRM_FORMAT_XBGR2101010:
2831                 dspcntr |= DISPPLANE_RGBX101010;
2832                 break;
2833         default:
2834                 BUG();
2835         }
2836
2837         if (obj->tiling_mode != I915_TILING_NONE)
2838                 dspcntr |= DISPPLANE_TILED;
2839
2840         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2841                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2842
2843         linear_offset = y * fb->pitches[0] + x * pixel_size;
2844         intel_crtc->dspaddr_offset =
2845                 intel_gen4_compute_page_offset(dev_priv,
2846                                                &x, &y, obj->tiling_mode,
2847                                                pixel_size,
2848                                                fb->pitches[0]);
2849         linear_offset -= intel_crtc->dspaddr_offset;
2850         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2851                 dspcntr |= DISPPLANE_ROTATE_180;
2852
2853                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2854                         x += (intel_crtc->config->pipe_src_w - 1);
2855                         y += (intel_crtc->config->pipe_src_h - 1);
2856
2857                         /* Finding the last pixel of the last line of the display
2858                         data and adding to linear_offset*/
2859                         linear_offset +=
2860                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2861                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2862                 }
2863         }
2864
2865         I915_WRITE(reg, dspcntr);
2866
2867         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2868         I915_WRITE(DSPSURF(plane),
2869                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2870         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2871                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2872         } else {
2873                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2874                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2875         }
2876         POSTING_READ(reg);
2877 }
2878
2879 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2880                               uint32_t pixel_format)
2881 {
2882         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2883
2884         /*
2885          * The stride is either expressed as a multiple of 64 bytes
2886          * chunks for linear buffers or in number of tiles for tiled
2887          * buffers.
2888          */
2889         switch (fb_modifier) {
2890         case DRM_FORMAT_MOD_NONE:
2891                 return 64;
2892         case I915_FORMAT_MOD_X_TILED:
2893                 if (INTEL_INFO(dev)->gen == 2)
2894                         return 128;
2895                 return 512;
2896         case I915_FORMAT_MOD_Y_TILED:
2897                 /* No need to check for old gens and Y tiling since this is
2898                  * about the display engine and those will be blocked before
2899                  * we get here.
2900                  */
2901                 return 128;
2902         case I915_FORMAT_MOD_Yf_TILED:
2903                 if (bits_per_pixel == 8)
2904                         return 64;
2905                 else
2906                         return 128;
2907         default:
2908                 MISSING_CASE(fb_modifier);
2909                 return 64;
2910         }
2911 }
2912
2913 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2914                                      struct drm_i915_gem_object *obj)
2915 {
2916         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2917
2918         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2919                 view = &i915_ggtt_view_rotated;
2920
2921         return i915_gem_obj_ggtt_offset_view(obj, view);
2922 }
2923
2924 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2925 {
2926         struct drm_device *dev = intel_crtc->base.dev;
2927         struct drm_i915_private *dev_priv = dev->dev_private;
2928
2929         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2930         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2931         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2932         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2933                 intel_crtc->base.base.id, intel_crtc->pipe, id);
2934 }
2935
2936 /*
2937  * This function detaches (aka. unbinds) unused scalers in hardware
2938  */
2939 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2940 {
2941         struct intel_crtc_scaler_state *scaler_state;
2942         int i;
2943
2944         scaler_state = &intel_crtc->config->scaler_state;
2945
2946         /* loop through and disable scalers that aren't in use */
2947         for (i = 0; i < intel_crtc->num_scalers; i++) {
2948                 if (!scaler_state->scalers[i].in_use)
2949                         skl_detach_scaler(intel_crtc, i);
2950         }
2951 }
2952
2953 u32 skl_plane_ctl_format(uint32_t pixel_format)
2954 {
2955         switch (pixel_format) {
2956         case DRM_FORMAT_C8:
2957                 return PLANE_CTL_FORMAT_INDEXED;
2958         case DRM_FORMAT_RGB565:
2959                 return PLANE_CTL_FORMAT_RGB_565;
2960         case DRM_FORMAT_XBGR8888:
2961                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2962         case DRM_FORMAT_XRGB8888:
2963                 return PLANE_CTL_FORMAT_XRGB_8888;
2964         /*
2965          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2966          * to be already pre-multiplied. We need to add a knob (or a different
2967          * DRM_FORMAT) for user-space to configure that.
2968          */
2969         case DRM_FORMAT_ABGR8888:
2970                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2971                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2972         case DRM_FORMAT_ARGB8888:
2973                 return PLANE_CTL_FORMAT_XRGB_8888 |
2974                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2975         case DRM_FORMAT_XRGB2101010:
2976                 return PLANE_CTL_FORMAT_XRGB_2101010;
2977         case DRM_FORMAT_XBGR2101010:
2978                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2979         case DRM_FORMAT_YUYV:
2980                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2981         case DRM_FORMAT_YVYU:
2982                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2983         case DRM_FORMAT_UYVY:
2984                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2985         case DRM_FORMAT_VYUY:
2986                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2987         default:
2988                 MISSING_CASE(pixel_format);
2989         }
2990
2991         return 0;
2992 }
2993
2994 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2995 {
2996         switch (fb_modifier) {
2997         case DRM_FORMAT_MOD_NONE:
2998                 break;
2999         case I915_FORMAT_MOD_X_TILED:
3000                 return PLANE_CTL_TILED_X;
3001         case I915_FORMAT_MOD_Y_TILED:
3002                 return PLANE_CTL_TILED_Y;
3003         case I915_FORMAT_MOD_Yf_TILED:
3004                 return PLANE_CTL_TILED_YF;
3005         default:
3006                 MISSING_CASE(fb_modifier);
3007         }
3008
3009         return 0;
3010 }
3011
3012 u32 skl_plane_ctl_rotation(unsigned int rotation)
3013 {
3014         switch (rotation) {
3015         case BIT(DRM_ROTATE_0):
3016                 break;
3017         /*
3018          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3019          * while i915 HW rotation is clockwise, thats why this swapping.
3020          */
3021         case BIT(DRM_ROTATE_90):
3022                 return PLANE_CTL_ROTATE_270;
3023         case BIT(DRM_ROTATE_180):
3024                 return PLANE_CTL_ROTATE_180;
3025         case BIT(DRM_ROTATE_270):
3026                 return PLANE_CTL_ROTATE_90;
3027         default:
3028                 MISSING_CASE(rotation);
3029         }
3030
3031         return 0;
3032 }
3033
3034 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3035                                          struct drm_framebuffer *fb,
3036                                          int x, int y)
3037 {
3038         struct drm_device *dev = crtc->dev;
3039         struct drm_i915_private *dev_priv = dev->dev_private;
3040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3041         struct drm_plane *plane = crtc->primary;
3042         bool visible = to_intel_plane_state(plane->state)->visible;
3043         struct drm_i915_gem_object *obj;
3044         int pipe = intel_crtc->pipe;
3045         u32 plane_ctl, stride_div, stride;
3046         u32 tile_height, plane_offset, plane_size;
3047         unsigned int rotation;
3048         int x_offset, y_offset;
3049         unsigned long surf_addr;
3050         struct intel_crtc_state *crtc_state = intel_crtc->config;
3051         struct intel_plane_state *plane_state;
3052         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3053         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3054         int scaler_id = -1;
3055
3056         plane_state = to_intel_plane_state(plane->state);
3057
3058         if (!visible || !fb) {
3059                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3060                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3061                 POSTING_READ(PLANE_CTL(pipe, 0));
3062                 return;
3063         }
3064
3065         plane_ctl = PLANE_CTL_ENABLE |
3066                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3067                     PLANE_CTL_PIPE_CSC_ENABLE;
3068
3069         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3070         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3071         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3072
3073         rotation = plane->state->rotation;
3074         plane_ctl |= skl_plane_ctl_rotation(rotation);
3075
3076         obj = intel_fb_obj(fb);
3077         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3078                                                fb->pixel_format);
3079         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3080
3081         /*
3082          * FIXME: intel_plane_state->src, dst aren't set when transitional
3083          * update_plane helpers are called from legacy paths.
3084          * Once full atomic crtc is available, below check can be avoided.
3085          */
3086         if (drm_rect_width(&plane_state->src)) {
3087                 scaler_id = plane_state->scaler_id;
3088                 src_x = plane_state->src.x1 >> 16;
3089                 src_y = plane_state->src.y1 >> 16;
3090                 src_w = drm_rect_width(&plane_state->src) >> 16;
3091                 src_h = drm_rect_height(&plane_state->src) >> 16;
3092                 dst_x = plane_state->dst.x1;
3093                 dst_y = plane_state->dst.y1;
3094                 dst_w = drm_rect_width(&plane_state->dst);
3095                 dst_h = drm_rect_height(&plane_state->dst);
3096
3097                 WARN_ON(x != src_x || y != src_y);
3098         } else {
3099                 src_w = intel_crtc->config->pipe_src_w;
3100                 src_h = intel_crtc->config->pipe_src_h;
3101         }
3102
3103         if (intel_rotation_90_or_270(rotation)) {
3104                 /* stride = Surface height in tiles */
3105                 tile_height = intel_tile_height(dev, fb->pixel_format,
3106                                                 fb->modifier[0]);
3107                 stride = DIV_ROUND_UP(fb->height, tile_height);
3108                 x_offset = stride * tile_height - y - src_h;
3109                 y_offset = x;
3110                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3111         } else {
3112                 stride = fb->pitches[0] / stride_div;
3113                 x_offset = x;
3114                 y_offset = y;
3115                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3116         }
3117         plane_offset = y_offset << 16 | x_offset;
3118
3119         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3120         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3121         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3122         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3123
3124         if (scaler_id >= 0) {
3125                 uint32_t ps_ctrl = 0;
3126
3127                 WARN_ON(!dst_w || !dst_h);
3128                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3129                         crtc_state->scaler_state.scalers[scaler_id].mode;
3130                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3131                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3132                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3133                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3134                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3135         } else {
3136                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3137         }
3138
3139         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3140
3141         POSTING_READ(PLANE_SURF(pipe, 0));
3142 }
3143
3144 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3145 static int
3146 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3147                            int x, int y, enum mode_set_atomic state)
3148 {
3149         struct drm_device *dev = crtc->dev;
3150         struct drm_i915_private *dev_priv = dev->dev_private;
3151
3152         if (dev_priv->fbc.disable_fbc)
3153                 dev_priv->fbc.disable_fbc(dev_priv);
3154
3155         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3156
3157         return 0;
3158 }
3159
3160 static void intel_complete_page_flips(struct drm_device *dev)
3161 {
3162         struct drm_crtc *crtc;
3163
3164         for_each_crtc(dev, crtc) {
3165                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3166                 enum plane plane = intel_crtc->plane;
3167
3168                 intel_prepare_page_flip(dev, plane);
3169                 intel_finish_page_flip_plane(dev, plane);
3170         }
3171 }
3172
3173 static void intel_update_primary_planes(struct drm_device *dev)
3174 {
3175         struct drm_i915_private *dev_priv = dev->dev_private;
3176         struct drm_crtc *crtc;
3177
3178         for_each_crtc(dev, crtc) {
3179                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3180
3181                 drm_modeset_lock(&crtc->mutex, NULL);
3182                 /*
3183                  * FIXME: Once we have proper support for primary planes (and
3184                  * disabling them without disabling the entire crtc) allow again
3185                  * a NULL crtc->primary->fb.
3186                  */
3187                 if (intel_crtc->active && crtc->primary->fb)
3188                         dev_priv->display.update_primary_plane(crtc,
3189                                                                crtc->primary->fb,
3190                                                                crtc->x,
3191                                                                crtc->y);
3192                 drm_modeset_unlock(&crtc->mutex);
3193         }
3194 }
3195
3196 void intel_prepare_reset(struct drm_device *dev)
3197 {
3198         /* no reset support for gen2 */
3199         if (IS_GEN2(dev))
3200                 return;
3201
3202         /* reset doesn't touch the display */
3203         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3204                 return;
3205
3206         drm_modeset_lock_all(dev);
3207         /*
3208          * Disabling the crtcs gracefully seems nicer. Also the
3209          * g33 docs say we should at least disable all the planes.
3210          */
3211         intel_display_suspend(dev);
3212 }
3213
3214 void intel_finish_reset(struct drm_device *dev)
3215 {
3216         struct drm_i915_private *dev_priv = to_i915(dev);
3217
3218         /*
3219          * Flips in the rings will be nuked by the reset,
3220          * so complete all pending flips so that user space
3221          * will get its events and not get stuck.
3222          */
3223         intel_complete_page_flips(dev);
3224
3225         /* no reset support for gen2 */
3226         if (IS_GEN2(dev))
3227                 return;
3228
3229         /* reset doesn't touch the display */
3230         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3231                 /*
3232                  * Flips in the rings have been nuked by the reset,
3233                  * so update the base address of all primary
3234                  * planes to the the last fb to make sure we're
3235                  * showing the correct fb after a reset.
3236                  */
3237                 intel_update_primary_planes(dev);
3238                 return;
3239         }
3240
3241         /*
3242          * The display has been reset as well,
3243          * so need a full re-initialization.
3244          */
3245         intel_runtime_pm_disable_interrupts(dev_priv);
3246         intel_runtime_pm_enable_interrupts(dev_priv);
3247
3248         intel_modeset_init_hw(dev);
3249
3250         spin_lock_irq(&dev_priv->irq_lock);
3251         if (dev_priv->display.hpd_irq_setup)
3252                 dev_priv->display.hpd_irq_setup(dev);
3253         spin_unlock_irq(&dev_priv->irq_lock);
3254
3255         intel_display_resume(dev);
3256
3257         intel_hpd_init(dev_priv);
3258
3259         drm_modeset_unlock_all(dev);
3260 }
3261
3262 static void
3263 intel_finish_fb(struct drm_framebuffer *old_fb)
3264 {
3265         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3266         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3267         bool was_interruptible = dev_priv->mm.interruptible;
3268         int ret;
3269
3270         /* Big Hammer, we also need to ensure that any pending
3271          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3272          * current scanout is retired before unpinning the old
3273          * framebuffer. Note that we rely on userspace rendering
3274          * into the buffer attached to the pipe they are waiting
3275          * on. If not, userspace generates a GPU hang with IPEHR
3276          * point to the MI_WAIT_FOR_EVENT.
3277          *
3278          * This should only fail upon a hung GPU, in which case we
3279          * can safely continue.
3280          */
3281         dev_priv->mm.interruptible = false;
3282         ret = i915_gem_object_wait_rendering(obj, true);
3283         dev_priv->mm.interruptible = was_interruptible;
3284
3285         WARN_ON(ret);
3286 }
3287
3288 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3289 {
3290         struct drm_device *dev = crtc->dev;
3291         struct drm_i915_private *dev_priv = dev->dev_private;
3292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3293         bool pending;
3294
3295         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3296             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3297                 return false;
3298
3299         spin_lock_irq(&dev->event_lock);
3300         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3301         spin_unlock_irq(&dev->event_lock);
3302
3303         return pending;
3304 }
3305
3306 static void intel_update_pipe_size(struct intel_crtc *crtc)
3307 {
3308         struct drm_device *dev = crtc->base.dev;
3309         struct drm_i915_private *dev_priv = dev->dev_private;
3310         const struct drm_display_mode *adjusted_mode;
3311
3312         if (!i915.fastboot)
3313                 return;
3314
3315         /*
3316          * Update pipe size and adjust fitter if needed: the reason for this is
3317          * that in compute_mode_changes we check the native mode (not the pfit
3318          * mode) to see if we can flip rather than do a full mode set. In the
3319          * fastboot case, we'll flip, but if we don't update the pipesrc and
3320          * pfit state, we'll end up with a big fb scanned out into the wrong
3321          * sized surface.
3322          *
3323          * To fix this properly, we need to hoist the checks up into
3324          * compute_mode_changes (or above), check the actual pfit state and
3325          * whether the platform allows pfit disable with pipe active, and only
3326          * then update the pipesrc and pfit state, even on the flip path.
3327          */
3328
3329         adjusted_mode = &crtc->config->base.adjusted_mode;
3330
3331         I915_WRITE(PIPESRC(crtc->pipe),
3332                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3333                    (adjusted_mode->crtc_vdisplay - 1));
3334         if (!crtc->config->pch_pfit.enabled &&
3335             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3336              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3337                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3338                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3339                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3340         }
3341         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3342         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3343 }
3344
3345 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3346 {
3347         struct drm_device *dev = crtc->dev;
3348         struct drm_i915_private *dev_priv = dev->dev_private;
3349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3350         int pipe = intel_crtc->pipe;
3351         u32 reg, temp;
3352
3353         /* enable normal train */
3354         reg = FDI_TX_CTL(pipe);
3355         temp = I915_READ(reg);
3356         if (IS_IVYBRIDGE(dev)) {
3357                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3358                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3359         } else {
3360                 temp &= ~FDI_LINK_TRAIN_NONE;
3361                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3362         }
3363         I915_WRITE(reg, temp);
3364
3365         reg = FDI_RX_CTL(pipe);
3366         temp = I915_READ(reg);
3367         if (HAS_PCH_CPT(dev)) {
3368                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3369                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3370         } else {
3371                 temp &= ~FDI_LINK_TRAIN_NONE;
3372                 temp |= FDI_LINK_TRAIN_NONE;
3373         }
3374         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3375
3376         /* wait one idle pattern time */
3377         POSTING_READ(reg);
3378         udelay(1000);
3379
3380         /* IVB wants error correction enabled */
3381         if (IS_IVYBRIDGE(dev))
3382                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3383                            FDI_FE_ERRC_ENABLE);
3384 }
3385
3386 /* The FDI link training functions for ILK/Ibexpeak. */
3387 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3388 {
3389         struct drm_device *dev = crtc->dev;
3390         struct drm_i915_private *dev_priv = dev->dev_private;
3391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3392         int pipe = intel_crtc->pipe;
3393         u32 reg, temp, tries;
3394
3395         /* FDI needs bits from pipe first */
3396         assert_pipe_enabled(dev_priv, pipe);
3397
3398         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3399            for train result */
3400         reg = FDI_RX_IMR(pipe);
3401         temp = I915_READ(reg);
3402         temp &= ~FDI_RX_SYMBOL_LOCK;
3403         temp &= ~FDI_RX_BIT_LOCK;
3404         I915_WRITE(reg, temp);
3405         I915_READ(reg);
3406         udelay(150);
3407
3408         /* enable CPU FDI TX and PCH FDI RX */
3409         reg = FDI_TX_CTL(pipe);
3410         temp = I915_READ(reg);
3411         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3412         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3413         temp &= ~FDI_LINK_TRAIN_NONE;
3414         temp |= FDI_LINK_TRAIN_PATTERN_1;
3415         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3416
3417         reg = FDI_RX_CTL(pipe);
3418         temp = I915_READ(reg);
3419         temp &= ~FDI_LINK_TRAIN_NONE;
3420         temp |= FDI_LINK_TRAIN_PATTERN_1;
3421         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3422
3423         POSTING_READ(reg);
3424         udelay(150);
3425
3426         /* Ironlake workaround, enable clock pointer after FDI enable*/
3427         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3428         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3429                    FDI_RX_PHASE_SYNC_POINTER_EN);
3430
3431         reg = FDI_RX_IIR(pipe);
3432         for (tries = 0; tries < 5; tries++) {
3433                 temp = I915_READ(reg);
3434                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3435
3436                 if ((temp & FDI_RX_BIT_LOCK)) {
3437                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3438                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3439                         break;
3440                 }
3441         }
3442         if (tries == 5)
3443                 DRM_ERROR("FDI train 1 fail!\n");
3444
3445         /* Train 2 */
3446         reg = FDI_TX_CTL(pipe);
3447         temp = I915_READ(reg);
3448         temp &= ~FDI_LINK_TRAIN_NONE;
3449         temp |= FDI_LINK_TRAIN_PATTERN_2;
3450         I915_WRITE(reg, temp);
3451
3452         reg = FDI_RX_CTL(pipe);
3453         temp = I915_READ(reg);
3454         temp &= ~FDI_LINK_TRAIN_NONE;
3455         temp |= FDI_LINK_TRAIN_PATTERN_2;
3456         I915_WRITE(reg, temp);
3457
3458         POSTING_READ(reg);
3459         udelay(150);
3460
3461         reg = FDI_RX_IIR(pipe);
3462         for (tries = 0; tries < 5; tries++) {
3463                 temp = I915_READ(reg);
3464                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3465
3466                 if (temp & FDI_RX_SYMBOL_LOCK) {
3467                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3468                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3469                         break;
3470                 }
3471         }
3472         if (tries == 5)
3473                 DRM_ERROR("FDI train 2 fail!\n");
3474
3475         DRM_DEBUG_KMS("FDI train done\n");
3476
3477 }
3478
3479 static const int snb_b_fdi_train_param[] = {
3480         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3481         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3482         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3483         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3484 };
3485
3486 /* The FDI link training functions for SNB/Cougarpoint. */
3487 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3488 {
3489         struct drm_device *dev = crtc->dev;
3490         struct drm_i915_private *dev_priv = dev->dev_private;
3491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3492         int pipe = intel_crtc->pipe;
3493         u32 reg, temp, i, retry;
3494
3495         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3496            for train result */
3497         reg = FDI_RX_IMR(pipe);
3498         temp = I915_READ(reg);
3499         temp &= ~FDI_RX_SYMBOL_LOCK;
3500         temp &= ~FDI_RX_BIT_LOCK;
3501         I915_WRITE(reg, temp);
3502
3503         POSTING_READ(reg);
3504         udelay(150);
3505
3506         /* enable CPU FDI TX and PCH FDI RX */
3507         reg = FDI_TX_CTL(pipe);
3508         temp = I915_READ(reg);
3509         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3510         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3511         temp &= ~FDI_LINK_TRAIN_NONE;
3512         temp |= FDI_LINK_TRAIN_PATTERN_1;
3513         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3514         /* SNB-B */
3515         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3516         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3517
3518         I915_WRITE(FDI_RX_MISC(pipe),
3519                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3520
3521         reg = FDI_RX_CTL(pipe);
3522         temp = I915_READ(reg);
3523         if (HAS_PCH_CPT(dev)) {
3524                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3525                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3526         } else {
3527                 temp &= ~FDI_LINK_TRAIN_NONE;
3528                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3529         }
3530         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3531
3532         POSTING_READ(reg);
3533         udelay(150);
3534
3535         for (i = 0; i < 4; i++) {
3536                 reg = FDI_TX_CTL(pipe);
3537                 temp = I915_READ(reg);
3538                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3539                 temp |= snb_b_fdi_train_param[i];
3540                 I915_WRITE(reg, temp);
3541
3542                 POSTING_READ(reg);
3543                 udelay(500);
3544
3545                 for (retry = 0; retry < 5; retry++) {
3546                         reg = FDI_RX_IIR(pipe);
3547                         temp = I915_READ(reg);
3548                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3549                         if (temp & FDI_RX_BIT_LOCK) {
3550                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3551                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3552                                 break;
3553                         }
3554                         udelay(50);
3555                 }
3556                 if (retry < 5)
3557                         break;
3558         }
3559         if (i == 4)
3560                 DRM_ERROR("FDI train 1 fail!\n");
3561
3562         /* Train 2 */
3563         reg = FDI_TX_CTL(pipe);
3564         temp = I915_READ(reg);
3565         temp &= ~FDI_LINK_TRAIN_NONE;
3566         temp |= FDI_LINK_TRAIN_PATTERN_2;
3567         if (IS_GEN6(dev)) {
3568                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3569                 /* SNB-B */
3570                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3571         }
3572         I915_WRITE(reg, temp);
3573
3574         reg = FDI_RX_CTL(pipe);
3575         temp = I915_READ(reg);
3576         if (HAS_PCH_CPT(dev)) {
3577                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3578                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3579         } else {
3580                 temp &= ~FDI_LINK_TRAIN_NONE;
3581                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3582         }
3583         I915_WRITE(reg, temp);
3584
3585         POSTING_READ(reg);
3586         udelay(150);
3587
3588         for (i = 0; i < 4; i++) {
3589                 reg = FDI_TX_CTL(pipe);
3590                 temp = I915_READ(reg);
3591                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3592                 temp |= snb_b_fdi_train_param[i];
3593                 I915_WRITE(reg, temp);
3594
3595                 POSTING_READ(reg);
3596                 udelay(500);
3597
3598                 for (retry = 0; retry < 5; retry++) {
3599                         reg = FDI_RX_IIR(pipe);
3600                         temp = I915_READ(reg);
3601                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3602                         if (temp & FDI_RX_SYMBOL_LOCK) {
3603                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3604                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3605                                 break;
3606                         }
3607                         udelay(50);
3608                 }
3609                 if (retry < 5)
3610                         break;
3611         }
3612         if (i == 4)
3613                 DRM_ERROR("FDI train 2 fail!\n");
3614
3615         DRM_DEBUG_KMS("FDI train done.\n");
3616 }
3617
3618 /* Manual link training for Ivy Bridge A0 parts */
3619 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3620 {
3621         struct drm_device *dev = crtc->dev;
3622         struct drm_i915_private *dev_priv = dev->dev_private;
3623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3624         int pipe = intel_crtc->pipe;
3625         u32 reg, temp, i, j;
3626
3627         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3628            for train result */
3629         reg = FDI_RX_IMR(pipe);
3630         temp = I915_READ(reg);
3631         temp &= ~FDI_RX_SYMBOL_LOCK;
3632         temp &= ~FDI_RX_BIT_LOCK;
3633         I915_WRITE(reg, temp);
3634
3635         POSTING_READ(reg);
3636         udelay(150);
3637
3638         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3639                       I915_READ(FDI_RX_IIR(pipe)));
3640
3641         /* Try each vswing and preemphasis setting twice before moving on */
3642         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3643                 /* disable first in case we need to retry */
3644                 reg = FDI_TX_CTL(pipe);
3645                 temp = I915_READ(reg);
3646                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3647                 temp &= ~FDI_TX_ENABLE;
3648                 I915_WRITE(reg, temp);
3649
3650                 reg = FDI_RX_CTL(pipe);
3651                 temp = I915_READ(reg);
3652                 temp &= ~FDI_LINK_TRAIN_AUTO;
3653                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3654                 temp &= ~FDI_RX_ENABLE;
3655                 I915_WRITE(reg, temp);
3656
3657                 /* enable CPU FDI TX and PCH FDI RX */
3658                 reg = FDI_TX_CTL(pipe);
3659                 temp = I915_READ(reg);
3660                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3661                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3662                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3663                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3664                 temp |= snb_b_fdi_train_param[j/2];
3665                 temp |= FDI_COMPOSITE_SYNC;
3666                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3667
3668                 I915_WRITE(FDI_RX_MISC(pipe),
3669                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3670
3671                 reg = FDI_RX_CTL(pipe);
3672                 temp = I915_READ(reg);
3673                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3674                 temp |= FDI_COMPOSITE_SYNC;
3675                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3676
3677                 POSTING_READ(reg);
3678                 udelay(1); /* should be 0.5us */
3679
3680                 for (i = 0; i < 4; i++) {
3681                         reg = FDI_RX_IIR(pipe);
3682                         temp = I915_READ(reg);
3683                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3684
3685                         if (temp & FDI_RX_BIT_LOCK ||
3686                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3687                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3688                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3689                                               i);
3690                                 break;
3691                         }
3692                         udelay(1); /* should be 0.5us */
3693                 }
3694                 if (i == 4) {
3695                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3696                         continue;
3697                 }
3698
3699                 /* Train 2 */
3700                 reg = FDI_TX_CTL(pipe);
3701                 temp = I915_READ(reg);
3702                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3703                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3704                 I915_WRITE(reg, temp);
3705
3706                 reg = FDI_RX_CTL(pipe);
3707                 temp = I915_READ(reg);
3708                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3709                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3710                 I915_WRITE(reg, temp);
3711
3712                 POSTING_READ(reg);
3713                 udelay(2); /* should be 1.5us */
3714
3715                 for (i = 0; i < 4; i++) {
3716                         reg = FDI_RX_IIR(pipe);
3717                         temp = I915_READ(reg);
3718                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3719
3720                         if (temp & FDI_RX_SYMBOL_LOCK ||
3721                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3722                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3723                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3724                                               i);
3725                                 goto train_done;
3726                         }
3727                         udelay(2); /* should be 1.5us */
3728                 }
3729                 if (i == 4)
3730                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3731         }
3732
3733 train_done:
3734         DRM_DEBUG_KMS("FDI train done.\n");
3735 }
3736
3737 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3738 {
3739         struct drm_device *dev = intel_crtc->base.dev;
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         int pipe = intel_crtc->pipe;
3742         u32 reg, temp;
3743
3744
3745         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3746         reg = FDI_RX_CTL(pipe);
3747         temp = I915_READ(reg);
3748         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3749         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3750         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3751         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3752
3753         POSTING_READ(reg);
3754         udelay(200);
3755
3756         /* Switch from Rawclk to PCDclk */
3757         temp = I915_READ(reg);
3758         I915_WRITE(reg, temp | FDI_PCDCLK);
3759
3760         POSTING_READ(reg);
3761         udelay(200);
3762
3763         /* Enable CPU FDI TX PLL, always on for Ironlake */
3764         reg = FDI_TX_CTL(pipe);
3765         temp = I915_READ(reg);
3766         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3767                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3768
3769                 POSTING_READ(reg);
3770                 udelay(100);
3771         }
3772 }
3773
3774 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3775 {
3776         struct drm_device *dev = intel_crtc->base.dev;
3777         struct drm_i915_private *dev_priv = dev->dev_private;
3778         int pipe = intel_crtc->pipe;
3779         u32 reg, temp;
3780
3781         /* Switch from PCDclk to Rawclk */
3782         reg = FDI_RX_CTL(pipe);
3783         temp = I915_READ(reg);
3784         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3785
3786         /* Disable CPU FDI TX PLL */
3787         reg = FDI_TX_CTL(pipe);
3788         temp = I915_READ(reg);
3789         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3790
3791         POSTING_READ(reg);
3792         udelay(100);
3793
3794         reg = FDI_RX_CTL(pipe);
3795         temp = I915_READ(reg);
3796         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3797
3798         /* Wait for the clocks to turn off. */
3799         POSTING_READ(reg);
3800         udelay(100);
3801 }
3802
3803 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3804 {
3805         struct drm_device *dev = crtc->dev;
3806         struct drm_i915_private *dev_priv = dev->dev_private;
3807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3808         int pipe = intel_crtc->pipe;
3809         u32 reg, temp;
3810
3811         /* disable CPU FDI tx and PCH FDI rx */
3812         reg = FDI_TX_CTL(pipe);
3813         temp = I915_READ(reg);
3814         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3815         POSTING_READ(reg);
3816
3817         reg = FDI_RX_CTL(pipe);
3818         temp = I915_READ(reg);
3819         temp &= ~(0x7 << 16);
3820         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3821         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3822
3823         POSTING_READ(reg);
3824         udelay(100);
3825
3826         /* Ironlake workaround, disable clock pointer after downing FDI */
3827         if (HAS_PCH_IBX(dev))
3828                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3829
3830         /* still set train pattern 1 */
3831         reg = FDI_TX_CTL(pipe);
3832         temp = I915_READ(reg);
3833         temp &= ~FDI_LINK_TRAIN_NONE;
3834         temp |= FDI_LINK_TRAIN_PATTERN_1;
3835         I915_WRITE(reg, temp);
3836
3837         reg = FDI_RX_CTL(pipe);
3838         temp = I915_READ(reg);
3839         if (HAS_PCH_CPT(dev)) {
3840                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3841                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3842         } else {
3843                 temp &= ~FDI_LINK_TRAIN_NONE;
3844                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3845         }
3846         /* BPC in FDI rx is consistent with that in PIPECONF */
3847         temp &= ~(0x07 << 16);
3848         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3849         I915_WRITE(reg, temp);
3850
3851         POSTING_READ(reg);
3852         udelay(100);
3853 }
3854
3855 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3856 {
3857         struct intel_crtc *crtc;
3858
3859         /* Note that we don't need to be called with mode_config.lock here
3860          * as our list of CRTC objects is static for the lifetime of the
3861          * device and so cannot disappear as we iterate. Similarly, we can
3862          * happily treat the predicates as racy, atomic checks as userspace
3863          * cannot claim and pin a new fb without at least acquring the
3864          * struct_mutex and so serialising with us.
3865          */
3866         for_each_intel_crtc(dev, crtc) {
3867                 if (atomic_read(&crtc->unpin_work_count) == 0)
3868                         continue;
3869
3870                 if (crtc->unpin_work)
3871                         intel_wait_for_vblank(dev, crtc->pipe);
3872
3873                 return true;
3874         }
3875
3876         return false;
3877 }
3878
3879 static void page_flip_completed(struct intel_crtc *intel_crtc)
3880 {
3881         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3882         struct intel_unpin_work *work = intel_crtc->unpin_work;
3883
3884         /* ensure that the unpin work is consistent wrt ->pending. */
3885         smp_rmb();
3886         intel_crtc->unpin_work = NULL;
3887
3888         if (work->event)
3889                 drm_send_vblank_event(intel_crtc->base.dev,
3890                                       intel_crtc->pipe,
3891                                       work->event);
3892
3893         drm_crtc_vblank_put(&intel_crtc->base);
3894
3895         wake_up_all(&dev_priv->pending_flip_queue);
3896         queue_work(dev_priv->wq, &work->work);
3897
3898         trace_i915_flip_complete(intel_crtc->plane,
3899                                  work->pending_flip_obj);
3900 }
3901
3902 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3903 {
3904         struct drm_device *dev = crtc->dev;
3905         struct drm_i915_private *dev_priv = dev->dev_private;
3906
3907         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3908         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3909                                        !intel_crtc_has_pending_flip(crtc),
3910                                        60*HZ) == 0)) {
3911                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3912
3913                 spin_lock_irq(&dev->event_lock);
3914                 if (intel_crtc->unpin_work) {
3915                         WARN_ONCE(1, "Removing stuck page flip\n");
3916                         page_flip_completed(intel_crtc);
3917                 }
3918                 spin_unlock_irq(&dev->event_lock);
3919         }
3920
3921         if (crtc->primary->fb) {
3922                 mutex_lock(&dev->struct_mutex);
3923                 intel_finish_fb(crtc->primary->fb);
3924                 mutex_unlock(&dev->struct_mutex);
3925         }
3926 }
3927
3928 /* Program iCLKIP clock to the desired frequency */
3929 static void lpt_program_iclkip(struct drm_crtc *crtc)
3930 {
3931         struct drm_device *dev = crtc->dev;
3932         struct drm_i915_private *dev_priv = dev->dev_private;
3933         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3934         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3935         u32 temp;
3936
3937         mutex_lock(&dev_priv->sb_lock);
3938
3939         /* It is necessary to ungate the pixclk gate prior to programming
3940          * the divisors, and gate it back when it is done.
3941          */
3942         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3943
3944         /* Disable SSCCTL */
3945         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3946                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3947                                 SBI_SSCCTL_DISABLE,
3948                         SBI_ICLK);
3949
3950         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3951         if (clock == 20000) {
3952                 auxdiv = 1;
3953                 divsel = 0x41;
3954                 phaseinc = 0x20;
3955         } else {
3956                 /* The iCLK virtual clock root frequency is in MHz,
3957                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3958                  * divisors, it is necessary to divide one by another, so we
3959                  * convert the virtual clock precision to KHz here for higher
3960                  * precision.
3961                  */
3962                 u32 iclk_virtual_root_freq = 172800 * 1000;
3963                 u32 iclk_pi_range = 64;
3964                 u32 desired_divisor, msb_divisor_value, pi_value;
3965
3966                 desired_divisor = (iclk_virtual_root_freq / clock);
3967                 msb_divisor_value = desired_divisor / iclk_pi_range;
3968                 pi_value = desired_divisor % iclk_pi_range;
3969
3970                 auxdiv = 0;
3971                 divsel = msb_divisor_value - 2;
3972                 phaseinc = pi_value;
3973         }
3974
3975         /* This should not happen with any sane values */
3976         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3977                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3978         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3979                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3980
3981         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3982                         clock,
3983                         auxdiv,
3984                         divsel,
3985                         phasedir,
3986                         phaseinc);
3987
3988         /* Program SSCDIVINTPHASE6 */
3989         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3990         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3991         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3992         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3993         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3994         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3995         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3996         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3997
3998         /* Program SSCAUXDIV */
3999         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4000         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4001         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4002         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4003
4004         /* Enable modulator and associated divider */
4005         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4006         temp &= ~SBI_SSCCTL_DISABLE;
4007         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4008
4009         /* Wait for initialization time */
4010         udelay(24);
4011
4012         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4013
4014         mutex_unlock(&dev_priv->sb_lock);
4015 }
4016
4017 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4018                                                 enum pipe pch_transcoder)
4019 {
4020         struct drm_device *dev = crtc->base.dev;
4021         struct drm_i915_private *dev_priv = dev->dev_private;
4022         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4023
4024         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4025                    I915_READ(HTOTAL(cpu_transcoder)));
4026         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4027                    I915_READ(HBLANK(cpu_transcoder)));
4028         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4029                    I915_READ(HSYNC(cpu_transcoder)));
4030
4031         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4032                    I915_READ(VTOTAL(cpu_transcoder)));
4033         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4034                    I915_READ(VBLANK(cpu_transcoder)));
4035         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4036                    I915_READ(VSYNC(cpu_transcoder)));
4037         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4038                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4039 }
4040
4041 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4042 {
4043         struct drm_i915_private *dev_priv = dev->dev_private;
4044         uint32_t temp;
4045
4046         temp = I915_READ(SOUTH_CHICKEN1);
4047         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4048                 return;
4049
4050         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4051         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4052
4053         temp &= ~FDI_BC_BIFURCATION_SELECT;
4054         if (enable)
4055                 temp |= FDI_BC_BIFURCATION_SELECT;
4056
4057         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4058         I915_WRITE(SOUTH_CHICKEN1, temp);
4059         POSTING_READ(SOUTH_CHICKEN1);
4060 }
4061
4062 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4063 {
4064         struct drm_device *dev = intel_crtc->base.dev;
4065
4066         switch (intel_crtc->pipe) {
4067         case PIPE_A:
4068                 break;
4069         case PIPE_B:
4070                 if (intel_crtc->config->fdi_lanes > 2)
4071                         cpt_set_fdi_bc_bifurcation(dev, false);
4072                 else
4073                         cpt_set_fdi_bc_bifurcation(dev, true);
4074
4075                 break;
4076         case PIPE_C:
4077                 cpt_set_fdi_bc_bifurcation(dev, true);
4078
4079                 break;
4080         default:
4081                 BUG();
4082         }
4083 }
4084
4085 /*
4086  * Enable PCH resources required for PCH ports:
4087  *   - PCH PLLs
4088  *   - FDI training & RX/TX
4089  *   - update transcoder timings
4090  *   - DP transcoding bits
4091  *   - transcoder
4092  */
4093 static void ironlake_pch_enable(struct drm_crtc *crtc)
4094 {
4095         struct drm_device *dev = crtc->dev;
4096         struct drm_i915_private *dev_priv = dev->dev_private;
4097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4098         int pipe = intel_crtc->pipe;
4099         u32 reg, temp;
4100
4101         assert_pch_transcoder_disabled(dev_priv, pipe);
4102
4103         if (IS_IVYBRIDGE(dev))
4104                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4105
4106         /* Write the TU size bits before fdi link training, so that error
4107          * detection works. */
4108         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4109                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4110
4111         /* For PCH output, training FDI link */
4112         dev_priv->display.fdi_link_train(crtc);
4113
4114         /* We need to program the right clock selection before writing the pixel
4115          * mutliplier into the DPLL. */
4116         if (HAS_PCH_CPT(dev)) {
4117                 u32 sel;
4118
4119                 temp = I915_READ(PCH_DPLL_SEL);
4120                 temp |= TRANS_DPLL_ENABLE(pipe);
4121                 sel = TRANS_DPLLB_SEL(pipe);
4122                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4123                         temp |= sel;
4124                 else
4125                         temp &= ~sel;
4126                 I915_WRITE(PCH_DPLL_SEL, temp);
4127         }
4128
4129         /* XXX: pch pll's can be enabled any time before we enable the PCH
4130          * transcoder, and we actually should do this to not upset any PCH
4131          * transcoder that already use the clock when we share it.
4132          *
4133          * Note that enable_shared_dpll tries to do the right thing, but
4134          * get_shared_dpll unconditionally resets the pll - we need that to have
4135          * the right LVDS enable sequence. */
4136         intel_enable_shared_dpll(intel_crtc);
4137
4138         /* set transcoder timing, panel must allow it */
4139         assert_panel_unlocked(dev_priv, pipe);
4140         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4141
4142         intel_fdi_normal_train(crtc);
4143
4144         /* For PCH DP, enable TRANS_DP_CTL */
4145         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4146                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4147                 reg = TRANS_DP_CTL(pipe);
4148                 temp = I915_READ(reg);
4149                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4150                           TRANS_DP_SYNC_MASK |
4151                           TRANS_DP_BPC_MASK);
4152                 temp |= TRANS_DP_OUTPUT_ENABLE;
4153                 temp |= bpc << 9; /* same format but at 11:9 */
4154
4155                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4156                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4157                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4158                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4159
4160                 switch (intel_trans_dp_port_sel(crtc)) {
4161                 case PCH_DP_B:
4162                         temp |= TRANS_DP_PORT_SEL_B;
4163                         break;
4164                 case PCH_DP_C:
4165                         temp |= TRANS_DP_PORT_SEL_C;
4166                         break;
4167                 case PCH_DP_D:
4168                         temp |= TRANS_DP_PORT_SEL_D;
4169                         break;
4170                 default:
4171                         BUG();
4172                 }
4173
4174                 I915_WRITE(reg, temp);
4175         }
4176
4177         ironlake_enable_pch_transcoder(dev_priv, pipe);
4178 }
4179
4180 static void lpt_pch_enable(struct drm_crtc *crtc)
4181 {
4182         struct drm_device *dev = crtc->dev;
4183         struct drm_i915_private *dev_priv = dev->dev_private;
4184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4185         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4186
4187         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4188
4189         lpt_program_iclkip(crtc);
4190
4191         /* Set transcoder timing. */
4192         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4193
4194         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4195 }
4196
4197 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4198                                                 struct intel_crtc_state *crtc_state)
4199 {
4200         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4201         struct intel_shared_dpll *pll;
4202         struct intel_shared_dpll_config *shared_dpll;
4203         enum intel_dpll_id i;
4204
4205         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4206
4207         if (HAS_PCH_IBX(dev_priv->dev)) {
4208                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4209                 i = (enum intel_dpll_id) crtc->pipe;
4210                 pll = &dev_priv->shared_dplls[i];
4211
4212                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4213                               crtc->base.base.id, pll->name);
4214
4215                 WARN_ON(shared_dpll[i].crtc_mask);
4216
4217                 goto found;
4218         }
4219
4220         if (IS_BROXTON(dev_priv->dev)) {
4221                 /* PLL is attached to port in bxt */
4222                 struct intel_encoder *encoder;
4223                 struct intel_digital_port *intel_dig_port;
4224
4225                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4226                 if (WARN_ON(!encoder))
4227                         return NULL;
4228
4229                 intel_dig_port = enc_to_dig_port(&encoder->base);
4230                 /* 1:1 mapping between ports and PLLs */
4231                 i = (enum intel_dpll_id)intel_dig_port->port;
4232                 pll = &dev_priv->shared_dplls[i];
4233                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4234                         crtc->base.base.id, pll->name);
4235                 WARN_ON(shared_dpll[i].crtc_mask);
4236
4237                 goto found;
4238         }
4239
4240         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4241                 pll = &dev_priv->shared_dplls[i];
4242
4243                 /* Only want to check enabled timings first */
4244                 if (shared_dpll[i].crtc_mask == 0)
4245                         continue;
4246
4247                 if (memcmp(&crtc_state->dpll_hw_state,
4248                            &shared_dpll[i].hw_state,
4249                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4250                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4251                                       crtc->base.base.id, pll->name,
4252                                       shared_dpll[i].crtc_mask,
4253                                       pll->active);
4254                         goto found;
4255                 }
4256         }
4257
4258         /* Ok no matching timings, maybe there's a free one? */
4259         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4260                 pll = &dev_priv->shared_dplls[i];
4261                 if (shared_dpll[i].crtc_mask == 0) {
4262                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4263                                       crtc->base.base.id, pll->name);
4264                         goto found;
4265                 }
4266         }
4267
4268         return NULL;
4269
4270 found:
4271         if (shared_dpll[i].crtc_mask == 0)
4272                 shared_dpll[i].hw_state =
4273                         crtc_state->dpll_hw_state;
4274
4275         crtc_state->shared_dpll = i;
4276         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4277                          pipe_name(crtc->pipe));
4278
4279         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4280
4281         return pll;
4282 }
4283
4284 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4285 {
4286         struct drm_i915_private *dev_priv = to_i915(state->dev);
4287         struct intel_shared_dpll_config *shared_dpll;
4288         struct intel_shared_dpll *pll;
4289         enum intel_dpll_id i;
4290
4291         if (!to_intel_atomic_state(state)->dpll_set)
4292                 return;
4293
4294         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4295         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4296                 pll = &dev_priv->shared_dplls[i];
4297                 pll->config = shared_dpll[i];
4298         }
4299 }
4300
4301 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4302 {
4303         struct drm_i915_private *dev_priv = dev->dev_private;
4304         int dslreg = PIPEDSL(pipe);
4305         u32 temp;
4306
4307         temp = I915_READ(dslreg);
4308         udelay(500);
4309         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4310                 if (wait_for(I915_READ(dslreg) != temp, 5))
4311                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4312         }
4313 }
4314
4315 static int
4316 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4317                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4318                   int src_w, int src_h, int dst_w, int dst_h)
4319 {
4320         struct intel_crtc_scaler_state *scaler_state =
4321                 &crtc_state->scaler_state;
4322         struct intel_crtc *intel_crtc =
4323                 to_intel_crtc(crtc_state->base.crtc);
4324         int need_scaling;
4325
4326         need_scaling = intel_rotation_90_or_270(rotation) ?
4327                 (src_h != dst_w || src_w != dst_h):
4328                 (src_w != dst_w || src_h != dst_h);
4329
4330         /*
4331          * if plane is being disabled or scaler is no more required or force detach
4332          *  - free scaler binded to this plane/crtc
4333          *  - in order to do this, update crtc->scaler_usage
4334          *
4335          * Here scaler state in crtc_state is set free so that
4336          * scaler can be assigned to other user. Actual register
4337          * update to free the scaler is done in plane/panel-fit programming.
4338          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4339          */
4340         if (force_detach || !need_scaling) {
4341                 if (*scaler_id >= 0) {
4342                         scaler_state->scaler_users &= ~(1 << scaler_user);
4343                         scaler_state->scalers[*scaler_id].in_use = 0;
4344
4345                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4346                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4347                                 intel_crtc->pipe, scaler_user, *scaler_id,
4348                                 scaler_state->scaler_users);
4349                         *scaler_id = -1;
4350                 }
4351                 return 0;
4352         }
4353
4354         /* range checks */
4355         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4356                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4357
4358                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4359                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4360                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4361                         "size is out of scaler range\n",
4362                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4363                 return -EINVAL;
4364         }
4365
4366         /* mark this plane as a scaler user in crtc_state */
4367         scaler_state->scaler_users |= (1 << scaler_user);
4368         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4369                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4370                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4371                 scaler_state->scaler_users);
4372
4373         return 0;
4374 }
4375
4376 /**
4377  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4378  *
4379  * @state: crtc's scaler state
4380  *
4381  * Return
4382  *     0 - scaler_usage updated successfully
4383  *    error - requested scaling cannot be supported or other error condition
4384  */
4385 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4386 {
4387         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4388         struct drm_display_mode *adjusted_mode =
4389                 &state->base.adjusted_mode;
4390
4391         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4392                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4393
4394         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4395                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4396                 state->pipe_src_w, state->pipe_src_h,
4397                 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4398 }
4399
4400 /**
4401  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4402  *
4403  * @state: crtc's scaler state
4404  * @plane_state: atomic plane state to update
4405  *
4406  * Return
4407  *     0 - scaler_usage updated successfully
4408  *    error - requested scaling cannot be supported or other error condition
4409  */
4410 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4411                                    struct intel_plane_state *plane_state)
4412 {
4413
4414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4415         struct intel_plane *intel_plane =
4416                 to_intel_plane(plane_state->base.plane);
4417         struct drm_framebuffer *fb = plane_state->base.fb;
4418         int ret;
4419
4420         bool force_detach = !fb || !plane_state->visible;
4421
4422         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4423                       intel_plane->base.base.id, intel_crtc->pipe,
4424                       drm_plane_index(&intel_plane->base));
4425
4426         ret = skl_update_scaler(crtc_state, force_detach,
4427                                 drm_plane_index(&intel_plane->base),
4428                                 &plane_state->scaler_id,
4429                                 plane_state->base.rotation,
4430                                 drm_rect_width(&plane_state->src) >> 16,
4431                                 drm_rect_height(&plane_state->src) >> 16,
4432                                 drm_rect_width(&plane_state->dst),
4433                                 drm_rect_height(&plane_state->dst));
4434
4435         if (ret || plane_state->scaler_id < 0)
4436                 return ret;
4437
4438         /* check colorkey */
4439         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4440                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4441                               intel_plane->base.base.id);
4442                 return -EINVAL;
4443         }
4444
4445         /* Check src format */
4446         switch (fb->pixel_format) {
4447         case DRM_FORMAT_RGB565:
4448         case DRM_FORMAT_XBGR8888:
4449         case DRM_FORMAT_XRGB8888:
4450         case DRM_FORMAT_ABGR8888:
4451         case DRM_FORMAT_ARGB8888:
4452         case DRM_FORMAT_XRGB2101010:
4453         case DRM_FORMAT_XBGR2101010:
4454         case DRM_FORMAT_YUYV:
4455         case DRM_FORMAT_YVYU:
4456         case DRM_FORMAT_UYVY:
4457         case DRM_FORMAT_VYUY:
4458                 break;
4459         default:
4460                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4461                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4462                 return -EINVAL;
4463         }
4464
4465         return 0;
4466 }
4467
4468 static void skylake_scaler_disable(struct intel_crtc *crtc)
4469 {
4470         int i;
4471
4472         for (i = 0; i < crtc->num_scalers; i++)
4473                 skl_detach_scaler(crtc, i);
4474 }
4475
4476 static void skylake_pfit_enable(struct intel_crtc *crtc)
4477 {
4478         struct drm_device *dev = crtc->base.dev;
4479         struct drm_i915_private *dev_priv = dev->dev_private;
4480         int pipe = crtc->pipe;
4481         struct intel_crtc_scaler_state *scaler_state =
4482                 &crtc->config->scaler_state;
4483
4484         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4485
4486         if (crtc->config->pch_pfit.enabled) {
4487                 int id;
4488
4489                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4490                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4491                         return;
4492                 }
4493
4494                 id = scaler_state->scaler_id;
4495                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4496                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4497                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4498                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4499
4500                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4501         }
4502 }
4503
4504 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4505 {
4506         struct drm_device *dev = crtc->base.dev;
4507         struct drm_i915_private *dev_priv = dev->dev_private;
4508         int pipe = crtc->pipe;
4509
4510         if (crtc->config->pch_pfit.enabled) {
4511                 /* Force use of hard-coded filter coefficients
4512                  * as some pre-programmed values are broken,
4513                  * e.g. x201.
4514                  */
4515                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4516                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4517                                                  PF_PIPE_SEL_IVB(pipe));
4518                 else
4519                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4520                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4521                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4522         }
4523 }
4524
4525 void hsw_enable_ips(struct intel_crtc *crtc)
4526 {
4527         struct drm_device *dev = crtc->base.dev;
4528         struct drm_i915_private *dev_priv = dev->dev_private;
4529
4530         if (!crtc->config->ips_enabled)
4531                 return;
4532
4533         /* We can only enable IPS after we enable a plane and wait for a vblank */
4534         intel_wait_for_vblank(dev, crtc->pipe);
4535
4536         assert_plane_enabled(dev_priv, crtc->plane);
4537         if (IS_BROADWELL(dev)) {
4538                 mutex_lock(&dev_priv->rps.hw_lock);
4539                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4540                 mutex_unlock(&dev_priv->rps.hw_lock);
4541                 /* Quoting Art Runyan: "its not safe to expect any particular
4542                  * value in IPS_CTL bit 31 after enabling IPS through the
4543                  * mailbox." Moreover, the mailbox may return a bogus state,
4544                  * so we need to just enable it and continue on.
4545                  */
4546         } else {
4547                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4548                 /* The bit only becomes 1 in the next vblank, so this wait here
4549                  * is essentially intel_wait_for_vblank. If we don't have this
4550                  * and don't wait for vblanks until the end of crtc_enable, then
4551                  * the HW state readout code will complain that the expected
4552                  * IPS_CTL value is not the one we read. */
4553                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4554                         DRM_ERROR("Timed out waiting for IPS enable\n");
4555         }
4556 }
4557
4558 void hsw_disable_ips(struct intel_crtc *crtc)
4559 {
4560         struct drm_device *dev = crtc->base.dev;
4561         struct drm_i915_private *dev_priv = dev->dev_private;
4562
4563         if (!crtc->config->ips_enabled)
4564                 return;
4565
4566         assert_plane_enabled(dev_priv, crtc->plane);
4567         if (IS_BROADWELL(dev)) {
4568                 mutex_lock(&dev_priv->rps.hw_lock);
4569                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4570                 mutex_unlock(&dev_priv->rps.hw_lock);
4571                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4572                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4573                         DRM_ERROR("Timed out waiting for IPS disable\n");
4574         } else {
4575                 I915_WRITE(IPS_CTL, 0);
4576                 POSTING_READ(IPS_CTL);
4577         }
4578
4579         /* We need to wait for a vblank before we can disable the plane. */
4580         intel_wait_for_vblank(dev, crtc->pipe);
4581 }
4582
4583 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4584 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4585 {
4586         struct drm_device *dev = crtc->dev;
4587         struct drm_i915_private *dev_priv = dev->dev_private;
4588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4589         enum pipe pipe = intel_crtc->pipe;
4590         int palreg = PALETTE(pipe);
4591         int i;
4592         bool reenable_ips = false;
4593
4594         /* The clocks have to be on to load the palette. */
4595         if (!crtc->state->active)
4596                 return;
4597
4598         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4599                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4600                         assert_dsi_pll_enabled(dev_priv);
4601                 else
4602                         assert_pll_enabled(dev_priv, pipe);
4603         }
4604
4605         /* use legacy palette for Ironlake */
4606         if (!HAS_GMCH_DISPLAY(dev))
4607                 palreg = LGC_PALETTE(pipe);
4608
4609         /* Workaround : Do not read or write the pipe palette/gamma data while
4610          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4611          */
4612         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4613             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4614              GAMMA_MODE_MODE_SPLIT)) {
4615                 hsw_disable_ips(intel_crtc);
4616                 reenable_ips = true;
4617         }
4618
4619         for (i = 0; i < 256; i++) {
4620                 I915_WRITE(palreg + 4 * i,
4621                            (intel_crtc->lut_r[i] << 16) |
4622                            (intel_crtc->lut_g[i] << 8) |
4623                            intel_crtc->lut_b[i]);
4624         }
4625
4626         if (reenable_ips)
4627                 hsw_enable_ips(intel_crtc);
4628 }
4629
4630 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4631 {
4632         if (intel_crtc->overlay) {
4633                 struct drm_device *dev = intel_crtc->base.dev;
4634                 struct drm_i915_private *dev_priv = dev->dev_private;
4635
4636                 mutex_lock(&dev->struct_mutex);
4637                 dev_priv->mm.interruptible = false;
4638                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4639                 dev_priv->mm.interruptible = true;
4640                 mutex_unlock(&dev->struct_mutex);
4641         }
4642
4643         /* Let userspace switch the overlay on again. In most cases userspace
4644          * has to recompute where to put it anyway.
4645          */
4646 }
4647
4648 /**
4649  * intel_post_enable_primary - Perform operations after enabling primary plane
4650  * @crtc: the CRTC whose primary plane was just enabled
4651  *
4652  * Performs potentially sleeping operations that must be done after the primary
4653  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4654  * called due to an explicit primary plane update, or due to an implicit
4655  * re-enable that is caused when a sprite plane is updated to no longer
4656  * completely hide the primary plane.
4657  */
4658 static void
4659 intel_post_enable_primary(struct drm_crtc *crtc)
4660 {
4661         struct drm_device *dev = crtc->dev;
4662         struct drm_i915_private *dev_priv = dev->dev_private;
4663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4664         int pipe = intel_crtc->pipe;
4665
4666         /*
4667          * BDW signals flip done immediately if the plane
4668          * is disabled, even if the plane enable is already
4669          * armed to occur at the next vblank :(
4670          */
4671         if (IS_BROADWELL(dev))
4672                 intel_wait_for_vblank(dev, pipe);
4673
4674         /*
4675          * FIXME IPS should be fine as long as one plane is
4676          * enabled, but in practice it seems to have problems
4677          * when going from primary only to sprite only and vice
4678          * versa.
4679          */
4680         hsw_enable_ips(intel_crtc);
4681
4682         /*
4683          * Gen2 reports pipe underruns whenever all planes are disabled.
4684          * So don't enable underrun reporting before at least some planes
4685          * are enabled.
4686          * FIXME: Need to fix the logic to work when we turn off all planes
4687          * but leave the pipe running.
4688          */
4689         if (IS_GEN2(dev))
4690                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4691
4692         /* Underruns don't raise interrupts, so check manually. */
4693         if (HAS_GMCH_DISPLAY(dev))
4694                 i9xx_check_fifo_underruns(dev_priv);
4695 }
4696
4697 /**
4698  * intel_pre_disable_primary - Perform operations before disabling primary plane
4699  * @crtc: the CRTC whose primary plane is to be disabled
4700  *
4701  * Performs potentially sleeping operations that must be done before the
4702  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4703  * be called due to an explicit primary plane update, or due to an implicit
4704  * disable that is caused when a sprite plane completely hides the primary
4705  * plane.
4706  */
4707 static void
4708 intel_pre_disable_primary(struct drm_crtc *crtc)
4709 {
4710         struct drm_device *dev = crtc->dev;
4711         struct drm_i915_private *dev_priv = dev->dev_private;
4712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713         int pipe = intel_crtc->pipe;
4714
4715         /*
4716          * Gen2 reports pipe underruns whenever all planes are disabled.
4717          * So diasble underrun reporting before all the planes get disabled.
4718          * FIXME: Need to fix the logic to work when we turn off all planes
4719          * but leave the pipe running.
4720          */
4721         if (IS_GEN2(dev))
4722                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4723
4724         /*
4725          * Vblank time updates from the shadow to live plane control register
4726          * are blocked if the memory self-refresh mode is active at that
4727          * moment. So to make sure the plane gets truly disabled, disable
4728          * first the self-refresh mode. The self-refresh enable bit in turn
4729          * will be checked/applied by the HW only at the next frame start
4730          * event which is after the vblank start event, so we need to have a
4731          * wait-for-vblank between disabling the plane and the pipe.
4732          */
4733         if (HAS_GMCH_DISPLAY(dev)) {
4734                 intel_set_memory_cxsr(dev_priv, false);
4735                 dev_priv->wm.vlv.cxsr = false;
4736                 intel_wait_for_vblank(dev, pipe);
4737         }
4738
4739         /*
4740          * FIXME IPS should be fine as long as one plane is
4741          * enabled, but in practice it seems to have problems
4742          * when going from primary only to sprite only and vice
4743          * versa.
4744          */
4745         hsw_disable_ips(intel_crtc);
4746 }
4747
4748 static void intel_post_plane_update(struct intel_crtc *crtc)
4749 {
4750         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4751         struct drm_device *dev = crtc->base.dev;
4752         struct drm_i915_private *dev_priv = dev->dev_private;
4753         struct drm_plane *plane;
4754
4755         if (atomic->wait_vblank)
4756                 intel_wait_for_vblank(dev, crtc->pipe);
4757
4758         intel_frontbuffer_flip(dev, atomic->fb_bits);
4759
4760         if (atomic->disable_cxsr)
4761                 crtc->wm.cxsr_allowed = true;
4762
4763         if (crtc->atomic.update_wm_post)
4764                 intel_update_watermarks(&crtc->base);
4765
4766         if (atomic->update_fbc)
4767                 intel_fbc_update(dev_priv);
4768
4769         if (atomic->post_enable_primary)
4770                 intel_post_enable_primary(&crtc->base);
4771
4772         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4773                 intel_update_sprite_watermarks(plane, &crtc->base,
4774                                                0, 0, 0, false, false);
4775
4776         memset(atomic, 0, sizeof(*atomic));
4777 }
4778
4779 static void intel_pre_plane_update(struct intel_crtc *crtc)
4780 {
4781         struct drm_device *dev = crtc->base.dev;
4782         struct drm_i915_private *dev_priv = dev->dev_private;
4783         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4784         struct drm_plane *p;
4785
4786         /* Track fb's for any planes being disabled */
4787         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4788                 struct intel_plane *plane = to_intel_plane(p);
4789
4790                 mutex_lock(&dev->struct_mutex);
4791                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4792                                   plane->frontbuffer_bit);
4793                 mutex_unlock(&dev->struct_mutex);
4794         }
4795
4796         if (atomic->wait_for_flips)
4797                 intel_crtc_wait_for_pending_flips(&crtc->base);
4798
4799         if (atomic->disable_fbc)
4800                 intel_fbc_disable_crtc(crtc);
4801
4802         if (crtc->atomic.disable_ips)
4803                 hsw_disable_ips(crtc);
4804
4805         if (atomic->pre_disable_primary)
4806                 intel_pre_disable_primary(&crtc->base);
4807
4808         if (atomic->disable_cxsr) {
4809                 crtc->wm.cxsr_allowed = false;
4810                 intel_set_memory_cxsr(dev_priv, false);
4811         }
4812 }
4813
4814 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4815 {
4816         struct drm_device *dev = crtc->dev;
4817         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4818         struct drm_plane *p;
4819         int pipe = intel_crtc->pipe;
4820
4821         intel_crtc_dpms_overlay_disable(intel_crtc);
4822
4823         drm_for_each_plane_mask(p, dev, plane_mask)
4824                 to_intel_plane(p)->disable_plane(p, crtc);
4825
4826         /*
4827          * FIXME: Once we grow proper nuclear flip support out of this we need
4828          * to compute the mask of flip planes precisely. For the time being
4829          * consider this a flip to a NULL plane.
4830          */
4831         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4832 }
4833
4834 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4835 {
4836         struct drm_device *dev = crtc->dev;
4837         struct drm_i915_private *dev_priv = dev->dev_private;
4838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4839         struct intel_encoder *encoder;
4840         int pipe = intel_crtc->pipe;
4841
4842         if (WARN_ON(intel_crtc->active))
4843                 return;
4844
4845         if (intel_crtc->config->has_pch_encoder)
4846                 intel_prepare_shared_dpll(intel_crtc);
4847
4848         if (intel_crtc->config->has_dp_encoder)
4849                 intel_dp_set_m_n(intel_crtc, M1_N1);
4850
4851         intel_set_pipe_timings(intel_crtc);
4852
4853         if (intel_crtc->config->has_pch_encoder) {
4854                 intel_cpu_transcoder_set_m_n(intel_crtc,
4855                                      &intel_crtc->config->fdi_m_n, NULL);
4856         }
4857
4858         ironlake_set_pipeconf(crtc);
4859
4860         intel_crtc->active = true;
4861
4862         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4863         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4864
4865         for_each_encoder_on_crtc(dev, crtc, encoder)
4866                 if (encoder->pre_enable)
4867                         encoder->pre_enable(encoder);
4868
4869         if (intel_crtc->config->has_pch_encoder) {
4870                 /* Note: FDI PLL enabling _must_ be done before we enable the
4871                  * cpu pipes, hence this is separate from all the other fdi/pch
4872                  * enabling. */
4873                 ironlake_fdi_pll_enable(intel_crtc);
4874         } else {
4875                 assert_fdi_tx_disabled(dev_priv, pipe);
4876                 assert_fdi_rx_disabled(dev_priv, pipe);
4877         }
4878
4879         ironlake_pfit_enable(intel_crtc);
4880
4881         /*
4882          * On ILK+ LUT must be loaded before the pipe is running but with
4883          * clocks enabled
4884          */
4885         intel_crtc_load_lut(crtc);
4886
4887         intel_update_watermarks(crtc);
4888         intel_enable_pipe(intel_crtc);
4889
4890         if (intel_crtc->config->has_pch_encoder)
4891                 ironlake_pch_enable(crtc);
4892
4893         assert_vblank_disabled(crtc);
4894         drm_crtc_vblank_on(crtc);
4895
4896         for_each_encoder_on_crtc(dev, crtc, encoder)
4897                 encoder->enable(encoder);
4898
4899         if (HAS_PCH_CPT(dev))
4900                 cpt_verify_modeset(dev, intel_crtc->pipe);
4901 }
4902
4903 /* IPS only exists on ULT machines and is tied to pipe A. */
4904 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4905 {
4906         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4907 }
4908
4909 static void haswell_crtc_enable(struct drm_crtc *crtc)
4910 {
4911         struct drm_device *dev = crtc->dev;
4912         struct drm_i915_private *dev_priv = dev->dev_private;
4913         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4914         struct intel_encoder *encoder;
4915         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4916         struct intel_crtc_state *pipe_config =
4917                 to_intel_crtc_state(crtc->state);
4918
4919         if (WARN_ON(intel_crtc->active))
4920                 return;
4921
4922         if (intel_crtc_to_shared_dpll(intel_crtc))
4923                 intel_enable_shared_dpll(intel_crtc);
4924
4925         if (intel_crtc->config->has_dp_encoder)
4926                 intel_dp_set_m_n(intel_crtc, M1_N1);
4927
4928         intel_set_pipe_timings(intel_crtc);
4929
4930         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4931                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4932                            intel_crtc->config->pixel_multiplier - 1);
4933         }
4934
4935         if (intel_crtc->config->has_pch_encoder) {
4936                 intel_cpu_transcoder_set_m_n(intel_crtc,
4937                                      &intel_crtc->config->fdi_m_n, NULL);
4938         }
4939
4940         haswell_set_pipeconf(crtc);
4941
4942         intel_set_pipe_csc(crtc);
4943
4944         intel_crtc->active = true;
4945
4946         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4947         for_each_encoder_on_crtc(dev, crtc, encoder)
4948                 if (encoder->pre_enable)
4949                         encoder->pre_enable(encoder);
4950
4951         if (intel_crtc->config->has_pch_encoder) {
4952                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4953                                                       true);
4954                 dev_priv->display.fdi_link_train(crtc);
4955         }
4956
4957         intel_ddi_enable_pipe_clock(intel_crtc);
4958
4959         if (INTEL_INFO(dev)->gen == 9)
4960                 skylake_pfit_enable(intel_crtc);
4961         else if (INTEL_INFO(dev)->gen < 9)
4962                 ironlake_pfit_enable(intel_crtc);
4963         else
4964                 MISSING_CASE(INTEL_INFO(dev)->gen);
4965
4966         /*
4967          * On ILK+ LUT must be loaded before the pipe is running but with
4968          * clocks enabled
4969          */
4970         intel_crtc_load_lut(crtc);
4971
4972         intel_ddi_set_pipe_settings(crtc);
4973         intel_ddi_enable_transcoder_func(crtc);
4974
4975         intel_update_watermarks(crtc);
4976         intel_enable_pipe(intel_crtc);
4977
4978         if (intel_crtc->config->has_pch_encoder)
4979                 lpt_pch_enable(crtc);
4980
4981         if (intel_crtc->config->dp_encoder_is_mst)
4982                 intel_ddi_set_vc_payload_alloc(crtc, true);
4983
4984         assert_vblank_disabled(crtc);
4985         drm_crtc_vblank_on(crtc);
4986
4987         for_each_encoder_on_crtc(dev, crtc, encoder) {
4988                 encoder->enable(encoder);
4989                 intel_opregion_notify_encoder(encoder, true);
4990         }
4991
4992         /* If we change the relative order between pipe/planes enabling, we need
4993          * to change the workaround. */
4994         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4995         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4996                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4997                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4998         }
4999 }
5000
5001 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5002 {
5003         struct drm_device *dev = crtc->base.dev;
5004         struct drm_i915_private *dev_priv = dev->dev_private;
5005         int pipe = crtc->pipe;
5006
5007         /* To avoid upsetting the power well on haswell only disable the pfit if
5008          * it's in use. The hw state code will make sure we get this right. */
5009         if (crtc->config->pch_pfit.enabled) {
5010                 I915_WRITE(PF_CTL(pipe), 0);
5011                 I915_WRITE(PF_WIN_POS(pipe), 0);
5012                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5013         }
5014 }
5015
5016 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5017 {
5018         struct drm_device *dev = crtc->dev;
5019         struct drm_i915_private *dev_priv = dev->dev_private;
5020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5021         struct intel_encoder *encoder;
5022         int pipe = intel_crtc->pipe;
5023         u32 reg, temp;
5024
5025         for_each_encoder_on_crtc(dev, crtc, encoder)
5026                 encoder->disable(encoder);
5027
5028         drm_crtc_vblank_off(crtc);
5029         assert_vblank_disabled(crtc);
5030
5031         if (intel_crtc->config->has_pch_encoder)
5032                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5033
5034         intel_disable_pipe(intel_crtc);
5035
5036         ironlake_pfit_disable(intel_crtc);
5037
5038         if (intel_crtc->config->has_pch_encoder)
5039                 ironlake_fdi_disable(crtc);
5040
5041         for_each_encoder_on_crtc(dev, crtc, encoder)
5042                 if (encoder->post_disable)
5043                         encoder->post_disable(encoder);
5044
5045         if (intel_crtc->config->has_pch_encoder) {
5046                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5047
5048                 if (HAS_PCH_CPT(dev)) {
5049                         /* disable TRANS_DP_CTL */
5050                         reg = TRANS_DP_CTL(pipe);
5051                         temp = I915_READ(reg);
5052                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5053                                   TRANS_DP_PORT_SEL_MASK);
5054                         temp |= TRANS_DP_PORT_SEL_NONE;
5055                         I915_WRITE(reg, temp);
5056
5057                         /* disable DPLL_SEL */
5058                         temp = I915_READ(PCH_DPLL_SEL);
5059                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5060                         I915_WRITE(PCH_DPLL_SEL, temp);
5061                 }
5062
5063                 ironlake_fdi_pll_disable(intel_crtc);
5064         }
5065
5066         intel_crtc->active = false;
5067         intel_update_watermarks(crtc);
5068 }
5069
5070 static void haswell_crtc_disable(struct drm_crtc *crtc)
5071 {
5072         struct drm_device *dev = crtc->dev;
5073         struct drm_i915_private *dev_priv = dev->dev_private;
5074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5075         struct intel_encoder *encoder;
5076         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5077
5078         for_each_encoder_on_crtc(dev, crtc, encoder) {
5079                 intel_opregion_notify_encoder(encoder, false);
5080                 encoder->disable(encoder);
5081         }
5082
5083         drm_crtc_vblank_off(crtc);
5084         assert_vblank_disabled(crtc);
5085
5086         if (intel_crtc->config->has_pch_encoder)
5087                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5088                                                       false);
5089         intel_disable_pipe(intel_crtc);
5090
5091         if (intel_crtc->config->dp_encoder_is_mst)
5092                 intel_ddi_set_vc_payload_alloc(crtc, false);
5093
5094         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5095
5096         if (INTEL_INFO(dev)->gen == 9)
5097                 skylake_scaler_disable(intel_crtc);
5098         else if (INTEL_INFO(dev)->gen < 9)
5099                 ironlake_pfit_disable(intel_crtc);
5100         else
5101                 MISSING_CASE(INTEL_INFO(dev)->gen);
5102
5103         intel_ddi_disable_pipe_clock(intel_crtc);
5104
5105         if (intel_crtc->config->has_pch_encoder) {
5106                 lpt_disable_pch_transcoder(dev_priv);
5107                 intel_ddi_fdi_disable(crtc);
5108         }
5109
5110         for_each_encoder_on_crtc(dev, crtc, encoder)
5111                 if (encoder->post_disable)
5112                         encoder->post_disable(encoder);
5113
5114         intel_crtc->active = false;
5115         intel_update_watermarks(crtc);
5116 }
5117
5118 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5119 {
5120         struct drm_device *dev = crtc->base.dev;
5121         struct drm_i915_private *dev_priv = dev->dev_private;
5122         struct intel_crtc_state *pipe_config = crtc->config;
5123
5124         if (!pipe_config->gmch_pfit.control)
5125                 return;
5126
5127         /*
5128          * The panel fitter should only be adjusted whilst the pipe is disabled,
5129          * according to register description and PRM.
5130          */
5131         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5132         assert_pipe_disabled(dev_priv, crtc->pipe);
5133
5134         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5135         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5136
5137         /* Border color in case we don't scale up to the full screen. Black by
5138          * default, change to something else for debugging. */
5139         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5140 }
5141
5142 static enum intel_display_power_domain port_to_power_domain(enum port port)
5143 {
5144         switch (port) {
5145         case PORT_A:
5146                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5147         case PORT_B:
5148                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5149         case PORT_C:
5150                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5151         case PORT_D:
5152                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5153         default:
5154                 WARN_ON_ONCE(1);
5155                 return POWER_DOMAIN_PORT_OTHER;
5156         }
5157 }
5158
5159 #define for_each_power_domain(domain, mask)                             \
5160         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5161                 if ((1 << (domain)) & (mask))
5162
5163 enum intel_display_power_domain
5164 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5165 {
5166         struct drm_device *dev = intel_encoder->base.dev;
5167         struct intel_digital_port *intel_dig_port;
5168
5169         switch (intel_encoder->type) {
5170         case INTEL_OUTPUT_UNKNOWN:
5171                 /* Only DDI platforms should ever use this output type */
5172                 WARN_ON_ONCE(!HAS_DDI(dev));
5173         case INTEL_OUTPUT_DISPLAYPORT:
5174         case INTEL_OUTPUT_HDMI:
5175         case INTEL_OUTPUT_EDP:
5176                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5177                 return port_to_power_domain(intel_dig_port->port);
5178         case INTEL_OUTPUT_DP_MST:
5179                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5180                 return port_to_power_domain(intel_dig_port->port);
5181         case INTEL_OUTPUT_ANALOG:
5182                 return POWER_DOMAIN_PORT_CRT;
5183         case INTEL_OUTPUT_DSI:
5184                 return POWER_DOMAIN_PORT_DSI;
5185         default:
5186                 return POWER_DOMAIN_PORT_OTHER;
5187         }
5188 }
5189
5190 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5191 {
5192         struct drm_device *dev = crtc->dev;
5193         struct intel_encoder *intel_encoder;
5194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5195         enum pipe pipe = intel_crtc->pipe;
5196         unsigned long mask;
5197         enum transcoder transcoder;
5198
5199         if (!crtc->state->active)
5200                 return 0;
5201
5202         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5203
5204         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5205         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5206         if (intel_crtc->config->pch_pfit.enabled ||
5207             intel_crtc->config->pch_pfit.force_thru)
5208                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5209
5210         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5211                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5212
5213         return mask;
5214 }
5215
5216 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5217 {
5218         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5220         enum intel_display_power_domain domain;
5221         unsigned long domains, new_domains, old_domains;
5222
5223         old_domains = intel_crtc->enabled_power_domains;
5224         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5225
5226         domains = new_domains & ~old_domains;
5227
5228         for_each_power_domain(domain, domains)
5229                 intel_display_power_get(dev_priv, domain);
5230
5231         return old_domains & ~new_domains;
5232 }
5233
5234 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5235                                       unsigned long domains)
5236 {
5237         enum intel_display_power_domain domain;
5238
5239         for_each_power_domain(domain, domains)
5240                 intel_display_power_put(dev_priv, domain);
5241 }
5242
5243 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5244 {
5245         struct drm_device *dev = state->dev;
5246         struct drm_i915_private *dev_priv = dev->dev_private;
5247         unsigned long put_domains[I915_MAX_PIPES] = {};
5248         struct drm_crtc_state *crtc_state;
5249         struct drm_crtc *crtc;
5250         int i;
5251
5252         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5253                 if (needs_modeset(crtc->state))
5254                         put_domains[to_intel_crtc(crtc)->pipe] =
5255                                 modeset_get_crtc_power_domains(crtc);
5256         }
5257
5258         if (dev_priv->display.modeset_commit_cdclk) {
5259                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5260
5261                 if (cdclk != dev_priv->cdclk_freq &&
5262                     !WARN_ON(!state->allow_modeset))
5263                         dev_priv->display.modeset_commit_cdclk(state);
5264         }
5265
5266         for (i = 0; i < I915_MAX_PIPES; i++)
5267                 if (put_domains[i])
5268                         modeset_put_power_domains(dev_priv, put_domains[i]);
5269 }
5270
5271 static void intel_update_max_cdclk(struct drm_device *dev)
5272 {
5273         struct drm_i915_private *dev_priv = dev->dev_private;
5274
5275         if (IS_SKYLAKE(dev)) {
5276                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5277
5278                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5279                         dev_priv->max_cdclk_freq = 675000;
5280                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5281                         dev_priv->max_cdclk_freq = 540000;
5282                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5283                         dev_priv->max_cdclk_freq = 450000;
5284                 else
5285                         dev_priv->max_cdclk_freq = 337500;
5286         } else if (IS_BROADWELL(dev))  {
5287                 /*
5288                  * FIXME with extra cooling we can allow
5289                  * 540 MHz for ULX and 675 Mhz for ULT.
5290                  * How can we know if extra cooling is
5291                  * available? PCI ID, VTB, something else?
5292                  */
5293                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5294                         dev_priv->max_cdclk_freq = 450000;
5295                 else if (IS_BDW_ULX(dev))
5296                         dev_priv->max_cdclk_freq = 450000;
5297                 else if (IS_BDW_ULT(dev))
5298                         dev_priv->max_cdclk_freq = 540000;
5299                 else
5300                         dev_priv->max_cdclk_freq = 675000;
5301         } else if (IS_CHERRYVIEW(dev)) {
5302                 dev_priv->max_cdclk_freq = 320000;
5303         } else if (IS_VALLEYVIEW(dev)) {
5304                 dev_priv->max_cdclk_freq = 400000;
5305         } else {
5306                 /* otherwise assume cdclk is fixed */
5307                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5308         }
5309
5310         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5311                          dev_priv->max_cdclk_freq);
5312 }
5313
5314 static void intel_update_cdclk(struct drm_device *dev)
5315 {
5316         struct drm_i915_private *dev_priv = dev->dev_private;
5317
5318         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5319         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5320                          dev_priv->cdclk_freq);
5321
5322         /*
5323          * Program the gmbus_freq based on the cdclk frequency.
5324          * BSpec erroneously claims we should aim for 4MHz, but
5325          * in fact 1MHz is the correct frequency.
5326          */
5327         if (IS_VALLEYVIEW(dev)) {
5328                 /*
5329                  * Program the gmbus_freq based on the cdclk frequency.
5330                  * BSpec erroneously claims we should aim for 4MHz, but
5331                  * in fact 1MHz is the correct frequency.
5332                  */
5333                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5334         }
5335
5336         if (dev_priv->max_cdclk_freq == 0)
5337                 intel_update_max_cdclk(dev);
5338 }
5339
5340 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5341 {
5342         struct drm_i915_private *dev_priv = dev->dev_private;
5343         uint32_t divider;
5344         uint32_t ratio;
5345         uint32_t current_freq;
5346         int ret;
5347
5348         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5349         switch (frequency) {
5350         case 144000:
5351                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5352                 ratio = BXT_DE_PLL_RATIO(60);
5353                 break;
5354         case 288000:
5355                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5356                 ratio = BXT_DE_PLL_RATIO(60);
5357                 break;
5358         case 384000:
5359                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5360                 ratio = BXT_DE_PLL_RATIO(60);
5361                 break;
5362         case 576000:
5363                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5364                 ratio = BXT_DE_PLL_RATIO(60);
5365                 break;
5366         case 624000:
5367                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5368                 ratio = BXT_DE_PLL_RATIO(65);
5369                 break;
5370         case 19200:
5371                 /*
5372                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5373                  * to suppress GCC warning.
5374                  */
5375                 ratio = 0;
5376                 divider = 0;
5377                 break;
5378         default:
5379                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5380
5381                 return;
5382         }
5383
5384         mutex_lock(&dev_priv->rps.hw_lock);
5385         /* Inform power controller of upcoming frequency change */
5386         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5387                                       0x80000000);
5388         mutex_unlock(&dev_priv->rps.hw_lock);
5389
5390         if (ret) {
5391                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5392                           ret, frequency);
5393                 return;
5394         }
5395
5396         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5397         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5398         current_freq = current_freq * 500 + 1000;
5399
5400         /*
5401          * DE PLL has to be disabled when
5402          * - setting to 19.2MHz (bypass, PLL isn't used)
5403          * - before setting to 624MHz (PLL needs toggling)
5404          * - before setting to any frequency from 624MHz (PLL needs toggling)
5405          */
5406         if (frequency == 19200 || frequency == 624000 ||
5407             current_freq == 624000) {
5408                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5409                 /* Timeout 200us */
5410                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5411                              1))
5412                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5413         }
5414
5415         if (frequency != 19200) {
5416                 uint32_t val;
5417
5418                 val = I915_READ(BXT_DE_PLL_CTL);
5419                 val &= ~BXT_DE_PLL_RATIO_MASK;
5420                 val |= ratio;
5421                 I915_WRITE(BXT_DE_PLL_CTL, val);
5422
5423                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5424                 /* Timeout 200us */
5425                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5426                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5427
5428                 val = I915_READ(CDCLK_CTL);
5429                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5430                 val |= divider;
5431                 /*
5432                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5433                  * enable otherwise.
5434                  */
5435                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5436                 if (frequency >= 500000)
5437                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5438
5439                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5440                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5441                 val |= (frequency - 1000) / 500;
5442                 I915_WRITE(CDCLK_CTL, val);
5443         }
5444
5445         mutex_lock(&dev_priv->rps.hw_lock);
5446         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5447                                       DIV_ROUND_UP(frequency, 25000));
5448         mutex_unlock(&dev_priv->rps.hw_lock);
5449
5450         if (ret) {
5451                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5452                           ret, frequency);
5453                 return;
5454         }
5455
5456         intel_update_cdclk(dev);
5457 }
5458
5459 void broxton_init_cdclk(struct drm_device *dev)
5460 {
5461         struct drm_i915_private *dev_priv = dev->dev_private;
5462         uint32_t val;
5463
5464         /*
5465          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5466          * or else the reset will hang because there is no PCH to respond.
5467          * Move the handshake programming to initialization sequence.
5468          * Previously was left up to BIOS.
5469          */
5470         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5471         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5472         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5473
5474         /* Enable PG1 for cdclk */
5475         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5476
5477         /* check if cd clock is enabled */
5478         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5479                 DRM_DEBUG_KMS("Display already initialized\n");
5480                 return;
5481         }
5482
5483         /*
5484          * FIXME:
5485          * - The initial CDCLK needs to be read from VBT.
5486          *   Need to make this change after VBT has changes for BXT.
5487          * - check if setting the max (or any) cdclk freq is really necessary
5488          *   here, it belongs to modeset time
5489          */
5490         broxton_set_cdclk(dev, 624000);
5491
5492         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5493         POSTING_READ(DBUF_CTL);
5494
5495         udelay(10);
5496
5497         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5498                 DRM_ERROR("DBuf power enable timeout!\n");
5499 }
5500
5501 void broxton_uninit_cdclk(struct drm_device *dev)
5502 {
5503         struct drm_i915_private *dev_priv = dev->dev_private;
5504
5505         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5506         POSTING_READ(DBUF_CTL);
5507
5508         udelay(10);
5509
5510         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5511                 DRM_ERROR("DBuf power disable timeout!\n");
5512
5513         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5514         broxton_set_cdclk(dev, 19200);
5515
5516         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5517 }
5518
5519 static const struct skl_cdclk_entry {
5520         unsigned int freq;
5521         unsigned int vco;
5522 } skl_cdclk_frequencies[] = {
5523         { .freq = 308570, .vco = 8640 },
5524         { .freq = 337500, .vco = 8100 },
5525         { .freq = 432000, .vco = 8640 },
5526         { .freq = 450000, .vco = 8100 },
5527         { .freq = 540000, .vco = 8100 },
5528         { .freq = 617140, .vco = 8640 },
5529         { .freq = 675000, .vco = 8100 },
5530 };
5531
5532 static unsigned int skl_cdclk_decimal(unsigned int freq)
5533 {
5534         return (freq - 1000) / 500;
5535 }
5536
5537 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5538 {
5539         unsigned int i;
5540
5541         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5542                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5543
5544                 if (e->freq == freq)
5545                         return e->vco;
5546         }
5547
5548         return 8100;
5549 }
5550
5551 static void
5552 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5553 {
5554         unsigned int min_freq;
5555         u32 val;
5556
5557         /* select the minimum CDCLK before enabling DPLL 0 */
5558         val = I915_READ(CDCLK_CTL);
5559         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5560         val |= CDCLK_FREQ_337_308;
5561
5562         if (required_vco == 8640)
5563                 min_freq = 308570;
5564         else
5565                 min_freq = 337500;
5566
5567         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5568
5569         I915_WRITE(CDCLK_CTL, val);
5570         POSTING_READ(CDCLK_CTL);
5571
5572         /*
5573          * We always enable DPLL0 with the lowest link rate possible, but still
5574          * taking into account the VCO required to operate the eDP panel at the
5575          * desired frequency. The usual DP link rates operate with a VCO of
5576          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5577          * The modeset code is responsible for the selection of the exact link
5578          * rate later on, with the constraint of choosing a frequency that
5579          * works with required_vco.
5580          */
5581         val = I915_READ(DPLL_CTRL1);
5582
5583         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5584                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5585         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5586         if (required_vco == 8640)
5587                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5588                                             SKL_DPLL0);
5589         else
5590                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5591                                             SKL_DPLL0);
5592
5593         I915_WRITE(DPLL_CTRL1, val);
5594         POSTING_READ(DPLL_CTRL1);
5595
5596         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5597
5598         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5599                 DRM_ERROR("DPLL0 not locked\n");
5600 }
5601
5602 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5603 {
5604         int ret;
5605         u32 val;
5606
5607         /* inform PCU we want to change CDCLK */
5608         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5609         mutex_lock(&dev_priv->rps.hw_lock);
5610         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5611         mutex_unlock(&dev_priv->rps.hw_lock);
5612
5613         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5614 }
5615
5616 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5617 {
5618         unsigned int i;
5619
5620         for (i = 0; i < 15; i++) {
5621                 if (skl_cdclk_pcu_ready(dev_priv))
5622                         return true;
5623                 udelay(10);
5624         }
5625
5626         return false;
5627 }
5628
5629 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5630 {
5631         struct drm_device *dev = dev_priv->dev;
5632         u32 freq_select, pcu_ack;
5633
5634         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5635
5636         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5637                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5638                 return;
5639         }
5640
5641         /* set CDCLK_CTL */
5642         switch(freq) {
5643         case 450000:
5644         case 432000:
5645                 freq_select = CDCLK_FREQ_450_432;
5646                 pcu_ack = 1;
5647                 break;
5648         case 540000:
5649                 freq_select = CDCLK_FREQ_540;
5650                 pcu_ack = 2;
5651                 break;
5652         case 308570:
5653         case 337500:
5654         default:
5655                 freq_select = CDCLK_FREQ_337_308;
5656                 pcu_ack = 0;
5657                 break;
5658         case 617140:
5659         case 675000:
5660                 freq_select = CDCLK_FREQ_675_617;
5661                 pcu_ack = 3;
5662                 break;
5663         }
5664
5665         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5666         POSTING_READ(CDCLK_CTL);
5667
5668         /* inform PCU of the change */
5669         mutex_lock(&dev_priv->rps.hw_lock);
5670         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5671         mutex_unlock(&dev_priv->rps.hw_lock);
5672
5673         intel_update_cdclk(dev);
5674 }
5675
5676 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5677 {
5678         /* disable DBUF power */
5679         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5680         POSTING_READ(DBUF_CTL);
5681
5682         udelay(10);
5683
5684         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5685                 DRM_ERROR("DBuf power disable timeout\n");
5686
5687         /* disable DPLL0 */
5688         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5689         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5690                 DRM_ERROR("Couldn't disable DPLL0\n");
5691
5692         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5693 }
5694
5695 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5696 {
5697         u32 val;
5698         unsigned int required_vco;
5699
5700         /* enable PCH reset handshake */
5701         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5702         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5703
5704         /* enable PG1 and Misc I/O */
5705         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5706
5707         /* DPLL0 already enabed !? */
5708         if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5709                 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5710                 return;
5711         }
5712
5713         /* enable DPLL0 */
5714         required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5715         skl_dpll0_enable(dev_priv, required_vco);
5716
5717         /* set CDCLK to the frequency the BIOS chose */
5718         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5719
5720         /* enable DBUF power */
5721         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5722         POSTING_READ(DBUF_CTL);
5723
5724         udelay(10);
5725
5726         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5727                 DRM_ERROR("DBuf power enable timeout\n");
5728 }
5729
5730 /* returns HPLL frequency in kHz */
5731 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5732 {
5733         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5734
5735         /* Obtain SKU information */
5736         mutex_lock(&dev_priv->sb_lock);
5737         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5738                 CCK_FUSE_HPLL_FREQ_MASK;
5739         mutex_unlock(&dev_priv->sb_lock);
5740
5741         return vco_freq[hpll_freq] * 1000;
5742 }
5743
5744 /* Adjust CDclk dividers to allow high res or save power if possible */
5745 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5746 {
5747         struct drm_i915_private *dev_priv = dev->dev_private;
5748         u32 val, cmd;
5749
5750         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5751                                         != dev_priv->cdclk_freq);
5752
5753         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5754                 cmd = 2;
5755         else if (cdclk == 266667)
5756                 cmd = 1;
5757         else
5758                 cmd = 0;
5759
5760         mutex_lock(&dev_priv->rps.hw_lock);
5761         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5762         val &= ~DSPFREQGUAR_MASK;
5763         val |= (cmd << DSPFREQGUAR_SHIFT);
5764         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5765         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5766                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5767                      50)) {
5768                 DRM_ERROR("timed out waiting for CDclk change\n");
5769         }
5770         mutex_unlock(&dev_priv->rps.hw_lock);
5771
5772         mutex_lock(&dev_priv->sb_lock);
5773
5774         if (cdclk == 400000) {
5775                 u32 divider;
5776
5777                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5778
5779                 /* adjust cdclk divider */
5780                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5781                 val &= ~DISPLAY_FREQUENCY_VALUES;
5782                 val |= divider;
5783                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5784
5785                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5786                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5787                              50))
5788                         DRM_ERROR("timed out waiting for CDclk change\n");
5789         }
5790
5791         /* adjust self-refresh exit latency value */
5792         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5793         val &= ~0x7f;
5794
5795         /*
5796          * For high bandwidth configs, we set a higher latency in the bunit
5797          * so that the core display fetch happens in time to avoid underruns.
5798          */
5799         if (cdclk == 400000)
5800                 val |= 4500 / 250; /* 4.5 usec */
5801         else
5802                 val |= 3000 / 250; /* 3.0 usec */
5803         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5804
5805         mutex_unlock(&dev_priv->sb_lock);
5806
5807         intel_update_cdclk(dev);
5808 }
5809
5810 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5811 {
5812         struct drm_i915_private *dev_priv = dev->dev_private;
5813         u32 val, cmd;
5814
5815         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5816                                                 != dev_priv->cdclk_freq);
5817
5818         switch (cdclk) {
5819         case 333333:
5820         case 320000:
5821         case 266667:
5822         case 200000:
5823                 break;
5824         default:
5825                 MISSING_CASE(cdclk);
5826                 return;
5827         }
5828
5829         /*
5830          * Specs are full of misinformation, but testing on actual
5831          * hardware has shown that we just need to write the desired
5832          * CCK divider into the Punit register.
5833          */
5834         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5835
5836         mutex_lock(&dev_priv->rps.hw_lock);
5837         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5838         val &= ~DSPFREQGUAR_MASK_CHV;
5839         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5840         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5841         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5842                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5843                      50)) {
5844                 DRM_ERROR("timed out waiting for CDclk change\n");
5845         }
5846         mutex_unlock(&dev_priv->rps.hw_lock);
5847
5848         intel_update_cdclk(dev);
5849 }
5850
5851 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5852                                  int max_pixclk)
5853 {
5854         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5855         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5856
5857         /*
5858          * Really only a few cases to deal with, as only 4 CDclks are supported:
5859          *   200MHz
5860          *   267MHz
5861          *   320/333MHz (depends on HPLL freq)
5862          *   400MHz (VLV only)
5863          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5864          * of the lower bin and adjust if needed.
5865          *
5866          * We seem to get an unstable or solid color picture at 200MHz.
5867          * Not sure what's wrong. For now use 200MHz only when all pipes
5868          * are off.
5869          */
5870         if (!IS_CHERRYVIEW(dev_priv) &&
5871             max_pixclk > freq_320*limit/100)
5872                 return 400000;
5873         else if (max_pixclk > 266667*limit/100)
5874                 return freq_320;
5875         else if (max_pixclk > 0)
5876                 return 266667;
5877         else
5878                 return 200000;
5879 }
5880
5881 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5882                               int max_pixclk)
5883 {
5884         /*
5885          * FIXME:
5886          * - remove the guardband, it's not needed on BXT
5887          * - set 19.2MHz bypass frequency if there are no active pipes
5888          */
5889         if (max_pixclk > 576000*9/10)
5890                 return 624000;
5891         else if (max_pixclk > 384000*9/10)
5892                 return 576000;
5893         else if (max_pixclk > 288000*9/10)
5894                 return 384000;
5895         else if (max_pixclk > 144000*9/10)
5896                 return 288000;
5897         else
5898                 return 144000;
5899 }
5900
5901 /* Compute the max pixel clock for new configuration. Uses atomic state if
5902  * that's non-NULL, look at current state otherwise. */
5903 static int intel_mode_max_pixclk(struct drm_device *dev,
5904                                  struct drm_atomic_state *state)
5905 {
5906         struct intel_crtc *intel_crtc;
5907         struct intel_crtc_state *crtc_state;
5908         int max_pixclk = 0;
5909
5910         for_each_intel_crtc(dev, intel_crtc) {
5911                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5912                 if (IS_ERR(crtc_state))
5913                         return PTR_ERR(crtc_state);
5914
5915                 if (!crtc_state->base.enable)
5916                         continue;
5917
5918                 max_pixclk = max(max_pixclk,
5919                                  crtc_state->base.adjusted_mode.crtc_clock);
5920         }
5921
5922         return max_pixclk;
5923 }
5924
5925 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5926 {
5927         struct drm_device *dev = state->dev;
5928         struct drm_i915_private *dev_priv = dev->dev_private;
5929         int max_pixclk = intel_mode_max_pixclk(dev, state);
5930
5931         if (max_pixclk < 0)
5932                 return max_pixclk;
5933
5934         to_intel_atomic_state(state)->cdclk =
5935                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5936
5937         return 0;
5938 }
5939
5940 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5941 {
5942         struct drm_device *dev = state->dev;
5943         struct drm_i915_private *dev_priv = dev->dev_private;
5944         int max_pixclk = intel_mode_max_pixclk(dev, state);
5945
5946         if (max_pixclk < 0)
5947                 return max_pixclk;
5948
5949         to_intel_atomic_state(state)->cdclk =
5950                 broxton_calc_cdclk(dev_priv, max_pixclk);
5951
5952         return 0;
5953 }
5954
5955 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5956 {
5957         unsigned int credits, default_credits;
5958
5959         if (IS_CHERRYVIEW(dev_priv))
5960                 default_credits = PFI_CREDIT(12);
5961         else
5962                 default_credits = PFI_CREDIT(8);
5963
5964         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5965                 /* CHV suggested value is 31 or 63 */
5966                 if (IS_CHERRYVIEW(dev_priv))
5967                         credits = PFI_CREDIT_63;
5968                 else
5969                         credits = PFI_CREDIT(15);
5970         } else {
5971                 credits = default_credits;
5972         }
5973
5974         /*
5975          * WA - write default credits before re-programming
5976          * FIXME: should we also set the resend bit here?
5977          */
5978         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5979                    default_credits);
5980
5981         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5982                    credits | PFI_CREDIT_RESEND);
5983
5984         /*
5985          * FIXME is this guaranteed to clear
5986          * immediately or should we poll for it?
5987          */
5988         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5989 }
5990
5991 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5992 {
5993         struct drm_device *dev = old_state->dev;
5994         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5995         struct drm_i915_private *dev_priv = dev->dev_private;
5996
5997         /*
5998          * FIXME: We can end up here with all power domains off, yet
5999          * with a CDCLK frequency other than the minimum. To account
6000          * for this take the PIPE-A power domain, which covers the HW
6001          * blocks needed for the following programming. This can be
6002          * removed once it's guaranteed that we get here either with
6003          * the minimum CDCLK set, or the required power domains
6004          * enabled.
6005          */
6006         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6007
6008         if (IS_CHERRYVIEW(dev))
6009                 cherryview_set_cdclk(dev, req_cdclk);
6010         else
6011                 valleyview_set_cdclk(dev, req_cdclk);
6012
6013         vlv_program_pfi_credits(dev_priv);
6014
6015         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6016 }
6017
6018 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6019 {
6020         struct drm_device *dev = crtc->dev;
6021         struct drm_i915_private *dev_priv = to_i915(dev);
6022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6023         struct intel_encoder *encoder;
6024         int pipe = intel_crtc->pipe;
6025         bool is_dsi;
6026
6027         if (WARN_ON(intel_crtc->active))
6028                 return;
6029
6030         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6031
6032         if (!is_dsi) {
6033                 if (IS_CHERRYVIEW(dev))
6034                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6035                 else
6036                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6037         }
6038
6039         if (intel_crtc->config->has_dp_encoder)
6040                 intel_dp_set_m_n(intel_crtc, M1_N1);
6041
6042         intel_set_pipe_timings(intel_crtc);
6043
6044         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6045                 struct drm_i915_private *dev_priv = dev->dev_private;
6046
6047                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6048                 I915_WRITE(CHV_CANVAS(pipe), 0);
6049         }
6050
6051         i9xx_set_pipeconf(intel_crtc);
6052
6053         intel_crtc->active = true;
6054
6055         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6056
6057         for_each_encoder_on_crtc(dev, crtc, encoder)
6058                 if (encoder->pre_pll_enable)
6059                         encoder->pre_pll_enable(encoder);
6060
6061         if (!is_dsi) {
6062                 if (IS_CHERRYVIEW(dev))
6063                         chv_enable_pll(intel_crtc, intel_crtc->config);
6064                 else
6065                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6066         }
6067
6068         for_each_encoder_on_crtc(dev, crtc, encoder)
6069                 if (encoder->pre_enable)
6070                         encoder->pre_enable(encoder);
6071
6072         i9xx_pfit_enable(intel_crtc);
6073
6074         intel_crtc_load_lut(crtc);
6075
6076         intel_enable_pipe(intel_crtc);
6077
6078         assert_vblank_disabled(crtc);
6079         drm_crtc_vblank_on(crtc);
6080
6081         for_each_encoder_on_crtc(dev, crtc, encoder)
6082                 encoder->enable(encoder);
6083 }
6084
6085 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6086 {
6087         struct drm_device *dev = crtc->base.dev;
6088         struct drm_i915_private *dev_priv = dev->dev_private;
6089
6090         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6091         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6092 }
6093
6094 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6095 {
6096         struct drm_device *dev = crtc->dev;
6097         struct drm_i915_private *dev_priv = to_i915(dev);
6098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6099         struct intel_encoder *encoder;
6100         int pipe = intel_crtc->pipe;
6101
6102         if (WARN_ON(intel_crtc->active))
6103                 return;
6104
6105         i9xx_set_pll_dividers(intel_crtc);
6106
6107         if (intel_crtc->config->has_dp_encoder)
6108                 intel_dp_set_m_n(intel_crtc, M1_N1);
6109
6110         intel_set_pipe_timings(intel_crtc);
6111
6112         i9xx_set_pipeconf(intel_crtc);
6113
6114         intel_crtc->active = true;
6115
6116         if (!IS_GEN2(dev))
6117                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6118
6119         for_each_encoder_on_crtc(dev, crtc, encoder)
6120                 if (encoder->pre_enable)
6121                         encoder->pre_enable(encoder);
6122
6123         i9xx_enable_pll(intel_crtc);
6124
6125         i9xx_pfit_enable(intel_crtc);
6126
6127         intel_crtc_load_lut(crtc);
6128
6129         intel_update_watermarks(crtc);
6130         intel_enable_pipe(intel_crtc);
6131
6132         assert_vblank_disabled(crtc);
6133         drm_crtc_vblank_on(crtc);
6134
6135         for_each_encoder_on_crtc(dev, crtc, encoder)
6136                 encoder->enable(encoder);
6137 }
6138
6139 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6140 {
6141         struct drm_device *dev = crtc->base.dev;
6142         struct drm_i915_private *dev_priv = dev->dev_private;
6143
6144         if (!crtc->config->gmch_pfit.control)
6145                 return;
6146
6147         assert_pipe_disabled(dev_priv, crtc->pipe);
6148
6149         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6150                          I915_READ(PFIT_CONTROL));
6151         I915_WRITE(PFIT_CONTROL, 0);
6152 }
6153
6154 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6155 {
6156         struct drm_device *dev = crtc->dev;
6157         struct drm_i915_private *dev_priv = dev->dev_private;
6158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6159         struct intel_encoder *encoder;
6160         int pipe = intel_crtc->pipe;
6161
6162         /*
6163          * On gen2 planes are double buffered but the pipe isn't, so we must
6164          * wait for planes to fully turn off before disabling the pipe.
6165          * We also need to wait on all gmch platforms because of the
6166          * self-refresh mode constraint explained above.
6167          */
6168         intel_wait_for_vblank(dev, pipe);
6169
6170         for_each_encoder_on_crtc(dev, crtc, encoder)
6171                 encoder->disable(encoder);
6172
6173         drm_crtc_vblank_off(crtc);
6174         assert_vblank_disabled(crtc);
6175
6176         intel_disable_pipe(intel_crtc);
6177
6178         i9xx_pfit_disable(intel_crtc);
6179
6180         for_each_encoder_on_crtc(dev, crtc, encoder)
6181                 if (encoder->post_disable)
6182                         encoder->post_disable(encoder);
6183
6184         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6185                 if (IS_CHERRYVIEW(dev))
6186                         chv_disable_pll(dev_priv, pipe);
6187                 else if (IS_VALLEYVIEW(dev))
6188                         vlv_disable_pll(dev_priv, pipe);
6189                 else
6190                         i9xx_disable_pll(intel_crtc);
6191         }
6192
6193         if (!IS_GEN2(dev))
6194                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6195
6196         intel_crtc->active = false;
6197         intel_update_watermarks(crtc);
6198 }
6199
6200 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6201 {
6202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6203         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6204         enum intel_display_power_domain domain;
6205         unsigned long domains;
6206
6207         if (!intel_crtc->active)
6208                 return;
6209
6210         if (to_intel_plane_state(crtc->primary->state)->visible) {
6211                 intel_crtc_wait_for_pending_flips(crtc);
6212                 intel_pre_disable_primary(crtc);
6213         }
6214
6215         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6216         dev_priv->display.crtc_disable(crtc);
6217
6218         domains = intel_crtc->enabled_power_domains;
6219         for_each_power_domain(domain, domains)
6220                 intel_display_power_put(dev_priv, domain);
6221         intel_crtc->enabled_power_domains = 0;
6222 }
6223
6224 /*
6225  * turn all crtc's off, but do not adjust state
6226  * This has to be paired with a call to intel_modeset_setup_hw_state.
6227  */
6228 int intel_display_suspend(struct drm_device *dev)
6229 {
6230         struct drm_mode_config *config = &dev->mode_config;
6231         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6232         struct drm_atomic_state *state;
6233         struct drm_crtc *crtc;
6234         unsigned crtc_mask = 0;
6235         int ret = 0;
6236
6237         if (WARN_ON(!ctx))
6238                 return 0;
6239
6240         lockdep_assert_held(&ctx->ww_ctx);
6241         state = drm_atomic_state_alloc(dev);
6242         if (WARN_ON(!state))
6243                 return -ENOMEM;
6244
6245         state->acquire_ctx = ctx;
6246         state->allow_modeset = true;
6247
6248         for_each_crtc(dev, crtc) {
6249                 struct drm_crtc_state *crtc_state =
6250                         drm_atomic_get_crtc_state(state, crtc);
6251
6252                 ret = PTR_ERR_OR_ZERO(crtc_state);
6253                 if (ret)
6254                         goto free;
6255
6256                 if (!crtc_state->active)
6257                         continue;
6258
6259                 crtc_state->active = false;
6260                 crtc_mask |= 1 << drm_crtc_index(crtc);
6261         }
6262
6263         if (crtc_mask) {
6264                 ret = intel_set_mode(state);
6265
6266                 if (!ret) {
6267                         for_each_crtc(dev, crtc)
6268                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6269                                         crtc->state->active = true;
6270
6271                         return ret;
6272                 }
6273         }
6274
6275 free:
6276         if (ret)
6277                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6278         drm_atomic_state_free(state);
6279         return ret;
6280 }
6281
6282 /* Master function to enable/disable CRTC and corresponding power wells */
6283 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6284 {
6285         struct drm_device *dev = crtc->dev;
6286         struct drm_mode_config *config = &dev->mode_config;
6287         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6289         struct intel_crtc_state *pipe_config;
6290         struct drm_atomic_state *state;
6291         int ret;
6292
6293         if (enable == intel_crtc->active)
6294                 return 0;
6295
6296         if (enable && !crtc->state->enable)
6297                 return 0;
6298
6299         /* this function should be called with drm_modeset_lock_all for now */
6300         if (WARN_ON(!ctx))
6301                 return -EIO;
6302         lockdep_assert_held(&ctx->ww_ctx);
6303
6304         state = drm_atomic_state_alloc(dev);
6305         if (WARN_ON(!state))
6306                 return -ENOMEM;
6307
6308         state->acquire_ctx = ctx;
6309         state->allow_modeset = true;
6310
6311         pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6312         if (IS_ERR(pipe_config)) {
6313                 ret = PTR_ERR(pipe_config);
6314                 goto err;
6315         }
6316         pipe_config->base.active = enable;
6317
6318         ret = intel_set_mode(state);
6319         if (!ret)
6320                 return ret;
6321
6322 err:
6323         DRM_ERROR("Updating crtc active failed with %i\n", ret);
6324         drm_atomic_state_free(state);
6325         return ret;
6326 }
6327
6328 /**
6329  * Sets the power management mode of the pipe and plane.
6330  */
6331 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6332 {
6333         struct drm_device *dev = crtc->dev;
6334         struct intel_encoder *intel_encoder;
6335         bool enable = false;
6336
6337         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6338                 enable |= intel_encoder->connectors_active;
6339
6340         intel_crtc_control(crtc, enable);
6341 }
6342
6343 void intel_encoder_destroy(struct drm_encoder *encoder)
6344 {
6345         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6346
6347         drm_encoder_cleanup(encoder);
6348         kfree(intel_encoder);
6349 }
6350
6351 /* Simple dpms helper for encoders with just one connector, no cloning and only
6352  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6353  * state of the entire output pipe. */
6354 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6355 {
6356         if (mode == DRM_MODE_DPMS_ON) {
6357                 encoder->connectors_active = true;
6358
6359                 intel_crtc_update_dpms(encoder->base.crtc);
6360         } else {
6361                 encoder->connectors_active = false;
6362
6363                 intel_crtc_update_dpms(encoder->base.crtc);
6364         }
6365 }
6366
6367 /* Cross check the actual hw state with our own modeset state tracking (and it's
6368  * internal consistency). */
6369 static void intel_connector_check_state(struct intel_connector *connector)
6370 {
6371         if (connector->get_hw_state(connector)) {
6372                 struct intel_encoder *encoder = connector->encoder;
6373                 struct drm_crtc *crtc;
6374                 bool encoder_enabled;
6375                 enum pipe pipe;
6376
6377                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6378                               connector->base.base.id,
6379                               connector->base.name);
6380
6381                 /* there is no real hw state for MST connectors */
6382                 if (connector->mst_port)
6383                         return;
6384
6385                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6386                      "wrong connector dpms state\n");
6387                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6388                      "active connector not linked to encoder\n");
6389
6390                 if (encoder) {
6391                         I915_STATE_WARN(!encoder->connectors_active,
6392                              "encoder->connectors_active not set\n");
6393
6394                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6395                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6396                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
6397                                 return;
6398
6399                         crtc = encoder->base.crtc;
6400
6401                         I915_STATE_WARN(!crtc->state->enable,
6402                                         "crtc not enabled\n");
6403                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6404                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6405                              "encoder active on the wrong pipe\n");
6406                 }
6407         }
6408 }
6409
6410 int intel_connector_init(struct intel_connector *connector)
6411 {
6412         struct drm_connector_state *connector_state;
6413
6414         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6415         if (!connector_state)
6416                 return -ENOMEM;
6417
6418         connector->base.state = connector_state;
6419         return 0;
6420 }
6421
6422 struct intel_connector *intel_connector_alloc(void)
6423 {
6424         struct intel_connector *connector;
6425
6426         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6427         if (!connector)
6428                 return NULL;
6429
6430         if (intel_connector_init(connector) < 0) {
6431                 kfree(connector);
6432                 return NULL;
6433         }
6434
6435         return connector;
6436 }
6437
6438 /* Even simpler default implementation, if there's really no special case to
6439  * consider. */
6440 void intel_connector_dpms(struct drm_connector *connector, int mode)
6441 {
6442         /* All the simple cases only support two dpms states. */
6443         if (mode != DRM_MODE_DPMS_ON)
6444                 mode = DRM_MODE_DPMS_OFF;
6445
6446         if (mode == connector->dpms)
6447                 return;
6448
6449         connector->dpms = mode;
6450
6451         /* Only need to change hw state when actually enabled */
6452         if (connector->encoder)
6453                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6454
6455         intel_modeset_check_state(connector->dev);
6456 }
6457
6458 /* Simple connector->get_hw_state implementation for encoders that support only
6459  * one connector and no cloning and hence the encoder state determines the state
6460  * of the connector. */
6461 bool intel_connector_get_hw_state(struct intel_connector *connector)
6462 {
6463         enum pipe pipe = 0;
6464         struct intel_encoder *encoder = connector->encoder;
6465
6466         return encoder->get_hw_state(encoder, &pipe);
6467 }
6468
6469 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6470 {
6471         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6472                 return crtc_state->fdi_lanes;
6473
6474         return 0;
6475 }
6476
6477 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6478                                      struct intel_crtc_state *pipe_config)
6479 {
6480         struct drm_atomic_state *state = pipe_config->base.state;
6481         struct intel_crtc *other_crtc;
6482         struct intel_crtc_state *other_crtc_state;
6483
6484         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6485                       pipe_name(pipe), pipe_config->fdi_lanes);
6486         if (pipe_config->fdi_lanes > 4) {
6487                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6488                               pipe_name(pipe), pipe_config->fdi_lanes);
6489                 return -EINVAL;
6490         }
6491
6492         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6493                 if (pipe_config->fdi_lanes > 2) {
6494                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6495                                       pipe_config->fdi_lanes);
6496                         return -EINVAL;
6497                 } else {
6498                         return 0;
6499                 }
6500         }
6501
6502         if (INTEL_INFO(dev)->num_pipes == 2)
6503                 return 0;
6504
6505         /* Ivybridge 3 pipe is really complicated */
6506         switch (pipe) {
6507         case PIPE_A:
6508                 return 0;
6509         case PIPE_B:
6510                 if (pipe_config->fdi_lanes <= 2)
6511                         return 0;
6512
6513                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6514                 other_crtc_state =
6515                         intel_atomic_get_crtc_state(state, other_crtc);
6516                 if (IS_ERR(other_crtc_state))
6517                         return PTR_ERR(other_crtc_state);
6518
6519                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6520                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6521                                       pipe_name(pipe), pipe_config->fdi_lanes);
6522                         return -EINVAL;
6523                 }
6524                 return 0;
6525         case PIPE_C:
6526                 if (pipe_config->fdi_lanes > 2) {
6527                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6528                                       pipe_name(pipe), pipe_config->fdi_lanes);
6529                         return -EINVAL;
6530                 }
6531
6532                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6533                 other_crtc_state =
6534                         intel_atomic_get_crtc_state(state, other_crtc);
6535                 if (IS_ERR(other_crtc_state))
6536                         return PTR_ERR(other_crtc_state);
6537
6538                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6539                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6540                         return -EINVAL;
6541                 }
6542                 return 0;
6543         default:
6544                 BUG();
6545         }
6546 }
6547
6548 #define RETRY 1
6549 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6550                                        struct intel_crtc_state *pipe_config)
6551 {
6552         struct drm_device *dev = intel_crtc->base.dev;
6553         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6554         int lane, link_bw, fdi_dotclock, ret;
6555         bool needs_recompute = false;
6556
6557 retry:
6558         /* FDI is a binary signal running at ~2.7GHz, encoding
6559          * each output octet as 10 bits. The actual frequency
6560          * is stored as a divider into a 100MHz clock, and the
6561          * mode pixel clock is stored in units of 1KHz.
6562          * Hence the bw of each lane in terms of the mode signal
6563          * is:
6564          */
6565         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6566
6567         fdi_dotclock = adjusted_mode->crtc_clock;
6568
6569         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6570                                            pipe_config->pipe_bpp);
6571
6572         pipe_config->fdi_lanes = lane;
6573
6574         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6575                                link_bw, &pipe_config->fdi_m_n);
6576
6577         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6578                                        intel_crtc->pipe, pipe_config);
6579         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6580                 pipe_config->pipe_bpp -= 2*3;
6581                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6582                               pipe_config->pipe_bpp);
6583                 needs_recompute = true;
6584                 pipe_config->bw_constrained = true;
6585
6586                 goto retry;
6587         }
6588
6589         if (needs_recompute)
6590                 return RETRY;
6591
6592         return ret;
6593 }
6594
6595 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6596                                      struct intel_crtc_state *pipe_config)
6597 {
6598         if (pipe_config->pipe_bpp > 24)
6599                 return false;
6600
6601         /* HSW can handle pixel rate up to cdclk? */
6602         if (IS_HASWELL(dev_priv->dev))
6603                 return true;
6604
6605         /*
6606          * We compare against max which means we must take
6607          * the increased cdclk requirement into account when
6608          * calculating the new cdclk.
6609          *
6610          * Should measure whether using a lower cdclk w/o IPS
6611          */
6612         return ilk_pipe_pixel_rate(pipe_config) <=
6613                 dev_priv->max_cdclk_freq * 95 / 100;
6614 }
6615
6616 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6617                                    struct intel_crtc_state *pipe_config)
6618 {
6619         struct drm_device *dev = crtc->base.dev;
6620         struct drm_i915_private *dev_priv = dev->dev_private;
6621
6622         pipe_config->ips_enabled = i915.enable_ips &&
6623                 hsw_crtc_supports_ips(crtc) &&
6624                 pipe_config_supports_ips(dev_priv, pipe_config);
6625 }
6626
6627 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6628                                      struct intel_crtc_state *pipe_config)
6629 {
6630         struct drm_device *dev = crtc->base.dev;
6631         struct drm_i915_private *dev_priv = dev->dev_private;
6632         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6633
6634         /* FIXME should check pixel clock limits on all platforms */
6635         if (INTEL_INFO(dev)->gen < 4) {
6636                 int clock_limit = dev_priv->max_cdclk_freq;
6637
6638                 /*
6639                  * Enable pixel doubling when the dot clock
6640                  * is > 90% of the (display) core speed.
6641                  *
6642                  * GDG double wide on either pipe,
6643                  * otherwise pipe A only.
6644                  */
6645                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6646                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6647                         clock_limit *= 2;
6648                         pipe_config->double_wide = true;
6649                 }
6650
6651                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6652                         return -EINVAL;
6653         }
6654
6655         /*
6656          * Pipe horizontal size must be even in:
6657          * - DVO ganged mode
6658          * - LVDS dual channel mode
6659          * - Double wide pipe
6660          */
6661         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6662              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6663                 pipe_config->pipe_src_w &= ~1;
6664
6665         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6666          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6667          */
6668         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6669                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6670                 return -EINVAL;
6671
6672         if (HAS_IPS(dev))
6673                 hsw_compute_ips_config(crtc, pipe_config);
6674
6675         if (pipe_config->has_pch_encoder)
6676                 return ironlake_fdi_compute_config(crtc, pipe_config);
6677
6678         return 0;
6679 }
6680
6681 static int skylake_get_display_clock_speed(struct drm_device *dev)
6682 {
6683         struct drm_i915_private *dev_priv = to_i915(dev);
6684         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6685         uint32_t cdctl = I915_READ(CDCLK_CTL);
6686         uint32_t linkrate;
6687
6688         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6689                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6690
6691         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6692                 return 540000;
6693
6694         linkrate = (I915_READ(DPLL_CTRL1) &
6695                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6696
6697         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6698             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6699                 /* vco 8640 */
6700                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6701                 case CDCLK_FREQ_450_432:
6702                         return 432000;
6703                 case CDCLK_FREQ_337_308:
6704                         return 308570;
6705                 case CDCLK_FREQ_675_617:
6706                         return 617140;
6707                 default:
6708                         WARN(1, "Unknown cd freq selection\n");
6709                 }
6710         } else {
6711                 /* vco 8100 */
6712                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6713                 case CDCLK_FREQ_450_432:
6714                         return 450000;
6715                 case CDCLK_FREQ_337_308:
6716                         return 337500;
6717                 case CDCLK_FREQ_675_617:
6718                         return 675000;
6719                 default:
6720                         WARN(1, "Unknown cd freq selection\n");
6721                 }
6722         }
6723
6724         /* error case, do as if DPLL0 isn't enabled */
6725         return 24000;
6726 }
6727
6728 static int broxton_get_display_clock_speed(struct drm_device *dev)
6729 {
6730         struct drm_i915_private *dev_priv = to_i915(dev);
6731         uint32_t cdctl = I915_READ(CDCLK_CTL);
6732         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6733         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6734         int cdclk;
6735
6736         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6737                 return 19200;
6738
6739         cdclk = 19200 * pll_ratio / 2;
6740
6741         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6742         case BXT_CDCLK_CD2X_DIV_SEL_1:
6743                 return cdclk;  /* 576MHz or 624MHz */
6744         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6745                 return cdclk * 2 / 3; /* 384MHz */
6746         case BXT_CDCLK_CD2X_DIV_SEL_2:
6747                 return cdclk / 2; /* 288MHz */
6748         case BXT_CDCLK_CD2X_DIV_SEL_4:
6749                 return cdclk / 4; /* 144MHz */
6750         }
6751
6752         /* error case, do as if DE PLL isn't enabled */
6753         return 19200;
6754 }
6755
6756 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6757 {
6758         struct drm_i915_private *dev_priv = dev->dev_private;
6759         uint32_t lcpll = I915_READ(LCPLL_CTL);
6760         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6761
6762         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6763                 return 800000;
6764         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6765                 return 450000;
6766         else if (freq == LCPLL_CLK_FREQ_450)
6767                 return 450000;
6768         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6769                 return 540000;
6770         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6771                 return 337500;
6772         else
6773                 return 675000;
6774 }
6775
6776 static int haswell_get_display_clock_speed(struct drm_device *dev)
6777 {
6778         struct drm_i915_private *dev_priv = dev->dev_private;
6779         uint32_t lcpll = I915_READ(LCPLL_CTL);
6780         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6781
6782         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6783                 return 800000;
6784         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6785                 return 450000;
6786         else if (freq == LCPLL_CLK_FREQ_450)
6787                 return 450000;
6788         else if (IS_HSW_ULT(dev))
6789                 return 337500;
6790         else
6791                 return 540000;
6792 }
6793
6794 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6795 {
6796         struct drm_i915_private *dev_priv = dev->dev_private;
6797         u32 val;
6798         int divider;
6799
6800         if (dev_priv->hpll_freq == 0)
6801                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6802
6803         mutex_lock(&dev_priv->sb_lock);
6804         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6805         mutex_unlock(&dev_priv->sb_lock);
6806
6807         divider = val & DISPLAY_FREQUENCY_VALUES;
6808
6809         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6810              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6811              "cdclk change in progress\n");
6812
6813         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6814 }
6815
6816 static int ilk_get_display_clock_speed(struct drm_device *dev)
6817 {
6818         return 450000;
6819 }
6820
6821 static int i945_get_display_clock_speed(struct drm_device *dev)
6822 {
6823         return 400000;
6824 }
6825
6826 static int i915_get_display_clock_speed(struct drm_device *dev)
6827 {
6828         return 333333;
6829 }
6830
6831 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6832 {
6833         return 200000;
6834 }
6835
6836 static int pnv_get_display_clock_speed(struct drm_device *dev)
6837 {
6838         u16 gcfgc = 0;
6839
6840         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6841
6842         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6843         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6844                 return 266667;
6845         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6846                 return 333333;
6847         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6848                 return 444444;
6849         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6850                 return 200000;
6851         default:
6852                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6853         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6854                 return 133333;
6855         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6856                 return 166667;
6857         }
6858 }
6859
6860 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6861 {
6862         u16 gcfgc = 0;
6863
6864         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6865
6866         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6867                 return 133333;
6868         else {
6869                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6870                 case GC_DISPLAY_CLOCK_333_MHZ:
6871                         return 333333;
6872                 default:
6873                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6874                         return 190000;
6875                 }
6876         }
6877 }
6878
6879 static int i865_get_display_clock_speed(struct drm_device *dev)
6880 {
6881         return 266667;
6882 }
6883
6884 static int i85x_get_display_clock_speed(struct drm_device *dev)
6885 {
6886         u16 hpllcc = 0;
6887
6888         /*
6889          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6890          * encoding is different :(
6891          * FIXME is this the right way to detect 852GM/852GMV?
6892          */
6893         if (dev->pdev->revision == 0x1)
6894                 return 133333;
6895
6896         pci_bus_read_config_word(dev->pdev->bus,
6897                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6898
6899         /* Assume that the hardware is in the high speed state.  This
6900          * should be the default.
6901          */
6902         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6903         case GC_CLOCK_133_200:
6904         case GC_CLOCK_133_200_2:
6905         case GC_CLOCK_100_200:
6906                 return 200000;
6907         case GC_CLOCK_166_250:
6908                 return 250000;
6909         case GC_CLOCK_100_133:
6910                 return 133333;
6911         case GC_CLOCK_133_266:
6912         case GC_CLOCK_133_266_2:
6913         case GC_CLOCK_166_266:
6914                 return 266667;
6915         }
6916
6917         /* Shouldn't happen */
6918         return 0;
6919 }
6920
6921 static int i830_get_display_clock_speed(struct drm_device *dev)
6922 {
6923         return 133333;
6924 }
6925
6926 static unsigned int intel_hpll_vco(struct drm_device *dev)
6927 {
6928         struct drm_i915_private *dev_priv = dev->dev_private;
6929         static const unsigned int blb_vco[8] = {
6930                 [0] = 3200000,
6931                 [1] = 4000000,
6932                 [2] = 5333333,
6933                 [3] = 4800000,
6934                 [4] = 6400000,
6935         };
6936         static const unsigned int pnv_vco[8] = {
6937                 [0] = 3200000,
6938                 [1] = 4000000,
6939                 [2] = 5333333,
6940                 [3] = 4800000,
6941                 [4] = 2666667,
6942         };
6943         static const unsigned int cl_vco[8] = {
6944                 [0] = 3200000,
6945                 [1] = 4000000,
6946                 [2] = 5333333,
6947                 [3] = 6400000,
6948                 [4] = 3333333,
6949                 [5] = 3566667,
6950                 [6] = 4266667,
6951         };
6952         static const unsigned int elk_vco[8] = {
6953                 [0] = 3200000,
6954                 [1] = 4000000,
6955                 [2] = 5333333,
6956                 [3] = 4800000,
6957         };
6958         static const unsigned int ctg_vco[8] = {
6959                 [0] = 3200000,
6960                 [1] = 4000000,
6961                 [2] = 5333333,
6962                 [3] = 6400000,
6963                 [4] = 2666667,
6964                 [5] = 4266667,
6965         };
6966         const unsigned int *vco_table;
6967         unsigned int vco;
6968         uint8_t tmp = 0;
6969
6970         /* FIXME other chipsets? */
6971         if (IS_GM45(dev))
6972                 vco_table = ctg_vco;
6973         else if (IS_G4X(dev))
6974                 vco_table = elk_vco;
6975         else if (IS_CRESTLINE(dev))
6976                 vco_table = cl_vco;
6977         else if (IS_PINEVIEW(dev))
6978                 vco_table = pnv_vco;
6979         else if (IS_G33(dev))
6980                 vco_table = blb_vco;
6981         else
6982                 return 0;
6983
6984         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6985
6986         vco = vco_table[tmp & 0x7];
6987         if (vco == 0)
6988                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6989         else
6990                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6991
6992         return vco;
6993 }
6994
6995 static int gm45_get_display_clock_speed(struct drm_device *dev)
6996 {
6997         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6998         uint16_t tmp = 0;
6999
7000         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7001
7002         cdclk_sel = (tmp >> 12) & 0x1;
7003
7004         switch (vco) {
7005         case 2666667:
7006         case 4000000:
7007         case 5333333:
7008                 return cdclk_sel ? 333333 : 222222;
7009         case 3200000:
7010                 return cdclk_sel ? 320000 : 228571;
7011         default:
7012                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7013                 return 222222;
7014         }
7015 }
7016
7017 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7018 {
7019         static const uint8_t div_3200[] = { 16, 10,  8 };
7020         static const uint8_t div_4000[] = { 20, 12, 10 };
7021         static const uint8_t div_5333[] = { 24, 16, 14 };
7022         const uint8_t *div_table;
7023         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7024         uint16_t tmp = 0;
7025
7026         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7027
7028         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7029
7030         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7031                 goto fail;
7032
7033         switch (vco) {
7034         case 3200000:
7035                 div_table = div_3200;
7036                 break;
7037         case 4000000:
7038                 div_table = div_4000;
7039                 break;
7040         case 5333333:
7041                 div_table = div_5333;
7042                 break;
7043         default:
7044                 goto fail;
7045         }
7046
7047         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7048
7049 fail:
7050         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7051         return 200000;
7052 }
7053
7054 static int g33_get_display_clock_speed(struct drm_device *dev)
7055 {
7056         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7057         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7058         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7059         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7060         const uint8_t *div_table;
7061         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7062         uint16_t tmp = 0;
7063
7064         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7065
7066         cdclk_sel = (tmp >> 4) & 0x7;
7067
7068         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7069                 goto fail;
7070
7071         switch (vco) {
7072         case 3200000:
7073                 div_table = div_3200;
7074                 break;
7075         case 4000000:
7076                 div_table = div_4000;
7077                 break;
7078         case 4800000:
7079                 div_table = div_4800;
7080                 break;
7081         case 5333333:
7082                 div_table = div_5333;
7083                 break;
7084         default:
7085                 goto fail;
7086         }
7087
7088         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7089
7090 fail:
7091         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7092         return 190476;
7093 }
7094
7095 static void
7096 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7097 {
7098         while (*num > DATA_LINK_M_N_MASK ||
7099                *den > DATA_LINK_M_N_MASK) {
7100                 *num >>= 1;
7101                 *den >>= 1;
7102         }
7103 }
7104
7105 static void compute_m_n(unsigned int m, unsigned int n,
7106                         uint32_t *ret_m, uint32_t *ret_n)
7107 {
7108         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7109         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7110         intel_reduce_m_n_ratio(ret_m, ret_n);
7111 }
7112
7113 void
7114 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7115                        int pixel_clock, int link_clock,
7116                        struct intel_link_m_n *m_n)
7117 {
7118         m_n->tu = 64;
7119
7120         compute_m_n(bits_per_pixel * pixel_clock,
7121                     link_clock * nlanes * 8,
7122                     &m_n->gmch_m, &m_n->gmch_n);
7123
7124         compute_m_n(pixel_clock, link_clock,
7125                     &m_n->link_m, &m_n->link_n);
7126 }
7127
7128 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7129 {
7130         if (i915.panel_use_ssc >= 0)
7131                 return i915.panel_use_ssc != 0;
7132         return dev_priv->vbt.lvds_use_ssc
7133                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7134 }
7135
7136 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7137                            int num_connectors)
7138 {
7139         struct drm_device *dev = crtc_state->base.crtc->dev;
7140         struct drm_i915_private *dev_priv = dev->dev_private;
7141         int refclk;
7142
7143         WARN_ON(!crtc_state->base.state);
7144
7145         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7146                 refclk = 100000;
7147         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7148             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7149                 refclk = dev_priv->vbt.lvds_ssc_freq;
7150                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7151         } else if (!IS_GEN2(dev)) {
7152                 refclk = 96000;
7153         } else {
7154                 refclk = 48000;
7155         }
7156
7157         return refclk;
7158 }
7159
7160 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7161 {
7162         return (1 << dpll->n) << 16 | dpll->m2;
7163 }
7164
7165 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7166 {
7167         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7168 }
7169
7170 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7171                                      struct intel_crtc_state *crtc_state,
7172                                      intel_clock_t *reduced_clock)
7173 {
7174         struct drm_device *dev = crtc->base.dev;
7175         u32 fp, fp2 = 0;
7176
7177         if (IS_PINEVIEW(dev)) {
7178                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7179                 if (reduced_clock)
7180                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7181         } else {
7182                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7183                 if (reduced_clock)
7184                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7185         }
7186
7187         crtc_state->dpll_hw_state.fp0 = fp;
7188
7189         crtc->lowfreq_avail = false;
7190         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7191             reduced_clock) {
7192                 crtc_state->dpll_hw_state.fp1 = fp2;
7193                 crtc->lowfreq_avail = true;
7194         } else {
7195                 crtc_state->dpll_hw_state.fp1 = fp;
7196         }
7197 }
7198
7199 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7200                 pipe)
7201 {
7202         u32 reg_val;
7203
7204         /*
7205          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7206          * and set it to a reasonable value instead.
7207          */
7208         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7209         reg_val &= 0xffffff00;
7210         reg_val |= 0x00000030;
7211         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7212
7213         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7214         reg_val &= 0x8cffffff;
7215         reg_val = 0x8c000000;
7216         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7217
7218         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7219         reg_val &= 0xffffff00;
7220         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7221
7222         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7223         reg_val &= 0x00ffffff;
7224         reg_val |= 0xb0000000;
7225         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7226 }
7227
7228 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7229                                          struct intel_link_m_n *m_n)
7230 {
7231         struct drm_device *dev = crtc->base.dev;
7232         struct drm_i915_private *dev_priv = dev->dev_private;
7233         int pipe = crtc->pipe;
7234
7235         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7236         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7237         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7238         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7239 }
7240
7241 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7242                                          struct intel_link_m_n *m_n,
7243                                          struct intel_link_m_n *m2_n2)
7244 {
7245         struct drm_device *dev = crtc->base.dev;
7246         struct drm_i915_private *dev_priv = dev->dev_private;
7247         int pipe = crtc->pipe;
7248         enum transcoder transcoder = crtc->config->cpu_transcoder;
7249
7250         if (INTEL_INFO(dev)->gen >= 5) {
7251                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7252                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7253                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7254                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7255                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7256                  * for gen < 8) and if DRRS is supported (to make sure the
7257                  * registers are not unnecessarily accessed).
7258                  */
7259                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7260                         crtc->config->has_drrs) {
7261                         I915_WRITE(PIPE_DATA_M2(transcoder),
7262                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7263                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7264                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7265                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7266                 }
7267         } else {
7268                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7269                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7270                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7271                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7272         }
7273 }
7274
7275 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7276 {
7277         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7278
7279         if (m_n == M1_N1) {
7280                 dp_m_n = &crtc->config->dp_m_n;
7281                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7282         } else if (m_n == M2_N2) {
7283
7284                 /*
7285                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7286                  * needs to be programmed into M1_N1.
7287                  */
7288                 dp_m_n = &crtc->config->dp_m2_n2;
7289         } else {
7290                 DRM_ERROR("Unsupported divider value\n");
7291                 return;
7292         }
7293
7294         if (crtc->config->has_pch_encoder)
7295                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7296         else
7297                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7298 }
7299
7300 static void vlv_compute_dpll(struct intel_crtc *crtc,
7301                              struct intel_crtc_state *pipe_config)
7302 {
7303         u32 dpll, dpll_md;
7304
7305         /*
7306          * Enable DPIO clock input. We should never disable the reference
7307          * clock for pipe B, since VGA hotplug / manual detection depends
7308          * on it.
7309          */
7310         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7311                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7312         /* We should never disable this, set it here for state tracking */
7313         if (crtc->pipe == PIPE_B)
7314                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7315         dpll |= DPLL_VCO_ENABLE;
7316         pipe_config->dpll_hw_state.dpll = dpll;
7317
7318         dpll_md = (pipe_config->pixel_multiplier - 1)
7319                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7320         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7321 }
7322
7323 static void vlv_prepare_pll(struct intel_crtc *crtc,
7324                             const struct intel_crtc_state *pipe_config)
7325 {
7326         struct drm_device *dev = crtc->base.dev;
7327         struct drm_i915_private *dev_priv = dev->dev_private;
7328         int pipe = crtc->pipe;
7329         u32 mdiv;
7330         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7331         u32 coreclk, reg_val;
7332
7333         mutex_lock(&dev_priv->sb_lock);
7334
7335         bestn = pipe_config->dpll.n;
7336         bestm1 = pipe_config->dpll.m1;
7337         bestm2 = pipe_config->dpll.m2;
7338         bestp1 = pipe_config->dpll.p1;
7339         bestp2 = pipe_config->dpll.p2;
7340
7341         /* See eDP HDMI DPIO driver vbios notes doc */
7342
7343         /* PLL B needs special handling */
7344         if (pipe == PIPE_B)
7345                 vlv_pllb_recal_opamp(dev_priv, pipe);
7346
7347         /* Set up Tx target for periodic Rcomp update */
7348         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7349
7350         /* Disable target IRef on PLL */
7351         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7352         reg_val &= 0x00ffffff;
7353         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7354
7355         /* Disable fast lock */
7356         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7357
7358         /* Set idtafcrecal before PLL is enabled */
7359         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7360         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7361         mdiv |= ((bestn << DPIO_N_SHIFT));
7362         mdiv |= (1 << DPIO_K_SHIFT);
7363
7364         /*
7365          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7366          * but we don't support that).
7367          * Note: don't use the DAC post divider as it seems unstable.
7368          */
7369         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7370         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7371
7372         mdiv |= DPIO_ENABLE_CALIBRATION;
7373         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7374
7375         /* Set HBR and RBR LPF coefficients */
7376         if (pipe_config->port_clock == 162000 ||
7377             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7378             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7379                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7380                                  0x009f0003);
7381         else
7382                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7383                                  0x00d0000f);
7384
7385         if (pipe_config->has_dp_encoder) {
7386                 /* Use SSC source */
7387                 if (pipe == PIPE_A)
7388                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7389                                          0x0df40000);
7390                 else
7391                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7392                                          0x0df70000);
7393         } else { /* HDMI or VGA */
7394                 /* Use bend source */
7395                 if (pipe == PIPE_A)
7396                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7397                                          0x0df70000);
7398                 else
7399                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7400                                          0x0df40000);
7401         }
7402
7403         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7404         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7405         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7406             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7407                 coreclk |= 0x01000000;
7408         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7409
7410         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7411         mutex_unlock(&dev_priv->sb_lock);
7412 }
7413
7414 static void chv_compute_dpll(struct intel_crtc *crtc,
7415                              struct intel_crtc_state *pipe_config)
7416 {
7417         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7418                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7419                 DPLL_VCO_ENABLE;
7420         if (crtc->pipe != PIPE_A)
7421                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7422
7423         pipe_config->dpll_hw_state.dpll_md =
7424                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7425 }
7426
7427 static void chv_prepare_pll(struct intel_crtc *crtc,
7428                             const struct intel_crtc_state *pipe_config)
7429 {
7430         struct drm_device *dev = crtc->base.dev;
7431         struct drm_i915_private *dev_priv = dev->dev_private;
7432         int pipe = crtc->pipe;
7433         int dpll_reg = DPLL(crtc->pipe);
7434         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7435         u32 loopfilter, tribuf_calcntr;
7436         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7437         u32 dpio_val;
7438         int vco;
7439
7440         bestn = pipe_config->dpll.n;
7441         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7442         bestm1 = pipe_config->dpll.m1;
7443         bestm2 = pipe_config->dpll.m2 >> 22;
7444         bestp1 = pipe_config->dpll.p1;
7445         bestp2 = pipe_config->dpll.p2;
7446         vco = pipe_config->dpll.vco;
7447         dpio_val = 0;
7448         loopfilter = 0;
7449
7450         /*
7451          * Enable Refclk and SSC
7452          */
7453         I915_WRITE(dpll_reg,
7454                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7455
7456         mutex_lock(&dev_priv->sb_lock);
7457
7458         /* p1 and p2 divider */
7459         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7460                         5 << DPIO_CHV_S1_DIV_SHIFT |
7461                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7462                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7463                         1 << DPIO_CHV_K_DIV_SHIFT);
7464
7465         /* Feedback post-divider - m2 */
7466         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7467
7468         /* Feedback refclk divider - n and m1 */
7469         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7470                         DPIO_CHV_M1_DIV_BY_2 |
7471                         1 << DPIO_CHV_N_DIV_SHIFT);
7472
7473         /* M2 fraction division */
7474         if (bestm2_frac)
7475                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7476
7477         /* M2 fraction division enable */
7478         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7479         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7480         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7481         if (bestm2_frac)
7482                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7483         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7484
7485         /* Program digital lock detect threshold */
7486         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7487         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7488                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7489         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7490         if (!bestm2_frac)
7491                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7492         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7493
7494         /* Loop filter */
7495         if (vco == 5400000) {
7496                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7497                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7498                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7499                 tribuf_calcntr = 0x9;
7500         } else if (vco <= 6200000) {
7501                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7502                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7503                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7504                 tribuf_calcntr = 0x9;
7505         } else if (vco <= 6480000) {
7506                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7507                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7508                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7509                 tribuf_calcntr = 0x8;
7510         } else {
7511                 /* Not supported. Apply the same limits as in the max case */
7512                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7513                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7514                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7515                 tribuf_calcntr = 0;
7516         }
7517         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7518
7519         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7520         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7521         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7522         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7523
7524         /* AFC Recal */
7525         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7526                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7527                         DPIO_AFC_RECAL);
7528
7529         mutex_unlock(&dev_priv->sb_lock);
7530 }
7531
7532 /**
7533  * vlv_force_pll_on - forcibly enable just the PLL
7534  * @dev_priv: i915 private structure
7535  * @pipe: pipe PLL to enable
7536  * @dpll: PLL configuration
7537  *
7538  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7539  * in cases where we need the PLL enabled even when @pipe is not going to
7540  * be enabled.
7541  */
7542 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7543                       const struct dpll *dpll)
7544 {
7545         struct intel_crtc *crtc =
7546                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7547         struct intel_crtc_state pipe_config = {
7548                 .base.crtc = &crtc->base,
7549                 .pixel_multiplier = 1,
7550                 .dpll = *dpll,
7551         };
7552
7553         if (IS_CHERRYVIEW(dev)) {
7554                 chv_compute_dpll(crtc, &pipe_config);
7555                 chv_prepare_pll(crtc, &pipe_config);
7556                 chv_enable_pll(crtc, &pipe_config);
7557         } else {
7558                 vlv_compute_dpll(crtc, &pipe_config);
7559                 vlv_prepare_pll(crtc, &pipe_config);
7560                 vlv_enable_pll(crtc, &pipe_config);
7561         }
7562 }
7563
7564 /**
7565  * vlv_force_pll_off - forcibly disable just the PLL
7566  * @dev_priv: i915 private structure
7567  * @pipe: pipe PLL to disable
7568  *
7569  * Disable the PLL for @pipe. To be used in cases where we need
7570  * the PLL enabled even when @pipe is not going to be enabled.
7571  */
7572 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7573 {
7574         if (IS_CHERRYVIEW(dev))
7575                 chv_disable_pll(to_i915(dev), pipe);
7576         else
7577                 vlv_disable_pll(to_i915(dev), pipe);
7578 }
7579
7580 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7581                               struct intel_crtc_state *crtc_state,
7582                               intel_clock_t *reduced_clock,
7583                               int num_connectors)
7584 {
7585         struct drm_device *dev = crtc->base.dev;
7586         struct drm_i915_private *dev_priv = dev->dev_private;
7587         u32 dpll;
7588         bool is_sdvo;
7589         struct dpll *clock = &crtc_state->dpll;
7590
7591         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7592
7593         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7594                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7595
7596         dpll = DPLL_VGA_MODE_DIS;
7597
7598         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7599                 dpll |= DPLLB_MODE_LVDS;
7600         else
7601                 dpll |= DPLLB_MODE_DAC_SERIAL;
7602
7603         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7604                 dpll |= (crtc_state->pixel_multiplier - 1)
7605                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7606         }
7607
7608         if (is_sdvo)
7609                 dpll |= DPLL_SDVO_HIGH_SPEED;
7610
7611         if (crtc_state->has_dp_encoder)
7612                 dpll |= DPLL_SDVO_HIGH_SPEED;
7613
7614         /* compute bitmask from p1 value */
7615         if (IS_PINEVIEW(dev))
7616                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7617         else {
7618                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7619                 if (IS_G4X(dev) && reduced_clock)
7620                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7621         }
7622         switch (clock->p2) {
7623         case 5:
7624                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7625                 break;
7626         case 7:
7627                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7628                 break;
7629         case 10:
7630                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7631                 break;
7632         case 14:
7633                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7634                 break;
7635         }
7636         if (INTEL_INFO(dev)->gen >= 4)
7637                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7638
7639         if (crtc_state->sdvo_tv_clock)
7640                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7641         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7642                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7643                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7644         else
7645                 dpll |= PLL_REF_INPUT_DREFCLK;
7646
7647         dpll |= DPLL_VCO_ENABLE;
7648         crtc_state->dpll_hw_state.dpll = dpll;
7649
7650         if (INTEL_INFO(dev)->gen >= 4) {
7651                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7652                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7653                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7654         }
7655 }
7656
7657 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7658                               struct intel_crtc_state *crtc_state,
7659                               intel_clock_t *reduced_clock,
7660                               int num_connectors)
7661 {
7662         struct drm_device *dev = crtc->base.dev;
7663         struct drm_i915_private *dev_priv = dev->dev_private;
7664         u32 dpll;
7665         struct dpll *clock = &crtc_state->dpll;
7666
7667         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7668
7669         dpll = DPLL_VGA_MODE_DIS;
7670
7671         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7672                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7673         } else {
7674                 if (clock->p1 == 2)
7675                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7676                 else
7677                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7678                 if (clock->p2 == 4)
7679                         dpll |= PLL_P2_DIVIDE_BY_4;
7680         }
7681
7682         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7683                 dpll |= DPLL_DVO_2X_MODE;
7684
7685         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7686                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7687                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7688         else
7689                 dpll |= PLL_REF_INPUT_DREFCLK;
7690
7691         dpll |= DPLL_VCO_ENABLE;
7692         crtc_state->dpll_hw_state.dpll = dpll;
7693 }
7694
7695 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7696 {
7697         struct drm_device *dev = intel_crtc->base.dev;
7698         struct drm_i915_private *dev_priv = dev->dev_private;
7699         enum pipe pipe = intel_crtc->pipe;
7700         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7701         struct drm_display_mode *adjusted_mode =
7702                 &intel_crtc->config->base.adjusted_mode;
7703         uint32_t crtc_vtotal, crtc_vblank_end;
7704         int vsyncshift = 0;
7705
7706         /* We need to be careful not to changed the adjusted mode, for otherwise
7707          * the hw state checker will get angry at the mismatch. */
7708         crtc_vtotal = adjusted_mode->crtc_vtotal;
7709         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7710
7711         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7712                 /* the chip adds 2 halflines automatically */
7713                 crtc_vtotal -= 1;
7714                 crtc_vblank_end -= 1;
7715
7716                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7717                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7718                 else
7719                         vsyncshift = adjusted_mode->crtc_hsync_start -
7720                                 adjusted_mode->crtc_htotal / 2;
7721                 if (vsyncshift < 0)
7722                         vsyncshift += adjusted_mode->crtc_htotal;
7723         }
7724
7725         if (INTEL_INFO(dev)->gen > 3)
7726                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7727
7728         I915_WRITE(HTOTAL(cpu_transcoder),
7729                    (adjusted_mode->crtc_hdisplay - 1) |
7730                    ((adjusted_mode->crtc_htotal - 1) << 16));
7731         I915_WRITE(HBLANK(cpu_transcoder),
7732                    (adjusted_mode->crtc_hblank_start - 1) |
7733                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7734         I915_WRITE(HSYNC(cpu_transcoder),
7735                    (adjusted_mode->crtc_hsync_start - 1) |
7736                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7737
7738         I915_WRITE(VTOTAL(cpu_transcoder),
7739                    (adjusted_mode->crtc_vdisplay - 1) |
7740                    ((crtc_vtotal - 1) << 16));
7741         I915_WRITE(VBLANK(cpu_transcoder),
7742                    (adjusted_mode->crtc_vblank_start - 1) |
7743                    ((crtc_vblank_end - 1) << 16));
7744         I915_WRITE(VSYNC(cpu_transcoder),
7745                    (adjusted_mode->crtc_vsync_start - 1) |
7746                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7747
7748         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7749          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7750          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7751          * bits. */
7752         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7753             (pipe == PIPE_B || pipe == PIPE_C))
7754                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7755
7756         /* pipesrc controls the size that is scaled from, which should
7757          * always be the user's requested size.
7758          */
7759         I915_WRITE(PIPESRC(pipe),
7760                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7761                    (intel_crtc->config->pipe_src_h - 1));
7762 }
7763
7764 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7765                                    struct intel_crtc_state *pipe_config)
7766 {
7767         struct drm_device *dev = crtc->base.dev;
7768         struct drm_i915_private *dev_priv = dev->dev_private;
7769         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7770         uint32_t tmp;
7771
7772         tmp = I915_READ(HTOTAL(cpu_transcoder));
7773         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7774         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7775         tmp = I915_READ(HBLANK(cpu_transcoder));
7776         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7777         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7778         tmp = I915_READ(HSYNC(cpu_transcoder));
7779         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7780         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7781
7782         tmp = I915_READ(VTOTAL(cpu_transcoder));
7783         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7784         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7785         tmp = I915_READ(VBLANK(cpu_transcoder));
7786         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7787         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7788         tmp = I915_READ(VSYNC(cpu_transcoder));
7789         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7790         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7791
7792         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7793                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7794                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7795                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7796         }
7797
7798         tmp = I915_READ(PIPESRC(crtc->pipe));
7799         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7800         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7801
7802         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7803         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7804 }
7805
7806 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7807                                  struct intel_crtc_state *pipe_config)
7808 {
7809         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7810         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7811         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7812         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7813
7814         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7815         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7816         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7817         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7818
7819         mode->flags = pipe_config->base.adjusted_mode.flags;
7820
7821         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7822         mode->flags |= pipe_config->base.adjusted_mode.flags;
7823 }
7824
7825 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7826 {
7827         struct drm_device *dev = intel_crtc->base.dev;
7828         struct drm_i915_private *dev_priv = dev->dev_private;
7829         uint32_t pipeconf;
7830
7831         pipeconf = 0;
7832
7833         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7834             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7835                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7836
7837         if (intel_crtc->config->double_wide)
7838                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7839
7840         /* only g4x and later have fancy bpc/dither controls */
7841         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7842                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7843                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7844                         pipeconf |= PIPECONF_DITHER_EN |
7845                                     PIPECONF_DITHER_TYPE_SP;
7846
7847                 switch (intel_crtc->config->pipe_bpp) {
7848                 case 18:
7849                         pipeconf |= PIPECONF_6BPC;
7850                         break;
7851                 case 24:
7852                         pipeconf |= PIPECONF_8BPC;
7853                         break;
7854                 case 30:
7855                         pipeconf |= PIPECONF_10BPC;
7856                         break;
7857                 default:
7858                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7859                         BUG();
7860                 }
7861         }
7862
7863         if (HAS_PIPE_CXSR(dev)) {
7864                 if (intel_crtc->lowfreq_avail) {
7865                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7866                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7867                 } else {
7868                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7869                 }
7870         }
7871
7872         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7873                 if (INTEL_INFO(dev)->gen < 4 ||
7874                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7875                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7876                 else
7877                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7878         } else
7879                 pipeconf |= PIPECONF_PROGRESSIVE;
7880
7881         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7882                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7883
7884         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7885         POSTING_READ(PIPECONF(intel_crtc->pipe));
7886 }
7887
7888 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7889                                    struct intel_crtc_state *crtc_state)
7890 {
7891         struct drm_device *dev = crtc->base.dev;
7892         struct drm_i915_private *dev_priv = dev->dev_private;
7893         int refclk, num_connectors = 0;
7894         intel_clock_t clock;
7895         bool ok;
7896         bool is_dsi = false;
7897         struct intel_encoder *encoder;
7898         const intel_limit_t *limit;
7899         struct drm_atomic_state *state = crtc_state->base.state;
7900         struct drm_connector *connector;
7901         struct drm_connector_state *connector_state;
7902         int i;
7903
7904         memset(&crtc_state->dpll_hw_state, 0,
7905                sizeof(crtc_state->dpll_hw_state));
7906
7907         for_each_connector_in_state(state, connector, connector_state, i) {
7908                 if (connector_state->crtc != &crtc->base)
7909                         continue;
7910
7911                 encoder = to_intel_encoder(connector_state->best_encoder);
7912
7913                 switch (encoder->type) {
7914                 case INTEL_OUTPUT_DSI:
7915                         is_dsi = true;
7916                         break;
7917                 default:
7918                         break;
7919                 }
7920
7921                 num_connectors++;
7922         }
7923
7924         if (is_dsi)
7925                 return 0;
7926
7927         if (!crtc_state->clock_set) {
7928                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7929
7930                 /*
7931                  * Returns a set of divisors for the desired target clock with
7932                  * the given refclk, or FALSE.  The returned values represent
7933                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7934                  * 2) / p1 / p2.
7935                  */
7936                 limit = intel_limit(crtc_state, refclk);
7937                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7938                                                  crtc_state->port_clock,
7939                                                  refclk, NULL, &clock);
7940                 if (!ok) {
7941                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7942                         return -EINVAL;
7943                 }
7944
7945                 /* Compat-code for transition, will disappear. */
7946                 crtc_state->dpll.n = clock.n;
7947                 crtc_state->dpll.m1 = clock.m1;
7948                 crtc_state->dpll.m2 = clock.m2;
7949                 crtc_state->dpll.p1 = clock.p1;
7950                 crtc_state->dpll.p2 = clock.p2;
7951         }
7952
7953         if (IS_GEN2(dev)) {
7954                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7955                                   num_connectors);
7956         } else if (IS_CHERRYVIEW(dev)) {
7957                 chv_compute_dpll(crtc, crtc_state);
7958         } else if (IS_VALLEYVIEW(dev)) {
7959                 vlv_compute_dpll(crtc, crtc_state);
7960         } else {
7961                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7962                                   num_connectors);
7963         }
7964
7965         return 0;
7966 }
7967
7968 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7969                                  struct intel_crtc_state *pipe_config)
7970 {
7971         struct drm_device *dev = crtc->base.dev;
7972         struct drm_i915_private *dev_priv = dev->dev_private;
7973         uint32_t tmp;
7974
7975         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7976                 return;
7977
7978         tmp = I915_READ(PFIT_CONTROL);
7979         if (!(tmp & PFIT_ENABLE))
7980                 return;
7981
7982         /* Check whether the pfit is attached to our pipe. */
7983         if (INTEL_INFO(dev)->gen < 4) {
7984                 if (crtc->pipe != PIPE_B)
7985                         return;
7986         } else {
7987                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7988                         return;
7989         }
7990
7991         pipe_config->gmch_pfit.control = tmp;
7992         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7993         if (INTEL_INFO(dev)->gen < 5)
7994                 pipe_config->gmch_pfit.lvds_border_bits =
7995                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7996 }
7997
7998 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7999                                struct intel_crtc_state *pipe_config)
8000 {
8001         struct drm_device *dev = crtc->base.dev;
8002         struct drm_i915_private *dev_priv = dev->dev_private;
8003         int pipe = pipe_config->cpu_transcoder;
8004         intel_clock_t clock;
8005         u32 mdiv;
8006         int refclk = 100000;
8007
8008         /* In case of MIPI DPLL will not even be used */
8009         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8010                 return;
8011
8012         mutex_lock(&dev_priv->sb_lock);
8013         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8014         mutex_unlock(&dev_priv->sb_lock);
8015
8016         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8017         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8018         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8019         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8020         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8021
8022         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8023 }
8024
8025 static void
8026 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8027                               struct intel_initial_plane_config *plane_config)
8028 {
8029         struct drm_device *dev = crtc->base.dev;
8030         struct drm_i915_private *dev_priv = dev->dev_private;
8031         u32 val, base, offset;
8032         int pipe = crtc->pipe, plane = crtc->plane;
8033         int fourcc, pixel_format;
8034         unsigned int aligned_height;
8035         struct drm_framebuffer *fb;
8036         struct intel_framebuffer *intel_fb;
8037
8038         val = I915_READ(DSPCNTR(plane));
8039         if (!(val & DISPLAY_PLANE_ENABLE))
8040                 return;
8041
8042         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8043         if (!intel_fb) {
8044                 DRM_DEBUG_KMS("failed to alloc fb\n");
8045                 return;
8046         }
8047
8048         fb = &intel_fb->base;
8049
8050         if (INTEL_INFO(dev)->gen >= 4) {
8051                 if (val & DISPPLANE_TILED) {
8052                         plane_config->tiling = I915_TILING_X;
8053                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8054                 }
8055         }
8056
8057         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8058         fourcc = i9xx_format_to_fourcc(pixel_format);
8059         fb->pixel_format = fourcc;
8060         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8061
8062         if (INTEL_INFO(dev)->gen >= 4) {
8063                 if (plane_config->tiling)
8064                         offset = I915_READ(DSPTILEOFF(plane));
8065                 else
8066                         offset = I915_READ(DSPLINOFF(plane));
8067                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8068         } else {
8069                 base = I915_READ(DSPADDR(plane));
8070         }
8071         plane_config->base = base;
8072
8073         val = I915_READ(PIPESRC(pipe));
8074         fb->width = ((val >> 16) & 0xfff) + 1;
8075         fb->height = ((val >> 0) & 0xfff) + 1;
8076
8077         val = I915_READ(DSPSTRIDE(pipe));
8078         fb->pitches[0] = val & 0xffffffc0;
8079
8080         aligned_height = intel_fb_align_height(dev, fb->height,
8081                                                fb->pixel_format,
8082                                                fb->modifier[0]);
8083
8084         plane_config->size = fb->pitches[0] * aligned_height;
8085
8086         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8087                       pipe_name(pipe), plane, fb->width, fb->height,
8088                       fb->bits_per_pixel, base, fb->pitches[0],
8089                       plane_config->size);
8090
8091         plane_config->fb = intel_fb;
8092 }
8093
8094 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8095                                struct intel_crtc_state *pipe_config)
8096 {
8097         struct drm_device *dev = crtc->base.dev;
8098         struct drm_i915_private *dev_priv = dev->dev_private;
8099         int pipe = pipe_config->cpu_transcoder;
8100         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8101         intel_clock_t clock;
8102         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8103         int refclk = 100000;
8104
8105         mutex_lock(&dev_priv->sb_lock);
8106         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8107         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8108         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8109         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8110         mutex_unlock(&dev_priv->sb_lock);
8111
8112         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8113         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8114         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8115         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8116         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8117
8118         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8119 }
8120
8121 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8122                                  struct intel_crtc_state *pipe_config)
8123 {
8124         struct drm_device *dev = crtc->base.dev;
8125         struct drm_i915_private *dev_priv = dev->dev_private;
8126         uint32_t tmp;
8127
8128         if (!intel_display_power_is_enabled(dev_priv,
8129                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8130                 return false;
8131
8132         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8133         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8134
8135         tmp = I915_READ(PIPECONF(crtc->pipe));
8136         if (!(tmp & PIPECONF_ENABLE))
8137                 return false;
8138
8139         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8140                 switch (tmp & PIPECONF_BPC_MASK) {
8141                 case PIPECONF_6BPC:
8142                         pipe_config->pipe_bpp = 18;
8143                         break;
8144                 case PIPECONF_8BPC:
8145                         pipe_config->pipe_bpp = 24;
8146                         break;
8147                 case PIPECONF_10BPC:
8148                         pipe_config->pipe_bpp = 30;
8149                         break;
8150                 default:
8151                         break;
8152                 }
8153         }
8154
8155         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8156                 pipe_config->limited_color_range = true;
8157
8158         if (INTEL_INFO(dev)->gen < 4)
8159                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8160
8161         intel_get_pipe_timings(crtc, pipe_config);
8162
8163         i9xx_get_pfit_config(crtc, pipe_config);
8164
8165         if (INTEL_INFO(dev)->gen >= 4) {
8166                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8167                 pipe_config->pixel_multiplier =
8168                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8169                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8170                 pipe_config->dpll_hw_state.dpll_md = tmp;
8171         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8172                 tmp = I915_READ(DPLL(crtc->pipe));
8173                 pipe_config->pixel_multiplier =
8174                         ((tmp & SDVO_MULTIPLIER_MASK)
8175                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8176         } else {
8177                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8178                  * port and will be fixed up in the encoder->get_config
8179                  * function. */
8180                 pipe_config->pixel_multiplier = 1;
8181         }
8182         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8183         if (!IS_VALLEYVIEW(dev)) {
8184                 /*
8185                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8186                  * on 830. Filter it out here so that we don't
8187                  * report errors due to that.
8188                  */
8189                 if (IS_I830(dev))
8190                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8191
8192                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8193                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8194         } else {
8195                 /* Mask out read-only status bits. */
8196                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8197                                                      DPLL_PORTC_READY_MASK |
8198                                                      DPLL_PORTB_READY_MASK);
8199         }
8200
8201         if (IS_CHERRYVIEW(dev))
8202                 chv_crtc_clock_get(crtc, pipe_config);
8203         else if (IS_VALLEYVIEW(dev))
8204                 vlv_crtc_clock_get(crtc, pipe_config);
8205         else
8206                 i9xx_crtc_clock_get(crtc, pipe_config);
8207
8208         return true;
8209 }
8210
8211 static void ironlake_init_pch_refclk(struct drm_device *dev)
8212 {
8213         struct drm_i915_private *dev_priv = dev->dev_private;
8214         struct intel_encoder *encoder;
8215         u32 val, final;
8216         bool has_lvds = false;
8217         bool has_cpu_edp = false;
8218         bool has_panel = false;
8219         bool has_ck505 = false;
8220         bool can_ssc = false;
8221
8222         /* We need to take the global config into account */
8223         for_each_intel_encoder(dev, encoder) {
8224                 switch (encoder->type) {
8225                 case INTEL_OUTPUT_LVDS:
8226                         has_panel = true;
8227                         has_lvds = true;
8228                         break;
8229                 case INTEL_OUTPUT_EDP:
8230                         has_panel = true;
8231                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8232                                 has_cpu_edp = true;
8233                         break;
8234                 default:
8235                         break;
8236                 }
8237         }
8238
8239         if (HAS_PCH_IBX(dev)) {
8240                 has_ck505 = dev_priv->vbt.display_clock_mode;
8241                 can_ssc = has_ck505;
8242         } else {
8243                 has_ck505 = false;
8244                 can_ssc = true;
8245         }
8246
8247         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8248                       has_panel, has_lvds, has_ck505);
8249
8250         /* Ironlake: try to setup display ref clock before DPLL
8251          * enabling. This is only under driver's control after
8252          * PCH B stepping, previous chipset stepping should be
8253          * ignoring this setting.
8254          */
8255         val = I915_READ(PCH_DREF_CONTROL);
8256
8257         /* As we must carefully and slowly disable/enable each source in turn,
8258          * compute the final state we want first and check if we need to
8259          * make any changes at all.
8260          */
8261         final = val;
8262         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8263         if (has_ck505)
8264                 final |= DREF_NONSPREAD_CK505_ENABLE;
8265         else
8266                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8267
8268         final &= ~DREF_SSC_SOURCE_MASK;
8269         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8270         final &= ~DREF_SSC1_ENABLE;
8271
8272         if (has_panel) {
8273                 final |= DREF_SSC_SOURCE_ENABLE;
8274
8275                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8276                         final |= DREF_SSC1_ENABLE;
8277
8278                 if (has_cpu_edp) {
8279                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8280                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8281                         else
8282                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8283                 } else
8284                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8285         } else {
8286                 final |= DREF_SSC_SOURCE_DISABLE;
8287                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8288         }
8289
8290         if (final == val)
8291                 return;
8292
8293         /* Always enable nonspread source */
8294         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8295
8296         if (has_ck505)
8297                 val |= DREF_NONSPREAD_CK505_ENABLE;
8298         else
8299                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8300
8301         if (has_panel) {
8302                 val &= ~DREF_SSC_SOURCE_MASK;
8303                 val |= DREF_SSC_SOURCE_ENABLE;
8304
8305                 /* SSC must be turned on before enabling the CPU output  */
8306                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8307                         DRM_DEBUG_KMS("Using SSC on panel\n");
8308                         val |= DREF_SSC1_ENABLE;
8309                 } else
8310                         val &= ~DREF_SSC1_ENABLE;
8311
8312                 /* Get SSC going before enabling the outputs */
8313                 I915_WRITE(PCH_DREF_CONTROL, val);
8314                 POSTING_READ(PCH_DREF_CONTROL);
8315                 udelay(200);
8316
8317                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8318
8319                 /* Enable CPU source on CPU attached eDP */
8320                 if (has_cpu_edp) {
8321                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8322                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8323                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8324                         } else
8325                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8326                 } else
8327                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8328
8329                 I915_WRITE(PCH_DREF_CONTROL, val);
8330                 POSTING_READ(PCH_DREF_CONTROL);
8331                 udelay(200);
8332         } else {
8333                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8334
8335                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8336
8337                 /* Turn off CPU output */
8338                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8339
8340                 I915_WRITE(PCH_DREF_CONTROL, val);
8341                 POSTING_READ(PCH_DREF_CONTROL);
8342                 udelay(200);
8343
8344                 /* Turn off the SSC source */
8345                 val &= ~DREF_SSC_SOURCE_MASK;
8346                 val |= DREF_SSC_SOURCE_DISABLE;
8347
8348                 /* Turn off SSC1 */
8349                 val &= ~DREF_SSC1_ENABLE;
8350
8351                 I915_WRITE(PCH_DREF_CONTROL, val);
8352                 POSTING_READ(PCH_DREF_CONTROL);
8353                 udelay(200);
8354         }
8355
8356         BUG_ON(val != final);
8357 }
8358
8359 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8360 {
8361         uint32_t tmp;
8362
8363         tmp = I915_READ(SOUTH_CHICKEN2);
8364         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8365         I915_WRITE(SOUTH_CHICKEN2, tmp);
8366
8367         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8368                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8369                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8370
8371         tmp = I915_READ(SOUTH_CHICKEN2);
8372         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8373         I915_WRITE(SOUTH_CHICKEN2, tmp);
8374
8375         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8376                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8377                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8378 }
8379
8380 /* WaMPhyProgramming:hsw */
8381 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8382 {
8383         uint32_t tmp;
8384
8385         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8386         tmp &= ~(0xFF << 24);
8387         tmp |= (0x12 << 24);
8388         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8389
8390         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8391         tmp |= (1 << 11);
8392         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8393
8394         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8395         tmp |= (1 << 11);
8396         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8397
8398         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8399         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8400         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8401
8402         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8403         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8404         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8405
8406         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8407         tmp &= ~(7 << 13);
8408         tmp |= (5 << 13);
8409         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8410
8411         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8412         tmp &= ~(7 << 13);
8413         tmp |= (5 << 13);
8414         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8415
8416         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8417         tmp &= ~0xFF;
8418         tmp |= 0x1C;
8419         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8420
8421         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8422         tmp &= ~0xFF;
8423         tmp |= 0x1C;
8424         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8425
8426         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8427         tmp &= ~(0xFF << 16);
8428         tmp |= (0x1C << 16);
8429         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8430
8431         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8432         tmp &= ~(0xFF << 16);
8433         tmp |= (0x1C << 16);
8434         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8435
8436         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8437         tmp |= (1 << 27);
8438         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8439
8440         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8441         tmp |= (1 << 27);
8442         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8443
8444         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8445         tmp &= ~(0xF << 28);
8446         tmp |= (4 << 28);
8447         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8448
8449         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8450         tmp &= ~(0xF << 28);
8451         tmp |= (4 << 28);
8452         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8453 }
8454
8455 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8456  * Programming" based on the parameters passed:
8457  * - Sequence to enable CLKOUT_DP
8458  * - Sequence to enable CLKOUT_DP without spread
8459  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8460  */
8461 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8462                                  bool with_fdi)
8463 {
8464         struct drm_i915_private *dev_priv = dev->dev_private;
8465         uint32_t reg, tmp;
8466
8467         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8468                 with_spread = true;
8469         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8470                  with_fdi, "LP PCH doesn't have FDI\n"))
8471                 with_fdi = false;
8472
8473         mutex_lock(&dev_priv->sb_lock);
8474
8475         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8476         tmp &= ~SBI_SSCCTL_DISABLE;
8477         tmp |= SBI_SSCCTL_PATHALT;
8478         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8479
8480         udelay(24);
8481
8482         if (with_spread) {
8483                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8484                 tmp &= ~SBI_SSCCTL_PATHALT;
8485                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8486
8487                 if (with_fdi) {
8488                         lpt_reset_fdi_mphy(dev_priv);
8489                         lpt_program_fdi_mphy(dev_priv);
8490                 }
8491         }
8492
8493         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8494                SBI_GEN0 : SBI_DBUFF0;
8495         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8496         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8497         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8498
8499         mutex_unlock(&dev_priv->sb_lock);
8500 }
8501
8502 /* Sequence to disable CLKOUT_DP */
8503 static void lpt_disable_clkout_dp(struct drm_device *dev)
8504 {
8505         struct drm_i915_private *dev_priv = dev->dev_private;
8506         uint32_t reg, tmp;
8507
8508         mutex_lock(&dev_priv->sb_lock);
8509
8510         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8511                SBI_GEN0 : SBI_DBUFF0;
8512         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8513         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8514         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8515
8516         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8517         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8518                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8519                         tmp |= SBI_SSCCTL_PATHALT;
8520                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8521                         udelay(32);
8522                 }
8523                 tmp |= SBI_SSCCTL_DISABLE;
8524                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8525         }
8526
8527         mutex_unlock(&dev_priv->sb_lock);
8528 }
8529
8530 static void lpt_init_pch_refclk(struct drm_device *dev)
8531 {
8532         struct intel_encoder *encoder;
8533         bool has_vga = false;
8534
8535         for_each_intel_encoder(dev, encoder) {
8536                 switch (encoder->type) {
8537                 case INTEL_OUTPUT_ANALOG:
8538                         has_vga = true;
8539                         break;
8540                 default:
8541                         break;
8542                 }
8543         }
8544
8545         if (has_vga)
8546                 lpt_enable_clkout_dp(dev, true, true);
8547         else
8548                 lpt_disable_clkout_dp(dev);
8549 }
8550
8551 /*
8552  * Initialize reference clocks when the driver loads
8553  */
8554 void intel_init_pch_refclk(struct drm_device *dev)
8555 {
8556         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8557                 ironlake_init_pch_refclk(dev);
8558         else if (HAS_PCH_LPT(dev))
8559                 lpt_init_pch_refclk(dev);
8560 }
8561
8562 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8563 {
8564         struct drm_device *dev = crtc_state->base.crtc->dev;
8565         struct drm_i915_private *dev_priv = dev->dev_private;
8566         struct drm_atomic_state *state = crtc_state->base.state;
8567         struct drm_connector *connector;
8568         struct drm_connector_state *connector_state;
8569         struct intel_encoder *encoder;
8570         int num_connectors = 0, i;
8571         bool is_lvds = false;
8572
8573         for_each_connector_in_state(state, connector, connector_state, i) {
8574                 if (connector_state->crtc != crtc_state->base.crtc)
8575                         continue;
8576
8577                 encoder = to_intel_encoder(connector_state->best_encoder);
8578
8579                 switch (encoder->type) {
8580                 case INTEL_OUTPUT_LVDS:
8581                         is_lvds = true;
8582                         break;
8583                 default:
8584                         break;
8585                 }
8586                 num_connectors++;
8587         }
8588
8589         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8590                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8591                               dev_priv->vbt.lvds_ssc_freq);
8592                 return dev_priv->vbt.lvds_ssc_freq;
8593         }
8594
8595         return 120000;
8596 }
8597
8598 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8599 {
8600         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8602         int pipe = intel_crtc->pipe;
8603         uint32_t val;
8604
8605         val = 0;
8606
8607         switch (intel_crtc->config->pipe_bpp) {
8608         case 18:
8609                 val |= PIPECONF_6BPC;
8610                 break;
8611         case 24:
8612                 val |= PIPECONF_8BPC;
8613                 break;
8614         case 30:
8615                 val |= PIPECONF_10BPC;
8616                 break;
8617         case 36:
8618                 val |= PIPECONF_12BPC;
8619                 break;
8620         default:
8621                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8622                 BUG();
8623         }
8624
8625         if (intel_crtc->config->dither)
8626                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8627
8628         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8629                 val |= PIPECONF_INTERLACED_ILK;
8630         else
8631                 val |= PIPECONF_PROGRESSIVE;
8632
8633         if (intel_crtc->config->limited_color_range)
8634                 val |= PIPECONF_COLOR_RANGE_SELECT;
8635
8636         I915_WRITE(PIPECONF(pipe), val);
8637         POSTING_READ(PIPECONF(pipe));
8638 }
8639
8640 /*
8641  * Set up the pipe CSC unit.
8642  *
8643  * Currently only full range RGB to limited range RGB conversion
8644  * is supported, but eventually this should handle various
8645  * RGB<->YCbCr scenarios as well.
8646  */
8647 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8648 {
8649         struct drm_device *dev = crtc->dev;
8650         struct drm_i915_private *dev_priv = dev->dev_private;
8651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8652         int pipe = intel_crtc->pipe;
8653         uint16_t coeff = 0x7800; /* 1.0 */
8654
8655         /*
8656          * TODO: Check what kind of values actually come out of the pipe
8657          * with these coeff/postoff values and adjust to get the best
8658          * accuracy. Perhaps we even need to take the bpc value into
8659          * consideration.
8660          */
8661
8662         if (intel_crtc->config->limited_color_range)
8663                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8664
8665         /*
8666          * GY/GU and RY/RU should be the other way around according
8667          * to BSpec, but reality doesn't agree. Just set them up in
8668          * a way that results in the correct picture.
8669          */
8670         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8671         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8672
8673         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8674         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8675
8676         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8677         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8678
8679         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8680         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8681         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8682
8683         if (INTEL_INFO(dev)->gen > 6) {
8684                 uint16_t postoff = 0;
8685
8686                 if (intel_crtc->config->limited_color_range)
8687                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8688
8689                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8690                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8691                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8692
8693                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8694         } else {
8695                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8696
8697                 if (intel_crtc->config->limited_color_range)
8698                         mode |= CSC_BLACK_SCREEN_OFFSET;
8699
8700                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8701         }
8702 }
8703
8704 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8705 {
8706         struct drm_device *dev = crtc->dev;
8707         struct drm_i915_private *dev_priv = dev->dev_private;
8708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8709         enum pipe pipe = intel_crtc->pipe;
8710         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8711         uint32_t val;
8712
8713         val = 0;
8714
8715         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8716                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8717
8718         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8719                 val |= PIPECONF_INTERLACED_ILK;
8720         else
8721                 val |= PIPECONF_PROGRESSIVE;
8722
8723         I915_WRITE(PIPECONF(cpu_transcoder), val);
8724         POSTING_READ(PIPECONF(cpu_transcoder));
8725
8726         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8727         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8728
8729         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8730                 val = 0;
8731
8732                 switch (intel_crtc->config->pipe_bpp) {
8733                 case 18:
8734                         val |= PIPEMISC_DITHER_6_BPC;
8735                         break;
8736                 case 24:
8737                         val |= PIPEMISC_DITHER_8_BPC;
8738                         break;
8739                 case 30:
8740                         val |= PIPEMISC_DITHER_10_BPC;
8741                         break;
8742                 case 36:
8743                         val |= PIPEMISC_DITHER_12_BPC;
8744                         break;
8745                 default:
8746                         /* Case prevented by pipe_config_set_bpp. */
8747                         BUG();
8748                 }
8749
8750                 if (intel_crtc->config->dither)
8751                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8752
8753                 I915_WRITE(PIPEMISC(pipe), val);
8754         }
8755 }
8756
8757 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8758                                     struct intel_crtc_state *crtc_state,
8759                                     intel_clock_t *clock,
8760                                     bool *has_reduced_clock,
8761                                     intel_clock_t *reduced_clock)
8762 {
8763         struct drm_device *dev = crtc->dev;
8764         struct drm_i915_private *dev_priv = dev->dev_private;
8765         int refclk;
8766         const intel_limit_t *limit;
8767         bool ret;
8768
8769         refclk = ironlake_get_refclk(crtc_state);
8770
8771         /*
8772          * Returns a set of divisors for the desired target clock with the given
8773          * refclk, or FALSE.  The returned values represent the clock equation:
8774          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8775          */
8776         limit = intel_limit(crtc_state, refclk);
8777         ret = dev_priv->display.find_dpll(limit, crtc_state,
8778                                           crtc_state->port_clock,
8779                                           refclk, NULL, clock);
8780         if (!ret)
8781                 return false;
8782
8783         return true;
8784 }
8785
8786 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8787 {
8788         /*
8789          * Account for spread spectrum to avoid
8790          * oversubscribing the link. Max center spread
8791          * is 2.5%; use 5% for safety's sake.
8792          */
8793         u32 bps = target_clock * bpp * 21 / 20;
8794         return DIV_ROUND_UP(bps, link_bw * 8);
8795 }
8796
8797 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8798 {
8799         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8800 }
8801
8802 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8803                                       struct intel_crtc_state *crtc_state,
8804                                       u32 *fp,
8805                                       intel_clock_t *reduced_clock, u32 *fp2)
8806 {
8807         struct drm_crtc *crtc = &intel_crtc->base;
8808         struct drm_device *dev = crtc->dev;
8809         struct drm_i915_private *dev_priv = dev->dev_private;
8810         struct drm_atomic_state *state = crtc_state->base.state;
8811         struct drm_connector *connector;
8812         struct drm_connector_state *connector_state;
8813         struct intel_encoder *encoder;
8814         uint32_t dpll;
8815         int factor, num_connectors = 0, i;
8816         bool is_lvds = false, is_sdvo = false;
8817
8818         for_each_connector_in_state(state, connector, connector_state, i) {
8819                 if (connector_state->crtc != crtc_state->base.crtc)
8820                         continue;
8821
8822                 encoder = to_intel_encoder(connector_state->best_encoder);
8823
8824                 switch (encoder->type) {
8825                 case INTEL_OUTPUT_LVDS:
8826                         is_lvds = true;
8827                         break;
8828                 case INTEL_OUTPUT_SDVO:
8829                 case INTEL_OUTPUT_HDMI:
8830                         is_sdvo = true;
8831                         break;
8832                 default:
8833                         break;
8834                 }
8835
8836                 num_connectors++;
8837         }
8838
8839         /* Enable autotuning of the PLL clock (if permissible) */
8840         factor = 21;
8841         if (is_lvds) {
8842                 if ((intel_panel_use_ssc(dev_priv) &&
8843                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8844                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8845                         factor = 25;
8846         } else if (crtc_state->sdvo_tv_clock)
8847                 factor = 20;
8848
8849         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8850                 *fp |= FP_CB_TUNE;
8851
8852         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8853                 *fp2 |= FP_CB_TUNE;
8854
8855         dpll = 0;
8856
8857         if (is_lvds)
8858                 dpll |= DPLLB_MODE_LVDS;
8859         else
8860                 dpll |= DPLLB_MODE_DAC_SERIAL;
8861
8862         dpll |= (crtc_state->pixel_multiplier - 1)
8863                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8864
8865         if (is_sdvo)
8866                 dpll |= DPLL_SDVO_HIGH_SPEED;
8867         if (crtc_state->has_dp_encoder)
8868                 dpll |= DPLL_SDVO_HIGH_SPEED;
8869
8870         /* compute bitmask from p1 value */
8871         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8872         /* also FPA1 */
8873         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8874
8875         switch (crtc_state->dpll.p2) {
8876         case 5:
8877                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8878                 break;
8879         case 7:
8880                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8881                 break;
8882         case 10:
8883                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8884                 break;
8885         case 14:
8886                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8887                 break;
8888         }
8889
8890         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8891                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8892         else
8893                 dpll |= PLL_REF_INPUT_DREFCLK;
8894
8895         return dpll | DPLL_VCO_ENABLE;
8896 }
8897
8898 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8899                                        struct intel_crtc_state *crtc_state)
8900 {
8901         struct drm_device *dev = crtc->base.dev;
8902         intel_clock_t clock, reduced_clock;
8903         u32 dpll = 0, fp = 0, fp2 = 0;
8904         bool ok, has_reduced_clock = false;
8905         bool is_lvds = false;
8906         struct intel_shared_dpll *pll;
8907
8908         memset(&crtc_state->dpll_hw_state, 0,
8909                sizeof(crtc_state->dpll_hw_state));
8910
8911         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8912
8913         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8914              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8915
8916         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8917                                      &has_reduced_clock, &reduced_clock);
8918         if (!ok && !crtc_state->clock_set) {
8919                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8920                 return -EINVAL;
8921         }
8922         /* Compat-code for transition, will disappear. */
8923         if (!crtc_state->clock_set) {
8924                 crtc_state->dpll.n = clock.n;
8925                 crtc_state->dpll.m1 = clock.m1;
8926                 crtc_state->dpll.m2 = clock.m2;
8927                 crtc_state->dpll.p1 = clock.p1;
8928                 crtc_state->dpll.p2 = clock.p2;
8929         }
8930
8931         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8932         if (crtc_state->has_pch_encoder) {
8933                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8934                 if (has_reduced_clock)
8935                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8936
8937                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8938                                              &fp, &reduced_clock,
8939                                              has_reduced_clock ? &fp2 : NULL);
8940
8941                 crtc_state->dpll_hw_state.dpll = dpll;
8942                 crtc_state->dpll_hw_state.fp0 = fp;
8943                 if (has_reduced_clock)
8944                         crtc_state->dpll_hw_state.fp1 = fp2;
8945                 else
8946                         crtc_state->dpll_hw_state.fp1 = fp;
8947
8948                 pll = intel_get_shared_dpll(crtc, crtc_state);
8949                 if (pll == NULL) {
8950                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8951                                          pipe_name(crtc->pipe));
8952                         return -EINVAL;
8953                 }
8954         }
8955
8956         if (is_lvds && has_reduced_clock)
8957                 crtc->lowfreq_avail = true;
8958         else
8959                 crtc->lowfreq_avail = false;
8960
8961         return 0;
8962 }
8963
8964 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8965                                          struct intel_link_m_n *m_n)
8966 {
8967         struct drm_device *dev = crtc->base.dev;
8968         struct drm_i915_private *dev_priv = dev->dev_private;
8969         enum pipe pipe = crtc->pipe;
8970
8971         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8972         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8973         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8974                 & ~TU_SIZE_MASK;
8975         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8976         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8977                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8978 }
8979
8980 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8981                                          enum transcoder transcoder,
8982                                          struct intel_link_m_n *m_n,
8983                                          struct intel_link_m_n *m2_n2)
8984 {
8985         struct drm_device *dev = crtc->base.dev;
8986         struct drm_i915_private *dev_priv = dev->dev_private;
8987         enum pipe pipe = crtc->pipe;
8988
8989         if (INTEL_INFO(dev)->gen >= 5) {
8990                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8991                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8992                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8993                         & ~TU_SIZE_MASK;
8994                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8995                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8996                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8997                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8998                  * gen < 8) and if DRRS is supported (to make sure the
8999                  * registers are not unnecessarily read).
9000                  */
9001                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9002                         crtc->config->has_drrs) {
9003                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9004                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9005                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9006                                         & ~TU_SIZE_MASK;
9007                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9008                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9009                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9010                 }
9011         } else {
9012                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9013                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9014                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9015                         & ~TU_SIZE_MASK;
9016                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9017                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9018                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9019         }
9020 }
9021
9022 void intel_dp_get_m_n(struct intel_crtc *crtc,
9023                       struct intel_crtc_state *pipe_config)
9024 {
9025         if (pipe_config->has_pch_encoder)
9026                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9027         else
9028                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9029                                              &pipe_config->dp_m_n,
9030                                              &pipe_config->dp_m2_n2);
9031 }
9032
9033 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9034                                         struct intel_crtc_state *pipe_config)
9035 {
9036         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9037                                      &pipe_config->fdi_m_n, NULL);
9038 }
9039
9040 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9041                                     struct intel_crtc_state *pipe_config)
9042 {
9043         struct drm_device *dev = crtc->base.dev;
9044         struct drm_i915_private *dev_priv = dev->dev_private;
9045         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9046         uint32_t ps_ctrl = 0;
9047         int id = -1;
9048         int i;
9049
9050         /* find scaler attached to this pipe */
9051         for (i = 0; i < crtc->num_scalers; i++) {
9052                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9053                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9054                         id = i;
9055                         pipe_config->pch_pfit.enabled = true;
9056                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9057                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9058                         break;
9059                 }
9060         }
9061
9062         scaler_state->scaler_id = id;
9063         if (id >= 0) {
9064                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9065         } else {
9066                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9067         }
9068 }
9069
9070 static void
9071 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9072                                  struct intel_initial_plane_config *plane_config)
9073 {
9074         struct drm_device *dev = crtc->base.dev;
9075         struct drm_i915_private *dev_priv = dev->dev_private;
9076         u32 val, base, offset, stride_mult, tiling;
9077         int pipe = crtc->pipe;
9078         int fourcc, pixel_format;
9079         unsigned int aligned_height;
9080         struct drm_framebuffer *fb;
9081         struct intel_framebuffer *intel_fb;
9082
9083         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9084         if (!intel_fb) {
9085                 DRM_DEBUG_KMS("failed to alloc fb\n");
9086                 return;
9087         }
9088
9089         fb = &intel_fb->base;
9090
9091         val = I915_READ(PLANE_CTL(pipe, 0));
9092         if (!(val & PLANE_CTL_ENABLE))
9093                 goto error;
9094
9095         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9096         fourcc = skl_format_to_fourcc(pixel_format,
9097                                       val & PLANE_CTL_ORDER_RGBX,
9098                                       val & PLANE_CTL_ALPHA_MASK);
9099         fb->pixel_format = fourcc;
9100         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9101
9102         tiling = val & PLANE_CTL_TILED_MASK;
9103         switch (tiling) {
9104         case PLANE_CTL_TILED_LINEAR:
9105                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9106                 break;
9107         case PLANE_CTL_TILED_X:
9108                 plane_config->tiling = I915_TILING_X;
9109                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9110                 break;
9111         case PLANE_CTL_TILED_Y:
9112                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9113                 break;
9114         case PLANE_CTL_TILED_YF:
9115                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9116                 break;
9117         default:
9118                 MISSING_CASE(tiling);
9119                 goto error;
9120         }
9121
9122         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9123         plane_config->base = base;
9124
9125         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9126
9127         val = I915_READ(PLANE_SIZE(pipe, 0));
9128         fb->height = ((val >> 16) & 0xfff) + 1;
9129         fb->width = ((val >> 0) & 0x1fff) + 1;
9130
9131         val = I915_READ(PLANE_STRIDE(pipe, 0));
9132         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9133                                                 fb->pixel_format);
9134         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9135
9136         aligned_height = intel_fb_align_height(dev, fb->height,
9137                                                fb->pixel_format,
9138                                                fb->modifier[0]);
9139
9140         plane_config->size = fb->pitches[0] * aligned_height;
9141
9142         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9143                       pipe_name(pipe), fb->width, fb->height,
9144                       fb->bits_per_pixel, base, fb->pitches[0],
9145                       plane_config->size);
9146
9147         plane_config->fb = intel_fb;
9148         return;
9149
9150 error:
9151         kfree(fb);
9152 }
9153
9154 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9155                                      struct intel_crtc_state *pipe_config)
9156 {
9157         struct drm_device *dev = crtc->base.dev;
9158         struct drm_i915_private *dev_priv = dev->dev_private;
9159         uint32_t tmp;
9160
9161         tmp = I915_READ(PF_CTL(crtc->pipe));
9162
9163         if (tmp & PF_ENABLE) {
9164                 pipe_config->pch_pfit.enabled = true;
9165                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9166                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9167
9168                 /* We currently do not free assignements of panel fitters on
9169                  * ivb/hsw (since we don't use the higher upscaling modes which
9170                  * differentiates them) so just WARN about this case for now. */
9171                 if (IS_GEN7(dev)) {
9172                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9173                                 PF_PIPE_SEL_IVB(crtc->pipe));
9174                 }
9175         }
9176 }
9177
9178 static void
9179 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9180                                   struct intel_initial_plane_config *plane_config)
9181 {
9182         struct drm_device *dev = crtc->base.dev;
9183         struct drm_i915_private *dev_priv = dev->dev_private;
9184         u32 val, base, offset;
9185         int pipe = crtc->pipe;
9186         int fourcc, pixel_format;
9187         unsigned int aligned_height;
9188         struct drm_framebuffer *fb;
9189         struct intel_framebuffer *intel_fb;
9190
9191         val = I915_READ(DSPCNTR(pipe));
9192         if (!(val & DISPLAY_PLANE_ENABLE))
9193                 return;
9194
9195         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9196         if (!intel_fb) {
9197                 DRM_DEBUG_KMS("failed to alloc fb\n");
9198                 return;
9199         }
9200
9201         fb = &intel_fb->base;
9202
9203         if (INTEL_INFO(dev)->gen >= 4) {
9204                 if (val & DISPPLANE_TILED) {
9205                         plane_config->tiling = I915_TILING_X;
9206                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9207                 }
9208         }
9209
9210         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9211         fourcc = i9xx_format_to_fourcc(pixel_format);
9212         fb->pixel_format = fourcc;
9213         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9214
9215         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9216         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9217                 offset = I915_READ(DSPOFFSET(pipe));
9218         } else {
9219                 if (plane_config->tiling)
9220                         offset = I915_READ(DSPTILEOFF(pipe));
9221                 else
9222                         offset = I915_READ(DSPLINOFF(pipe));
9223         }
9224         plane_config->base = base;
9225
9226         val = I915_READ(PIPESRC(pipe));
9227         fb->width = ((val >> 16) & 0xfff) + 1;
9228         fb->height = ((val >> 0) & 0xfff) + 1;
9229
9230         val = I915_READ(DSPSTRIDE(pipe));
9231         fb->pitches[0] = val & 0xffffffc0;
9232
9233         aligned_height = intel_fb_align_height(dev, fb->height,
9234                                                fb->pixel_format,
9235                                                fb->modifier[0]);
9236
9237         plane_config->size = fb->pitches[0] * aligned_height;
9238
9239         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9240                       pipe_name(pipe), fb->width, fb->height,
9241                       fb->bits_per_pixel, base, fb->pitches[0],
9242                       plane_config->size);
9243
9244         plane_config->fb = intel_fb;
9245 }
9246
9247 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9248                                      struct intel_crtc_state *pipe_config)
9249 {
9250         struct drm_device *dev = crtc->base.dev;
9251         struct drm_i915_private *dev_priv = dev->dev_private;
9252         uint32_t tmp;
9253
9254         if (!intel_display_power_is_enabled(dev_priv,
9255                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9256                 return false;
9257
9258         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9259         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9260
9261         tmp = I915_READ(PIPECONF(crtc->pipe));
9262         if (!(tmp & PIPECONF_ENABLE))
9263                 return false;
9264
9265         switch (tmp & PIPECONF_BPC_MASK) {
9266         case PIPECONF_6BPC:
9267                 pipe_config->pipe_bpp = 18;
9268                 break;
9269         case PIPECONF_8BPC:
9270                 pipe_config->pipe_bpp = 24;
9271                 break;
9272         case PIPECONF_10BPC:
9273                 pipe_config->pipe_bpp = 30;
9274                 break;
9275         case PIPECONF_12BPC:
9276                 pipe_config->pipe_bpp = 36;
9277                 break;
9278         default:
9279                 break;
9280         }
9281
9282         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9283                 pipe_config->limited_color_range = true;
9284
9285         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9286                 struct intel_shared_dpll *pll;
9287
9288                 pipe_config->has_pch_encoder = true;
9289
9290                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9291                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9292                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9293
9294                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9295
9296                 if (HAS_PCH_IBX(dev_priv->dev)) {
9297                         pipe_config->shared_dpll =
9298                                 (enum intel_dpll_id) crtc->pipe;
9299                 } else {
9300                         tmp = I915_READ(PCH_DPLL_SEL);
9301                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9302                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9303                         else
9304                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9305                 }
9306
9307                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9308
9309                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9310                                            &pipe_config->dpll_hw_state));
9311
9312                 tmp = pipe_config->dpll_hw_state.dpll;
9313                 pipe_config->pixel_multiplier =
9314                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9315                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9316
9317                 ironlake_pch_clock_get(crtc, pipe_config);
9318         } else {
9319                 pipe_config->pixel_multiplier = 1;
9320         }
9321
9322         intel_get_pipe_timings(crtc, pipe_config);
9323
9324         ironlake_get_pfit_config(crtc, pipe_config);
9325
9326         return true;
9327 }
9328
9329 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9330 {
9331         struct drm_device *dev = dev_priv->dev;
9332         struct intel_crtc *crtc;
9333
9334         for_each_intel_crtc(dev, crtc)
9335                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9336                      pipe_name(crtc->pipe));
9337
9338         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9339         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9340         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9341         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9342         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9343         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9344              "CPU PWM1 enabled\n");
9345         if (IS_HASWELL(dev))
9346                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9347                      "CPU PWM2 enabled\n");
9348         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9349              "PCH PWM1 enabled\n");
9350         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9351              "Utility pin enabled\n");
9352         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9353
9354         /*
9355          * In theory we can still leave IRQs enabled, as long as only the HPD
9356          * interrupts remain enabled. We used to check for that, but since it's
9357          * gen-specific and since we only disable LCPLL after we fully disable
9358          * the interrupts, the check below should be enough.
9359          */
9360         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9361 }
9362
9363 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9364 {
9365         struct drm_device *dev = dev_priv->dev;
9366
9367         if (IS_HASWELL(dev))
9368                 return I915_READ(D_COMP_HSW);
9369         else
9370                 return I915_READ(D_COMP_BDW);
9371 }
9372
9373 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9374 {
9375         struct drm_device *dev = dev_priv->dev;
9376
9377         if (IS_HASWELL(dev)) {
9378                 mutex_lock(&dev_priv->rps.hw_lock);
9379                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9380                                             val))
9381                         DRM_ERROR("Failed to write to D_COMP\n");
9382                 mutex_unlock(&dev_priv->rps.hw_lock);
9383         } else {
9384                 I915_WRITE(D_COMP_BDW, val);
9385                 POSTING_READ(D_COMP_BDW);
9386         }
9387 }
9388
9389 /*
9390  * This function implements pieces of two sequences from BSpec:
9391  * - Sequence for display software to disable LCPLL
9392  * - Sequence for display software to allow package C8+
9393  * The steps implemented here are just the steps that actually touch the LCPLL
9394  * register. Callers should take care of disabling all the display engine
9395  * functions, doing the mode unset, fixing interrupts, etc.
9396  */
9397 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9398                               bool switch_to_fclk, bool allow_power_down)
9399 {
9400         uint32_t val;
9401
9402         assert_can_disable_lcpll(dev_priv);
9403
9404         val = I915_READ(LCPLL_CTL);
9405
9406         if (switch_to_fclk) {
9407                 val |= LCPLL_CD_SOURCE_FCLK;
9408                 I915_WRITE(LCPLL_CTL, val);
9409
9410                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9411                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9412                         DRM_ERROR("Switching to FCLK failed\n");
9413
9414                 val = I915_READ(LCPLL_CTL);
9415         }
9416
9417         val |= LCPLL_PLL_DISABLE;
9418         I915_WRITE(LCPLL_CTL, val);
9419         POSTING_READ(LCPLL_CTL);
9420
9421         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9422                 DRM_ERROR("LCPLL still locked\n");
9423
9424         val = hsw_read_dcomp(dev_priv);
9425         val |= D_COMP_COMP_DISABLE;
9426         hsw_write_dcomp(dev_priv, val);
9427         ndelay(100);
9428
9429         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9430                      1))
9431                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9432
9433         if (allow_power_down) {
9434                 val = I915_READ(LCPLL_CTL);
9435                 val |= LCPLL_POWER_DOWN_ALLOW;
9436                 I915_WRITE(LCPLL_CTL, val);
9437                 POSTING_READ(LCPLL_CTL);
9438         }
9439 }
9440
9441 /*
9442  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9443  * source.
9444  */
9445 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9446 {
9447         uint32_t val;
9448
9449         val = I915_READ(LCPLL_CTL);
9450
9451         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9452                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9453                 return;
9454
9455         /*
9456          * Make sure we're not on PC8 state before disabling PC8, otherwise
9457          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9458          */
9459         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9460
9461         if (val & LCPLL_POWER_DOWN_ALLOW) {
9462                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9463                 I915_WRITE(LCPLL_CTL, val);
9464                 POSTING_READ(LCPLL_CTL);
9465         }
9466
9467         val = hsw_read_dcomp(dev_priv);
9468         val |= D_COMP_COMP_FORCE;
9469         val &= ~D_COMP_COMP_DISABLE;
9470         hsw_write_dcomp(dev_priv, val);
9471
9472         val = I915_READ(LCPLL_CTL);
9473         val &= ~LCPLL_PLL_DISABLE;
9474         I915_WRITE(LCPLL_CTL, val);
9475
9476         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9477                 DRM_ERROR("LCPLL not locked yet\n");
9478
9479         if (val & LCPLL_CD_SOURCE_FCLK) {
9480                 val = I915_READ(LCPLL_CTL);
9481                 val &= ~LCPLL_CD_SOURCE_FCLK;
9482                 I915_WRITE(LCPLL_CTL, val);
9483
9484                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9485                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9486                         DRM_ERROR("Switching back to LCPLL failed\n");
9487         }
9488
9489         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9490         intel_update_cdclk(dev_priv->dev);
9491 }
9492
9493 /*
9494  * Package states C8 and deeper are really deep PC states that can only be
9495  * reached when all the devices on the system allow it, so even if the graphics
9496  * device allows PC8+, it doesn't mean the system will actually get to these
9497  * states. Our driver only allows PC8+ when going into runtime PM.
9498  *
9499  * The requirements for PC8+ are that all the outputs are disabled, the power
9500  * well is disabled and most interrupts are disabled, and these are also
9501  * requirements for runtime PM. When these conditions are met, we manually do
9502  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9503  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9504  * hang the machine.
9505  *
9506  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9507  * the state of some registers, so when we come back from PC8+ we need to
9508  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9509  * need to take care of the registers kept by RC6. Notice that this happens even
9510  * if we don't put the device in PCI D3 state (which is what currently happens
9511  * because of the runtime PM support).
9512  *
9513  * For more, read "Display Sequences for Package C8" on the hardware
9514  * documentation.
9515  */
9516 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9517 {
9518         struct drm_device *dev = dev_priv->dev;
9519         uint32_t val;
9520
9521         DRM_DEBUG_KMS("Enabling package C8+\n");
9522
9523         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9524                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9525                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9526                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9527         }
9528
9529         lpt_disable_clkout_dp(dev);
9530         hsw_disable_lcpll(dev_priv, true, true);
9531 }
9532
9533 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9534 {
9535         struct drm_device *dev = dev_priv->dev;
9536         uint32_t val;
9537
9538         DRM_DEBUG_KMS("Disabling package C8+\n");
9539
9540         hsw_restore_lcpll(dev_priv);
9541         lpt_init_pch_refclk(dev);
9542
9543         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9544                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9545                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9546                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9547         }
9548
9549         intel_prepare_ddi(dev);
9550 }
9551
9552 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9553 {
9554         struct drm_device *dev = old_state->dev;
9555         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9556
9557         broxton_set_cdclk(dev, req_cdclk);
9558 }
9559
9560 /* compute the max rate for new configuration */
9561 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9562 {
9563         struct intel_crtc *intel_crtc;
9564         struct intel_crtc_state *crtc_state;
9565         int max_pixel_rate = 0;
9566
9567         for_each_intel_crtc(state->dev, intel_crtc) {
9568                 int pixel_rate;
9569
9570                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9571                 if (IS_ERR(crtc_state))
9572                         return PTR_ERR(crtc_state);
9573
9574                 if (!crtc_state->base.enable)
9575                         continue;
9576
9577                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9578
9579                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9580                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9581                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9582
9583                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9584         }
9585
9586         return max_pixel_rate;
9587 }
9588
9589 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9590 {
9591         struct drm_i915_private *dev_priv = dev->dev_private;
9592         uint32_t val, data;
9593         int ret;
9594
9595         if (WARN((I915_READ(LCPLL_CTL) &
9596                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9597                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9598                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9599                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9600                  "trying to change cdclk frequency with cdclk not enabled\n"))
9601                 return;
9602
9603         mutex_lock(&dev_priv->rps.hw_lock);
9604         ret = sandybridge_pcode_write(dev_priv,
9605                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9606         mutex_unlock(&dev_priv->rps.hw_lock);
9607         if (ret) {
9608                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9609                 return;
9610         }
9611
9612         val = I915_READ(LCPLL_CTL);
9613         val |= LCPLL_CD_SOURCE_FCLK;
9614         I915_WRITE(LCPLL_CTL, val);
9615
9616         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9617                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9618                 DRM_ERROR("Switching to FCLK failed\n");
9619
9620         val = I915_READ(LCPLL_CTL);
9621         val &= ~LCPLL_CLK_FREQ_MASK;
9622
9623         switch (cdclk) {
9624         case 450000:
9625                 val |= LCPLL_CLK_FREQ_450;
9626                 data = 0;
9627                 break;
9628         case 540000:
9629                 val |= LCPLL_CLK_FREQ_54O_BDW;
9630                 data = 1;
9631                 break;
9632         case 337500:
9633                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9634                 data = 2;
9635                 break;
9636         case 675000:
9637                 val |= LCPLL_CLK_FREQ_675_BDW;
9638                 data = 3;
9639                 break;
9640         default:
9641                 WARN(1, "invalid cdclk frequency\n");
9642                 return;
9643         }
9644
9645         I915_WRITE(LCPLL_CTL, val);
9646
9647         val = I915_READ(LCPLL_CTL);
9648         val &= ~LCPLL_CD_SOURCE_FCLK;
9649         I915_WRITE(LCPLL_CTL, val);
9650
9651         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9652                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9653                 DRM_ERROR("Switching back to LCPLL failed\n");
9654
9655         mutex_lock(&dev_priv->rps.hw_lock);
9656         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9657         mutex_unlock(&dev_priv->rps.hw_lock);
9658
9659         intel_update_cdclk(dev);
9660
9661         WARN(cdclk != dev_priv->cdclk_freq,
9662              "cdclk requested %d kHz but got %d kHz\n",
9663              cdclk, dev_priv->cdclk_freq);
9664 }
9665
9666 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9667 {
9668         struct drm_i915_private *dev_priv = to_i915(state->dev);
9669         int max_pixclk = ilk_max_pixel_rate(state);
9670         int cdclk;
9671
9672         /*
9673          * FIXME should also account for plane ratio
9674          * once 64bpp pixel formats are supported.
9675          */
9676         if (max_pixclk > 540000)
9677                 cdclk = 675000;
9678         else if (max_pixclk > 450000)
9679                 cdclk = 540000;
9680         else if (max_pixclk > 337500)
9681                 cdclk = 450000;
9682         else
9683                 cdclk = 337500;
9684
9685         /*
9686          * FIXME move the cdclk caclulation to
9687          * compute_config() so we can fail gracegully.
9688          */
9689         if (cdclk > dev_priv->max_cdclk_freq) {
9690                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9691                           cdclk, dev_priv->max_cdclk_freq);
9692                 cdclk = dev_priv->max_cdclk_freq;
9693         }
9694
9695         to_intel_atomic_state(state)->cdclk = cdclk;
9696
9697         return 0;
9698 }
9699
9700 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9701 {
9702         struct drm_device *dev = old_state->dev;
9703         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9704
9705         broadwell_set_cdclk(dev, req_cdclk);
9706 }
9707
9708 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9709                                       struct intel_crtc_state *crtc_state)
9710 {
9711         if (!intel_ddi_pll_select(crtc, crtc_state))
9712                 return -EINVAL;
9713
9714         crtc->lowfreq_avail = false;
9715
9716         return 0;
9717 }
9718
9719 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9720                                 enum port port,
9721                                 struct intel_crtc_state *pipe_config)
9722 {
9723         switch (port) {
9724         case PORT_A:
9725                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9726                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9727                 break;
9728         case PORT_B:
9729                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9730                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9731                 break;
9732         case PORT_C:
9733                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9734                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9735                 break;
9736         default:
9737                 DRM_ERROR("Incorrect port type\n");
9738         }
9739 }
9740
9741 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9742                                 enum port port,
9743                                 struct intel_crtc_state *pipe_config)
9744 {
9745         u32 temp, dpll_ctl1;
9746
9747         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9748         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9749
9750         switch (pipe_config->ddi_pll_sel) {
9751         case SKL_DPLL0:
9752                 /*
9753                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9754                  * of the shared DPLL framework and thus needs to be read out
9755                  * separately
9756                  */
9757                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9758                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9759                 break;
9760         case SKL_DPLL1:
9761                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9762                 break;
9763         case SKL_DPLL2:
9764                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9765                 break;
9766         case SKL_DPLL3:
9767                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9768                 break;
9769         }
9770 }
9771
9772 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9773                                 enum port port,
9774                                 struct intel_crtc_state *pipe_config)
9775 {
9776         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9777
9778         switch (pipe_config->ddi_pll_sel) {
9779         case PORT_CLK_SEL_WRPLL1:
9780                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9781                 break;
9782         case PORT_CLK_SEL_WRPLL2:
9783                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9784                 break;
9785         }
9786 }
9787
9788 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9789                                        struct intel_crtc_state *pipe_config)
9790 {
9791         struct drm_device *dev = crtc->base.dev;
9792         struct drm_i915_private *dev_priv = dev->dev_private;
9793         struct intel_shared_dpll *pll;
9794         enum port port;
9795         uint32_t tmp;
9796
9797         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9798
9799         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9800
9801         if (IS_SKYLAKE(dev))
9802                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9803         else if (IS_BROXTON(dev))
9804                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9805         else
9806                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9807
9808         if (pipe_config->shared_dpll >= 0) {
9809                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9810
9811                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9812                                            &pipe_config->dpll_hw_state));
9813         }
9814
9815         /*
9816          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9817          * DDI E. So just check whether this pipe is wired to DDI E and whether
9818          * the PCH transcoder is on.
9819          */
9820         if (INTEL_INFO(dev)->gen < 9 &&
9821             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9822                 pipe_config->has_pch_encoder = true;
9823
9824                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9825                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9826                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9827
9828                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9829         }
9830 }
9831
9832 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9833                                     struct intel_crtc_state *pipe_config)
9834 {
9835         struct drm_device *dev = crtc->base.dev;
9836         struct drm_i915_private *dev_priv = dev->dev_private;
9837         enum intel_display_power_domain pfit_domain;
9838         uint32_t tmp;
9839
9840         if (!intel_display_power_is_enabled(dev_priv,
9841                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9842                 return false;
9843
9844         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9845         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9846
9847         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9848         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9849                 enum pipe trans_edp_pipe;
9850                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9851                 default:
9852                         WARN(1, "unknown pipe linked to edp transcoder\n");
9853                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9854                 case TRANS_DDI_EDP_INPUT_A_ON:
9855                         trans_edp_pipe = PIPE_A;
9856                         break;
9857                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9858                         trans_edp_pipe = PIPE_B;
9859                         break;
9860                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9861                         trans_edp_pipe = PIPE_C;
9862                         break;
9863                 }
9864
9865                 if (trans_edp_pipe == crtc->pipe)
9866                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9867         }
9868
9869         if (!intel_display_power_is_enabled(dev_priv,
9870                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9871                 return false;
9872
9873         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9874         if (!(tmp & PIPECONF_ENABLE))
9875                 return false;
9876
9877         haswell_get_ddi_port_state(crtc, pipe_config);
9878
9879         intel_get_pipe_timings(crtc, pipe_config);
9880
9881         if (INTEL_INFO(dev)->gen >= 9) {
9882                 skl_init_scalers(dev, crtc, pipe_config);
9883         }
9884
9885         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9886
9887         if (INTEL_INFO(dev)->gen >= 9) {
9888                 pipe_config->scaler_state.scaler_id = -1;
9889                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9890         }
9891
9892         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9893                 if (INTEL_INFO(dev)->gen == 9)
9894                         skylake_get_pfit_config(crtc, pipe_config);
9895                 else if (INTEL_INFO(dev)->gen < 9)
9896                         ironlake_get_pfit_config(crtc, pipe_config);
9897                 else
9898                         MISSING_CASE(INTEL_INFO(dev)->gen);
9899         }
9900
9901         if (IS_HASWELL(dev))
9902                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9903                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9904
9905         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9906                 pipe_config->pixel_multiplier =
9907                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9908         } else {
9909                 pipe_config->pixel_multiplier = 1;
9910         }
9911
9912         return true;
9913 }
9914
9915 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9916 {
9917         struct drm_device *dev = crtc->dev;
9918         struct drm_i915_private *dev_priv = dev->dev_private;
9919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9920         uint32_t cntl = 0, size = 0;
9921
9922         if (base) {
9923                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9924                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9925                 unsigned int stride = roundup_pow_of_two(width) * 4;
9926
9927                 switch (stride) {
9928                 default:
9929                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9930                                   width, stride);
9931                         stride = 256;
9932                         /* fallthrough */
9933                 case 256:
9934                 case 512:
9935                 case 1024:
9936                 case 2048:
9937                         break;
9938                 }
9939
9940                 cntl |= CURSOR_ENABLE |
9941                         CURSOR_GAMMA_ENABLE |
9942                         CURSOR_FORMAT_ARGB |
9943                         CURSOR_STRIDE(stride);
9944
9945                 size = (height << 12) | width;
9946         }
9947
9948         if (intel_crtc->cursor_cntl != 0 &&
9949             (intel_crtc->cursor_base != base ||
9950              intel_crtc->cursor_size != size ||
9951              intel_crtc->cursor_cntl != cntl)) {
9952                 /* On these chipsets we can only modify the base/size/stride
9953                  * whilst the cursor is disabled.
9954                  */
9955                 I915_WRITE(_CURACNTR, 0);
9956                 POSTING_READ(_CURACNTR);
9957                 intel_crtc->cursor_cntl = 0;
9958         }
9959
9960         if (intel_crtc->cursor_base != base) {
9961                 I915_WRITE(_CURABASE, base);
9962                 intel_crtc->cursor_base = base;
9963         }
9964
9965         if (intel_crtc->cursor_size != size) {
9966                 I915_WRITE(CURSIZE, size);
9967                 intel_crtc->cursor_size = size;
9968         }
9969
9970         if (intel_crtc->cursor_cntl != cntl) {
9971                 I915_WRITE(_CURACNTR, cntl);
9972                 POSTING_READ(_CURACNTR);
9973                 intel_crtc->cursor_cntl = cntl;
9974         }
9975 }
9976
9977 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9978 {
9979         struct drm_device *dev = crtc->dev;
9980         struct drm_i915_private *dev_priv = dev->dev_private;
9981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9982         int pipe = intel_crtc->pipe;
9983         uint32_t cntl;
9984
9985         cntl = 0;
9986         if (base) {
9987                 cntl = MCURSOR_GAMMA_ENABLE;
9988                 switch (intel_crtc->base.cursor->state->crtc_w) {
9989                         case 64:
9990                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9991                                 break;
9992                         case 128:
9993                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9994                                 break;
9995                         case 256:
9996                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9997                                 break;
9998                         default:
9999                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10000                                 return;
10001                 }
10002                 cntl |= pipe << 28; /* Connect to correct pipe */
10003
10004                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10005                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10006         }
10007
10008         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10009                 cntl |= CURSOR_ROTATE_180;
10010
10011         if (intel_crtc->cursor_cntl != cntl) {
10012                 I915_WRITE(CURCNTR(pipe), cntl);
10013                 POSTING_READ(CURCNTR(pipe));
10014                 intel_crtc->cursor_cntl = cntl;
10015         }
10016
10017         /* and commit changes on next vblank */
10018         I915_WRITE(CURBASE(pipe), base);
10019         POSTING_READ(CURBASE(pipe));
10020
10021         intel_crtc->cursor_base = base;
10022 }
10023
10024 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10025 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10026                                      bool on)
10027 {
10028         struct drm_device *dev = crtc->dev;
10029         struct drm_i915_private *dev_priv = dev->dev_private;
10030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10031         int pipe = intel_crtc->pipe;
10032         int x = crtc->cursor_x;
10033         int y = crtc->cursor_y;
10034         u32 base = 0, pos = 0;
10035
10036         if (on)
10037                 base = intel_crtc->cursor_addr;
10038
10039         if (x >= intel_crtc->config->pipe_src_w)
10040                 base = 0;
10041
10042         if (y >= intel_crtc->config->pipe_src_h)
10043                 base = 0;
10044
10045         if (x < 0) {
10046                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10047                         base = 0;
10048
10049                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10050                 x = -x;
10051         }
10052         pos |= x << CURSOR_X_SHIFT;
10053
10054         if (y < 0) {
10055                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10056                         base = 0;
10057
10058                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10059                 y = -y;
10060         }
10061         pos |= y << CURSOR_Y_SHIFT;
10062
10063         if (base == 0 && intel_crtc->cursor_base == 0)
10064                 return;
10065
10066         I915_WRITE(CURPOS(pipe), pos);
10067
10068         /* ILK+ do this automagically */
10069         if (HAS_GMCH_DISPLAY(dev) &&
10070             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10071                 base += (intel_crtc->base.cursor->state->crtc_h *
10072                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10073         }
10074
10075         if (IS_845G(dev) || IS_I865G(dev))
10076                 i845_update_cursor(crtc, base);
10077         else
10078                 i9xx_update_cursor(crtc, base);
10079 }
10080
10081 static bool cursor_size_ok(struct drm_device *dev,
10082                            uint32_t width, uint32_t height)
10083 {
10084         if (width == 0 || height == 0)
10085                 return false;
10086
10087         /*
10088          * 845g/865g are special in that they are only limited by
10089          * the width of their cursors, the height is arbitrary up to
10090          * the precision of the register. Everything else requires
10091          * square cursors, limited to a few power-of-two sizes.
10092          */
10093         if (IS_845G(dev) || IS_I865G(dev)) {
10094                 if ((width & 63) != 0)
10095                         return false;
10096
10097                 if (width > (IS_845G(dev) ? 64 : 512))
10098                         return false;
10099
10100                 if (height > 1023)
10101                         return false;
10102         } else {
10103                 switch (width | height) {
10104                 case 256:
10105                 case 128:
10106                         if (IS_GEN2(dev))
10107                                 return false;
10108                 case 64:
10109                         break;
10110                 default:
10111                         return false;
10112                 }
10113         }
10114
10115         return true;
10116 }
10117
10118 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10119                                  u16 *blue, uint32_t start, uint32_t size)
10120 {
10121         int end = (start + size > 256) ? 256 : start + size, i;
10122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10123
10124         for (i = start; i < end; i++) {
10125                 intel_crtc->lut_r[i] = red[i] >> 8;
10126                 intel_crtc->lut_g[i] = green[i] >> 8;
10127                 intel_crtc->lut_b[i] = blue[i] >> 8;
10128         }
10129
10130         intel_crtc_load_lut(crtc);
10131 }
10132
10133 /* VESA 640x480x72Hz mode to set on the pipe */
10134 static struct drm_display_mode load_detect_mode = {
10135         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10136                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10137 };
10138
10139 struct drm_framebuffer *
10140 __intel_framebuffer_create(struct drm_device *dev,
10141                            struct drm_mode_fb_cmd2 *mode_cmd,
10142                            struct drm_i915_gem_object *obj)
10143 {
10144         struct intel_framebuffer *intel_fb;
10145         int ret;
10146
10147         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10148         if (!intel_fb) {
10149                 drm_gem_object_unreference(&obj->base);
10150                 return ERR_PTR(-ENOMEM);
10151         }
10152
10153         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10154         if (ret)
10155                 goto err;
10156
10157         return &intel_fb->base;
10158 err:
10159         drm_gem_object_unreference(&obj->base);
10160         kfree(intel_fb);
10161
10162         return ERR_PTR(ret);
10163 }
10164
10165 static struct drm_framebuffer *
10166 intel_framebuffer_create(struct drm_device *dev,
10167                          struct drm_mode_fb_cmd2 *mode_cmd,
10168                          struct drm_i915_gem_object *obj)
10169 {
10170         struct drm_framebuffer *fb;
10171         int ret;
10172
10173         ret = i915_mutex_lock_interruptible(dev);
10174         if (ret)
10175                 return ERR_PTR(ret);
10176         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10177         mutex_unlock(&dev->struct_mutex);
10178
10179         return fb;
10180 }
10181
10182 static u32
10183 intel_framebuffer_pitch_for_width(int width, int bpp)
10184 {
10185         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10186         return ALIGN(pitch, 64);
10187 }
10188
10189 static u32
10190 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10191 {
10192         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10193         return PAGE_ALIGN(pitch * mode->vdisplay);
10194 }
10195
10196 static struct drm_framebuffer *
10197 intel_framebuffer_create_for_mode(struct drm_device *dev,
10198                                   struct drm_display_mode *mode,
10199                                   int depth, int bpp)
10200 {
10201         struct drm_i915_gem_object *obj;
10202         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10203
10204         obj = i915_gem_alloc_object(dev,
10205                                     intel_framebuffer_size_for_mode(mode, bpp));
10206         if (obj == NULL)
10207                 return ERR_PTR(-ENOMEM);
10208
10209         mode_cmd.width = mode->hdisplay;
10210         mode_cmd.height = mode->vdisplay;
10211         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10212                                                                 bpp);
10213         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10214
10215         return intel_framebuffer_create(dev, &mode_cmd, obj);
10216 }
10217
10218 static struct drm_framebuffer *
10219 mode_fits_in_fbdev(struct drm_device *dev,
10220                    struct drm_display_mode *mode)
10221 {
10222 #ifdef CONFIG_DRM_I915_FBDEV
10223         struct drm_i915_private *dev_priv = dev->dev_private;
10224         struct drm_i915_gem_object *obj;
10225         struct drm_framebuffer *fb;
10226
10227         if (!dev_priv->fbdev)
10228                 return NULL;
10229
10230         if (!dev_priv->fbdev->fb)
10231                 return NULL;
10232
10233         obj = dev_priv->fbdev->fb->obj;
10234         BUG_ON(!obj);
10235
10236         fb = &dev_priv->fbdev->fb->base;
10237         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10238                                                                fb->bits_per_pixel))
10239                 return NULL;
10240
10241         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10242                 return NULL;
10243
10244         return fb;
10245 #else
10246         return NULL;
10247 #endif
10248 }
10249
10250 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10251                                            struct drm_crtc *crtc,
10252                                            struct drm_display_mode *mode,
10253                                            struct drm_framebuffer *fb,
10254                                            int x, int y)
10255 {
10256         struct drm_plane_state *plane_state;
10257         int hdisplay, vdisplay;
10258         int ret;
10259
10260         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10261         if (IS_ERR(plane_state))
10262                 return PTR_ERR(plane_state);
10263
10264         if (mode)
10265                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10266         else
10267                 hdisplay = vdisplay = 0;
10268
10269         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10270         if (ret)
10271                 return ret;
10272         drm_atomic_set_fb_for_plane(plane_state, fb);
10273         plane_state->crtc_x = 0;
10274         plane_state->crtc_y = 0;
10275         plane_state->crtc_w = hdisplay;
10276         plane_state->crtc_h = vdisplay;
10277         plane_state->src_x = x << 16;
10278         plane_state->src_y = y << 16;
10279         plane_state->src_w = hdisplay << 16;
10280         plane_state->src_h = vdisplay << 16;
10281
10282         return 0;
10283 }
10284
10285 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10286                                 struct drm_display_mode *mode,
10287                                 struct intel_load_detect_pipe *old,
10288                                 struct drm_modeset_acquire_ctx *ctx)
10289 {
10290         struct intel_crtc *intel_crtc;
10291         struct intel_encoder *intel_encoder =
10292                 intel_attached_encoder(connector);
10293         struct drm_crtc *possible_crtc;
10294         struct drm_encoder *encoder = &intel_encoder->base;
10295         struct drm_crtc *crtc = NULL;
10296         struct drm_device *dev = encoder->dev;
10297         struct drm_framebuffer *fb;
10298         struct drm_mode_config *config = &dev->mode_config;
10299         struct drm_atomic_state *state = NULL;
10300         struct drm_connector_state *connector_state;
10301         struct intel_crtc_state *crtc_state;
10302         int ret, i = -1;
10303
10304         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10305                       connector->base.id, connector->name,
10306                       encoder->base.id, encoder->name);
10307
10308 retry:
10309         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10310         if (ret)
10311                 goto fail;
10312
10313         /*
10314          * Algorithm gets a little messy:
10315          *
10316          *   - if the connector already has an assigned crtc, use it (but make
10317          *     sure it's on first)
10318          *
10319          *   - try to find the first unused crtc that can drive this connector,
10320          *     and use that if we find one
10321          */
10322
10323         /* See if we already have a CRTC for this connector */
10324         if (encoder->crtc) {
10325                 crtc = encoder->crtc;
10326
10327                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10328                 if (ret)
10329                         goto fail;
10330                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10331                 if (ret)
10332                         goto fail;
10333
10334                 old->dpms_mode = connector->dpms;
10335                 old->load_detect_temp = false;
10336
10337                 /* Make sure the crtc and connector are running */
10338                 if (connector->dpms != DRM_MODE_DPMS_ON)
10339                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10340
10341                 return true;
10342         }
10343
10344         /* Find an unused one (if possible) */
10345         for_each_crtc(dev, possible_crtc) {
10346                 i++;
10347                 if (!(encoder->possible_crtcs & (1 << i)))
10348                         continue;
10349                 if (possible_crtc->state->enable)
10350                         continue;
10351
10352                 crtc = possible_crtc;
10353                 break;
10354         }
10355
10356         /*
10357          * If we didn't find an unused CRTC, don't use any.
10358          */
10359         if (!crtc) {
10360                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10361                 goto fail;
10362         }
10363
10364         ret = drm_modeset_lock(&crtc->mutex, ctx);
10365         if (ret)
10366                 goto fail;
10367         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10368         if (ret)
10369                 goto fail;
10370
10371         intel_crtc = to_intel_crtc(crtc);
10372         old->dpms_mode = connector->dpms;
10373         old->load_detect_temp = true;
10374         old->release_fb = NULL;
10375
10376         state = drm_atomic_state_alloc(dev);
10377         if (!state)
10378                 return false;
10379
10380         state->acquire_ctx = ctx;
10381
10382         connector_state = drm_atomic_get_connector_state(state, connector);
10383         if (IS_ERR(connector_state)) {
10384                 ret = PTR_ERR(connector_state);
10385                 goto fail;
10386         }
10387
10388         connector_state->crtc = crtc;
10389         connector_state->best_encoder = &intel_encoder->base;
10390
10391         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10392         if (IS_ERR(crtc_state)) {
10393                 ret = PTR_ERR(crtc_state);
10394                 goto fail;
10395         }
10396
10397         crtc_state->base.active = crtc_state->base.enable = true;
10398
10399         if (!mode)
10400                 mode = &load_detect_mode;
10401
10402         /* We need a framebuffer large enough to accommodate all accesses
10403          * that the plane may generate whilst we perform load detection.
10404          * We can not rely on the fbcon either being present (we get called
10405          * during its initialisation to detect all boot displays, or it may
10406          * not even exist) or that it is large enough to satisfy the
10407          * requested mode.
10408          */
10409         fb = mode_fits_in_fbdev(dev, mode);
10410         if (fb == NULL) {
10411                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10412                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10413                 old->release_fb = fb;
10414         } else
10415                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10416         if (IS_ERR(fb)) {
10417                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10418                 goto fail;
10419         }
10420
10421         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10422         if (ret)
10423                 goto fail;
10424
10425         drm_mode_copy(&crtc_state->base.mode, mode);
10426
10427         if (intel_set_mode(state)) {
10428                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10429                 if (old->release_fb)
10430                         old->release_fb->funcs->destroy(old->release_fb);
10431                 goto fail;
10432         }
10433         crtc->primary->crtc = crtc;
10434
10435         /* let the connector get through one full cycle before testing */
10436         intel_wait_for_vblank(dev, intel_crtc->pipe);
10437         return true;
10438
10439 fail:
10440         drm_atomic_state_free(state);
10441         state = NULL;
10442
10443         if (ret == -EDEADLK) {
10444                 drm_modeset_backoff(ctx);
10445                 goto retry;
10446         }
10447
10448         return false;
10449 }
10450
10451 void intel_release_load_detect_pipe(struct drm_connector *connector,
10452                                     struct intel_load_detect_pipe *old,
10453                                     struct drm_modeset_acquire_ctx *ctx)
10454 {
10455         struct drm_device *dev = connector->dev;
10456         struct intel_encoder *intel_encoder =
10457                 intel_attached_encoder(connector);
10458         struct drm_encoder *encoder = &intel_encoder->base;
10459         struct drm_crtc *crtc = encoder->crtc;
10460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10461         struct drm_atomic_state *state;
10462         struct drm_connector_state *connector_state;
10463         struct intel_crtc_state *crtc_state;
10464         int ret;
10465
10466         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10467                       connector->base.id, connector->name,
10468                       encoder->base.id, encoder->name);
10469
10470         if (old->load_detect_temp) {
10471                 state = drm_atomic_state_alloc(dev);
10472                 if (!state)
10473                         goto fail;
10474
10475                 state->acquire_ctx = ctx;
10476
10477                 connector_state = drm_atomic_get_connector_state(state, connector);
10478                 if (IS_ERR(connector_state))
10479                         goto fail;
10480
10481                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10482                 if (IS_ERR(crtc_state))
10483                         goto fail;
10484
10485                 connector_state->best_encoder = NULL;
10486                 connector_state->crtc = NULL;
10487
10488                 crtc_state->base.enable = crtc_state->base.active = false;
10489
10490                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10491                                                       0, 0);
10492                 if (ret)
10493                         goto fail;
10494
10495                 ret = intel_set_mode(state);
10496                 if (ret)
10497                         goto fail;
10498
10499                 if (old->release_fb) {
10500                         drm_framebuffer_unregister_private(old->release_fb);
10501                         drm_framebuffer_unreference(old->release_fb);
10502                 }
10503
10504                 return;
10505         }
10506
10507         /* Switch crtc and encoder back off if necessary */
10508         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10509                 connector->funcs->dpms(connector, old->dpms_mode);
10510
10511         return;
10512 fail:
10513         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10514         drm_atomic_state_free(state);
10515 }
10516
10517 static int i9xx_pll_refclk(struct drm_device *dev,
10518                            const struct intel_crtc_state *pipe_config)
10519 {
10520         struct drm_i915_private *dev_priv = dev->dev_private;
10521         u32 dpll = pipe_config->dpll_hw_state.dpll;
10522
10523         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10524                 return dev_priv->vbt.lvds_ssc_freq;
10525         else if (HAS_PCH_SPLIT(dev))
10526                 return 120000;
10527         else if (!IS_GEN2(dev))
10528                 return 96000;
10529         else
10530                 return 48000;
10531 }
10532
10533 /* Returns the clock of the currently programmed mode of the given pipe. */
10534 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10535                                 struct intel_crtc_state *pipe_config)
10536 {
10537         struct drm_device *dev = crtc->base.dev;
10538         struct drm_i915_private *dev_priv = dev->dev_private;
10539         int pipe = pipe_config->cpu_transcoder;
10540         u32 dpll = pipe_config->dpll_hw_state.dpll;
10541         u32 fp;
10542         intel_clock_t clock;
10543         int port_clock;
10544         int refclk = i9xx_pll_refclk(dev, pipe_config);
10545
10546         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10547                 fp = pipe_config->dpll_hw_state.fp0;
10548         else
10549                 fp = pipe_config->dpll_hw_state.fp1;
10550
10551         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10552         if (IS_PINEVIEW(dev)) {
10553                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10554                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10555         } else {
10556                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10557                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10558         }
10559
10560         if (!IS_GEN2(dev)) {
10561                 if (IS_PINEVIEW(dev))
10562                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10563                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10564                 else
10565                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10566                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10567
10568                 switch (dpll & DPLL_MODE_MASK) {
10569                 case DPLLB_MODE_DAC_SERIAL:
10570                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10571                                 5 : 10;
10572                         break;
10573                 case DPLLB_MODE_LVDS:
10574                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10575                                 7 : 14;
10576                         break;
10577                 default:
10578                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10579                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10580                         return;
10581                 }
10582
10583                 if (IS_PINEVIEW(dev))
10584                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10585                 else
10586                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10587         } else {
10588                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10589                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10590
10591                 if (is_lvds) {
10592                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10593                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10594
10595                         if (lvds & LVDS_CLKB_POWER_UP)
10596                                 clock.p2 = 7;
10597                         else
10598                                 clock.p2 = 14;
10599                 } else {
10600                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10601                                 clock.p1 = 2;
10602                         else {
10603                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10604                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10605                         }
10606                         if (dpll & PLL_P2_DIVIDE_BY_4)
10607                                 clock.p2 = 4;
10608                         else
10609                                 clock.p2 = 2;
10610                 }
10611
10612                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10613         }
10614
10615         /*
10616          * This value includes pixel_multiplier. We will use
10617          * port_clock to compute adjusted_mode.crtc_clock in the
10618          * encoder's get_config() function.
10619          */
10620         pipe_config->port_clock = port_clock;
10621 }
10622
10623 int intel_dotclock_calculate(int link_freq,
10624                              const struct intel_link_m_n *m_n)
10625 {
10626         /*
10627          * The calculation for the data clock is:
10628          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10629          * But we want to avoid losing precison if possible, so:
10630          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10631          *
10632          * and the link clock is simpler:
10633          * link_clock = (m * link_clock) / n
10634          */
10635
10636         if (!m_n->link_n)
10637                 return 0;
10638
10639         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10640 }
10641
10642 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10643                                    struct intel_crtc_state *pipe_config)
10644 {
10645         struct drm_device *dev = crtc->base.dev;
10646
10647         /* read out port_clock from the DPLL */
10648         i9xx_crtc_clock_get(crtc, pipe_config);
10649
10650         /*
10651          * This value does not include pixel_multiplier.
10652          * We will check that port_clock and adjusted_mode.crtc_clock
10653          * agree once we know their relationship in the encoder's
10654          * get_config() function.
10655          */
10656         pipe_config->base.adjusted_mode.crtc_clock =
10657                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10658                                          &pipe_config->fdi_m_n);
10659 }
10660
10661 /** Returns the currently programmed mode of the given pipe. */
10662 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10663                                              struct drm_crtc *crtc)
10664 {
10665         struct drm_i915_private *dev_priv = dev->dev_private;
10666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10667         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10668         struct drm_display_mode *mode;
10669         struct intel_crtc_state pipe_config;
10670         int htot = I915_READ(HTOTAL(cpu_transcoder));
10671         int hsync = I915_READ(HSYNC(cpu_transcoder));
10672         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10673         int vsync = I915_READ(VSYNC(cpu_transcoder));
10674         enum pipe pipe = intel_crtc->pipe;
10675
10676         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10677         if (!mode)
10678                 return NULL;
10679
10680         /*
10681          * Construct a pipe_config sufficient for getting the clock info
10682          * back out of crtc_clock_get.
10683          *
10684          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10685          * to use a real value here instead.
10686          */
10687         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10688         pipe_config.pixel_multiplier = 1;
10689         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10690         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10691         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10692         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10693
10694         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10695         mode->hdisplay = (htot & 0xffff) + 1;
10696         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10697         mode->hsync_start = (hsync & 0xffff) + 1;
10698         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10699         mode->vdisplay = (vtot & 0xffff) + 1;
10700         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10701         mode->vsync_start = (vsync & 0xffff) + 1;
10702         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10703
10704         drm_mode_set_name(mode);
10705
10706         return mode;
10707 }
10708
10709 void intel_mark_busy(struct drm_device *dev)
10710 {
10711         struct drm_i915_private *dev_priv = dev->dev_private;
10712
10713         if (dev_priv->mm.busy)
10714                 return;
10715
10716         intel_runtime_pm_get(dev_priv);
10717         i915_update_gfx_val(dev_priv);
10718         if (INTEL_INFO(dev)->gen >= 6)
10719                 gen6_rps_busy(dev_priv);
10720         dev_priv->mm.busy = true;
10721 }
10722
10723 void intel_mark_idle(struct drm_device *dev)
10724 {
10725         struct drm_i915_private *dev_priv = dev->dev_private;
10726
10727         if (!dev_priv->mm.busy)
10728                 return;
10729
10730         dev_priv->mm.busy = false;
10731
10732         if (INTEL_INFO(dev)->gen >= 6)
10733                 gen6_rps_idle(dev->dev_private);
10734
10735         intel_runtime_pm_put(dev_priv);
10736 }
10737
10738 static void intel_crtc_destroy(struct drm_crtc *crtc)
10739 {
10740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10741         struct drm_device *dev = crtc->dev;
10742         struct intel_unpin_work *work;
10743
10744         spin_lock_irq(&dev->event_lock);
10745         work = intel_crtc->unpin_work;
10746         intel_crtc->unpin_work = NULL;
10747         spin_unlock_irq(&dev->event_lock);
10748
10749         if (work) {
10750                 cancel_work_sync(&work->work);
10751                 kfree(work);
10752         }
10753
10754         drm_crtc_cleanup(crtc);
10755
10756         kfree(intel_crtc);
10757 }
10758
10759 static void intel_unpin_work_fn(struct work_struct *__work)
10760 {
10761         struct intel_unpin_work *work =
10762                 container_of(__work, struct intel_unpin_work, work);
10763         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10764         struct drm_device *dev = crtc->base.dev;
10765         struct drm_i915_private *dev_priv = dev->dev_private;
10766         struct drm_plane *primary = crtc->base.primary;
10767
10768         mutex_lock(&dev->struct_mutex);
10769         intel_unpin_fb_obj(work->old_fb, primary->state);
10770         drm_gem_object_unreference(&work->pending_flip_obj->base);
10771
10772         intel_fbc_update(dev_priv);
10773
10774         if (work->flip_queued_req)
10775                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10776         mutex_unlock(&dev->struct_mutex);
10777
10778         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10779         drm_framebuffer_unreference(work->old_fb);
10780
10781         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10782         atomic_dec(&crtc->unpin_work_count);
10783
10784         kfree(work);
10785 }
10786
10787 static void do_intel_finish_page_flip(struct drm_device *dev,
10788                                       struct drm_crtc *crtc)
10789 {
10790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10791         struct intel_unpin_work *work;
10792         unsigned long flags;
10793
10794         /* Ignore early vblank irqs */
10795         if (intel_crtc == NULL)
10796                 return;
10797
10798         /*
10799          * This is called both by irq handlers and the reset code (to complete
10800          * lost pageflips) so needs the full irqsave spinlocks.
10801          */
10802         spin_lock_irqsave(&dev->event_lock, flags);
10803         work = intel_crtc->unpin_work;
10804
10805         /* Ensure we don't miss a work->pending update ... */
10806         smp_rmb();
10807
10808         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10809                 spin_unlock_irqrestore(&dev->event_lock, flags);
10810                 return;
10811         }
10812
10813         page_flip_completed(intel_crtc);
10814
10815         spin_unlock_irqrestore(&dev->event_lock, flags);
10816 }
10817
10818 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10819 {
10820         struct drm_i915_private *dev_priv = dev->dev_private;
10821         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10822
10823         do_intel_finish_page_flip(dev, crtc);
10824 }
10825
10826 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10827 {
10828         struct drm_i915_private *dev_priv = dev->dev_private;
10829         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10830
10831         do_intel_finish_page_flip(dev, crtc);
10832 }
10833
10834 /* Is 'a' after or equal to 'b'? */
10835 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10836 {
10837         return !((a - b) & 0x80000000);
10838 }
10839
10840 static bool page_flip_finished(struct intel_crtc *crtc)
10841 {
10842         struct drm_device *dev = crtc->base.dev;
10843         struct drm_i915_private *dev_priv = dev->dev_private;
10844
10845         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10846             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10847                 return true;
10848
10849         /*
10850          * The relevant registers doen't exist on pre-ctg.
10851          * As the flip done interrupt doesn't trigger for mmio
10852          * flips on gmch platforms, a flip count check isn't
10853          * really needed there. But since ctg has the registers,
10854          * include it in the check anyway.
10855          */
10856         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10857                 return true;
10858
10859         /*
10860          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10861          * used the same base address. In that case the mmio flip might
10862          * have completed, but the CS hasn't even executed the flip yet.
10863          *
10864          * A flip count check isn't enough as the CS might have updated
10865          * the base address just after start of vblank, but before we
10866          * managed to process the interrupt. This means we'd complete the
10867          * CS flip too soon.
10868          *
10869          * Combining both checks should get us a good enough result. It may
10870          * still happen that the CS flip has been executed, but has not
10871          * yet actually completed. But in case the base address is the same
10872          * anyway, we don't really care.
10873          */
10874         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10875                 crtc->unpin_work->gtt_offset &&
10876                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10877                                     crtc->unpin_work->flip_count);
10878 }
10879
10880 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10881 {
10882         struct drm_i915_private *dev_priv = dev->dev_private;
10883         struct intel_crtc *intel_crtc =
10884                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10885         unsigned long flags;
10886
10887
10888         /*
10889          * This is called both by irq handlers and the reset code (to complete
10890          * lost pageflips) so needs the full irqsave spinlocks.
10891          *
10892          * NB: An MMIO update of the plane base pointer will also
10893          * generate a page-flip completion irq, i.e. every modeset
10894          * is also accompanied by a spurious intel_prepare_page_flip().
10895          */
10896         spin_lock_irqsave(&dev->event_lock, flags);
10897         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10898                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10899         spin_unlock_irqrestore(&dev->event_lock, flags);
10900 }
10901
10902 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10903 {
10904         /* Ensure that the work item is consistent when activating it ... */
10905         smp_wmb();
10906         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10907         /* and that it is marked active as soon as the irq could fire. */
10908         smp_wmb();
10909 }
10910
10911 static int intel_gen2_queue_flip(struct drm_device *dev,
10912                                  struct drm_crtc *crtc,
10913                                  struct drm_framebuffer *fb,
10914                                  struct drm_i915_gem_object *obj,
10915                                  struct drm_i915_gem_request *req,
10916                                  uint32_t flags)
10917 {
10918         struct intel_engine_cs *ring = req->ring;
10919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10920         u32 flip_mask;
10921         int ret;
10922
10923         ret = intel_ring_begin(req, 6);
10924         if (ret)
10925                 return ret;
10926
10927         /* Can't queue multiple flips, so wait for the previous
10928          * one to finish before executing the next.
10929          */
10930         if (intel_crtc->plane)
10931                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10932         else
10933                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10934         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10935         intel_ring_emit(ring, MI_NOOP);
10936         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10937                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10938         intel_ring_emit(ring, fb->pitches[0]);
10939         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10940         intel_ring_emit(ring, 0); /* aux display base address, unused */
10941
10942         intel_mark_page_flip_active(intel_crtc);
10943         return 0;
10944 }
10945
10946 static int intel_gen3_queue_flip(struct drm_device *dev,
10947                                  struct drm_crtc *crtc,
10948                                  struct drm_framebuffer *fb,
10949                                  struct drm_i915_gem_object *obj,
10950                                  struct drm_i915_gem_request *req,
10951                                  uint32_t flags)
10952 {
10953         struct intel_engine_cs *ring = req->ring;
10954         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10955         u32 flip_mask;
10956         int ret;
10957
10958         ret = intel_ring_begin(req, 6);
10959         if (ret)
10960                 return ret;
10961
10962         if (intel_crtc->plane)
10963                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10964         else
10965                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10966         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10967         intel_ring_emit(ring, MI_NOOP);
10968         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10969                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10970         intel_ring_emit(ring, fb->pitches[0]);
10971         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10972         intel_ring_emit(ring, MI_NOOP);
10973
10974         intel_mark_page_flip_active(intel_crtc);
10975         return 0;
10976 }
10977
10978 static int intel_gen4_queue_flip(struct drm_device *dev,
10979                                  struct drm_crtc *crtc,
10980                                  struct drm_framebuffer *fb,
10981                                  struct drm_i915_gem_object *obj,
10982                                  struct drm_i915_gem_request *req,
10983                                  uint32_t flags)
10984 {
10985         struct intel_engine_cs *ring = req->ring;
10986         struct drm_i915_private *dev_priv = dev->dev_private;
10987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10988         uint32_t pf, pipesrc;
10989         int ret;
10990
10991         ret = intel_ring_begin(req, 4);
10992         if (ret)
10993                 return ret;
10994
10995         /* i965+ uses the linear or tiled offsets from the
10996          * Display Registers (which do not change across a page-flip)
10997          * so we need only reprogram the base address.
10998          */
10999         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11000                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11001         intel_ring_emit(ring, fb->pitches[0]);
11002         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11003                         obj->tiling_mode);
11004
11005         /* XXX Enabling the panel-fitter across page-flip is so far
11006          * untested on non-native modes, so ignore it for now.
11007          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11008          */
11009         pf = 0;
11010         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11011         intel_ring_emit(ring, pf | pipesrc);
11012
11013         intel_mark_page_flip_active(intel_crtc);
11014         return 0;
11015 }
11016
11017 static int intel_gen6_queue_flip(struct drm_device *dev,
11018                                  struct drm_crtc *crtc,
11019                                  struct drm_framebuffer *fb,
11020                                  struct drm_i915_gem_object *obj,
11021                                  struct drm_i915_gem_request *req,
11022                                  uint32_t flags)
11023 {
11024         struct intel_engine_cs *ring = req->ring;
11025         struct drm_i915_private *dev_priv = dev->dev_private;
11026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11027         uint32_t pf, pipesrc;
11028         int ret;
11029
11030         ret = intel_ring_begin(req, 4);
11031         if (ret)
11032                 return ret;
11033
11034         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11035                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11036         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11037         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11038
11039         /* Contrary to the suggestions in the documentation,
11040          * "Enable Panel Fitter" does not seem to be required when page
11041          * flipping with a non-native mode, and worse causes a normal
11042          * modeset to fail.
11043          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11044          */
11045         pf = 0;
11046         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11047         intel_ring_emit(ring, pf | pipesrc);
11048
11049         intel_mark_page_flip_active(intel_crtc);
11050         return 0;
11051 }
11052
11053 static int intel_gen7_queue_flip(struct drm_device *dev,
11054                                  struct drm_crtc *crtc,
11055                                  struct drm_framebuffer *fb,
11056                                  struct drm_i915_gem_object *obj,
11057                                  struct drm_i915_gem_request *req,
11058                                  uint32_t flags)
11059 {
11060         struct intel_engine_cs *ring = req->ring;
11061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11062         uint32_t plane_bit = 0;
11063         int len, ret;
11064
11065         switch (intel_crtc->plane) {
11066         case PLANE_A:
11067                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11068                 break;
11069         case PLANE_B:
11070                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11071                 break;
11072         case PLANE_C:
11073                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11074                 break;
11075         default:
11076                 WARN_ONCE(1, "unknown plane in flip command\n");
11077                 return -ENODEV;
11078         }
11079
11080         len = 4;
11081         if (ring->id == RCS) {
11082                 len += 6;
11083                 /*
11084                  * On Gen 8, SRM is now taking an extra dword to accommodate
11085                  * 48bits addresses, and we need a NOOP for the batch size to
11086                  * stay even.
11087                  */
11088                 if (IS_GEN8(dev))
11089                         len += 2;
11090         }
11091
11092         /*
11093          * BSpec MI_DISPLAY_FLIP for IVB:
11094          * "The full packet must be contained within the same cache line."
11095          *
11096          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11097          * cacheline, if we ever start emitting more commands before
11098          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11099          * then do the cacheline alignment, and finally emit the
11100          * MI_DISPLAY_FLIP.
11101          */
11102         ret = intel_ring_cacheline_align(req);
11103         if (ret)
11104                 return ret;
11105
11106         ret = intel_ring_begin(req, len);
11107         if (ret)
11108                 return ret;
11109
11110         /* Unmask the flip-done completion message. Note that the bspec says that
11111          * we should do this for both the BCS and RCS, and that we must not unmask
11112          * more than one flip event at any time (or ensure that one flip message
11113          * can be sent by waiting for flip-done prior to queueing new flips).
11114          * Experimentation says that BCS works despite DERRMR masking all
11115          * flip-done completion events and that unmasking all planes at once
11116          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11117          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11118          */
11119         if (ring->id == RCS) {
11120                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11121                 intel_ring_emit(ring, DERRMR);
11122                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11123                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11124                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11125                 if (IS_GEN8(dev))
11126                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11127                                               MI_SRM_LRM_GLOBAL_GTT);
11128                 else
11129                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11130                                               MI_SRM_LRM_GLOBAL_GTT);
11131                 intel_ring_emit(ring, DERRMR);
11132                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11133                 if (IS_GEN8(dev)) {
11134                         intel_ring_emit(ring, 0);
11135                         intel_ring_emit(ring, MI_NOOP);
11136                 }
11137         }
11138
11139         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11140         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11141         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11142         intel_ring_emit(ring, (MI_NOOP));
11143
11144         intel_mark_page_flip_active(intel_crtc);
11145         return 0;
11146 }
11147
11148 static bool use_mmio_flip(struct intel_engine_cs *ring,
11149                           struct drm_i915_gem_object *obj)
11150 {
11151         /*
11152          * This is not being used for older platforms, because
11153          * non-availability of flip done interrupt forces us to use
11154          * CS flips. Older platforms derive flip done using some clever
11155          * tricks involving the flip_pending status bits and vblank irqs.
11156          * So using MMIO flips there would disrupt this mechanism.
11157          */
11158
11159         if (ring == NULL)
11160                 return true;
11161
11162         if (INTEL_INFO(ring->dev)->gen < 5)
11163                 return false;
11164
11165         if (i915.use_mmio_flip < 0)
11166                 return false;
11167         else if (i915.use_mmio_flip > 0)
11168                 return true;
11169         else if (i915.enable_execlists)
11170                 return true;
11171         else
11172                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11173 }
11174
11175 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11176 {
11177         struct drm_device *dev = intel_crtc->base.dev;
11178         struct drm_i915_private *dev_priv = dev->dev_private;
11179         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11180         const enum pipe pipe = intel_crtc->pipe;
11181         u32 ctl, stride;
11182
11183         ctl = I915_READ(PLANE_CTL(pipe, 0));
11184         ctl &= ~PLANE_CTL_TILED_MASK;
11185         switch (fb->modifier[0]) {
11186         case DRM_FORMAT_MOD_NONE:
11187                 break;
11188         case I915_FORMAT_MOD_X_TILED:
11189                 ctl |= PLANE_CTL_TILED_X;
11190                 break;
11191         case I915_FORMAT_MOD_Y_TILED:
11192                 ctl |= PLANE_CTL_TILED_Y;
11193                 break;
11194         case I915_FORMAT_MOD_Yf_TILED:
11195                 ctl |= PLANE_CTL_TILED_YF;
11196                 break;
11197         default:
11198                 MISSING_CASE(fb->modifier[0]);
11199         }
11200
11201         /*
11202          * The stride is either expressed as a multiple of 64 bytes chunks for
11203          * linear buffers or in number of tiles for tiled buffers.
11204          */
11205         stride = fb->pitches[0] /
11206                  intel_fb_stride_alignment(dev, fb->modifier[0],
11207                                            fb->pixel_format);
11208
11209         /*
11210          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11211          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11212          */
11213         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11214         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11215
11216         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11217         POSTING_READ(PLANE_SURF(pipe, 0));
11218 }
11219
11220 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11221 {
11222         struct drm_device *dev = intel_crtc->base.dev;
11223         struct drm_i915_private *dev_priv = dev->dev_private;
11224         struct intel_framebuffer *intel_fb =
11225                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11226         struct drm_i915_gem_object *obj = intel_fb->obj;
11227         u32 dspcntr;
11228         u32 reg;
11229
11230         reg = DSPCNTR(intel_crtc->plane);
11231         dspcntr = I915_READ(reg);
11232
11233         if (obj->tiling_mode != I915_TILING_NONE)
11234                 dspcntr |= DISPPLANE_TILED;
11235         else
11236                 dspcntr &= ~DISPPLANE_TILED;
11237
11238         I915_WRITE(reg, dspcntr);
11239
11240         I915_WRITE(DSPSURF(intel_crtc->plane),
11241                    intel_crtc->unpin_work->gtt_offset);
11242         POSTING_READ(DSPSURF(intel_crtc->plane));
11243
11244 }
11245
11246 /*
11247  * XXX: This is the temporary way to update the plane registers until we get
11248  * around to using the usual plane update functions for MMIO flips
11249  */
11250 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11251 {
11252         struct drm_device *dev = intel_crtc->base.dev;
11253         bool atomic_update;
11254         u32 start_vbl_count;
11255
11256         intel_mark_page_flip_active(intel_crtc);
11257
11258         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11259
11260         if (INTEL_INFO(dev)->gen >= 9)
11261                 skl_do_mmio_flip(intel_crtc);
11262         else
11263                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11264                 ilk_do_mmio_flip(intel_crtc);
11265
11266         if (atomic_update)
11267                 intel_pipe_update_end(intel_crtc, start_vbl_count);
11268 }
11269
11270 static void intel_mmio_flip_work_func(struct work_struct *work)
11271 {
11272         struct intel_mmio_flip *mmio_flip =
11273                 container_of(work, struct intel_mmio_flip, work);
11274
11275         if (mmio_flip->req)
11276                 WARN_ON(__i915_wait_request(mmio_flip->req,
11277                                             mmio_flip->crtc->reset_counter,
11278                                             false, NULL,
11279                                             &mmio_flip->i915->rps.mmioflips));
11280
11281         intel_do_mmio_flip(mmio_flip->crtc);
11282
11283         i915_gem_request_unreference__unlocked(mmio_flip->req);
11284         kfree(mmio_flip);
11285 }
11286
11287 static int intel_queue_mmio_flip(struct drm_device *dev,
11288                                  struct drm_crtc *crtc,
11289                                  struct drm_framebuffer *fb,
11290                                  struct drm_i915_gem_object *obj,
11291                                  struct intel_engine_cs *ring,
11292                                  uint32_t flags)
11293 {
11294         struct intel_mmio_flip *mmio_flip;
11295
11296         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11297         if (mmio_flip == NULL)
11298                 return -ENOMEM;
11299
11300         mmio_flip->i915 = to_i915(dev);
11301         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11302         mmio_flip->crtc = to_intel_crtc(crtc);
11303
11304         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11305         schedule_work(&mmio_flip->work);
11306
11307         return 0;
11308 }
11309
11310 static int intel_default_queue_flip(struct drm_device *dev,
11311                                     struct drm_crtc *crtc,
11312                                     struct drm_framebuffer *fb,
11313                                     struct drm_i915_gem_object *obj,
11314                                     struct drm_i915_gem_request *req,
11315                                     uint32_t flags)
11316 {
11317         return -ENODEV;
11318 }
11319
11320 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11321                                          struct drm_crtc *crtc)
11322 {
11323         struct drm_i915_private *dev_priv = dev->dev_private;
11324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11325         struct intel_unpin_work *work = intel_crtc->unpin_work;
11326         u32 addr;
11327
11328         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11329                 return true;
11330
11331         if (!work->enable_stall_check)
11332                 return false;
11333
11334         if (work->flip_ready_vblank == 0) {
11335                 if (work->flip_queued_req &&
11336                     !i915_gem_request_completed(work->flip_queued_req, true))
11337                         return false;
11338
11339                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11340         }
11341
11342         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11343                 return false;
11344
11345         /* Potential stall - if we see that the flip has happened,
11346          * assume a missed interrupt. */
11347         if (INTEL_INFO(dev)->gen >= 4)
11348                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11349         else
11350                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11351
11352         /* There is a potential issue here with a false positive after a flip
11353          * to the same address. We could address this by checking for a
11354          * non-incrementing frame counter.
11355          */
11356         return addr == work->gtt_offset;
11357 }
11358
11359 void intel_check_page_flip(struct drm_device *dev, int pipe)
11360 {
11361         struct drm_i915_private *dev_priv = dev->dev_private;
11362         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11364         struct intel_unpin_work *work;
11365
11366         WARN_ON(!in_interrupt());
11367
11368         if (crtc == NULL)
11369                 return;
11370
11371         spin_lock(&dev->event_lock);
11372         work = intel_crtc->unpin_work;
11373         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11374                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11375                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11376                 page_flip_completed(intel_crtc);
11377                 work = NULL;
11378         }
11379         if (work != NULL &&
11380             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11381                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11382         spin_unlock(&dev->event_lock);
11383 }
11384
11385 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11386                                 struct drm_framebuffer *fb,
11387                                 struct drm_pending_vblank_event *event,
11388                                 uint32_t page_flip_flags)
11389 {
11390         struct drm_device *dev = crtc->dev;
11391         struct drm_i915_private *dev_priv = dev->dev_private;
11392         struct drm_framebuffer *old_fb = crtc->primary->fb;
11393         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11395         struct drm_plane *primary = crtc->primary;
11396         enum pipe pipe = intel_crtc->pipe;
11397         struct intel_unpin_work *work;
11398         struct intel_engine_cs *ring;
11399         bool mmio_flip;
11400         struct drm_i915_gem_request *request = NULL;
11401         int ret;
11402
11403         /*
11404          * drm_mode_page_flip_ioctl() should already catch this, but double
11405          * check to be safe.  In the future we may enable pageflipping from
11406          * a disabled primary plane.
11407          */
11408         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11409                 return -EBUSY;
11410
11411         /* Can't change pixel format via MI display flips. */
11412         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11413                 return -EINVAL;
11414
11415         /*
11416          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11417          * Note that pitch changes could also affect these register.
11418          */
11419         if (INTEL_INFO(dev)->gen > 3 &&
11420             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11421              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11422                 return -EINVAL;
11423
11424         if (i915_terminally_wedged(&dev_priv->gpu_error))
11425                 goto out_hang;
11426
11427         work = kzalloc(sizeof(*work), GFP_KERNEL);
11428         if (work == NULL)
11429                 return -ENOMEM;
11430
11431         work->event = event;
11432         work->crtc = crtc;
11433         work->old_fb = old_fb;
11434         INIT_WORK(&work->work, intel_unpin_work_fn);
11435
11436         ret = drm_crtc_vblank_get(crtc);
11437         if (ret)
11438                 goto free_work;
11439
11440         /* We borrow the event spin lock for protecting unpin_work */
11441         spin_lock_irq(&dev->event_lock);
11442         if (intel_crtc->unpin_work) {
11443                 /* Before declaring the flip queue wedged, check if
11444                  * the hardware completed the operation behind our backs.
11445                  */
11446                 if (__intel_pageflip_stall_check(dev, crtc)) {
11447                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11448                         page_flip_completed(intel_crtc);
11449                 } else {
11450                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11451                         spin_unlock_irq(&dev->event_lock);
11452
11453                         drm_crtc_vblank_put(crtc);
11454                         kfree(work);
11455                         return -EBUSY;
11456                 }
11457         }
11458         intel_crtc->unpin_work = work;
11459         spin_unlock_irq(&dev->event_lock);
11460
11461         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11462                 flush_workqueue(dev_priv->wq);
11463
11464         /* Reference the objects for the scheduled work. */
11465         drm_framebuffer_reference(work->old_fb);
11466         drm_gem_object_reference(&obj->base);
11467
11468         crtc->primary->fb = fb;
11469         update_state_fb(crtc->primary);
11470
11471         work->pending_flip_obj = obj;
11472
11473         ret = i915_mutex_lock_interruptible(dev);
11474         if (ret)
11475                 goto cleanup;
11476
11477         atomic_inc(&intel_crtc->unpin_work_count);
11478         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11479
11480         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11481                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11482
11483         if (IS_VALLEYVIEW(dev)) {
11484                 ring = &dev_priv->ring[BCS];
11485                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11486                         /* vlv: DISPLAY_FLIP fails to change tiling */
11487                         ring = NULL;
11488         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11489                 ring = &dev_priv->ring[BCS];
11490         } else if (INTEL_INFO(dev)->gen >= 7) {
11491                 ring = i915_gem_request_get_ring(obj->last_write_req);
11492                 if (ring == NULL || ring->id != RCS)
11493                         ring = &dev_priv->ring[BCS];
11494         } else {
11495                 ring = &dev_priv->ring[RCS];
11496         }
11497
11498         mmio_flip = use_mmio_flip(ring, obj);
11499
11500         /* When using CS flips, we want to emit semaphores between rings.
11501          * However, when using mmio flips we will create a task to do the
11502          * synchronisation, so all we want here is to pin the framebuffer
11503          * into the display plane and skip any waits.
11504          */
11505         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11506                                          crtc->primary->state,
11507                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11508         if (ret)
11509                 goto cleanup_pending;
11510
11511         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11512                                                   + intel_crtc->dspaddr_offset;
11513
11514         if (mmio_flip) {
11515                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11516                                             page_flip_flags);
11517                 if (ret)
11518                         goto cleanup_unpin;
11519
11520                 i915_gem_request_assign(&work->flip_queued_req,
11521                                         obj->last_write_req);
11522         } else {
11523                 if (!request) {
11524                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11525                         if (ret)
11526                                 goto cleanup_unpin;
11527                 }
11528
11529                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11530                                                    page_flip_flags);
11531                 if (ret)
11532                         goto cleanup_unpin;
11533
11534                 i915_gem_request_assign(&work->flip_queued_req, request);
11535         }
11536
11537         if (request)
11538                 i915_add_request_no_flush(request);
11539
11540         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11541         work->enable_stall_check = true;
11542
11543         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11544                           to_intel_plane(primary)->frontbuffer_bit);
11545         mutex_unlock(&dev->struct_mutex);
11546
11547         intel_fbc_disable(dev_priv);
11548         intel_frontbuffer_flip_prepare(dev,
11549                                        to_intel_plane(primary)->frontbuffer_bit);
11550
11551         trace_i915_flip_request(intel_crtc->plane, obj);
11552
11553         return 0;
11554
11555 cleanup_unpin:
11556         intel_unpin_fb_obj(fb, crtc->primary->state);
11557 cleanup_pending:
11558         if (request)
11559                 i915_gem_request_cancel(request);
11560         atomic_dec(&intel_crtc->unpin_work_count);
11561         mutex_unlock(&dev->struct_mutex);
11562 cleanup:
11563         crtc->primary->fb = old_fb;
11564         update_state_fb(crtc->primary);
11565
11566         drm_gem_object_unreference_unlocked(&obj->base);
11567         drm_framebuffer_unreference(work->old_fb);
11568
11569         spin_lock_irq(&dev->event_lock);
11570         intel_crtc->unpin_work = NULL;
11571         spin_unlock_irq(&dev->event_lock);
11572
11573         drm_crtc_vblank_put(crtc);
11574 free_work:
11575         kfree(work);
11576
11577         if (ret == -EIO) {
11578                 struct drm_atomic_state *state;
11579                 struct drm_plane_state *plane_state;
11580
11581 out_hang:
11582                 state = drm_atomic_state_alloc(dev);
11583                 if (!state)
11584                         return -ENOMEM;
11585                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11586
11587 retry:
11588                 plane_state = drm_atomic_get_plane_state(state, primary);
11589                 ret = PTR_ERR_OR_ZERO(plane_state);
11590                 if (!ret) {
11591                         drm_atomic_set_fb_for_plane(plane_state, fb);
11592
11593                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11594                         if (!ret)
11595                                 ret = drm_atomic_commit(state);
11596                 }
11597
11598                 if (ret == -EDEADLK) {
11599                         drm_modeset_backoff(state->acquire_ctx);
11600                         drm_atomic_state_clear(state);
11601                         goto retry;
11602                 }
11603
11604                 if (ret)
11605                         drm_atomic_state_free(state);
11606
11607                 if (ret == 0 && event) {
11608                         spin_lock_irq(&dev->event_lock);
11609                         drm_send_vblank_event(dev, pipe, event);
11610                         spin_unlock_irq(&dev->event_lock);
11611                 }
11612         }
11613         return ret;
11614 }
11615
11616
11617 /**
11618  * intel_wm_need_update - Check whether watermarks need updating
11619  * @plane: drm plane
11620  * @state: new plane state
11621  *
11622  * Check current plane state versus the new one to determine whether
11623  * watermarks need to be recalculated.
11624  *
11625  * Returns true or false.
11626  */
11627 static bool intel_wm_need_update(struct drm_plane *plane,
11628                                  struct drm_plane_state *state)
11629 {
11630         /* Update watermarks on tiling changes. */
11631         if (!plane->state->fb || !state->fb ||
11632             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11633             plane->state->rotation != state->rotation)
11634                 return true;
11635
11636         if (plane->state->crtc_w != state->crtc_w)
11637                 return true;
11638
11639         return false;
11640 }
11641
11642 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11643                                     struct drm_plane_state *plane_state)
11644 {
11645         struct drm_crtc *crtc = crtc_state->crtc;
11646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11647         struct drm_plane *plane = plane_state->plane;
11648         struct drm_device *dev = crtc->dev;
11649         struct drm_i915_private *dev_priv = dev->dev_private;
11650         struct intel_plane_state *old_plane_state =
11651                 to_intel_plane_state(plane->state);
11652         int idx = intel_crtc->base.base.id, ret;
11653         int i = drm_plane_index(plane);
11654         bool mode_changed = needs_modeset(crtc_state);
11655         bool was_crtc_enabled = crtc->state->active;
11656         bool is_crtc_enabled = crtc_state->active;
11657
11658         bool turn_off, turn_on, visible, was_visible;
11659         struct drm_framebuffer *fb = plane_state->fb;
11660
11661         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11662             plane->type != DRM_PLANE_TYPE_CURSOR) {
11663                 ret = skl_update_scaler_plane(
11664                         to_intel_crtc_state(crtc_state),
11665                         to_intel_plane_state(plane_state));
11666                 if (ret)
11667                         return ret;
11668         }
11669
11670         /*
11671          * Disabling a plane is always okay; we just need to update
11672          * fb tracking in a special way since cleanup_fb() won't
11673          * get called by the plane helpers.
11674          */
11675         if (old_plane_state->base.fb && !fb)
11676                 intel_crtc->atomic.disabled_planes |= 1 << i;
11677
11678         was_visible = old_plane_state->visible;
11679         visible = to_intel_plane_state(plane_state)->visible;
11680
11681         if (!was_crtc_enabled && WARN_ON(was_visible))
11682                 was_visible = false;
11683
11684         if (!is_crtc_enabled && WARN_ON(visible))
11685                 visible = false;
11686
11687         if (!was_visible && !visible)
11688                 return 0;
11689
11690         turn_off = was_visible && (!visible || mode_changed);
11691         turn_on = visible && (!was_visible || mode_changed);
11692
11693         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11694                          plane->base.id, fb ? fb->base.id : -1);
11695
11696         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11697                          plane->base.id, was_visible, visible,
11698                          turn_off, turn_on, mode_changed);
11699
11700         if (turn_on) {
11701                 intel_crtc->atomic.update_wm_pre = true;
11702                 /* must disable cxsr around plane enable/disable */
11703                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11704                         intel_crtc->atomic.disable_cxsr = true;
11705                         /* to potentially re-enable cxsr */
11706                         intel_crtc->atomic.wait_vblank = true;
11707                         intel_crtc->atomic.update_wm_post = true;
11708                 }
11709         } else if (turn_off) {
11710                 intel_crtc->atomic.update_wm_post = true;
11711                 /* must disable cxsr around plane enable/disable */
11712                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11713                         if (is_crtc_enabled)
11714                                 intel_crtc->atomic.wait_vblank = true;
11715                         intel_crtc->atomic.disable_cxsr = true;
11716                 }
11717         } else if (intel_wm_need_update(plane, plane_state)) {
11718                 intel_crtc->atomic.update_wm_pre = true;
11719         }
11720
11721         if (visible)
11722                 intel_crtc->atomic.fb_bits |=
11723                         to_intel_plane(plane)->frontbuffer_bit;
11724
11725         switch (plane->type) {
11726         case DRM_PLANE_TYPE_PRIMARY:
11727                 intel_crtc->atomic.wait_for_flips = true;
11728                 intel_crtc->atomic.pre_disable_primary = turn_off;
11729                 intel_crtc->atomic.post_enable_primary = turn_on;
11730
11731                 if (turn_off) {
11732                         /*
11733                          * FIXME: Actually if we will still have any other
11734                          * plane enabled on the pipe we could let IPS enabled
11735                          * still, but for now lets consider that when we make
11736                          * primary invisible by setting DSPCNTR to 0 on
11737                          * update_primary_plane function IPS needs to be
11738                          * disable.
11739                          */
11740                         intel_crtc->atomic.disable_ips = true;
11741
11742                         intel_crtc->atomic.disable_fbc = true;
11743                 }
11744
11745                 /*
11746                  * FBC does not work on some platforms for rotated
11747                  * planes, so disable it when rotation is not 0 and
11748                  * update it when rotation is set back to 0.
11749                  *
11750                  * FIXME: This is redundant with the fbc update done in
11751                  * the primary plane enable function except that that
11752                  * one is done too late. We eventually need to unify
11753                  * this.
11754                  */
11755
11756                 if (visible &&
11757                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11758                     dev_priv->fbc.crtc == intel_crtc &&
11759                     plane_state->rotation != BIT(DRM_ROTATE_0))
11760                         intel_crtc->atomic.disable_fbc = true;
11761
11762                 /*
11763                  * BDW signals flip done immediately if the plane
11764                  * is disabled, even if the plane enable is already
11765                  * armed to occur at the next vblank :(
11766                  */
11767                 if (turn_on && IS_BROADWELL(dev))
11768                         intel_crtc->atomic.wait_vblank = true;
11769
11770                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11771                 break;
11772         case DRM_PLANE_TYPE_CURSOR:
11773                 break;
11774         case DRM_PLANE_TYPE_OVERLAY:
11775                 if (turn_off && !mode_changed) {
11776                         intel_crtc->atomic.wait_vblank = true;
11777                         intel_crtc->atomic.update_sprite_watermarks |=
11778                                 1 << i;
11779                 }
11780         }
11781         return 0;
11782 }
11783
11784 static bool encoders_cloneable(const struct intel_encoder *a,
11785                                const struct intel_encoder *b)
11786 {
11787         /* masks could be asymmetric, so check both ways */
11788         return a == b || (a->cloneable & (1 << b->type) &&
11789                           b->cloneable & (1 << a->type));
11790 }
11791
11792 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11793                                          struct intel_crtc *crtc,
11794                                          struct intel_encoder *encoder)
11795 {
11796         struct intel_encoder *source_encoder;
11797         struct drm_connector *connector;
11798         struct drm_connector_state *connector_state;
11799         int i;
11800
11801         for_each_connector_in_state(state, connector, connector_state, i) {
11802                 if (connector_state->crtc != &crtc->base)
11803                         continue;
11804
11805                 source_encoder =
11806                         to_intel_encoder(connector_state->best_encoder);
11807                 if (!encoders_cloneable(encoder, source_encoder))
11808                         return false;
11809         }
11810
11811         return true;
11812 }
11813
11814 static bool check_encoder_cloning(struct drm_atomic_state *state,
11815                                   struct intel_crtc *crtc)
11816 {
11817         struct intel_encoder *encoder;
11818         struct drm_connector *connector;
11819         struct drm_connector_state *connector_state;
11820         int i;
11821
11822         for_each_connector_in_state(state, connector, connector_state, i) {
11823                 if (connector_state->crtc != &crtc->base)
11824                         continue;
11825
11826                 encoder = to_intel_encoder(connector_state->best_encoder);
11827                 if (!check_single_encoder_cloning(state, crtc, encoder))
11828                         return false;
11829         }
11830
11831         return true;
11832 }
11833
11834 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11835                                    struct drm_crtc_state *crtc_state)
11836 {
11837         struct drm_device *dev = crtc->dev;
11838         struct drm_i915_private *dev_priv = dev->dev_private;
11839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11840         struct intel_crtc_state *pipe_config =
11841                 to_intel_crtc_state(crtc_state);
11842         struct drm_atomic_state *state = crtc_state->state;
11843         int ret, idx = crtc->base.id;
11844         bool mode_changed = needs_modeset(crtc_state);
11845
11846         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11847                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11848                 return -EINVAL;
11849         }
11850
11851         I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11852                 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11853                 idx, crtc->state->active, intel_crtc->active);
11854
11855         if (mode_changed && !crtc_state->active)
11856                 intel_crtc->atomic.update_wm_post = true;
11857
11858         if (mode_changed && crtc_state->enable &&
11859             dev_priv->display.crtc_compute_clock &&
11860             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11861                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11862                                                            pipe_config);
11863                 if (ret)
11864                         return ret;
11865         }
11866
11867         ret = 0;
11868         if (INTEL_INFO(dev)->gen >= 9) {
11869                 if (mode_changed)
11870                         ret = skl_update_scaler_crtc(pipe_config);
11871
11872                 if (!ret)
11873                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11874                                                          pipe_config);
11875         }
11876
11877         return ret;
11878 }
11879
11880 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11881         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11882         .load_lut = intel_crtc_load_lut,
11883         .atomic_begin = intel_begin_crtc_commit,
11884         .atomic_flush = intel_finish_crtc_commit,
11885         .atomic_check = intel_crtc_atomic_check,
11886 };
11887
11888 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11889 {
11890         struct intel_connector *connector;
11891
11892         for_each_intel_connector(dev, connector) {
11893                 if (connector->base.encoder) {
11894                         connector->base.state->best_encoder =
11895                                 connector->base.encoder;
11896                         connector->base.state->crtc =
11897                                 connector->base.encoder->crtc;
11898                 } else {
11899                         connector->base.state->best_encoder = NULL;
11900                         connector->base.state->crtc = NULL;
11901                 }
11902         }
11903 }
11904
11905 static void
11906 connected_sink_compute_bpp(struct intel_connector *connector,
11907                            struct intel_crtc_state *pipe_config)
11908 {
11909         int bpp = pipe_config->pipe_bpp;
11910
11911         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11912                 connector->base.base.id,
11913                 connector->base.name);
11914
11915         /* Don't use an invalid EDID bpc value */
11916         if (connector->base.display_info.bpc &&
11917             connector->base.display_info.bpc * 3 < bpp) {
11918                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11919                               bpp, connector->base.display_info.bpc*3);
11920                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11921         }
11922
11923         /* Clamp bpp to 8 on screens without EDID 1.4 */
11924         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11925                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11926                               bpp);
11927                 pipe_config->pipe_bpp = 24;
11928         }
11929 }
11930
11931 static int
11932 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11933                           struct intel_crtc_state *pipe_config)
11934 {
11935         struct drm_device *dev = crtc->base.dev;
11936         struct drm_atomic_state *state;
11937         struct drm_connector *connector;
11938         struct drm_connector_state *connector_state;
11939         int bpp, i;
11940
11941         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11942                 bpp = 10*3;
11943         else if (INTEL_INFO(dev)->gen >= 5)
11944                 bpp = 12*3;
11945         else
11946                 bpp = 8*3;
11947
11948
11949         pipe_config->pipe_bpp = bpp;
11950
11951         state = pipe_config->base.state;
11952
11953         /* Clamp display bpp to EDID value */
11954         for_each_connector_in_state(state, connector, connector_state, i) {
11955                 if (connector_state->crtc != &crtc->base)
11956                         continue;
11957
11958                 connected_sink_compute_bpp(to_intel_connector(connector),
11959                                            pipe_config);
11960         }
11961
11962         return bpp;
11963 }
11964
11965 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11966 {
11967         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11968                         "type: 0x%x flags: 0x%x\n",
11969                 mode->crtc_clock,
11970                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11971                 mode->crtc_hsync_end, mode->crtc_htotal,
11972                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11973                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11974 }
11975
11976 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11977                                    struct intel_crtc_state *pipe_config,
11978                                    const char *context)
11979 {
11980         struct drm_device *dev = crtc->base.dev;
11981         struct drm_plane *plane;
11982         struct intel_plane *intel_plane;
11983         struct intel_plane_state *state;
11984         struct drm_framebuffer *fb;
11985
11986         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11987                       context, pipe_config, pipe_name(crtc->pipe));
11988
11989         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11990         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11991                       pipe_config->pipe_bpp, pipe_config->dither);
11992         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11993                       pipe_config->has_pch_encoder,
11994                       pipe_config->fdi_lanes,
11995                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11996                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11997                       pipe_config->fdi_m_n.tu);
11998         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11999                       pipe_config->has_dp_encoder,
12000                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12001                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12002                       pipe_config->dp_m_n.tu);
12003
12004         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12005                       pipe_config->has_dp_encoder,
12006                       pipe_config->dp_m2_n2.gmch_m,
12007                       pipe_config->dp_m2_n2.gmch_n,
12008                       pipe_config->dp_m2_n2.link_m,
12009                       pipe_config->dp_m2_n2.link_n,
12010                       pipe_config->dp_m2_n2.tu);
12011
12012         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12013                       pipe_config->has_audio,
12014                       pipe_config->has_infoframe);
12015
12016         DRM_DEBUG_KMS("requested mode:\n");
12017         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12018         DRM_DEBUG_KMS("adjusted mode:\n");
12019         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12020         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12021         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12022         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12023                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12024         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12025                       crtc->num_scalers,
12026                       pipe_config->scaler_state.scaler_users,
12027                       pipe_config->scaler_state.scaler_id);
12028         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12029                       pipe_config->gmch_pfit.control,
12030                       pipe_config->gmch_pfit.pgm_ratios,
12031                       pipe_config->gmch_pfit.lvds_border_bits);
12032         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12033                       pipe_config->pch_pfit.pos,
12034                       pipe_config->pch_pfit.size,
12035                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12036         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12037         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12038
12039         if (IS_BROXTON(dev)) {
12040                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12041                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12042                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12043                               pipe_config->ddi_pll_sel,
12044                               pipe_config->dpll_hw_state.ebb0,
12045                               pipe_config->dpll_hw_state.ebb4,
12046                               pipe_config->dpll_hw_state.pll0,
12047                               pipe_config->dpll_hw_state.pll1,
12048                               pipe_config->dpll_hw_state.pll2,
12049                               pipe_config->dpll_hw_state.pll3,
12050                               pipe_config->dpll_hw_state.pll6,
12051                               pipe_config->dpll_hw_state.pll8,
12052                               pipe_config->dpll_hw_state.pll9,
12053                               pipe_config->dpll_hw_state.pll10,
12054                               pipe_config->dpll_hw_state.pcsdw12);
12055         } else if (IS_SKYLAKE(dev)) {
12056                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12057                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12058                               pipe_config->ddi_pll_sel,
12059                               pipe_config->dpll_hw_state.ctrl1,
12060                               pipe_config->dpll_hw_state.cfgcr1,
12061                               pipe_config->dpll_hw_state.cfgcr2);
12062         } else if (HAS_DDI(dev)) {
12063                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12064                               pipe_config->ddi_pll_sel,
12065                               pipe_config->dpll_hw_state.wrpll);
12066         } else {
12067                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12068                               "fp0: 0x%x, fp1: 0x%x\n",
12069                               pipe_config->dpll_hw_state.dpll,
12070                               pipe_config->dpll_hw_state.dpll_md,
12071                               pipe_config->dpll_hw_state.fp0,
12072                               pipe_config->dpll_hw_state.fp1);
12073         }
12074
12075         DRM_DEBUG_KMS("planes on this crtc\n");
12076         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12077                 intel_plane = to_intel_plane(plane);
12078                 if (intel_plane->pipe != crtc->pipe)
12079                         continue;
12080
12081                 state = to_intel_plane_state(plane->state);
12082                 fb = state->base.fb;
12083                 if (!fb) {
12084                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12085                                 "disabled, scaler_id = %d\n",
12086                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12087                                 plane->base.id, intel_plane->pipe,
12088                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12089                                 drm_plane_index(plane), state->scaler_id);
12090                         continue;
12091                 }
12092
12093                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12094                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12095                         plane->base.id, intel_plane->pipe,
12096                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12097                         drm_plane_index(plane));
12098                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12099                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12100                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12101                         state->scaler_id,
12102                         state->src.x1 >> 16, state->src.y1 >> 16,
12103                         drm_rect_width(&state->src) >> 16,
12104                         drm_rect_height(&state->src) >> 16,
12105                         state->dst.x1, state->dst.y1,
12106                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12107         }
12108 }
12109
12110 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12111 {
12112         struct drm_device *dev = state->dev;
12113         struct intel_encoder *encoder;
12114         struct drm_connector *connector;
12115         struct drm_connector_state *connector_state;
12116         unsigned int used_ports = 0;
12117         int i;
12118
12119         /*
12120          * Walk the connector list instead of the encoder
12121          * list to detect the problem on ddi platforms
12122          * where there's just one encoder per digital port.
12123          */
12124         for_each_connector_in_state(state, connector, connector_state, i) {
12125                 if (!connector_state->best_encoder)
12126                         continue;
12127
12128                 encoder = to_intel_encoder(connector_state->best_encoder);
12129
12130                 WARN_ON(!connector_state->crtc);
12131
12132                 switch (encoder->type) {
12133                         unsigned int port_mask;
12134                 case INTEL_OUTPUT_UNKNOWN:
12135                         if (WARN_ON(!HAS_DDI(dev)))
12136                                 break;
12137                 case INTEL_OUTPUT_DISPLAYPORT:
12138                 case INTEL_OUTPUT_HDMI:
12139                 case INTEL_OUTPUT_EDP:
12140                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12141
12142                         /* the same port mustn't appear more than once */
12143                         if (used_ports & port_mask)
12144                                 return false;
12145
12146                         used_ports |= port_mask;
12147                 default:
12148                         break;
12149                 }
12150         }
12151
12152         return true;
12153 }
12154
12155 static void
12156 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12157 {
12158         struct drm_crtc_state tmp_state;
12159         struct intel_crtc_scaler_state scaler_state;
12160         struct intel_dpll_hw_state dpll_hw_state;
12161         enum intel_dpll_id shared_dpll;
12162         uint32_t ddi_pll_sel;
12163
12164         /* FIXME: before the switch to atomic started, a new pipe_config was
12165          * kzalloc'd. Code that depends on any field being zero should be
12166          * fixed, so that the crtc_state can be safely duplicated. For now,
12167          * only fields that are know to not cause problems are preserved. */
12168
12169         tmp_state = crtc_state->base;
12170         scaler_state = crtc_state->scaler_state;
12171         shared_dpll = crtc_state->shared_dpll;
12172         dpll_hw_state = crtc_state->dpll_hw_state;
12173         ddi_pll_sel = crtc_state->ddi_pll_sel;
12174
12175         memset(crtc_state, 0, sizeof *crtc_state);
12176
12177         crtc_state->base = tmp_state;
12178         crtc_state->scaler_state = scaler_state;
12179         crtc_state->shared_dpll = shared_dpll;
12180         crtc_state->dpll_hw_state = dpll_hw_state;
12181         crtc_state->ddi_pll_sel = ddi_pll_sel;
12182 }
12183
12184 static int
12185 intel_modeset_pipe_config(struct drm_crtc *crtc,
12186                           struct intel_crtc_state *pipe_config)
12187 {
12188         struct drm_atomic_state *state = pipe_config->base.state;
12189         struct intel_encoder *encoder;
12190         struct drm_connector *connector;
12191         struct drm_connector_state *connector_state;
12192         int base_bpp, ret = -EINVAL;
12193         int i;
12194         bool retry = true;
12195
12196         clear_intel_crtc_state(pipe_config);
12197
12198         pipe_config->cpu_transcoder =
12199                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12200
12201         /*
12202          * Sanitize sync polarity flags based on requested ones. If neither
12203          * positive or negative polarity is requested, treat this as meaning
12204          * negative polarity.
12205          */
12206         if (!(pipe_config->base.adjusted_mode.flags &
12207               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12208                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12209
12210         if (!(pipe_config->base.adjusted_mode.flags &
12211               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12212                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12213
12214         /* Compute a starting value for pipe_config->pipe_bpp taking the source
12215          * plane pixel format and any sink constraints into account. Returns the
12216          * source plane bpp so that dithering can be selected on mismatches
12217          * after encoders and crtc also have had their say. */
12218         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12219                                              pipe_config);
12220         if (base_bpp < 0)
12221                 goto fail;
12222
12223         /*
12224          * Determine the real pipe dimensions. Note that stereo modes can
12225          * increase the actual pipe size due to the frame doubling and
12226          * insertion of additional space for blanks between the frame. This
12227          * is stored in the crtc timings. We use the requested mode to do this
12228          * computation to clearly distinguish it from the adjusted mode, which
12229          * can be changed by the connectors in the below retry loop.
12230          */
12231         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12232                                &pipe_config->pipe_src_w,
12233                                &pipe_config->pipe_src_h);
12234
12235 encoder_retry:
12236         /* Ensure the port clock defaults are reset when retrying. */
12237         pipe_config->port_clock = 0;
12238         pipe_config->pixel_multiplier = 1;
12239
12240         /* Fill in default crtc timings, allow encoders to overwrite them. */
12241         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12242                               CRTC_STEREO_DOUBLE);
12243
12244         /* Pass our mode to the connectors and the CRTC to give them a chance to
12245          * adjust it according to limitations or connector properties, and also
12246          * a chance to reject the mode entirely.
12247          */
12248         for_each_connector_in_state(state, connector, connector_state, i) {
12249                 if (connector_state->crtc != crtc)
12250                         continue;
12251
12252                 encoder = to_intel_encoder(connector_state->best_encoder);
12253
12254                 if (!(encoder->compute_config(encoder, pipe_config))) {
12255                         DRM_DEBUG_KMS("Encoder config failure\n");
12256                         goto fail;
12257                 }
12258         }
12259
12260         /* Set default port clock if not overwritten by the encoder. Needs to be
12261          * done afterwards in case the encoder adjusts the mode. */
12262         if (!pipe_config->port_clock)
12263                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12264                         * pipe_config->pixel_multiplier;
12265
12266         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12267         if (ret < 0) {
12268                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12269                 goto fail;
12270         }
12271
12272         if (ret == RETRY) {
12273                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12274                         ret = -EINVAL;
12275                         goto fail;
12276                 }
12277
12278                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12279                 retry = false;
12280                 goto encoder_retry;
12281         }
12282
12283         pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12284         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12285                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12286
12287 fail:
12288         return ret;
12289 }
12290
12291 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12292 {
12293         struct drm_encoder *encoder;
12294         struct drm_device *dev = crtc->dev;
12295
12296         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12297                 if (encoder->crtc == crtc)
12298                         return true;
12299
12300         return false;
12301 }
12302
12303 static void
12304 intel_modeset_update_state(struct drm_atomic_state *state)
12305 {
12306         struct drm_device *dev = state->dev;
12307         struct intel_encoder *intel_encoder;
12308         struct drm_crtc *crtc;
12309         struct drm_crtc_state *crtc_state;
12310         struct drm_connector *connector;
12311         int i;
12312
12313         intel_shared_dpll_commit(state);
12314
12315         for_each_intel_encoder(dev, intel_encoder) {
12316                 if (!intel_encoder->base.crtc)
12317                         continue;
12318
12319                 crtc = intel_encoder->base.crtc;
12320                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12321                 if (!crtc_state || !needs_modeset(crtc->state))
12322                         continue;
12323
12324                 intel_encoder->connectors_active = false;
12325         }
12326
12327         drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12328
12329         /* Double check state. */
12330         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12331                 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12332
12333                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12334
12335                 /* Update hwmode for vblank functions */
12336                 if (crtc->state->active)
12337                         crtc->hwmode = crtc->state->adjusted_mode;
12338                 else
12339                         crtc->hwmode.crtc_clock = 0;
12340         }
12341
12342         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12343                 if (!connector->encoder || !connector->encoder->crtc)
12344                         continue;
12345
12346                 crtc = connector->encoder->crtc;
12347                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12348                 if (!crtc_state || !needs_modeset(crtc->state))
12349                         continue;
12350
12351                 if (crtc->state->active) {
12352                         struct drm_property *dpms_property =
12353                                 dev->mode_config.dpms_property;
12354
12355                         connector->dpms = DRM_MODE_DPMS_ON;
12356                         drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12357
12358                         intel_encoder = to_intel_encoder(connector->encoder);
12359                         intel_encoder->connectors_active = true;
12360                 } else
12361                         connector->dpms = DRM_MODE_DPMS_OFF;
12362         }
12363 }
12364
12365 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12366 {
12367         int diff;
12368
12369         if (clock1 == clock2)
12370                 return true;
12371
12372         if (!clock1 || !clock2)
12373                 return false;
12374
12375         diff = abs(clock1 - clock2);
12376
12377         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12378                 return true;
12379
12380         return false;
12381 }
12382
12383 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12384         list_for_each_entry((intel_crtc), \
12385                             &(dev)->mode_config.crtc_list, \
12386                             base.head) \
12387                 if (mask & (1 <<(intel_crtc)->pipe))
12388
12389
12390 static bool
12391 intel_compare_m_n(unsigned int m, unsigned int n,
12392                   unsigned int m2, unsigned int n2,
12393                   bool exact)
12394 {
12395         if (m == m2 && n == n2)
12396                 return true;
12397
12398         if (exact || !m || !n || !m2 || !n2)
12399                 return false;
12400
12401         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12402
12403         if (m > m2) {
12404                 while (m > m2) {
12405                         m2 <<= 1;
12406                         n2 <<= 1;
12407                 }
12408         } else if (m < m2) {
12409                 while (m < m2) {
12410                         m <<= 1;
12411                         n <<= 1;
12412                 }
12413         }
12414
12415         return m == m2 && n == n2;
12416 }
12417
12418 static bool
12419 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12420                        struct intel_link_m_n *m2_n2,
12421                        bool adjust)
12422 {
12423         if (m_n->tu == m2_n2->tu &&
12424             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12425                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12426             intel_compare_m_n(m_n->link_m, m_n->link_n,
12427                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12428                 if (adjust)
12429                         *m2_n2 = *m_n;
12430
12431                 return true;
12432         }
12433
12434         return false;
12435 }
12436
12437 static bool
12438 intel_pipe_config_compare(struct drm_device *dev,
12439                           struct intel_crtc_state *current_config,
12440                           struct intel_crtc_state *pipe_config,
12441                           bool adjust)
12442 {
12443         bool ret = true;
12444
12445 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12446         do { \
12447                 if (!adjust) \
12448                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12449                 else \
12450                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12451         } while (0)
12452
12453 #define PIPE_CONF_CHECK_X(name) \
12454         if (current_config->name != pipe_config->name) { \
12455                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12456                           "(expected 0x%08x, found 0x%08x)\n", \
12457                           current_config->name, \
12458                           pipe_config->name); \
12459                 ret = false; \
12460         }
12461
12462 #define PIPE_CONF_CHECK_I(name) \
12463         if (current_config->name != pipe_config->name) { \
12464                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12465                           "(expected %i, found %i)\n", \
12466                           current_config->name, \
12467                           pipe_config->name); \
12468                 ret = false; \
12469         }
12470
12471 #define PIPE_CONF_CHECK_M_N(name) \
12472         if (!intel_compare_link_m_n(&current_config->name, \
12473                                     &pipe_config->name,\
12474                                     adjust)) { \
12475                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12476                           "(expected tu %i gmch %i/%i link %i/%i, " \
12477                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12478                           current_config->name.tu, \
12479                           current_config->name.gmch_m, \
12480                           current_config->name.gmch_n, \
12481                           current_config->name.link_m, \
12482                           current_config->name.link_n, \
12483                           pipe_config->name.tu, \
12484                           pipe_config->name.gmch_m, \
12485                           pipe_config->name.gmch_n, \
12486                           pipe_config->name.link_m, \
12487                           pipe_config->name.link_n); \
12488                 ret = false; \
12489         }
12490
12491 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12492         if (!intel_compare_link_m_n(&current_config->name, \
12493                                     &pipe_config->name, adjust) && \
12494             !intel_compare_link_m_n(&current_config->alt_name, \
12495                                     &pipe_config->name, adjust)) { \
12496                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12497                           "(expected tu %i gmch %i/%i link %i/%i, " \
12498                           "or tu %i gmch %i/%i link %i/%i, " \
12499                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12500                           current_config->name.tu, \
12501                           current_config->name.gmch_m, \
12502                           current_config->name.gmch_n, \
12503                           current_config->name.link_m, \
12504                           current_config->name.link_n, \
12505                           current_config->alt_name.tu, \
12506                           current_config->alt_name.gmch_m, \
12507                           current_config->alt_name.gmch_n, \
12508                           current_config->alt_name.link_m, \
12509                           current_config->alt_name.link_n, \
12510                           pipe_config->name.tu, \
12511                           pipe_config->name.gmch_m, \
12512                           pipe_config->name.gmch_n, \
12513                           pipe_config->name.link_m, \
12514                           pipe_config->name.link_n); \
12515                 ret = false; \
12516         }
12517
12518 /* This is required for BDW+ where there is only one set of registers for
12519  * switching between high and low RR.
12520  * This macro can be used whenever a comparison has to be made between one
12521  * hw state and multiple sw state variables.
12522  */
12523 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12524         if ((current_config->name != pipe_config->name) && \
12525                 (current_config->alt_name != pipe_config->name)) { \
12526                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12527                                   "(expected %i or %i, found %i)\n", \
12528                                   current_config->name, \
12529                                   current_config->alt_name, \
12530                                   pipe_config->name); \
12531                         ret = false; \
12532         }
12533
12534 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12535         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12536                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12537                           "(expected %i, found %i)\n", \
12538                           current_config->name & (mask), \
12539                           pipe_config->name & (mask)); \
12540                 ret = false; \
12541         }
12542
12543 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12544         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12545                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12546                           "(expected %i, found %i)\n", \
12547                           current_config->name, \
12548                           pipe_config->name); \
12549                 ret = false; \
12550         }
12551
12552 #define PIPE_CONF_QUIRK(quirk)  \
12553         ((current_config->quirks | pipe_config->quirks) & (quirk))
12554
12555         PIPE_CONF_CHECK_I(cpu_transcoder);
12556
12557         PIPE_CONF_CHECK_I(has_pch_encoder);
12558         PIPE_CONF_CHECK_I(fdi_lanes);
12559         PIPE_CONF_CHECK_M_N(fdi_m_n);
12560
12561         PIPE_CONF_CHECK_I(has_dp_encoder);
12562
12563         if (INTEL_INFO(dev)->gen < 8) {
12564                 PIPE_CONF_CHECK_M_N(dp_m_n);
12565
12566                 PIPE_CONF_CHECK_I(has_drrs);
12567                 if (current_config->has_drrs)
12568                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12569         } else
12570                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12571
12572         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12573         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12574         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12575         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12576         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12577         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12578
12579         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12580         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12581         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12582         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12583         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12584         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12585
12586         PIPE_CONF_CHECK_I(pixel_multiplier);
12587         PIPE_CONF_CHECK_I(has_hdmi_sink);
12588         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12589             IS_VALLEYVIEW(dev))
12590                 PIPE_CONF_CHECK_I(limited_color_range);
12591         PIPE_CONF_CHECK_I(has_infoframe);
12592
12593         PIPE_CONF_CHECK_I(has_audio);
12594
12595         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12596                               DRM_MODE_FLAG_INTERLACE);
12597
12598         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12599                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12600                                       DRM_MODE_FLAG_PHSYNC);
12601                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12602                                       DRM_MODE_FLAG_NHSYNC);
12603                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12604                                       DRM_MODE_FLAG_PVSYNC);
12605                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12606                                       DRM_MODE_FLAG_NVSYNC);
12607         }
12608
12609         PIPE_CONF_CHECK_I(pipe_src_w);
12610         PIPE_CONF_CHECK_I(pipe_src_h);
12611
12612         /*
12613          * FIXME: BIOS likes to set up a cloned config with lvds+external
12614          * screen. Since we don't yet re-compute the pipe config when moving
12615          * just the lvds port away to another pipe the sw tracking won't match.
12616          *
12617          * Proper atomic modesets with recomputed global state will fix this.
12618          * Until then just don't check gmch state for inherited modes.
12619          */
12620         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12621                 PIPE_CONF_CHECK_I(gmch_pfit.control);
12622                 /* pfit ratios are autocomputed by the hw on gen4+ */
12623                 if (INTEL_INFO(dev)->gen < 4)
12624                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12625                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12626         }
12627
12628         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12629         if (current_config->pch_pfit.enabled) {
12630                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12631                 PIPE_CONF_CHECK_I(pch_pfit.size);
12632         }
12633
12634         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12635
12636         /* BDW+ don't expose a synchronous way to read the state */
12637         if (IS_HASWELL(dev))
12638                 PIPE_CONF_CHECK_I(ips_enabled);
12639
12640         PIPE_CONF_CHECK_I(double_wide);
12641
12642         PIPE_CONF_CHECK_X(ddi_pll_sel);
12643
12644         PIPE_CONF_CHECK_I(shared_dpll);
12645         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12646         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12647         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12648         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12649         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12650         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12651         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12652         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12653
12654         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12655                 PIPE_CONF_CHECK_I(pipe_bpp);
12656
12657         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12658         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12659
12660 #undef PIPE_CONF_CHECK_X
12661 #undef PIPE_CONF_CHECK_I
12662 #undef PIPE_CONF_CHECK_I_ALT
12663 #undef PIPE_CONF_CHECK_FLAGS
12664 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12665 #undef PIPE_CONF_QUIRK
12666 #undef INTEL_ERR_OR_DBG_KMS
12667
12668         return ret;
12669 }
12670
12671 static void check_wm_state(struct drm_device *dev)
12672 {
12673         struct drm_i915_private *dev_priv = dev->dev_private;
12674         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12675         struct intel_crtc *intel_crtc;
12676         int plane;
12677
12678         if (INTEL_INFO(dev)->gen < 9)
12679                 return;
12680
12681         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12682         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12683
12684         for_each_intel_crtc(dev, intel_crtc) {
12685                 struct skl_ddb_entry *hw_entry, *sw_entry;
12686                 const enum pipe pipe = intel_crtc->pipe;
12687
12688                 if (!intel_crtc->active)
12689                         continue;
12690
12691                 /* planes */
12692                 for_each_plane(dev_priv, pipe, plane) {
12693                         hw_entry = &hw_ddb.plane[pipe][plane];
12694                         sw_entry = &sw_ddb->plane[pipe][plane];
12695
12696                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12697                                 continue;
12698
12699                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12700                                   "(expected (%u,%u), found (%u,%u))\n",
12701                                   pipe_name(pipe), plane + 1,
12702                                   sw_entry->start, sw_entry->end,
12703                                   hw_entry->start, hw_entry->end);
12704                 }
12705
12706                 /* cursor */
12707                 hw_entry = &hw_ddb.cursor[pipe];
12708                 sw_entry = &sw_ddb->cursor[pipe];
12709
12710                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12711                         continue;
12712
12713                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12714                           "(expected (%u,%u), found (%u,%u))\n",
12715                           pipe_name(pipe),
12716                           sw_entry->start, sw_entry->end,
12717                           hw_entry->start, hw_entry->end);
12718         }
12719 }
12720
12721 static void
12722 check_connector_state(struct drm_device *dev)
12723 {
12724         struct intel_connector *connector;
12725
12726         for_each_intel_connector(dev, connector) {
12727                 struct drm_encoder *encoder = connector->base.encoder;
12728                 struct drm_connector_state *state = connector->base.state;
12729
12730                 /* This also checks the encoder/connector hw state with the
12731                  * ->get_hw_state callbacks. */
12732                 intel_connector_check_state(connector);
12733
12734                 I915_STATE_WARN(state->best_encoder != encoder,
12735                      "connector's staged encoder doesn't match current encoder\n");
12736         }
12737 }
12738
12739 static void
12740 check_encoder_state(struct drm_device *dev)
12741 {
12742         struct intel_encoder *encoder;
12743         struct intel_connector *connector;
12744
12745         for_each_intel_encoder(dev, encoder) {
12746                 bool enabled = false;
12747                 bool active = false;
12748                 enum pipe pipe, tracked_pipe;
12749
12750                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12751                               encoder->base.base.id,
12752                               encoder->base.name);
12753
12754                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12755                      "encoder's active_connectors set, but no crtc\n");
12756
12757                 for_each_intel_connector(dev, connector) {
12758                         if (connector->base.encoder != &encoder->base)
12759                                 continue;
12760                         enabled = true;
12761                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12762                                 active = true;
12763
12764                         I915_STATE_WARN(connector->base.state->crtc !=
12765                                         encoder->base.crtc,
12766                              "connector's crtc doesn't match encoder crtc\n");
12767                 }
12768                 /*
12769                  * for MST connectors if we unplug the connector is gone
12770                  * away but the encoder is still connected to a crtc
12771                  * until a modeset happens in response to the hotplug.
12772                  */
12773                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12774                         continue;
12775
12776                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12777                      "encoder's enabled state mismatch "
12778                      "(expected %i, found %i)\n",
12779                      !!encoder->base.crtc, enabled);
12780                 I915_STATE_WARN(active && !encoder->base.crtc,
12781                      "active encoder with no crtc\n");
12782
12783                 I915_STATE_WARN(encoder->connectors_active != active,
12784                      "encoder's computed active state doesn't match tracked active state "
12785                      "(expected %i, found %i)\n", active, encoder->connectors_active);
12786
12787                 active = encoder->get_hw_state(encoder, &pipe);
12788                 I915_STATE_WARN(active != encoder->connectors_active,
12789                      "encoder's hw state doesn't match sw tracking "
12790                      "(expected %i, found %i)\n",
12791                      encoder->connectors_active, active);
12792
12793                 if (!encoder->base.crtc)
12794                         continue;
12795
12796                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12797                 I915_STATE_WARN(active && pipe != tracked_pipe,
12798                      "active encoder's pipe doesn't match"
12799                      "(expected %i, found %i)\n",
12800                      tracked_pipe, pipe);
12801
12802         }
12803 }
12804
12805 static void
12806 check_crtc_state(struct drm_device *dev)
12807 {
12808         struct drm_i915_private *dev_priv = dev->dev_private;
12809         struct intel_crtc *crtc;
12810         struct intel_encoder *encoder;
12811         struct intel_crtc_state pipe_config;
12812
12813         for_each_intel_crtc(dev, crtc) {
12814                 bool enabled = false;
12815                 bool active = false;
12816
12817                 memset(&pipe_config, 0, sizeof(pipe_config));
12818
12819                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12820                               crtc->base.base.id);
12821
12822                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12823                      "active crtc, but not enabled in sw tracking\n");
12824
12825                 for_each_intel_encoder(dev, encoder) {
12826                         if (encoder->base.crtc != &crtc->base)
12827                                 continue;
12828                         enabled = true;
12829                         if (encoder->connectors_active)
12830                                 active = true;
12831                 }
12832
12833                 I915_STATE_WARN(active != crtc->active,
12834                      "crtc's computed active state doesn't match tracked active state "
12835                      "(expected %i, found %i)\n", active, crtc->active);
12836                 I915_STATE_WARN(enabled != crtc->base.state->enable,
12837                      "crtc's computed enabled state doesn't match tracked enabled state "
12838                      "(expected %i, found %i)\n", enabled,
12839                                 crtc->base.state->enable);
12840
12841                 active = dev_priv->display.get_pipe_config(crtc,
12842                                                            &pipe_config);
12843
12844                 /* hw state is inconsistent with the pipe quirk */
12845                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12846                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12847                         active = crtc->active;
12848
12849                 for_each_intel_encoder(dev, encoder) {
12850                         enum pipe pipe;
12851                         if (encoder->base.crtc != &crtc->base)
12852                                 continue;
12853                         if (encoder->get_hw_state(encoder, &pipe))
12854                                 encoder->get_config(encoder, &pipe_config);
12855                 }
12856
12857                 I915_STATE_WARN(crtc->active != active,
12858                      "crtc active state doesn't match with hw state "
12859                      "(expected %i, found %i)\n", crtc->active, active);
12860
12861                 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12862                      "transitional active state does not match atomic hw state "
12863                      "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12864
12865                 if (!active)
12866                         continue;
12867
12868                 if (!intel_pipe_config_compare(dev, crtc->config,
12869                                                &pipe_config, false)) {
12870                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12871                         intel_dump_pipe_config(crtc, &pipe_config,
12872                                                "[hw state]");
12873                         intel_dump_pipe_config(crtc, crtc->config,
12874                                                "[sw state]");
12875                 }
12876         }
12877 }
12878
12879 static void
12880 check_shared_dpll_state(struct drm_device *dev)
12881 {
12882         struct drm_i915_private *dev_priv = dev->dev_private;
12883         struct intel_crtc *crtc;
12884         struct intel_dpll_hw_state dpll_hw_state;
12885         int i;
12886
12887         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12888                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12889                 int enabled_crtcs = 0, active_crtcs = 0;
12890                 bool active;
12891
12892                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12893
12894                 DRM_DEBUG_KMS("%s\n", pll->name);
12895
12896                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12897
12898                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12899                      "more active pll users than references: %i vs %i\n",
12900                      pll->active, hweight32(pll->config.crtc_mask));
12901                 I915_STATE_WARN(pll->active && !pll->on,
12902                      "pll in active use but not on in sw tracking\n");
12903                 I915_STATE_WARN(pll->on && !pll->active,
12904                      "pll in on but not on in use in sw tracking\n");
12905                 I915_STATE_WARN(pll->on != active,
12906                      "pll on state mismatch (expected %i, found %i)\n",
12907                      pll->on, active);
12908
12909                 for_each_intel_crtc(dev, crtc) {
12910                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12911                                 enabled_crtcs++;
12912                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12913                                 active_crtcs++;
12914                 }
12915                 I915_STATE_WARN(pll->active != active_crtcs,
12916                      "pll active crtcs mismatch (expected %i, found %i)\n",
12917                      pll->active, active_crtcs);
12918                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12919                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12920                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12921
12922                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12923                                        sizeof(dpll_hw_state)),
12924                      "pll hw state mismatch\n");
12925         }
12926 }
12927
12928 void
12929 intel_modeset_check_state(struct drm_device *dev)
12930 {
12931         check_wm_state(dev);
12932         check_connector_state(dev);
12933         check_encoder_state(dev);
12934         check_crtc_state(dev);
12935         check_shared_dpll_state(dev);
12936 }
12937
12938 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12939                                      int dotclock)
12940 {
12941         /*
12942          * FDI already provided one idea for the dotclock.
12943          * Yell if the encoder disagrees.
12944          */
12945         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12946              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12947              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12948 }
12949
12950 static void update_scanline_offset(struct intel_crtc *crtc)
12951 {
12952         struct drm_device *dev = crtc->base.dev;
12953
12954         /*
12955          * The scanline counter increments at the leading edge of hsync.
12956          *
12957          * On most platforms it starts counting from vtotal-1 on the
12958          * first active line. That means the scanline counter value is
12959          * always one less than what we would expect. Ie. just after
12960          * start of vblank, which also occurs at start of hsync (on the
12961          * last active line), the scanline counter will read vblank_start-1.
12962          *
12963          * On gen2 the scanline counter starts counting from 1 instead
12964          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12965          * to keep the value positive), instead of adding one.
12966          *
12967          * On HSW+ the behaviour of the scanline counter depends on the output
12968          * type. For DP ports it behaves like most other platforms, but on HDMI
12969          * there's an extra 1 line difference. So we need to add two instead of
12970          * one to the value.
12971          */
12972         if (IS_GEN2(dev)) {
12973                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12974                 int vtotal;
12975
12976                 vtotal = mode->crtc_vtotal;
12977                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12978                         vtotal /= 2;
12979
12980                 crtc->scanline_offset = vtotal - 1;
12981         } else if (HAS_DDI(dev) &&
12982                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12983                 crtc->scanline_offset = 2;
12984         } else
12985                 crtc->scanline_offset = 1;
12986 }
12987
12988 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12989 {
12990         struct drm_device *dev = state->dev;
12991         struct drm_i915_private *dev_priv = to_i915(dev);
12992         struct intel_shared_dpll_config *shared_dpll = NULL;
12993         struct intel_crtc *intel_crtc;
12994         struct intel_crtc_state *intel_crtc_state;
12995         struct drm_crtc *crtc;
12996         struct drm_crtc_state *crtc_state;
12997         int i;
12998
12999         if (!dev_priv->display.crtc_compute_clock)
13000                 return;
13001
13002         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13003                 int dpll;
13004
13005                 intel_crtc = to_intel_crtc(crtc);
13006                 intel_crtc_state = to_intel_crtc_state(crtc_state);
13007                 dpll = intel_crtc_state->shared_dpll;
13008
13009                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13010                         continue;
13011
13012                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13013
13014                 if (!shared_dpll)
13015                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13016
13017                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13018         }
13019 }
13020
13021 /*
13022  * This implements the workaround described in the "notes" section of the mode
13023  * set sequence documentation. When going from no pipes or single pipe to
13024  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13025  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13026  */
13027 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13028 {
13029         struct drm_crtc_state *crtc_state;
13030         struct intel_crtc *intel_crtc;
13031         struct drm_crtc *crtc;
13032         struct intel_crtc_state *first_crtc_state = NULL;
13033         struct intel_crtc_state *other_crtc_state = NULL;
13034         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13035         int i;
13036
13037         /* look at all crtc's that are going to be enabled in during modeset */
13038         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13039                 intel_crtc = to_intel_crtc(crtc);
13040
13041                 if (!crtc_state->active || !needs_modeset(crtc_state))
13042                         continue;
13043
13044                 if (first_crtc_state) {
13045                         other_crtc_state = to_intel_crtc_state(crtc_state);
13046                         break;
13047                 } else {
13048                         first_crtc_state = to_intel_crtc_state(crtc_state);
13049                         first_pipe = intel_crtc->pipe;
13050                 }
13051         }
13052
13053         /* No workaround needed? */
13054         if (!first_crtc_state)
13055                 return 0;
13056
13057         /* w/a possibly needed, check how many crtc's are already enabled. */
13058         for_each_intel_crtc(state->dev, intel_crtc) {
13059                 struct intel_crtc_state *pipe_config;
13060
13061                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13062                 if (IS_ERR(pipe_config))
13063                         return PTR_ERR(pipe_config);
13064
13065                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13066
13067                 if (!pipe_config->base.active ||
13068                     needs_modeset(&pipe_config->base))
13069                         continue;
13070
13071                 /* 2 or more enabled crtcs means no need for w/a */
13072                 if (enabled_pipe != INVALID_PIPE)
13073                         return 0;
13074
13075                 enabled_pipe = intel_crtc->pipe;
13076         }
13077
13078         if (enabled_pipe != INVALID_PIPE)
13079                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13080         else if (other_crtc_state)
13081                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13082
13083         return 0;
13084 }
13085
13086 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13087 {
13088         struct drm_crtc *crtc;
13089         struct drm_crtc_state *crtc_state;
13090         int ret = 0;
13091
13092         /* add all active pipes to the state */
13093         for_each_crtc(state->dev, crtc) {
13094                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13095                 if (IS_ERR(crtc_state))
13096                         return PTR_ERR(crtc_state);
13097
13098                 if (!crtc_state->active || needs_modeset(crtc_state))
13099                         continue;
13100
13101                 crtc_state->mode_changed = true;
13102
13103                 ret = drm_atomic_add_affected_connectors(state, crtc);
13104                 if (ret)
13105                         break;
13106
13107                 ret = drm_atomic_add_affected_planes(state, crtc);
13108                 if (ret)
13109                         break;
13110         }
13111
13112         return ret;
13113 }
13114
13115
13116 /* Code that should eventually be part of atomic_check() */
13117 static int intel_modeset_checks(struct drm_atomic_state *state)
13118 {
13119         struct drm_device *dev = state->dev;
13120         struct drm_i915_private *dev_priv = dev->dev_private;
13121         int ret;
13122
13123         if (!check_digital_port_conflicts(state)) {
13124                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13125                 return -EINVAL;
13126         }
13127
13128         /*
13129          * See if the config requires any additional preparation, e.g.
13130          * to adjust global state with pipes off.  We need to do this
13131          * here so we can get the modeset_pipe updated config for the new
13132          * mode set on this crtc.  For other crtcs we need to use the
13133          * adjusted_mode bits in the crtc directly.
13134          */
13135         if (dev_priv->display.modeset_calc_cdclk) {
13136                 unsigned int cdclk;
13137
13138                 ret = dev_priv->display.modeset_calc_cdclk(state);
13139
13140                 cdclk = to_intel_atomic_state(state)->cdclk;
13141                 if (!ret && cdclk != dev_priv->cdclk_freq)
13142                         ret = intel_modeset_all_pipes(state);
13143
13144                 if (ret < 0)
13145                         return ret;
13146         } else
13147                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13148
13149         intel_modeset_clear_plls(state);
13150
13151         if (IS_HASWELL(dev))
13152                 return haswell_mode_set_planes_workaround(state);
13153
13154         return 0;
13155 }
13156
13157 static int
13158 intel_modeset_compute_config(struct drm_atomic_state *state)
13159 {
13160         struct drm_crtc *crtc;
13161         struct drm_crtc_state *crtc_state;
13162         int ret, i;
13163         bool any_ms = false;
13164
13165         ret = drm_atomic_helper_check_modeset(state->dev, state);
13166         if (ret)
13167                 return ret;
13168
13169         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13170                 struct intel_crtc_state *pipe_config =
13171                         to_intel_crtc_state(crtc_state);
13172                 bool modeset, recalc = false;
13173
13174                 if (!crtc_state->enable) {
13175                         if (needs_modeset(crtc_state))
13176                                 any_ms = true;
13177                         continue;
13178                 }
13179
13180                 modeset = needs_modeset(crtc_state);
13181                 /* see comment in intel_modeset_readout_hw_state */
13182                 if (!modeset && crtc_state->mode_blob != crtc->state->mode_blob &&
13183                     pipe_config->quirks & PIPE_CONFIG_QUIRK_INHERITED_MODE)
13184                         recalc = true;
13185
13186                 if (!modeset && !recalc)
13187                         continue;
13188
13189                 if (recalc) {
13190                         ret = drm_atomic_add_affected_connectors(state, crtc);
13191                         if (ret)
13192                                 return ret;
13193                 }
13194
13195                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13196                 if (ret)
13197                         return ret;
13198
13199                 if (recalc && (!i915.fastboot ||
13200                     !intel_pipe_config_compare(state->dev,
13201                                         to_intel_crtc_state(crtc->state),
13202                                         pipe_config, true))) {
13203                         modeset = crtc_state->mode_changed = true;
13204
13205                         ret = drm_atomic_add_affected_planes(state, crtc);
13206                         if (ret)
13207                                 return ret;
13208                 }
13209
13210                 any_ms = modeset;
13211                 intel_dump_pipe_config(to_intel_crtc(crtc),
13212                                        pipe_config,
13213                                        modeset ? "[modeset]" : "[fastboot]");
13214         }
13215
13216         if (any_ms) {
13217                 ret = intel_modeset_checks(state);
13218
13219                 if (ret)
13220                         return ret;
13221         } else
13222                 to_intel_atomic_state(state)->cdclk =
13223                         to_i915(state->dev)->cdclk_freq;
13224
13225         return drm_atomic_helper_check_planes(state->dev, state);
13226 }
13227
13228 static int __intel_set_mode(struct drm_atomic_state *state)
13229 {
13230         struct drm_device *dev = state->dev;
13231         struct drm_i915_private *dev_priv = dev->dev_private;
13232         struct drm_crtc *crtc;
13233         struct drm_crtc_state *crtc_state;
13234         int ret = 0;
13235         int i;
13236         bool any_ms = false;
13237
13238         ret = drm_atomic_helper_prepare_planes(dev, state);
13239         if (ret)
13240                 return ret;
13241
13242         drm_atomic_helper_swap_state(dev, state);
13243
13244         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13245                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13246
13247                 if (!needs_modeset(crtc->state))
13248                         continue;
13249
13250                 any_ms = true;
13251                 intel_pre_plane_update(intel_crtc);
13252
13253                 if (crtc_state->active) {
13254                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13255                         dev_priv->display.crtc_disable(crtc);
13256                         intel_crtc->active = false;
13257                         intel_disable_shared_dpll(intel_crtc);
13258                 }
13259         }
13260
13261         /* Only after disabling all output pipelines that will be changed can we
13262          * update the the output configuration. */
13263         intel_modeset_update_state(state);
13264
13265         /* The state has been swaped above, so state actually contains the
13266          * old state now. */
13267         if (any_ms)
13268                 modeset_update_crtc_power_domains(state);
13269
13270         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13271         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13272                 if (needs_modeset(crtc->state) && crtc->state->active) {
13273                         update_scanline_offset(to_intel_crtc(crtc));
13274                         dev_priv->display.crtc_enable(crtc);
13275                 }
13276
13277                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13278         }
13279
13280         /* FIXME: add subpixel order */
13281
13282         drm_atomic_helper_cleanup_planes(dev, state);
13283
13284         drm_atomic_state_free(state);
13285
13286         return 0;
13287 }
13288
13289 static int intel_set_mode_checked(struct drm_atomic_state *state)
13290 {
13291         struct drm_device *dev = state->dev;
13292         int ret;
13293
13294         ret = __intel_set_mode(state);
13295         if (ret == 0)
13296                 intel_modeset_check_state(dev);
13297
13298         return ret;
13299 }
13300
13301 static int intel_set_mode(struct drm_atomic_state *state)
13302 {
13303         int ret;
13304
13305         ret = intel_modeset_compute_config(state);
13306         if (ret)
13307                 return ret;
13308
13309         return intel_set_mode_checked(state);
13310 }
13311
13312 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13313 {
13314         struct drm_device *dev = crtc->dev;
13315         struct drm_atomic_state *state;
13316         struct drm_crtc_state *crtc_state;
13317         int ret;
13318
13319         state = drm_atomic_state_alloc(dev);
13320         if (!state) {
13321                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13322                               crtc->base.id);
13323                 return;
13324         }
13325
13326         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13327
13328 retry:
13329         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13330         ret = PTR_ERR_OR_ZERO(crtc_state);
13331         if (!ret) {
13332                 if (!crtc_state->active)
13333                         goto out;
13334
13335                 crtc_state->mode_changed = true;
13336                 ret = intel_set_mode(state);
13337         }
13338
13339         if (ret == -EDEADLK) {
13340                 drm_atomic_state_clear(state);
13341                 drm_modeset_backoff(state->acquire_ctx);
13342                 goto retry;
13343         }
13344
13345         if (ret)
13346 out:
13347                 drm_atomic_state_free(state);
13348 }
13349
13350 #undef for_each_intel_crtc_masked
13351
13352 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13353                                         struct drm_mode_set *set)
13354 {
13355         int ro;
13356
13357         for (ro = 0; ro < set->num_connectors; ro++)
13358                 if (set->connectors[ro] == &connector->base)
13359                         return true;
13360
13361         return false;
13362 }
13363
13364 static int
13365 intel_modeset_stage_output_state(struct drm_device *dev,
13366                                  struct drm_mode_set *set,
13367                                  struct drm_atomic_state *state)
13368 {
13369         struct intel_connector *connector;
13370         struct drm_connector *drm_connector;
13371         struct drm_connector_state *connector_state;
13372         struct drm_crtc *crtc;
13373         struct drm_crtc_state *crtc_state;
13374         int i, ret;
13375
13376         /* The upper layers ensure that we either disable a crtc or have a list
13377          * of connectors. For paranoia, double-check this. */
13378         WARN_ON(!set->fb && (set->num_connectors != 0));
13379         WARN_ON(set->fb && (set->num_connectors == 0));
13380
13381         for_each_intel_connector(dev, connector) {
13382                 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13383
13384                 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13385                         continue;
13386
13387                 connector_state =
13388                         drm_atomic_get_connector_state(state, &connector->base);
13389                 if (IS_ERR(connector_state))
13390                         return PTR_ERR(connector_state);
13391
13392                 if (in_mode_set) {
13393                         int pipe = to_intel_crtc(set->crtc)->pipe;
13394                         connector_state->best_encoder =
13395                                 &intel_find_encoder(connector, pipe)->base;
13396                 }
13397
13398                 if (connector->base.state->crtc != set->crtc)
13399                         continue;
13400
13401                 /* If we disable the crtc, disable all its connectors. Also, if
13402                  * the connector is on the changing crtc but not on the new
13403                  * connector list, disable it. */
13404                 if (!set->fb || !in_mode_set) {
13405                         connector_state->best_encoder = NULL;
13406
13407                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13408                                 connector->base.base.id,
13409                                 connector->base.name);
13410                 }
13411         }
13412         /* connector->new_encoder is now updated for all connectors. */
13413
13414         for_each_connector_in_state(state, drm_connector, connector_state, i) {
13415                 connector = to_intel_connector(drm_connector);
13416
13417                 if (!connector_state->best_encoder) {
13418                         ret = drm_atomic_set_crtc_for_connector(connector_state,
13419                                                                 NULL);
13420                         if (ret)
13421                                 return ret;
13422
13423                         continue;
13424                 }
13425
13426                 if (intel_connector_in_mode_set(connector, set)) {
13427                         struct drm_crtc *crtc = connector->base.state->crtc;
13428
13429                         /* If this connector was in a previous crtc, add it
13430                          * to the state. We might need to disable it. */
13431                         if (crtc) {
13432                                 crtc_state =
13433                                         drm_atomic_get_crtc_state(state, crtc);
13434                                 if (IS_ERR(crtc_state))
13435                                         return PTR_ERR(crtc_state);
13436                         }
13437
13438                         ret = drm_atomic_set_crtc_for_connector(connector_state,
13439                                                                 set->crtc);
13440                         if (ret)
13441                                 return ret;
13442                 }
13443
13444                 /* Make sure the new CRTC will work with the encoder */
13445                 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13446                                          connector_state->crtc)) {
13447                         return -EINVAL;
13448                 }
13449
13450                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13451                         connector->base.base.id,
13452                         connector->base.name,
13453                         connector_state->crtc->base.id);
13454
13455                 if (connector_state->best_encoder != &connector->encoder->base)
13456                         connector->encoder =
13457                                 to_intel_encoder(connector_state->best_encoder);
13458         }
13459
13460         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13461                 bool has_connectors;
13462
13463                 ret = drm_atomic_add_affected_connectors(state, crtc);
13464                 if (ret)
13465                         return ret;
13466
13467                 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13468                 if (has_connectors != crtc_state->enable)
13469                         crtc_state->enable =
13470                         crtc_state->active = has_connectors;
13471         }
13472
13473         ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13474                                               set->fb, set->x, set->y);
13475         if (ret)
13476                 return ret;
13477
13478         crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13479         if (IS_ERR(crtc_state))
13480                 return PTR_ERR(crtc_state);
13481
13482         ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13483         if (ret)
13484                 return ret;
13485
13486         if (set->num_connectors)
13487                 crtc_state->active = true;
13488
13489         return 0;
13490 }
13491
13492 static int intel_crtc_set_config(struct drm_mode_set *set)
13493 {
13494         struct drm_device *dev;
13495         struct drm_atomic_state *state = NULL;
13496         int ret;
13497
13498         BUG_ON(!set);
13499         BUG_ON(!set->crtc);
13500         BUG_ON(!set->crtc->helper_private);
13501
13502         /* Enforce sane interface api - has been abused by the fb helper. */
13503         BUG_ON(!set->mode && set->fb);
13504         BUG_ON(set->fb && set->num_connectors == 0);
13505
13506         if (set->fb) {
13507                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13508                                 set->crtc->base.id, set->fb->base.id,
13509                                 (int)set->num_connectors, set->x, set->y);
13510         } else {
13511                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13512         }
13513
13514         dev = set->crtc->dev;
13515
13516         state = drm_atomic_state_alloc(dev);
13517         if (!state)
13518                 return -ENOMEM;
13519
13520         state->acquire_ctx = dev->mode_config.acquire_ctx;
13521
13522         ret = intel_modeset_stage_output_state(dev, set, state);
13523         if (ret)
13524                 goto out;
13525
13526         ret = intel_modeset_compute_config(state);
13527         if (ret)
13528                 goto out;
13529
13530         intel_update_pipe_size(to_intel_crtc(set->crtc));
13531
13532         ret = intel_set_mode_checked(state);
13533         if (ret) {
13534                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13535                               set->crtc->base.id, ret);
13536         }
13537
13538 out:
13539         if (ret)
13540                 drm_atomic_state_free(state);
13541         return ret;
13542 }
13543
13544 static const struct drm_crtc_funcs intel_crtc_funcs = {
13545         .gamma_set = intel_crtc_gamma_set,
13546         .set_config = intel_crtc_set_config,
13547         .destroy = intel_crtc_destroy,
13548         .page_flip = intel_crtc_page_flip,
13549         .atomic_duplicate_state = intel_crtc_duplicate_state,
13550         .atomic_destroy_state = intel_crtc_destroy_state,
13551 };
13552
13553 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13554                                       struct intel_shared_dpll *pll,
13555                                       struct intel_dpll_hw_state *hw_state)
13556 {
13557         uint32_t val;
13558
13559         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13560                 return false;
13561
13562         val = I915_READ(PCH_DPLL(pll->id));
13563         hw_state->dpll = val;
13564         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13565         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13566
13567         return val & DPLL_VCO_ENABLE;
13568 }
13569
13570 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13571                                   struct intel_shared_dpll *pll)
13572 {
13573         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13574         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13575 }
13576
13577 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13578                                 struct intel_shared_dpll *pll)
13579 {
13580         /* PCH refclock must be enabled first */
13581         ibx_assert_pch_refclk_enabled(dev_priv);
13582
13583         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13584
13585         /* Wait for the clocks to stabilize. */
13586         POSTING_READ(PCH_DPLL(pll->id));
13587         udelay(150);
13588
13589         /* The pixel multiplier can only be updated once the
13590          * DPLL is enabled and the clocks are stable.
13591          *
13592          * So write it again.
13593          */
13594         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13595         POSTING_READ(PCH_DPLL(pll->id));
13596         udelay(200);
13597 }
13598
13599 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13600                                  struct intel_shared_dpll *pll)
13601 {
13602         struct drm_device *dev = dev_priv->dev;
13603         struct intel_crtc *crtc;
13604
13605         /* Make sure no transcoder isn't still depending on us. */
13606         for_each_intel_crtc(dev, crtc) {
13607                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13608                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13609         }
13610
13611         I915_WRITE(PCH_DPLL(pll->id), 0);
13612         POSTING_READ(PCH_DPLL(pll->id));
13613         udelay(200);
13614 }
13615
13616 static char *ibx_pch_dpll_names[] = {
13617         "PCH DPLL A",
13618         "PCH DPLL B",
13619 };
13620
13621 static void ibx_pch_dpll_init(struct drm_device *dev)
13622 {
13623         struct drm_i915_private *dev_priv = dev->dev_private;
13624         int i;
13625
13626         dev_priv->num_shared_dpll = 2;
13627
13628         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13629                 dev_priv->shared_dplls[i].id = i;
13630                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13631                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13632                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13633                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13634                 dev_priv->shared_dplls[i].get_hw_state =
13635                         ibx_pch_dpll_get_hw_state;
13636         }
13637 }
13638
13639 static void intel_shared_dpll_init(struct drm_device *dev)
13640 {
13641         struct drm_i915_private *dev_priv = dev->dev_private;
13642
13643         intel_update_cdclk(dev);
13644
13645         if (HAS_DDI(dev))
13646                 intel_ddi_pll_init(dev);
13647         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13648                 ibx_pch_dpll_init(dev);
13649         else
13650                 dev_priv->num_shared_dpll = 0;
13651
13652         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13653 }
13654
13655 /**
13656  * intel_prepare_plane_fb - Prepare fb for usage on plane
13657  * @plane: drm plane to prepare for
13658  * @fb: framebuffer to prepare for presentation
13659  *
13660  * Prepares a framebuffer for usage on a display plane.  Generally this
13661  * involves pinning the underlying object and updating the frontbuffer tracking
13662  * bits.  Some older platforms need special physical address handling for
13663  * cursor planes.
13664  *
13665  * Returns 0 on success, negative error code on failure.
13666  */
13667 int
13668 intel_prepare_plane_fb(struct drm_plane *plane,
13669                        struct drm_framebuffer *fb,
13670                        const struct drm_plane_state *new_state)
13671 {
13672         struct drm_device *dev = plane->dev;
13673         struct intel_plane *intel_plane = to_intel_plane(plane);
13674         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13675         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13676         int ret = 0;
13677
13678         if (!obj)
13679                 return 0;
13680
13681         mutex_lock(&dev->struct_mutex);
13682
13683         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13684             INTEL_INFO(dev)->cursor_needs_physical) {
13685                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13686                 ret = i915_gem_object_attach_phys(obj, align);
13687                 if (ret)
13688                         DRM_DEBUG_KMS("failed to attach phys object\n");
13689         } else {
13690                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13691         }
13692
13693         if (ret == 0)
13694                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13695
13696         mutex_unlock(&dev->struct_mutex);
13697
13698         return ret;
13699 }
13700
13701 /**
13702  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13703  * @plane: drm plane to clean up for
13704  * @fb: old framebuffer that was on plane
13705  *
13706  * Cleans up a framebuffer that has just been removed from a plane.
13707  */
13708 void
13709 intel_cleanup_plane_fb(struct drm_plane *plane,
13710                        struct drm_framebuffer *fb,
13711                        const struct drm_plane_state *old_state)
13712 {
13713         struct drm_device *dev = plane->dev;
13714         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13715
13716         if (WARN_ON(!obj))
13717                 return;
13718
13719         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13720             !INTEL_INFO(dev)->cursor_needs_physical) {
13721                 mutex_lock(&dev->struct_mutex);
13722                 intel_unpin_fb_obj(fb, old_state);
13723                 mutex_unlock(&dev->struct_mutex);
13724         }
13725 }
13726
13727 int
13728 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13729 {
13730         int max_scale;
13731         struct drm_device *dev;
13732         struct drm_i915_private *dev_priv;
13733         int crtc_clock, cdclk;
13734
13735         if (!intel_crtc || !crtc_state)
13736                 return DRM_PLANE_HELPER_NO_SCALING;
13737
13738         dev = intel_crtc->base.dev;
13739         dev_priv = dev->dev_private;
13740         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13741         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13742
13743         if (!crtc_clock || !cdclk)
13744                 return DRM_PLANE_HELPER_NO_SCALING;
13745
13746         /*
13747          * skl max scale is lower of:
13748          *    close to 3 but not 3, -1 is for that purpose
13749          *            or
13750          *    cdclk/crtc_clock
13751          */
13752         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13753
13754         return max_scale;
13755 }
13756
13757 static int
13758 intel_check_primary_plane(struct drm_plane *plane,
13759                           struct intel_crtc_state *crtc_state,
13760                           struct intel_plane_state *state)
13761 {
13762         struct drm_crtc *crtc = state->base.crtc;
13763         struct drm_framebuffer *fb = state->base.fb;
13764         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13765         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13766         bool can_position = false;
13767
13768         /* use scaler when colorkey is not required */
13769         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13770             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13771                 min_scale = 1;
13772                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13773                 can_position = true;
13774         }
13775
13776         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13777                                              &state->dst, &state->clip,
13778                                              min_scale, max_scale,
13779                                              can_position, true,
13780                                              &state->visible);
13781 }
13782
13783 static void
13784 intel_commit_primary_plane(struct drm_plane *plane,
13785                            struct intel_plane_state *state)
13786 {
13787         struct drm_crtc *crtc = state->base.crtc;
13788         struct drm_framebuffer *fb = state->base.fb;
13789         struct drm_device *dev = plane->dev;
13790         struct drm_i915_private *dev_priv = dev->dev_private;
13791         struct intel_crtc *intel_crtc;
13792         struct drm_rect *src = &state->src;
13793
13794         crtc = crtc ? crtc : plane->crtc;
13795         intel_crtc = to_intel_crtc(crtc);
13796
13797         plane->fb = fb;
13798         crtc->x = src->x1 >> 16;
13799         crtc->y = src->y1 >> 16;
13800
13801         if (!crtc->state->active)
13802                 return;
13803
13804         if (state->visible)
13805                 /* FIXME: kill this fastboot hack */
13806                 intel_update_pipe_size(intel_crtc);
13807
13808         dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13809 }
13810
13811 static void
13812 intel_disable_primary_plane(struct drm_plane *plane,
13813                             struct drm_crtc *crtc)
13814 {
13815         struct drm_device *dev = plane->dev;
13816         struct drm_i915_private *dev_priv = dev->dev_private;
13817
13818         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13819 }
13820
13821 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13822 {
13823         struct drm_device *dev = crtc->dev;
13824         struct drm_i915_private *dev_priv = dev->dev_private;
13825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13826
13827         if (!needs_modeset(crtc->state))
13828                 intel_pre_plane_update(intel_crtc);
13829
13830         if (intel_crtc->atomic.update_wm_pre)
13831                 intel_update_watermarks(crtc);
13832
13833         intel_runtime_pm_get(dev_priv);
13834
13835         /* Perform vblank evasion around commit operation */
13836         if (crtc->state->active)
13837                 intel_crtc->atomic.evade =
13838                         intel_pipe_update_start(intel_crtc,
13839                                                 &intel_crtc->atomic.start_vbl_count);
13840
13841         if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13842                 skl_detach_scalers(intel_crtc);
13843 }
13844
13845 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13846 {
13847         struct drm_device *dev = crtc->dev;
13848         struct drm_i915_private *dev_priv = dev->dev_private;
13849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13850
13851         if (intel_crtc->atomic.evade)
13852                 intel_pipe_update_end(intel_crtc,
13853                                       intel_crtc->atomic.start_vbl_count);
13854
13855         intel_runtime_pm_put(dev_priv);
13856
13857         intel_post_plane_update(intel_crtc);
13858 }
13859
13860 /**
13861  * intel_plane_destroy - destroy a plane
13862  * @plane: plane to destroy
13863  *
13864  * Common destruction function for all types of planes (primary, cursor,
13865  * sprite).
13866  */
13867 void intel_plane_destroy(struct drm_plane *plane)
13868 {
13869         struct intel_plane *intel_plane = to_intel_plane(plane);
13870         drm_plane_cleanup(plane);
13871         kfree(intel_plane);
13872 }
13873
13874 const struct drm_plane_funcs intel_plane_funcs = {
13875         .update_plane = drm_atomic_helper_update_plane,
13876         .disable_plane = drm_atomic_helper_disable_plane,
13877         .destroy = intel_plane_destroy,
13878         .set_property = drm_atomic_helper_plane_set_property,
13879         .atomic_get_property = intel_plane_atomic_get_property,
13880         .atomic_set_property = intel_plane_atomic_set_property,
13881         .atomic_duplicate_state = intel_plane_duplicate_state,
13882         .atomic_destroy_state = intel_plane_destroy_state,
13883
13884 };
13885
13886 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13887                                                     int pipe)
13888 {
13889         struct intel_plane *primary;
13890         struct intel_plane_state *state;
13891         const uint32_t *intel_primary_formats;
13892         int num_formats;
13893
13894         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13895         if (primary == NULL)
13896                 return NULL;
13897
13898         state = intel_create_plane_state(&primary->base);
13899         if (!state) {
13900                 kfree(primary);
13901                 return NULL;
13902         }
13903         primary->base.state = &state->base;
13904
13905         primary->can_scale = false;
13906         primary->max_downscale = 1;
13907         if (INTEL_INFO(dev)->gen >= 9) {
13908                 primary->can_scale = true;
13909                 state->scaler_id = -1;
13910         }
13911         primary->pipe = pipe;
13912         primary->plane = pipe;
13913         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13914         primary->check_plane = intel_check_primary_plane;
13915         primary->commit_plane = intel_commit_primary_plane;
13916         primary->disable_plane = intel_disable_primary_plane;
13917         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13918                 primary->plane = !pipe;
13919
13920         if (INTEL_INFO(dev)->gen >= 9) {
13921                 intel_primary_formats = skl_primary_formats;
13922                 num_formats = ARRAY_SIZE(skl_primary_formats);
13923         } else if (INTEL_INFO(dev)->gen >= 4) {
13924                 intel_primary_formats = i965_primary_formats;
13925                 num_formats = ARRAY_SIZE(i965_primary_formats);
13926         } else {
13927                 intel_primary_formats = i8xx_primary_formats;
13928                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13929         }
13930
13931         drm_universal_plane_init(dev, &primary->base, 0,
13932                                  &intel_plane_funcs,
13933                                  intel_primary_formats, num_formats,
13934                                  DRM_PLANE_TYPE_PRIMARY);
13935
13936         if (INTEL_INFO(dev)->gen >= 4)
13937                 intel_create_rotation_property(dev, primary);
13938
13939         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13940
13941         return &primary->base;
13942 }
13943
13944 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13945 {
13946         if (!dev->mode_config.rotation_property) {
13947                 unsigned long flags = BIT(DRM_ROTATE_0) |
13948                         BIT(DRM_ROTATE_180);
13949
13950                 if (INTEL_INFO(dev)->gen >= 9)
13951                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13952
13953                 dev->mode_config.rotation_property =
13954                         drm_mode_create_rotation_property(dev, flags);
13955         }
13956         if (dev->mode_config.rotation_property)
13957                 drm_object_attach_property(&plane->base.base,
13958                                 dev->mode_config.rotation_property,
13959                                 plane->base.state->rotation);
13960 }
13961
13962 static int
13963 intel_check_cursor_plane(struct drm_plane *plane,
13964                          struct intel_crtc_state *crtc_state,
13965                          struct intel_plane_state *state)
13966 {
13967         struct drm_crtc *crtc = crtc_state->base.crtc;
13968         struct drm_framebuffer *fb = state->base.fb;
13969         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13970         unsigned stride;
13971         int ret;
13972
13973         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13974                                             &state->dst, &state->clip,
13975                                             DRM_PLANE_HELPER_NO_SCALING,
13976                                             DRM_PLANE_HELPER_NO_SCALING,
13977                                             true, true, &state->visible);
13978         if (ret)
13979                 return ret;
13980
13981         /* if we want to turn off the cursor ignore width and height */
13982         if (!obj)
13983                 return 0;
13984
13985         /* Check for which cursor types we support */
13986         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13987                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13988                           state->base.crtc_w, state->base.crtc_h);
13989                 return -EINVAL;
13990         }
13991
13992         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13993         if (obj->base.size < stride * state->base.crtc_h) {
13994                 DRM_DEBUG_KMS("buffer is too small\n");
13995                 return -ENOMEM;
13996         }
13997
13998         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13999                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14000                 return -EINVAL;
14001         }
14002
14003         return 0;
14004 }
14005
14006 static void
14007 intel_disable_cursor_plane(struct drm_plane *plane,
14008                            struct drm_crtc *crtc)
14009 {
14010         intel_crtc_update_cursor(crtc, false);
14011 }
14012
14013 static void
14014 intel_commit_cursor_plane(struct drm_plane *plane,
14015                           struct intel_plane_state *state)
14016 {
14017         struct drm_crtc *crtc = state->base.crtc;
14018         struct drm_device *dev = plane->dev;
14019         struct intel_crtc *intel_crtc;
14020         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14021         uint32_t addr;
14022
14023         crtc = crtc ? crtc : plane->crtc;
14024         intel_crtc = to_intel_crtc(crtc);
14025
14026         plane->fb = state->base.fb;
14027         crtc->cursor_x = state->base.crtc_x;
14028         crtc->cursor_y = state->base.crtc_y;
14029
14030         if (intel_crtc->cursor_bo == obj)
14031                 goto update;
14032
14033         if (!obj)
14034                 addr = 0;
14035         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14036                 addr = i915_gem_obj_ggtt_offset(obj);
14037         else
14038                 addr = obj->phys_handle->busaddr;
14039
14040         intel_crtc->cursor_addr = addr;
14041         intel_crtc->cursor_bo = obj;
14042
14043 update:
14044         if (crtc->state->active)
14045                 intel_crtc_update_cursor(crtc, state->visible);
14046 }
14047
14048 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14049                                                    int pipe)
14050 {
14051         struct intel_plane *cursor;
14052         struct intel_plane_state *state;
14053
14054         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14055         if (cursor == NULL)
14056                 return NULL;
14057
14058         state = intel_create_plane_state(&cursor->base);
14059         if (!state) {
14060                 kfree(cursor);
14061                 return NULL;
14062         }
14063         cursor->base.state = &state->base;
14064
14065         cursor->can_scale = false;
14066         cursor->max_downscale = 1;
14067         cursor->pipe = pipe;
14068         cursor->plane = pipe;
14069         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14070         cursor->check_plane = intel_check_cursor_plane;
14071         cursor->commit_plane = intel_commit_cursor_plane;
14072         cursor->disable_plane = intel_disable_cursor_plane;
14073
14074         drm_universal_plane_init(dev, &cursor->base, 0,
14075                                  &intel_plane_funcs,
14076                                  intel_cursor_formats,
14077                                  ARRAY_SIZE(intel_cursor_formats),
14078                                  DRM_PLANE_TYPE_CURSOR);
14079
14080         if (INTEL_INFO(dev)->gen >= 4) {
14081                 if (!dev->mode_config.rotation_property)
14082                         dev->mode_config.rotation_property =
14083                                 drm_mode_create_rotation_property(dev,
14084                                                         BIT(DRM_ROTATE_0) |
14085                                                         BIT(DRM_ROTATE_180));
14086                 if (dev->mode_config.rotation_property)
14087                         drm_object_attach_property(&cursor->base.base,
14088                                 dev->mode_config.rotation_property,
14089                                 state->base.rotation);
14090         }
14091
14092         if (INTEL_INFO(dev)->gen >=9)
14093                 state->scaler_id = -1;
14094
14095         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14096
14097         return &cursor->base;
14098 }
14099
14100 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14101         struct intel_crtc_state *crtc_state)
14102 {
14103         int i;
14104         struct intel_scaler *intel_scaler;
14105         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14106
14107         for (i = 0; i < intel_crtc->num_scalers; i++) {
14108                 intel_scaler = &scaler_state->scalers[i];
14109                 intel_scaler->in_use = 0;
14110                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14111         }
14112
14113         scaler_state->scaler_id = -1;
14114 }
14115
14116 static void intel_crtc_init(struct drm_device *dev, int pipe)
14117 {
14118         struct drm_i915_private *dev_priv = dev->dev_private;
14119         struct intel_crtc *intel_crtc;
14120         struct intel_crtc_state *crtc_state = NULL;
14121         struct drm_plane *primary = NULL;
14122         struct drm_plane *cursor = NULL;
14123         int i, ret;
14124
14125         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14126         if (intel_crtc == NULL)
14127                 return;
14128
14129         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14130         if (!crtc_state)
14131                 goto fail;
14132         intel_crtc->config = crtc_state;
14133         intel_crtc->base.state = &crtc_state->base;
14134         crtc_state->base.crtc = &intel_crtc->base;
14135
14136         /* initialize shared scalers */
14137         if (INTEL_INFO(dev)->gen >= 9) {
14138                 if (pipe == PIPE_C)
14139                         intel_crtc->num_scalers = 1;
14140                 else
14141                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14142
14143                 skl_init_scalers(dev, intel_crtc, crtc_state);
14144         }
14145
14146         primary = intel_primary_plane_create(dev, pipe);
14147         if (!primary)
14148                 goto fail;
14149
14150         cursor = intel_cursor_plane_create(dev, pipe);
14151         if (!cursor)
14152                 goto fail;
14153
14154         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14155                                         cursor, &intel_crtc_funcs);
14156         if (ret)
14157                 goto fail;
14158
14159         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14160         for (i = 0; i < 256; i++) {
14161                 intel_crtc->lut_r[i] = i;
14162                 intel_crtc->lut_g[i] = i;
14163                 intel_crtc->lut_b[i] = i;
14164         }
14165
14166         /*
14167          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14168          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14169          */
14170         intel_crtc->pipe = pipe;
14171         intel_crtc->plane = pipe;
14172         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14173                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14174                 intel_crtc->plane = !pipe;
14175         }
14176
14177         intel_crtc->cursor_base = ~0;
14178         intel_crtc->cursor_cntl = ~0;
14179         intel_crtc->cursor_size = ~0;
14180
14181         intel_crtc->wm.cxsr_allowed = true;
14182
14183         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14184                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14185         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14186         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14187
14188         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14189
14190         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14191         return;
14192
14193 fail:
14194         if (primary)
14195                 drm_plane_cleanup(primary);
14196         if (cursor)
14197                 drm_plane_cleanup(cursor);
14198         kfree(crtc_state);
14199         kfree(intel_crtc);
14200 }
14201
14202 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14203 {
14204         struct drm_encoder *encoder = connector->base.encoder;
14205         struct drm_device *dev = connector->base.dev;
14206
14207         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14208
14209         if (!encoder || WARN_ON(!encoder->crtc))
14210                 return INVALID_PIPE;
14211
14212         return to_intel_crtc(encoder->crtc)->pipe;
14213 }
14214
14215 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14216                                 struct drm_file *file)
14217 {
14218         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14219         struct drm_crtc *drmmode_crtc;
14220         struct intel_crtc *crtc;
14221
14222         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14223
14224         if (!drmmode_crtc) {
14225                 DRM_ERROR("no such CRTC id\n");
14226                 return -ENOENT;
14227         }
14228
14229         crtc = to_intel_crtc(drmmode_crtc);
14230         pipe_from_crtc_id->pipe = crtc->pipe;
14231
14232         return 0;
14233 }
14234
14235 static int intel_encoder_clones(struct intel_encoder *encoder)
14236 {
14237         struct drm_device *dev = encoder->base.dev;
14238         struct intel_encoder *source_encoder;
14239         int index_mask = 0;
14240         int entry = 0;
14241
14242         for_each_intel_encoder(dev, source_encoder) {
14243                 if (encoders_cloneable(encoder, source_encoder))
14244                         index_mask |= (1 << entry);
14245
14246                 entry++;
14247         }
14248
14249         return index_mask;
14250 }
14251
14252 static bool has_edp_a(struct drm_device *dev)
14253 {
14254         struct drm_i915_private *dev_priv = dev->dev_private;
14255
14256         if (!IS_MOBILE(dev))
14257                 return false;
14258
14259         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14260                 return false;
14261
14262         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14263                 return false;
14264
14265         return true;
14266 }
14267
14268 static bool intel_crt_present(struct drm_device *dev)
14269 {
14270         struct drm_i915_private *dev_priv = dev->dev_private;
14271
14272         if (INTEL_INFO(dev)->gen >= 9)
14273                 return false;
14274
14275         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14276                 return false;
14277
14278         if (IS_CHERRYVIEW(dev))
14279                 return false;
14280
14281         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14282                 return false;
14283
14284         return true;
14285 }
14286
14287 static void intel_setup_outputs(struct drm_device *dev)
14288 {
14289         struct drm_i915_private *dev_priv = dev->dev_private;
14290         struct intel_encoder *encoder;
14291         bool dpd_is_edp = false;
14292
14293         intel_lvds_init(dev);
14294
14295         if (intel_crt_present(dev))
14296                 intel_crt_init(dev);
14297
14298         if (IS_BROXTON(dev)) {
14299                 /*
14300                  * FIXME: Broxton doesn't support port detection via the
14301                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14302                  * detect the ports.
14303                  */
14304                 intel_ddi_init(dev, PORT_A);
14305                 intel_ddi_init(dev, PORT_B);
14306                 intel_ddi_init(dev, PORT_C);
14307         } else if (HAS_DDI(dev)) {
14308                 int found;
14309
14310                 /*
14311                  * Haswell uses DDI functions to detect digital outputs.
14312                  * On SKL pre-D0 the strap isn't connected, so we assume
14313                  * it's there.
14314                  */
14315                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14316                 /* WaIgnoreDDIAStrap: skl */
14317                 if (found ||
14318                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14319                         intel_ddi_init(dev, PORT_A);
14320
14321                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14322                  * register */
14323                 found = I915_READ(SFUSE_STRAP);
14324
14325                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14326                         intel_ddi_init(dev, PORT_B);
14327                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14328                         intel_ddi_init(dev, PORT_C);
14329                 if (found & SFUSE_STRAP_DDID_DETECTED)
14330                         intel_ddi_init(dev, PORT_D);
14331         } else if (HAS_PCH_SPLIT(dev)) {
14332                 int found;
14333                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14334
14335                 if (has_edp_a(dev))
14336                         intel_dp_init(dev, DP_A, PORT_A);
14337
14338                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14339                         /* PCH SDVOB multiplex with HDMIB */
14340                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14341                         if (!found)
14342                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14343                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14344                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14345                 }
14346
14347                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14348                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14349
14350                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14351                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14352
14353                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14354                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14355
14356                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14357                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14358         } else if (IS_VALLEYVIEW(dev)) {
14359                 /*
14360                  * The DP_DETECTED bit is the latched state of the DDC
14361                  * SDA pin at boot. However since eDP doesn't require DDC
14362                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14363                  * eDP ports may have been muxed to an alternate function.
14364                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14365                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14366                  * detect eDP ports.
14367                  */
14368                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14369                     !intel_dp_is_edp(dev, PORT_B))
14370                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14371                                         PORT_B);
14372                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14373                     intel_dp_is_edp(dev, PORT_B))
14374                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14375
14376                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14377                     !intel_dp_is_edp(dev, PORT_C))
14378                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14379                                         PORT_C);
14380                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14381                     intel_dp_is_edp(dev, PORT_C))
14382                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14383
14384                 if (IS_CHERRYVIEW(dev)) {
14385                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14386                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14387                                                 PORT_D);
14388                         /* eDP not supported on port D, so don't check VBT */
14389                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14390                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14391                 }
14392
14393                 intel_dsi_init(dev);
14394         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14395                 bool found = false;
14396
14397                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14398                         DRM_DEBUG_KMS("probing SDVOB\n");
14399                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14400                         if (!found && IS_G4X(dev)) {
14401                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14402                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14403                         }
14404
14405                         if (!found && IS_G4X(dev))
14406                                 intel_dp_init(dev, DP_B, PORT_B);
14407                 }
14408
14409                 /* Before G4X SDVOC doesn't have its own detect register */
14410
14411                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14412                         DRM_DEBUG_KMS("probing SDVOC\n");
14413                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14414                 }
14415
14416                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14417
14418                         if (IS_G4X(dev)) {
14419                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14420                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14421                         }
14422                         if (IS_G4X(dev))
14423                                 intel_dp_init(dev, DP_C, PORT_C);
14424                 }
14425
14426                 if (IS_G4X(dev) &&
14427                     (I915_READ(DP_D) & DP_DETECTED))
14428                         intel_dp_init(dev, DP_D, PORT_D);
14429         } else if (IS_GEN2(dev))
14430                 intel_dvo_init(dev);
14431
14432         if (SUPPORTS_TV(dev))
14433                 intel_tv_init(dev);
14434
14435         intel_psr_init(dev);
14436
14437         for_each_intel_encoder(dev, encoder) {
14438                 encoder->base.possible_crtcs = encoder->crtc_mask;
14439                 encoder->base.possible_clones =
14440                         intel_encoder_clones(encoder);
14441         }
14442
14443         intel_init_pch_refclk(dev);
14444
14445         drm_helper_move_panel_connectors_to_head(dev);
14446 }
14447
14448 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14449 {
14450         struct drm_device *dev = fb->dev;
14451         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14452
14453         drm_framebuffer_cleanup(fb);
14454         mutex_lock(&dev->struct_mutex);
14455         WARN_ON(!intel_fb->obj->framebuffer_references--);
14456         drm_gem_object_unreference(&intel_fb->obj->base);
14457         mutex_unlock(&dev->struct_mutex);
14458         kfree(intel_fb);
14459 }
14460
14461 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14462                                                 struct drm_file *file,
14463                                                 unsigned int *handle)
14464 {
14465         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14466         struct drm_i915_gem_object *obj = intel_fb->obj;
14467
14468         return drm_gem_handle_create(file, &obj->base, handle);
14469 }
14470
14471 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14472                                         struct drm_file *file,
14473                                         unsigned flags, unsigned color,
14474                                         struct drm_clip_rect *clips,
14475                                         unsigned num_clips)
14476 {
14477         struct drm_device *dev = fb->dev;
14478         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14479         struct drm_i915_gem_object *obj = intel_fb->obj;
14480
14481         mutex_lock(&dev->struct_mutex);
14482         intel_fb_obj_flush(obj, false, ORIGIN_GTT);
14483         mutex_unlock(&dev->struct_mutex);
14484
14485         return 0;
14486 }
14487
14488 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14489         .destroy = intel_user_framebuffer_destroy,
14490         .create_handle = intel_user_framebuffer_create_handle,
14491         .dirty = intel_user_framebuffer_dirty,
14492 };
14493
14494 static
14495 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14496                          uint32_t pixel_format)
14497 {
14498         u32 gen = INTEL_INFO(dev)->gen;
14499
14500         if (gen >= 9) {
14501                 /* "The stride in bytes must not exceed the of the size of 8K
14502                  *  pixels and 32K bytes."
14503                  */
14504                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14505         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14506                 return 32*1024;
14507         } else if (gen >= 4) {
14508                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14509                         return 16*1024;
14510                 else
14511                         return 32*1024;
14512         } else if (gen >= 3) {
14513                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14514                         return 8*1024;
14515                 else
14516                         return 16*1024;
14517         } else {
14518                 /* XXX DSPC is limited to 4k tiled */
14519                 return 8*1024;
14520         }
14521 }
14522
14523 static int intel_framebuffer_init(struct drm_device *dev,
14524                                   struct intel_framebuffer *intel_fb,
14525                                   struct drm_mode_fb_cmd2 *mode_cmd,
14526                                   struct drm_i915_gem_object *obj)
14527 {
14528         unsigned int aligned_height;
14529         int ret;
14530         u32 pitch_limit, stride_alignment;
14531
14532         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14533
14534         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14535                 /* Enforce that fb modifier and tiling mode match, but only for
14536                  * X-tiled. This is needed for FBC. */
14537                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14538                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14539                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14540                         return -EINVAL;
14541                 }
14542         } else {
14543                 if (obj->tiling_mode == I915_TILING_X)
14544                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14545                 else if (obj->tiling_mode == I915_TILING_Y) {
14546                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14547                         return -EINVAL;
14548                 }
14549         }
14550
14551         /* Passed in modifier sanity checking. */
14552         switch (mode_cmd->modifier[0]) {
14553         case I915_FORMAT_MOD_Y_TILED:
14554         case I915_FORMAT_MOD_Yf_TILED:
14555                 if (INTEL_INFO(dev)->gen < 9) {
14556                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14557                                   mode_cmd->modifier[0]);
14558                         return -EINVAL;
14559                 }
14560         case DRM_FORMAT_MOD_NONE:
14561         case I915_FORMAT_MOD_X_TILED:
14562                 break;
14563         default:
14564                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14565                           mode_cmd->modifier[0]);
14566                 return -EINVAL;
14567         }
14568
14569         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14570                                                      mode_cmd->pixel_format);
14571         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14572                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14573                           mode_cmd->pitches[0], stride_alignment);
14574                 return -EINVAL;
14575         }
14576
14577         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14578                                            mode_cmd->pixel_format);
14579         if (mode_cmd->pitches[0] > pitch_limit) {
14580                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14581                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14582                           "tiled" : "linear",
14583                           mode_cmd->pitches[0], pitch_limit);
14584                 return -EINVAL;
14585         }
14586
14587         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14588             mode_cmd->pitches[0] != obj->stride) {
14589                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14590                           mode_cmd->pitches[0], obj->stride);
14591                 return -EINVAL;
14592         }
14593
14594         /* Reject formats not supported by any plane early. */
14595         switch (mode_cmd->pixel_format) {
14596         case DRM_FORMAT_C8:
14597         case DRM_FORMAT_RGB565:
14598         case DRM_FORMAT_XRGB8888:
14599         case DRM_FORMAT_ARGB8888:
14600                 break;
14601         case DRM_FORMAT_XRGB1555:
14602                 if (INTEL_INFO(dev)->gen > 3) {
14603                         DRM_DEBUG("unsupported pixel format: %s\n",
14604                                   drm_get_format_name(mode_cmd->pixel_format));
14605                         return -EINVAL;
14606                 }
14607                 break;
14608         case DRM_FORMAT_ABGR8888:
14609                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14610                         DRM_DEBUG("unsupported pixel format: %s\n",
14611                                   drm_get_format_name(mode_cmd->pixel_format));
14612                         return -EINVAL;
14613                 }
14614                 break;
14615         case DRM_FORMAT_XBGR8888:
14616         case DRM_FORMAT_XRGB2101010:
14617         case DRM_FORMAT_XBGR2101010:
14618                 if (INTEL_INFO(dev)->gen < 4) {
14619                         DRM_DEBUG("unsupported pixel format: %s\n",
14620                                   drm_get_format_name(mode_cmd->pixel_format));
14621                         return -EINVAL;
14622                 }
14623                 break;
14624         case DRM_FORMAT_ABGR2101010:
14625                 if (!IS_VALLEYVIEW(dev)) {
14626                         DRM_DEBUG("unsupported pixel format: %s\n",
14627                                   drm_get_format_name(mode_cmd->pixel_format));
14628                         return -EINVAL;
14629                 }
14630                 break;
14631         case DRM_FORMAT_YUYV:
14632         case DRM_FORMAT_UYVY:
14633         case DRM_FORMAT_YVYU:
14634         case DRM_FORMAT_VYUY:
14635                 if (INTEL_INFO(dev)->gen < 5) {
14636                         DRM_DEBUG("unsupported pixel format: %s\n",
14637                                   drm_get_format_name(mode_cmd->pixel_format));
14638                         return -EINVAL;
14639                 }
14640                 break;
14641         default:
14642                 DRM_DEBUG("unsupported pixel format: %s\n",
14643                           drm_get_format_name(mode_cmd->pixel_format));
14644                 return -EINVAL;
14645         }
14646
14647         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14648         if (mode_cmd->offsets[0] != 0)
14649                 return -EINVAL;
14650
14651         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14652                                                mode_cmd->pixel_format,
14653                                                mode_cmd->modifier[0]);
14654         /* FIXME drm helper for size checks (especially planar formats)? */
14655         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14656                 return -EINVAL;
14657
14658         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14659         intel_fb->obj = obj;
14660         intel_fb->obj->framebuffer_references++;
14661
14662         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14663         if (ret) {
14664                 DRM_ERROR("framebuffer init failed %d\n", ret);
14665                 return ret;
14666         }
14667
14668         return 0;
14669 }
14670
14671 static struct drm_framebuffer *
14672 intel_user_framebuffer_create(struct drm_device *dev,
14673                               struct drm_file *filp,
14674                               struct drm_mode_fb_cmd2 *mode_cmd)
14675 {
14676         struct drm_i915_gem_object *obj;
14677
14678         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14679                                                 mode_cmd->handles[0]));
14680         if (&obj->base == NULL)
14681                 return ERR_PTR(-ENOENT);
14682
14683         return intel_framebuffer_create(dev, mode_cmd, obj);
14684 }
14685
14686 #ifndef CONFIG_DRM_I915_FBDEV
14687 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14688 {
14689 }
14690 #endif
14691
14692 static const struct drm_mode_config_funcs intel_mode_funcs = {
14693         .fb_create = intel_user_framebuffer_create,
14694         .output_poll_changed = intel_fbdev_output_poll_changed,
14695         .atomic_check = intel_atomic_check,
14696         .atomic_commit = intel_atomic_commit,
14697         .atomic_state_alloc = intel_atomic_state_alloc,
14698         .atomic_state_clear = intel_atomic_state_clear,
14699 };
14700
14701 /* Set up chip specific display functions */
14702 static void intel_init_display(struct drm_device *dev)
14703 {
14704         struct drm_i915_private *dev_priv = dev->dev_private;
14705
14706         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14707                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14708         else if (IS_CHERRYVIEW(dev))
14709                 dev_priv->display.find_dpll = chv_find_best_dpll;
14710         else if (IS_VALLEYVIEW(dev))
14711                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14712         else if (IS_PINEVIEW(dev))
14713                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14714         else
14715                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14716
14717         if (INTEL_INFO(dev)->gen >= 9) {
14718                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14719                 dev_priv->display.get_initial_plane_config =
14720                         skylake_get_initial_plane_config;
14721                 dev_priv->display.crtc_compute_clock =
14722                         haswell_crtc_compute_clock;
14723                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14724                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14725                 dev_priv->display.update_primary_plane =
14726                         skylake_update_primary_plane;
14727         } else if (HAS_DDI(dev)) {
14728                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14729                 dev_priv->display.get_initial_plane_config =
14730                         ironlake_get_initial_plane_config;
14731                 dev_priv->display.crtc_compute_clock =
14732                         haswell_crtc_compute_clock;
14733                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14734                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14735                 dev_priv->display.update_primary_plane =
14736                         ironlake_update_primary_plane;
14737         } else if (HAS_PCH_SPLIT(dev)) {
14738                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14739                 dev_priv->display.get_initial_plane_config =
14740                         ironlake_get_initial_plane_config;
14741                 dev_priv->display.crtc_compute_clock =
14742                         ironlake_crtc_compute_clock;
14743                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14744                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14745                 dev_priv->display.update_primary_plane =
14746                         ironlake_update_primary_plane;
14747         } else if (IS_VALLEYVIEW(dev)) {
14748                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14749                 dev_priv->display.get_initial_plane_config =
14750                         i9xx_get_initial_plane_config;
14751                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14752                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14753                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14754                 dev_priv->display.update_primary_plane =
14755                         i9xx_update_primary_plane;
14756         } else {
14757                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14758                 dev_priv->display.get_initial_plane_config =
14759                         i9xx_get_initial_plane_config;
14760                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14761                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14762                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14763                 dev_priv->display.update_primary_plane =
14764                         i9xx_update_primary_plane;
14765         }
14766
14767         /* Returns the core display clock speed */
14768         if (IS_SKYLAKE(dev))
14769                 dev_priv->display.get_display_clock_speed =
14770                         skylake_get_display_clock_speed;
14771         else if (IS_BROXTON(dev))
14772                 dev_priv->display.get_display_clock_speed =
14773                         broxton_get_display_clock_speed;
14774         else if (IS_BROADWELL(dev))
14775                 dev_priv->display.get_display_clock_speed =
14776                         broadwell_get_display_clock_speed;
14777         else if (IS_HASWELL(dev))
14778                 dev_priv->display.get_display_clock_speed =
14779                         haswell_get_display_clock_speed;
14780         else if (IS_VALLEYVIEW(dev))
14781                 dev_priv->display.get_display_clock_speed =
14782                         valleyview_get_display_clock_speed;
14783         else if (IS_GEN5(dev))
14784                 dev_priv->display.get_display_clock_speed =
14785                         ilk_get_display_clock_speed;
14786         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14787                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14788                 dev_priv->display.get_display_clock_speed =
14789                         i945_get_display_clock_speed;
14790         else if (IS_GM45(dev))
14791                 dev_priv->display.get_display_clock_speed =
14792                         gm45_get_display_clock_speed;
14793         else if (IS_CRESTLINE(dev))
14794                 dev_priv->display.get_display_clock_speed =
14795                         i965gm_get_display_clock_speed;
14796         else if (IS_PINEVIEW(dev))
14797                 dev_priv->display.get_display_clock_speed =
14798                         pnv_get_display_clock_speed;
14799         else if (IS_G33(dev) || IS_G4X(dev))
14800                 dev_priv->display.get_display_clock_speed =
14801                         g33_get_display_clock_speed;
14802         else if (IS_I915G(dev))
14803                 dev_priv->display.get_display_clock_speed =
14804                         i915_get_display_clock_speed;
14805         else if (IS_I945GM(dev) || IS_845G(dev))
14806                 dev_priv->display.get_display_clock_speed =
14807                         i9xx_misc_get_display_clock_speed;
14808         else if (IS_PINEVIEW(dev))
14809                 dev_priv->display.get_display_clock_speed =
14810                         pnv_get_display_clock_speed;
14811         else if (IS_I915GM(dev))
14812                 dev_priv->display.get_display_clock_speed =
14813                         i915gm_get_display_clock_speed;
14814         else if (IS_I865G(dev))
14815                 dev_priv->display.get_display_clock_speed =
14816                         i865_get_display_clock_speed;
14817         else if (IS_I85X(dev))
14818                 dev_priv->display.get_display_clock_speed =
14819                         i85x_get_display_clock_speed;
14820         else { /* 830 */
14821                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14822                 dev_priv->display.get_display_clock_speed =
14823                         i830_get_display_clock_speed;
14824         }
14825
14826         if (IS_GEN5(dev)) {
14827                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14828         } else if (IS_GEN6(dev)) {
14829                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14830         } else if (IS_IVYBRIDGE(dev)) {
14831                 /* FIXME: detect B0+ stepping and use auto training */
14832                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14833         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14834                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14835                 if (IS_BROADWELL(dev)) {
14836                         dev_priv->display.modeset_commit_cdclk =
14837                                 broadwell_modeset_commit_cdclk;
14838                         dev_priv->display.modeset_calc_cdclk =
14839                                 broadwell_modeset_calc_cdclk;
14840                 }
14841         } else if (IS_VALLEYVIEW(dev)) {
14842                 dev_priv->display.modeset_commit_cdclk =
14843                         valleyview_modeset_commit_cdclk;
14844                 dev_priv->display.modeset_calc_cdclk =
14845                         valleyview_modeset_calc_cdclk;
14846         } else if (IS_BROXTON(dev)) {
14847                 dev_priv->display.modeset_commit_cdclk =
14848                         broxton_modeset_commit_cdclk;
14849                 dev_priv->display.modeset_calc_cdclk =
14850                         broxton_modeset_calc_cdclk;
14851         }
14852
14853         switch (INTEL_INFO(dev)->gen) {
14854         case 2:
14855                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14856                 break;
14857
14858         case 3:
14859                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14860                 break;
14861
14862         case 4:
14863         case 5:
14864                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14865                 break;
14866
14867         case 6:
14868                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14869                 break;
14870         case 7:
14871         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14872                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14873                 break;
14874         case 9:
14875                 /* Drop through - unsupported since execlist only. */
14876         default:
14877                 /* Default just returns -ENODEV to indicate unsupported */
14878                 dev_priv->display.queue_flip = intel_default_queue_flip;
14879         }
14880
14881         intel_panel_init_backlight_funcs(dev);
14882
14883         mutex_init(&dev_priv->pps_mutex);
14884 }
14885
14886 /*
14887  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14888  * resume, or other times.  This quirk makes sure that's the case for
14889  * affected systems.
14890  */
14891 static void quirk_pipea_force(struct drm_device *dev)
14892 {
14893         struct drm_i915_private *dev_priv = dev->dev_private;
14894
14895         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14896         DRM_INFO("applying pipe a force quirk\n");
14897 }
14898
14899 static void quirk_pipeb_force(struct drm_device *dev)
14900 {
14901         struct drm_i915_private *dev_priv = dev->dev_private;
14902
14903         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14904         DRM_INFO("applying pipe b force quirk\n");
14905 }
14906
14907 /*
14908  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14909  */
14910 static void quirk_ssc_force_disable(struct drm_device *dev)
14911 {
14912         struct drm_i915_private *dev_priv = dev->dev_private;
14913         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14914         DRM_INFO("applying lvds SSC disable quirk\n");
14915 }
14916
14917 /*
14918  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14919  * brightness value
14920  */
14921 static void quirk_invert_brightness(struct drm_device *dev)
14922 {
14923         struct drm_i915_private *dev_priv = dev->dev_private;
14924         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14925         DRM_INFO("applying inverted panel brightness quirk\n");
14926 }
14927
14928 /* Some VBT's incorrectly indicate no backlight is present */
14929 static void quirk_backlight_present(struct drm_device *dev)
14930 {
14931         struct drm_i915_private *dev_priv = dev->dev_private;
14932         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14933         DRM_INFO("applying backlight present quirk\n");
14934 }
14935
14936 struct intel_quirk {
14937         int device;
14938         int subsystem_vendor;
14939         int subsystem_device;
14940         void (*hook)(struct drm_device *dev);
14941 };
14942
14943 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14944 struct intel_dmi_quirk {
14945         void (*hook)(struct drm_device *dev);
14946         const struct dmi_system_id (*dmi_id_list)[];
14947 };
14948
14949 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14950 {
14951         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14952         return 1;
14953 }
14954
14955 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14956         {
14957                 .dmi_id_list = &(const struct dmi_system_id[]) {
14958                         {
14959                                 .callback = intel_dmi_reverse_brightness,
14960                                 .ident = "NCR Corporation",
14961                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14962                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14963                                 },
14964                         },
14965                         { }  /* terminating entry */
14966                 },
14967                 .hook = quirk_invert_brightness,
14968         },
14969 };
14970
14971 static struct intel_quirk intel_quirks[] = {
14972         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14973         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14974
14975         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14976         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14977
14978         /* 830 needs to leave pipe A & dpll A up */
14979         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14980
14981         /* 830 needs to leave pipe B & dpll B up */
14982         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14983
14984         /* Lenovo U160 cannot use SSC on LVDS */
14985         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14986
14987         /* Sony Vaio Y cannot use SSC on LVDS */
14988         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14989
14990         /* Acer Aspire 5734Z must invert backlight brightness */
14991         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14992
14993         /* Acer/eMachines G725 */
14994         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14995
14996         /* Acer/eMachines e725 */
14997         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14998
14999         /* Acer/Packard Bell NCL20 */
15000         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15001
15002         /* Acer Aspire 4736Z */
15003         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15004
15005         /* Acer Aspire 5336 */
15006         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15007
15008         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15009         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15010
15011         /* Acer C720 Chromebook (Core i3 4005U) */
15012         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15013
15014         /* Apple Macbook 2,1 (Core 2 T7400) */
15015         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15016
15017         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15018         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15019
15020         /* HP Chromebook 14 (Celeron 2955U) */
15021         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15022
15023         /* Dell Chromebook 11 */
15024         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15025 };
15026
15027 static void intel_init_quirks(struct drm_device *dev)
15028 {
15029         struct pci_dev *d = dev->pdev;
15030         int i;
15031
15032         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15033                 struct intel_quirk *q = &intel_quirks[i];
15034
15035                 if (d->device == q->device &&
15036                     (d->subsystem_vendor == q->subsystem_vendor ||
15037                      q->subsystem_vendor == PCI_ANY_ID) &&
15038                     (d->subsystem_device == q->subsystem_device ||
15039                      q->subsystem_device == PCI_ANY_ID))
15040                         q->hook(dev);
15041         }
15042         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15043                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15044                         intel_dmi_quirks[i].hook(dev);
15045         }
15046 }
15047
15048 /* Disable the VGA plane that we never use */
15049 static void i915_disable_vga(struct drm_device *dev)
15050 {
15051         struct drm_i915_private *dev_priv = dev->dev_private;
15052         u8 sr1;
15053         u32 vga_reg = i915_vgacntrl_reg(dev);
15054
15055         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15056         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15057         outb(SR01, VGA_SR_INDEX);
15058         sr1 = inb(VGA_SR_DATA);
15059         outb(sr1 | 1<<5, VGA_SR_DATA);
15060         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15061         udelay(300);
15062
15063         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15064         POSTING_READ(vga_reg);
15065 }
15066
15067 void intel_modeset_init_hw(struct drm_device *dev)
15068 {
15069         intel_update_cdclk(dev);
15070         intel_prepare_ddi(dev);
15071         intel_init_clock_gating(dev);
15072         intel_enable_gt_powersave(dev);
15073 }
15074
15075 void intel_modeset_init(struct drm_device *dev)
15076 {
15077         struct drm_i915_private *dev_priv = dev->dev_private;
15078         int sprite, ret;
15079         enum pipe pipe;
15080         struct intel_crtc *crtc;
15081
15082         drm_mode_config_init(dev);
15083
15084         dev->mode_config.min_width = 0;
15085         dev->mode_config.min_height = 0;
15086
15087         dev->mode_config.preferred_depth = 24;
15088         dev->mode_config.prefer_shadow = 1;
15089
15090         dev->mode_config.allow_fb_modifiers = true;
15091
15092         dev->mode_config.funcs = &intel_mode_funcs;
15093
15094         intel_init_quirks(dev);
15095
15096         intel_init_pm(dev);
15097
15098         if (INTEL_INFO(dev)->num_pipes == 0)
15099                 return;
15100
15101         intel_init_display(dev);
15102         intel_init_audio(dev);
15103
15104         if (IS_GEN2(dev)) {
15105                 dev->mode_config.max_width = 2048;
15106                 dev->mode_config.max_height = 2048;
15107         } else if (IS_GEN3(dev)) {
15108                 dev->mode_config.max_width = 4096;
15109                 dev->mode_config.max_height = 4096;
15110         } else {
15111                 dev->mode_config.max_width = 8192;
15112                 dev->mode_config.max_height = 8192;
15113         }
15114
15115         if (IS_845G(dev) || IS_I865G(dev)) {
15116                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15117                 dev->mode_config.cursor_height = 1023;
15118         } else if (IS_GEN2(dev)) {
15119                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15120                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15121         } else {
15122                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15123                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15124         }
15125
15126         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15127
15128         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15129                       INTEL_INFO(dev)->num_pipes,
15130                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15131
15132         for_each_pipe(dev_priv, pipe) {
15133                 intel_crtc_init(dev, pipe);
15134                 for_each_sprite(dev_priv, pipe, sprite) {
15135                         ret = intel_plane_init(dev, pipe, sprite);
15136                         if (ret)
15137                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15138                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15139                 }
15140         }
15141
15142         intel_init_dpio(dev);
15143
15144         intel_shared_dpll_init(dev);
15145
15146         /* Just disable it once at startup */
15147         i915_disable_vga(dev);
15148         intel_setup_outputs(dev);
15149
15150         /* Just in case the BIOS is doing something questionable. */
15151         intel_fbc_disable(dev_priv);
15152
15153         drm_modeset_lock_all(dev);
15154         intel_modeset_setup_hw_state(dev);
15155         drm_modeset_unlock_all(dev);
15156
15157         for_each_intel_crtc(dev, crtc) {
15158                 struct intel_initial_plane_config plane_config = {};
15159
15160                 if (!crtc->active)
15161                         continue;
15162
15163                 /*
15164                  * Note that reserving the BIOS fb up front prevents us
15165                  * from stuffing other stolen allocations like the ring
15166                  * on top.  This prevents some ugliness at boot time, and
15167                  * can even allow for smooth boot transitions if the BIOS
15168                  * fb is large enough for the active pipe configuration.
15169                  */
15170                 dev_priv->display.get_initial_plane_config(crtc,
15171                                                            &plane_config);
15172
15173                 /*
15174                  * If the fb is shared between multiple heads, we'll
15175                  * just get the first one.
15176                  */
15177                 intel_find_initial_plane_obj(crtc, &plane_config);
15178         }
15179 }
15180
15181 static void intel_enable_pipe_a(struct drm_device *dev)
15182 {
15183         struct intel_connector *connector;
15184         struct drm_connector *crt = NULL;
15185         struct intel_load_detect_pipe load_detect_temp;
15186         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15187
15188         /* We can't just switch on the pipe A, we need to set things up with a
15189          * proper mode and output configuration. As a gross hack, enable pipe A
15190          * by enabling the load detect pipe once. */
15191         for_each_intel_connector(dev, connector) {
15192                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15193                         crt = &connector->base;
15194                         break;
15195                 }
15196         }
15197
15198         if (!crt)
15199                 return;
15200
15201         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15202                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15203 }
15204
15205 static bool
15206 intel_check_plane_mapping(struct intel_crtc *crtc)
15207 {
15208         struct drm_device *dev = crtc->base.dev;
15209         struct drm_i915_private *dev_priv = dev->dev_private;
15210         u32 reg, val;
15211
15212         if (INTEL_INFO(dev)->num_pipes == 1)
15213                 return true;
15214
15215         reg = DSPCNTR(!crtc->plane);
15216         val = I915_READ(reg);
15217
15218         if ((val & DISPLAY_PLANE_ENABLE) &&
15219             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15220                 return false;
15221
15222         return true;
15223 }
15224
15225 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15226 {
15227         struct drm_device *dev = crtc->base.dev;
15228         struct drm_i915_private *dev_priv = dev->dev_private;
15229         struct intel_encoder *encoder;
15230         u32 reg;
15231         bool enable;
15232
15233         /* Clear any frame start delays used for debugging left by the BIOS */
15234         reg = PIPECONF(crtc->config->cpu_transcoder);
15235         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15236
15237         /* restore vblank interrupts to correct state */
15238         drm_crtc_vblank_reset(&crtc->base);
15239         if (crtc->active) {
15240                 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15241                 update_scanline_offset(crtc);
15242                 drm_crtc_vblank_on(&crtc->base);
15243         }
15244
15245         /* We need to sanitize the plane -> pipe mapping first because this will
15246          * disable the crtc (and hence change the state) if it is wrong. Note
15247          * that gen4+ has a fixed plane -> pipe mapping.  */
15248         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15249                 bool plane;
15250
15251                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15252                               crtc->base.base.id);
15253
15254                 /* Pipe has the wrong plane attached and the plane is active.
15255                  * Temporarily change the plane mapping and disable everything
15256                  * ...  */
15257                 plane = crtc->plane;
15258                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15259                 crtc->plane = !plane;
15260                 intel_crtc_disable_noatomic(&crtc->base);
15261                 crtc->plane = plane;
15262         }
15263
15264         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15265             crtc->pipe == PIPE_A && !crtc->active) {
15266                 /* BIOS forgot to enable pipe A, this mostly happens after
15267                  * resume. Force-enable the pipe to fix this, the update_dpms
15268                  * call below we restore the pipe to the right state, but leave
15269                  * the required bits on. */
15270                 intel_enable_pipe_a(dev);
15271         }
15272
15273         /* Adjust the state of the output pipe according to whether we
15274          * have active connectors/encoders. */
15275         enable = false;
15276         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15277                 enable |= encoder->connectors_active;
15278
15279         if (!enable)
15280                 intel_crtc_disable_noatomic(&crtc->base);
15281
15282         if (crtc->active != crtc->base.state->active) {
15283
15284                 /* This can happen either due to bugs in the get_hw_state
15285                  * functions or because of calls to intel_crtc_disable_noatomic,
15286                  * or because the pipe is force-enabled due to the
15287                  * pipe A quirk. */
15288                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15289                               crtc->base.base.id,
15290                               crtc->base.state->enable ? "enabled" : "disabled",
15291                               crtc->active ? "enabled" : "disabled");
15292
15293                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15294                 crtc->base.state->active = crtc->active;
15295                 crtc->base.enabled = crtc->active;
15296
15297                 /* Because we only establish the connector -> encoder ->
15298                  * crtc links if something is active, this means the
15299                  * crtc is now deactivated. Break the links. connector
15300                  * -> encoder links are only establish when things are
15301                  *  actually up, hence no need to break them. */
15302                 WARN_ON(crtc->active);
15303
15304                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15305                         WARN_ON(encoder->connectors_active);
15306                         encoder->base.crtc = NULL;
15307                 }
15308         }
15309
15310         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15311                 /*
15312                  * We start out with underrun reporting disabled to avoid races.
15313                  * For correct bookkeeping mark this on active crtcs.
15314                  *
15315                  * Also on gmch platforms we dont have any hardware bits to
15316                  * disable the underrun reporting. Which means we need to start
15317                  * out with underrun reporting disabled also on inactive pipes,
15318                  * since otherwise we'll complain about the garbage we read when
15319                  * e.g. coming up after runtime pm.
15320                  *
15321                  * No protection against concurrent access is required - at
15322                  * worst a fifo underrun happens which also sets this to false.
15323                  */
15324                 crtc->cpu_fifo_underrun_disabled = true;
15325                 crtc->pch_fifo_underrun_disabled = true;
15326         }
15327 }
15328
15329 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15330 {
15331         struct intel_connector *connector;
15332         struct drm_device *dev = encoder->base.dev;
15333
15334         /* We need to check both for a crtc link (meaning that the
15335          * encoder is active and trying to read from a pipe) and the
15336          * pipe itself being active. */
15337         bool has_active_crtc = encoder->base.crtc &&
15338                 to_intel_crtc(encoder->base.crtc)->active;
15339
15340         if (encoder->connectors_active && !has_active_crtc) {
15341                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15342                               encoder->base.base.id,
15343                               encoder->base.name);
15344
15345                 /* Connector is active, but has no active pipe. This is
15346                  * fallout from our resume register restoring. Disable
15347                  * the encoder manually again. */
15348                 if (encoder->base.crtc) {
15349                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15350                                       encoder->base.base.id,
15351                                       encoder->base.name);
15352                         encoder->disable(encoder);
15353                         if (encoder->post_disable)
15354                                 encoder->post_disable(encoder);
15355                 }
15356                 encoder->base.crtc = NULL;
15357                 encoder->connectors_active = false;
15358
15359                 /* Inconsistent output/port/pipe state happens presumably due to
15360                  * a bug in one of the get_hw_state functions. Or someplace else
15361                  * in our code, like the register restore mess on resume. Clamp
15362                  * things to off as a safer default. */
15363                 for_each_intel_connector(dev, connector) {
15364                         if (connector->encoder != encoder)
15365                                 continue;
15366                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15367                         connector->base.encoder = NULL;
15368                 }
15369         }
15370         /* Enabled encoders without active connectors will be fixed in
15371          * the crtc fixup. */
15372 }
15373
15374 void i915_redisable_vga_power_on(struct drm_device *dev)
15375 {
15376         struct drm_i915_private *dev_priv = dev->dev_private;
15377         u32 vga_reg = i915_vgacntrl_reg(dev);
15378
15379         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15380                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15381                 i915_disable_vga(dev);
15382         }
15383 }
15384
15385 void i915_redisable_vga(struct drm_device *dev)
15386 {
15387         struct drm_i915_private *dev_priv = dev->dev_private;
15388
15389         /* This function can be called both from intel_modeset_setup_hw_state or
15390          * at a very early point in our resume sequence, where the power well
15391          * structures are not yet restored. Since this function is at a very
15392          * paranoid "someone might have enabled VGA while we were not looking"
15393          * level, just check if the power well is enabled instead of trying to
15394          * follow the "don't touch the power well if we don't need it" policy
15395          * the rest of the driver uses. */
15396         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15397                 return;
15398
15399         i915_redisable_vga_power_on(dev);
15400 }
15401
15402 static bool primary_get_hw_state(struct intel_crtc *crtc)
15403 {
15404         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15405
15406         return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15407 }
15408
15409 static void readout_plane_state(struct intel_crtc *crtc,
15410                                 struct intel_crtc_state *crtc_state)
15411 {
15412         struct intel_plane *p;
15413         struct intel_plane_state *plane_state;
15414         bool active = crtc_state->base.active;
15415
15416         for_each_intel_plane(crtc->base.dev, p) {
15417                 if (crtc->pipe != p->pipe)
15418                         continue;
15419
15420                 plane_state = to_intel_plane_state(p->base.state);
15421
15422                 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15423                         plane_state->visible = primary_get_hw_state(crtc);
15424                 else {
15425                         if (active)
15426                                 p->disable_plane(&p->base, &crtc->base);
15427
15428                         plane_state->visible = false;
15429                 }
15430         }
15431 }
15432
15433 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15434 {
15435         struct drm_i915_private *dev_priv = dev->dev_private;
15436         enum pipe pipe;
15437         struct intel_crtc *crtc;
15438         struct intel_encoder *encoder;
15439         struct intel_connector *connector;
15440         int i;
15441
15442         for_each_intel_crtc(dev, crtc) {
15443                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15444                 memset(crtc->config, 0, sizeof(*crtc->config));
15445                 crtc->config->base.crtc = &crtc->base;
15446
15447                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15448
15449                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15450                                                                  crtc->config);
15451
15452                 crtc->base.state->active = crtc->active;
15453                 crtc->base.enabled = crtc->active;
15454
15455                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15456                 if (crtc->base.state->active) {
15457                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15458                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15459                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15460
15461                         /*
15462                          * The initial mode needs to be set in order to keep
15463                          * the atomic core happy. It wants a valid mode if the
15464                          * crtc's enabled, so we do the above call.
15465                          *
15466                          * At this point some state updated by the connectors
15467                          * in their ->detect() callback has not run yet, so
15468                          * no recalculation can be done yet.
15469                          *
15470                          * Even if we could do a recalculation and modeset
15471                          * right now it would cause a double modeset if
15472                          * fbdev or userspace chooses a different initial mode.
15473                          *
15474                          * So to prevent the double modeset, fail the memcmp
15475                          * test in drm_atomic_set_mode_for_crtc to get a new
15476                          * mode blob, and compare if the mode blob changed
15477                          * when the PIPE_CONFIG_QUIRK_INHERITED_MODE quirk is
15478                          * set.
15479                          *
15480                          * If that happens, someone indicated they wanted a
15481                          * mode change, which means it's safe to do a full
15482                          * recalculation.
15483                          */
15484                         crtc->base.state->mode.private_flags = ~0;
15485                 }
15486
15487                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15488                 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15489
15490                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15491                               crtc->base.base.id,
15492                               crtc->active ? "enabled" : "disabled");
15493         }
15494
15495         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15496                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15497
15498                 pll->on = pll->get_hw_state(dev_priv, pll,
15499                                             &pll->config.hw_state);
15500                 pll->active = 0;
15501                 pll->config.crtc_mask = 0;
15502                 for_each_intel_crtc(dev, crtc) {
15503                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15504                                 pll->active++;
15505                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15506                         }
15507                 }
15508
15509                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15510                               pll->name, pll->config.crtc_mask, pll->on);
15511
15512                 if (pll->config.crtc_mask)
15513                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15514         }
15515
15516         for_each_intel_encoder(dev, encoder) {
15517                 pipe = 0;
15518
15519                 if (encoder->get_hw_state(encoder, &pipe)) {
15520                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15521                         encoder->base.crtc = &crtc->base;
15522                         encoder->get_config(encoder, crtc->config);
15523                 } else {
15524                         encoder->base.crtc = NULL;
15525                 }
15526
15527                 encoder->connectors_active = false;
15528                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15529                               encoder->base.base.id,
15530                               encoder->base.name,
15531                               encoder->base.crtc ? "enabled" : "disabled",
15532                               pipe_name(pipe));
15533         }
15534
15535         for_each_intel_connector(dev, connector) {
15536                 if (connector->get_hw_state(connector)) {
15537                         connector->base.dpms = DRM_MODE_DPMS_ON;
15538                         connector->encoder->connectors_active = true;
15539                         connector->base.encoder = &connector->encoder->base;
15540                 } else {
15541                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15542                         connector->base.encoder = NULL;
15543                 }
15544                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15545                               connector->base.base.id,
15546                               connector->base.name,
15547                               connector->base.encoder ? "enabled" : "disabled");
15548         }
15549 }
15550
15551 /* Scan out the current hw modeset state,
15552  * and sanitizes it to the current state
15553  */
15554 static void
15555 intel_modeset_setup_hw_state(struct drm_device *dev)
15556 {
15557         struct drm_i915_private *dev_priv = dev->dev_private;
15558         enum pipe pipe;
15559         struct intel_crtc *crtc;
15560         struct intel_encoder *encoder;
15561         int i;
15562
15563         intel_modeset_readout_hw_state(dev);
15564
15565         /* HW state is read out, now we need to sanitize this mess. */
15566         for_each_intel_encoder(dev, encoder) {
15567                 intel_sanitize_encoder(encoder);
15568         }
15569
15570         for_each_pipe(dev_priv, pipe) {
15571                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15572                 intel_sanitize_crtc(crtc);
15573                 intel_dump_pipe_config(crtc, crtc->config,
15574                                        "[setup_hw_state]");
15575         }
15576
15577         intel_modeset_update_connector_atomic_state(dev);
15578
15579         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15580                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15581
15582                 if (!pll->on || pll->active)
15583                         continue;
15584
15585                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15586
15587                 pll->disable(dev_priv, pll);
15588                 pll->on = false;
15589         }
15590
15591         if (IS_VALLEYVIEW(dev))
15592                 vlv_wm_get_hw_state(dev);
15593         else if (IS_GEN9(dev))
15594                 skl_wm_get_hw_state(dev);
15595         else if (HAS_PCH_SPLIT(dev))
15596                 ilk_wm_get_hw_state(dev);
15597
15598         for_each_intel_crtc(dev, crtc) {
15599                 unsigned long put_domains;
15600
15601                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15602                 if (WARN_ON(put_domains))
15603                         modeset_put_power_domains(dev_priv, put_domains);
15604         }
15605         intel_display_set_init_power(dev_priv, false);
15606 }
15607
15608 void intel_display_resume(struct drm_device *dev)
15609 {
15610         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15611         struct intel_connector *conn;
15612         struct intel_plane *plane;
15613         struct drm_crtc *crtc;
15614         int ret;
15615
15616         if (!state)
15617                 return;
15618
15619         state->acquire_ctx = dev->mode_config.acquire_ctx;
15620
15621         /* preserve complete old state, including dpll */
15622         intel_atomic_get_shared_dpll_state(state);
15623
15624         for_each_crtc(dev, crtc) {
15625                 struct drm_crtc_state *crtc_state =
15626                         drm_atomic_get_crtc_state(state, crtc);
15627
15628                 ret = PTR_ERR_OR_ZERO(crtc_state);
15629                 if (ret)
15630                         goto err;
15631
15632                 /* force a restore */
15633                 crtc_state->mode_changed = true;
15634         }
15635
15636         for_each_intel_plane(dev, plane) {
15637                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15638                 if (ret)
15639                         goto err;
15640         }
15641
15642         for_each_intel_connector(dev, conn) {
15643                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15644                 if (ret)
15645                         goto err;
15646         }
15647
15648         intel_modeset_setup_hw_state(dev);
15649
15650         i915_redisable_vga(dev);
15651         ret = intel_set_mode(state);
15652         if (!ret)
15653                 return;
15654
15655 err:
15656         DRM_ERROR("Restoring old state failed with %i\n", ret);
15657         drm_atomic_state_free(state);
15658 }
15659
15660 void intel_modeset_gem_init(struct drm_device *dev)
15661 {
15662         struct drm_i915_private *dev_priv = dev->dev_private;
15663         struct drm_crtc *c;
15664         struct drm_i915_gem_object *obj;
15665         int ret;
15666
15667         mutex_lock(&dev->struct_mutex);
15668         intel_init_gt_powersave(dev);
15669         mutex_unlock(&dev->struct_mutex);
15670
15671         /*
15672          * There may be no VBT; and if the BIOS enabled SSC we can
15673          * just keep using it to avoid unnecessary flicker.  Whereas if the
15674          * BIOS isn't using it, don't assume it will work even if the VBT
15675          * indicates as much.
15676          */
15677         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15678                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15679                                                 DREF_SSC1_ENABLE);
15680
15681         intel_modeset_init_hw(dev);
15682
15683         intel_setup_overlay(dev);
15684
15685         /*
15686          * Make sure any fbs we allocated at startup are properly
15687          * pinned & fenced.  When we do the allocation it's too early
15688          * for this.
15689          */
15690         for_each_crtc(dev, c) {
15691                 obj = intel_fb_obj(c->primary->fb);
15692                 if (obj == NULL)
15693                         continue;
15694
15695                 mutex_lock(&dev->struct_mutex);
15696                 ret = intel_pin_and_fence_fb_obj(c->primary,
15697                                                  c->primary->fb,
15698                                                  c->primary->state,
15699                                                  NULL, NULL);
15700                 mutex_unlock(&dev->struct_mutex);
15701                 if (ret) {
15702                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15703                                   to_intel_crtc(c)->pipe);
15704                         drm_framebuffer_unreference(c->primary->fb);
15705                         c->primary->fb = NULL;
15706                         c->primary->crtc = c->primary->state->crtc = NULL;
15707                         update_state_fb(c->primary);
15708                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15709                 }
15710         }
15711
15712         intel_backlight_register(dev);
15713 }
15714
15715 void intel_connector_unregister(struct intel_connector *intel_connector)
15716 {
15717         struct drm_connector *connector = &intel_connector->base;
15718
15719         intel_panel_destroy_backlight(connector);
15720         drm_connector_unregister(connector);
15721 }
15722
15723 void intel_modeset_cleanup(struct drm_device *dev)
15724 {
15725         struct drm_i915_private *dev_priv = dev->dev_private;
15726         struct drm_connector *connector;
15727
15728         intel_disable_gt_powersave(dev);
15729
15730         intel_backlight_unregister(dev);
15731
15732         /*
15733          * Interrupts and polling as the first thing to avoid creating havoc.
15734          * Too much stuff here (turning of connectors, ...) would
15735          * experience fancy races otherwise.
15736          */
15737         intel_irq_uninstall(dev_priv);
15738
15739         /*
15740          * Due to the hpd irq storm handling the hotplug work can re-arm the
15741          * poll handlers. Hence disable polling after hpd handling is shut down.
15742          */
15743         drm_kms_helper_poll_fini(dev);
15744
15745         intel_unregister_dsm_handler();
15746
15747         intel_fbc_disable(dev_priv);
15748
15749         /* flush any delayed tasks or pending work */
15750         flush_scheduled_work();
15751
15752         /* destroy the backlight and sysfs files before encoders/connectors */
15753         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15754                 struct intel_connector *intel_connector;
15755
15756                 intel_connector = to_intel_connector(connector);
15757                 intel_connector->unregister(intel_connector);
15758         }
15759
15760         drm_mode_config_cleanup(dev);
15761
15762         intel_cleanup_overlay(dev);
15763
15764         mutex_lock(&dev->struct_mutex);
15765         intel_cleanup_gt_powersave(dev);
15766         mutex_unlock(&dev->struct_mutex);
15767 }
15768
15769 /*
15770  * Return which encoder is currently attached for connector.
15771  */
15772 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15773 {
15774         return &intel_attached_encoder(connector)->base;
15775 }
15776
15777 void intel_connector_attach_encoder(struct intel_connector *connector,
15778                                     struct intel_encoder *encoder)
15779 {
15780         connector->encoder = encoder;
15781         drm_mode_connector_attach_encoder(&connector->base,
15782                                           &encoder->base);
15783 }
15784
15785 /*
15786  * set vga decode state - true == enable VGA decode
15787  */
15788 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15789 {
15790         struct drm_i915_private *dev_priv = dev->dev_private;
15791         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15792         u16 gmch_ctrl;
15793
15794         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15795                 DRM_ERROR("failed to read control word\n");
15796                 return -EIO;
15797         }
15798
15799         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15800                 return 0;
15801
15802         if (state)
15803                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15804         else
15805                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15806
15807         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15808                 DRM_ERROR("failed to write control word\n");
15809                 return -EIO;
15810         }
15811
15812         return 0;
15813 }
15814
15815 struct intel_display_error_state {
15816
15817         u32 power_well_driver;
15818
15819         int num_transcoders;
15820
15821         struct intel_cursor_error_state {
15822                 u32 control;
15823                 u32 position;
15824                 u32 base;
15825                 u32 size;
15826         } cursor[I915_MAX_PIPES];
15827
15828         struct intel_pipe_error_state {
15829                 bool power_domain_on;
15830                 u32 source;
15831                 u32 stat;
15832         } pipe[I915_MAX_PIPES];
15833
15834         struct intel_plane_error_state {
15835                 u32 control;
15836                 u32 stride;
15837                 u32 size;
15838                 u32 pos;
15839                 u32 addr;
15840                 u32 surface;
15841                 u32 tile_offset;
15842         } plane[I915_MAX_PIPES];
15843
15844         struct intel_transcoder_error_state {
15845                 bool power_domain_on;
15846                 enum transcoder cpu_transcoder;
15847
15848                 u32 conf;
15849
15850                 u32 htotal;
15851                 u32 hblank;
15852                 u32 hsync;
15853                 u32 vtotal;
15854                 u32 vblank;
15855                 u32 vsync;
15856         } transcoder[4];
15857 };
15858
15859 struct intel_display_error_state *
15860 intel_display_capture_error_state(struct drm_device *dev)
15861 {
15862         struct drm_i915_private *dev_priv = dev->dev_private;
15863         struct intel_display_error_state *error;
15864         int transcoders[] = {
15865                 TRANSCODER_A,
15866                 TRANSCODER_B,
15867                 TRANSCODER_C,
15868                 TRANSCODER_EDP,
15869         };
15870         int i;
15871
15872         if (INTEL_INFO(dev)->num_pipes == 0)
15873                 return NULL;
15874
15875         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15876         if (error == NULL)
15877                 return NULL;
15878
15879         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15880                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15881
15882         for_each_pipe(dev_priv, i) {
15883                 error->pipe[i].power_domain_on =
15884                         __intel_display_power_is_enabled(dev_priv,
15885                                                          POWER_DOMAIN_PIPE(i));
15886                 if (!error->pipe[i].power_domain_on)
15887                         continue;
15888
15889                 error->cursor[i].control = I915_READ(CURCNTR(i));
15890                 error->cursor[i].position = I915_READ(CURPOS(i));
15891                 error->cursor[i].base = I915_READ(CURBASE(i));
15892
15893                 error->plane[i].control = I915_READ(DSPCNTR(i));
15894                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15895                 if (INTEL_INFO(dev)->gen <= 3) {
15896                         error->plane[i].size = I915_READ(DSPSIZE(i));
15897                         error->plane[i].pos = I915_READ(DSPPOS(i));
15898                 }
15899                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15900                         error->plane[i].addr = I915_READ(DSPADDR(i));
15901                 if (INTEL_INFO(dev)->gen >= 4) {
15902                         error->plane[i].surface = I915_READ(DSPSURF(i));
15903                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15904                 }
15905
15906                 error->pipe[i].source = I915_READ(PIPESRC(i));
15907
15908                 if (HAS_GMCH_DISPLAY(dev))
15909                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15910         }
15911
15912         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15913         if (HAS_DDI(dev_priv->dev))
15914                 error->num_transcoders++; /* Account for eDP. */
15915
15916         for (i = 0; i < error->num_transcoders; i++) {
15917                 enum transcoder cpu_transcoder = transcoders[i];
15918
15919                 error->transcoder[i].power_domain_on =
15920                         __intel_display_power_is_enabled(dev_priv,
15921                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15922                 if (!error->transcoder[i].power_domain_on)
15923                         continue;
15924
15925                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15926
15927                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15928                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15929                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15930                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15931                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15932                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15933                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15934         }
15935
15936         return error;
15937 }
15938
15939 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15940
15941 void
15942 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15943                                 struct drm_device *dev,
15944                                 struct intel_display_error_state *error)
15945 {
15946         struct drm_i915_private *dev_priv = dev->dev_private;
15947         int i;
15948
15949         if (!error)
15950                 return;
15951
15952         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15953         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15954                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15955                            error->power_well_driver);
15956         for_each_pipe(dev_priv, i) {
15957                 err_printf(m, "Pipe [%d]:\n", i);
15958                 err_printf(m, "  Power: %s\n",
15959                            error->pipe[i].power_domain_on ? "on" : "off");
15960                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15961                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15962
15963                 err_printf(m, "Plane [%d]:\n", i);
15964                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15965                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15966                 if (INTEL_INFO(dev)->gen <= 3) {
15967                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15968                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15969                 }
15970                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15971                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15972                 if (INTEL_INFO(dev)->gen >= 4) {
15973                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15974                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15975                 }
15976
15977                 err_printf(m, "Cursor [%d]:\n", i);
15978                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15979                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15980                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15981         }
15982
15983         for (i = 0; i < error->num_transcoders; i++) {
15984                 err_printf(m, "CPU transcoder: %c\n",
15985                            transcoder_name(error->transcoder[i].cpu_transcoder));
15986                 err_printf(m, "  Power: %s\n",
15987                            error->transcoder[i].power_domain_on ? "on" : "off");
15988                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15989                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15990                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15991                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15992                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15993                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15994                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15995         }
15996 }
15997
15998 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15999 {
16000         struct intel_crtc *crtc;
16001
16002         for_each_intel_crtc(dev, crtc) {
16003                 struct intel_unpin_work *work;
16004
16005                 spin_lock_irq(&dev->event_lock);
16006
16007                 work = crtc->unpin_work;
16008
16009                 if (work && work->event &&
16010                     work->event->base.file_priv == file) {
16011                         kfree(work->event);
16012                         work->event = NULL;
16013                 }
16014
16015                 spin_unlock_irq(&dev->event_lock);
16016         }
16017 }