drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  50  * allocated we need to hook into the minor for release. */
  51 static int
  52 drm_add_fake_info_node(struct drm_minor *minor,
  53                        struct dentry *ent,
  54                        const void *key)
  55 {
  56         struct drm_info_node *node;
  57
  58         node = kmalloc(sizeof(*node), GFP_KERNEL);
  59         if (node == NULL) {
  60                 debugfs_remove(ent);
  61                 return -ENOMEM;
  62         }
  63
  64         node->minor = minor;
  65         node->dent = ent;
  66         node->info_ent = (void *) key;
  67
  68         mutex_lock(&minor->debugfs_lock);
  69         list_add(&node->list, &minor->debugfs_list);
  70         mutex_unlock(&minor->debugfs_lock);
  71
  72         return 0;
  73 }
  74
  75 static int i915_capabilities(struct seq_file *m, void *data)
  76 {
  77         struct drm_info_node *node = m->private;
  78         struct drm_device *dev = node->minor->dev;
  79         const struct intel_device_info *info = INTEL_INFO(dev);
  80
  81         seq_printf(m, "gen: %d\n", info->gen);
  82         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  83 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  84 #define SEP_SEMICOLON ;
  85         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  86 #undef PRINT_FLAG
  87 #undef SEP_SEMICOLON
  88
  89         return 0;
  90 }
  91
  92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  93 {
  94         if (obj->pin_display)
  95                 return "p";
  96         else
  97                 return " ";
  98 }
  99
 100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 101 {
 102         switch (obj->tiling_mode) {
 103         default:
 104         case I915_TILING_NONE: return " ";
 105         case I915_TILING_X: return "X";
 106         case I915_TILING_Y: return "Y";
 107         }
 108 }
 109
 110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 111 {
 112         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 113 }
 114
 115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 116 {
 117         u64 size = 0;
 118         struct i915_vma *vma;
 119
 120         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 121                 if (i915_is_ggtt(vma->vm) &&
 122                     drm_mm_node_allocated(&vma->node))
 123                         size += vma->node.size;
 124         }
 125
 126         return size;
 127 }
 128
 129 static void
 130 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 131 {
 132         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 133         struct intel_engine_cs *ring;
 134         struct i915_vma *vma;
 135         int pin_count = 0;
 136         int i;
 137
 138         seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
 139                    &obj->base,
 140                    obj->active ? "*" : " ",
 141                    get_pin_flag(obj),
 142                    get_tiling_flag(obj),
 143                    get_global_flag(obj),
 144                    obj->base.size / 1024,
 145                    obj->base.read_domains,
 146                    obj->base.write_domain);
 147         for_each_ring(ring, dev_priv, i)
 148                 seq_printf(m, "%x ",
 149                                 i915_gem_request_get_seqno(obj->last_read_req[i]));
 150         seq_printf(m, "] %x %x%s%s%s",
 151                    i915_gem_request_get_seqno(obj->last_write_req),
 152                    i915_gem_request_get_seqno(obj->last_fenced_req),
 153                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 154                    obj->dirty ? " dirty" : "",
 155                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 156         if (obj->base.name)
 157                 seq_printf(m, " (name: %d)", obj->base.name);
 158         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 159                 if (vma->pin_count > 0)
 160                         pin_count++;
 161         }
 162         seq_printf(m, " (pinned x %d)", pin_count);
 163         if (obj->pin_display)
 164                 seq_printf(m, " (display)");
 165         if (obj->fence_reg != I915_FENCE_REG_NONE)
 166                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 167         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 168                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 169                            i915_is_ggtt(vma->vm) ? "g" : "pp",
 170                            vma->node.start, vma->node.size);
 171                 if (i915_is_ggtt(vma->vm))
 172                         seq_printf(m, ", type: %u)", vma->ggtt_view.type);
 173                 else
 174                         seq_puts(m, ")");
 175         }
 176         if (obj->stolen)
 177                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 178         if (obj->pin_display || obj->fault_mappable) {
 179                 char s[3], *t = s;
 180                 if (obj->pin_display)
 181                         *t++ = 'p';
 182                 if (obj->fault_mappable)
 183                         *t++ = 'f';
 184                 *t = '\0';
 185                 seq_printf(m, " (%s mappable)", s);
 186         }
 187         if (obj->last_write_req != NULL)
 188                 seq_printf(m, " (%s)",
 189                            i915_gem_request_get_ring(obj->last_write_req)->name);
 190         if (obj->frontbuffer_bits)
 191                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 192 }
 193
 194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 195 {
 196         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 197         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 198         seq_putc(m, ' ');
 199 }
 200
 201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 202 {
 203         struct drm_info_node *node = m->private;
 204         uintptr_t list = (uintptr_t) node->info_ent->data;
 205         struct list_head *head;
 206         struct drm_device *dev = node->minor->dev;
 207         struct drm_i915_private *dev_priv = dev->dev_private;
 208         struct i915_address_space *vm = &dev_priv->gtt.base;
 209         struct i915_vma *vma;
 210         u64 total_obj_size, total_gtt_size;
 211         int count, ret;
 212
 213         ret = mutex_lock_interruptible(&dev->struct_mutex);
 214         if (ret)
 215                 return ret;
 216
 217         /* FIXME: the user of this interface might want more than just GGTT */
 218         switch (list) {
 219         case ACTIVE_LIST:
 220                 seq_puts(m, "Active:\n");
 221                 head = &vm->active_list;
 222                 break;
 223         case INACTIVE_LIST:
 224                 seq_puts(m, "Inactive:\n");
 225                 head = &vm->inactive_list;
 226                 break;
 227         default:
 228                 mutex_unlock(&dev->struct_mutex);
 229                 return -EINVAL;
 230         }
 231
 232         total_obj_size = total_gtt_size = count = 0;
 233         list_for_each_entry(vma, head, mm_list) {
 234                 seq_printf(m, "   ");
 235                 describe_obj(m, vma->obj);
 236                 seq_printf(m, "\n");
 237                 total_obj_size += vma->obj->base.size;
 238                 total_gtt_size += vma->node.size;
 239                 count++;
 240         }
 241         mutex_unlock(&dev->struct_mutex);
 242
 243         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 244                    count, total_obj_size, total_gtt_size);
 245         return 0;
 246 }
 247
 248 static int obj_rank_by_stolen(void *priv,
 249                               struct list_head *A, struct list_head *B)
 250 {
 251         struct drm_i915_gem_object *a =
 252                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 253         struct drm_i915_gem_object *b =
 254                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 255
 256         return a->stolen->start - b->stolen->start;
 257 }
 258
 259 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 260 {
 261         struct drm_info_node *node = m->private;
 262         struct drm_device *dev = node->minor->dev;
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         struct drm_i915_gem_object *obj;
 265         u64 total_obj_size, total_gtt_size;
 266         LIST_HEAD(stolen);
 267         int count, ret;
 268
 269         ret = mutex_lock_interruptible(&dev->struct_mutex);
 270         if (ret)
 271                 return ret;
 272
 273         total_obj_size = total_gtt_size = count = 0;
 274         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 275                 if (obj->stolen == NULL)
 276                         continue;
 277
 278                 list_add(&obj->obj_exec_link, &stolen);
 279
 280                 total_obj_size += obj->base.size;
 281                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 282                 count++;
 283         }
 284         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 285                 if (obj->stolen == NULL)
 286                         continue;
 287
 288                 list_add(&obj->obj_exec_link, &stolen);
 289
 290                 total_obj_size += obj->base.size;
 291                 count++;
 292         }
 293         list_sort(NULL, &stolen, obj_rank_by_stolen);
 294         seq_puts(m, "Stolen:\n");
 295         while (!list_empty(&stolen)) {
 296                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 297                 seq_puts(m, "   ");
 298                 describe_obj(m, obj);
 299                 seq_putc(m, '\n');
 300                 list_del_init(&obj->obj_exec_link);
 301         }
 302         mutex_unlock(&dev->struct_mutex);
 303
 304         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 305                    count, total_obj_size, total_gtt_size);
 306         return 0;
 307 }
 308
 309 #define count_objects(list, member) do { \
 310         list_for_each_entry(obj, list, member) { \
 311                 size += i915_gem_obj_total_ggtt_size(obj); \
 312                 ++count; \
 313                 if (obj->map_and_fenceable) { \
 314                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 315                         ++mappable_count; \
 316                 } \
 317         } \
 318 } while (0)
 319
 320 struct file_stats {
 321         struct drm_i915_file_private *file_priv;
 322         unsigned long count;
 323         u64 total, unbound;
 324         u64 global, shared;
 325         u64 active, inactive;
 326 };
 327
 328 static int per_file_stats(int id, void *ptr, void *data)
 329 {
 330         struct drm_i915_gem_object *obj = ptr;
 331         struct file_stats *stats = data;
 332         struct i915_vma *vma;
 333
 334         stats->count++;
 335         stats->total += obj->base.size;
 336
 337         if (obj->base.name || obj->base.dma_buf)
 338                 stats->shared += obj->base.size;
 339
 340         if (USES_FULL_PPGTT(obj->base.dev)) {
 341                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 342                         struct i915_hw_ppgtt *ppgtt;
 343
 344                         if (!drm_mm_node_allocated(&vma->node))
 345                                 continue;
 346
 347                         if (i915_is_ggtt(vma->vm)) {
 348                                 stats->global += obj->base.size;
 349                                 continue;
 350                         }
 351
 352                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 353                         if (ppgtt->file_priv != stats->file_priv)
 354                                 continue;
 355
 356                         if (obj->active) /* XXX per-vma statistic */
 357                                 stats->active += obj->base.size;
 358                         else
 359                                 stats->inactive += obj->base.size;
 360
 361                         return 0;
 362                 }
 363         } else {
 364                 if (i915_gem_obj_ggtt_bound(obj)) {
 365                         stats->global += obj->base.size;
 366                         if (obj->active)
 367                                 stats->active += obj->base.size;
 368                         else
 369                                 stats->inactive += obj->base.size;
 370                         return 0;
 371                 }
 372         }
 373
 374         if (!list_empty(&obj->global_list))
 375                 stats->unbound += obj->base.size;
 376
 377         return 0;
 378 }
 379
 380 #define print_file_stats(m, name, stats) do { \
 381         if (stats.count) \
 382                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 383                            name, \
 384                            stats.count, \
 385                            stats.total, \
 386                            stats.active, \
 387                            stats.inactive, \
 388                            stats.global, \
 389                            stats.shared, \
 390                            stats.unbound); \
 391 } while (0)
 392
 393 static void print_batch_pool_stats(struct seq_file *m,
 394                                    struct drm_i915_private *dev_priv)
 395 {
 396         struct drm_i915_gem_object *obj;
 397         struct file_stats stats;
 398         struct intel_engine_cs *ring;
 399         int i, j;
 400
 401         memset(&stats, 0, sizeof(stats));
 402
 403         for_each_ring(ring, dev_priv, i) {
 404                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 405                         list_for_each_entry(obj,
 406                                             &ring->batch_pool.cache_list[j],
 407                                             batch_pool_link)
 408                                 per_file_stats(0, obj, &stats);
 409                 }
 410         }
 411
 412         print_file_stats(m, "[k]batch pool", stats);
 413 }
 414
 415 #define count_vmas(list, member) do { \
 416         list_for_each_entry(vma, list, member) { \
 417                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 418                 ++count; \
 419                 if (vma->obj->map_and_fenceable) { \
 420                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 421                         ++mappable_count; \
 422                 } \
 423         } \
 424 } while (0)
 425
 426 static int i915_gem_object_info(struct seq_file *m, void* data)
 427 {
 428         struct drm_info_node *node = m->private;
 429         struct drm_device *dev = node->minor->dev;
 430         struct drm_i915_private *dev_priv = dev->dev_private;
 431         u32 count, mappable_count, purgeable_count;
 432         u64 size, mappable_size, purgeable_size;
 433         struct drm_i915_gem_object *obj;
 434         struct i915_address_space *vm = &dev_priv->gtt.base;
 435         struct drm_file *file;
 436         struct i915_vma *vma;
 437         int ret;
 438
 439         ret = mutex_lock_interruptible(&dev->struct_mutex);
 440         if (ret)
 441                 return ret;
 442
 443         seq_printf(m, "%u objects, %zu bytes\n",
 444                    dev_priv->mm.object_count,
 445                    dev_priv->mm.object_memory);
 446
 447         size = count = mappable_size = mappable_count = 0;
 448         count_objects(&dev_priv->mm.bound_list, global_list);
 449         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 450                    count, mappable_count, size, mappable_size);
 451
 452         size = count = mappable_size = mappable_count = 0;
 453         count_vmas(&vm->active_list, mm_list);
 454         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 455                    count, mappable_count, size, mappable_size);
 456
 457         size = count = mappable_size = mappable_count = 0;
 458         count_vmas(&vm->inactive_list, mm_list);
 459         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 460                    count, mappable_count, size, mappable_size);
 461
 462         size = count = purgeable_size = purgeable_count = 0;
 463         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 464                 size += obj->base.size, ++count;
 465                 if (obj->madv == I915_MADV_DONTNEED)
 466                         purgeable_size += obj->base.size, ++purgeable_count;
 467         }
 468         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 469
 470         size = count = mappable_size = mappable_count = 0;
 471         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 472                 if (obj->fault_mappable) {
 473                         size += i915_gem_obj_ggtt_size(obj);
 474                         ++count;
 475                 }
 476                 if (obj->pin_display) {
 477                         mappable_size += i915_gem_obj_ggtt_size(obj);
 478                         ++mappable_count;
 479                 }
 480                 if (obj->madv == I915_MADV_DONTNEED) {
 481                         purgeable_size += obj->base.size;
 482                         ++purgeable_count;
 483                 }
 484         }
 485         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 486                    purgeable_count, purgeable_size);
 487         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 488                    mappable_count, mappable_size);
 489         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 490                    count, size);
 491
 492         seq_printf(m, "%llu [%llu] gtt total\n",
 493                    dev_priv->gtt.base.total,
 494                    (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 495
 496         seq_putc(m, '\n');
 497         print_batch_pool_stats(m, dev_priv);
 498         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 499                 struct file_stats stats;
 500                 struct task_struct *task;
 501
 502                 memset(&stats, 0, sizeof(stats));
 503                 stats.file_priv = file->driver_priv;
 504                 spin_lock(&file->table_lock);
 505                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 506                 spin_unlock(&file->table_lock);
 507                 /*
 508                  * Although we have a valid reference on file->pid, that does
 509                  * not guarantee that the task_struct who called get_pid() is
 510                  * still alive (e.g. get_pid(current) => fork() => exit()).
 511                  * Therefore, we need to protect this ->comm access using RCU.
 512                  */
 513                 rcu_read_lock();
 514                 task = pid_task(file->pid, PIDTYPE_PID);
 515                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 516                 rcu_read_unlock();
 517         }
 518
 519         mutex_unlock(&dev->struct_mutex);
 520
 521         return 0;
 522 }
 523
 524 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 525 {
 526         struct drm_info_node *node = m->private;
 527         struct drm_device *dev = node->minor->dev;
 528         uintptr_t list = (uintptr_t) node->info_ent->data;
 529         struct drm_i915_private *dev_priv = dev->dev_private;
 530         struct drm_i915_gem_object *obj;
 531         u64 total_obj_size, total_gtt_size;
 532         int count, ret;
 533
 534         ret = mutex_lock_interruptible(&dev->struct_mutex);
 535         if (ret)
 536                 return ret;
 537
 538         total_obj_size = total_gtt_size = count = 0;
 539         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 540                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 541                         continue;
 542
 543                 seq_puts(m, "   ");
 544                 describe_obj(m, obj);
 545                 seq_putc(m, '\n');
 546                 total_obj_size += obj->base.size;
 547                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 548                 count++;
 549         }
 550
 551         mutex_unlock(&dev->struct_mutex);
 552
 553         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 554                    count, total_obj_size, total_gtt_size);
 555
 556         return 0;
 557 }
 558
 559 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 560 {
 561         struct drm_info_node *node = m->private;
 562         struct drm_device *dev = node->minor->dev;
 563         struct drm_i915_private *dev_priv = dev->dev_private;
 564         struct intel_crtc *crtc;
 565         int ret;
 566
 567         ret = mutex_lock_interruptible(&dev->struct_mutex);
 568         if (ret)
 569                 return ret;
 570
 571         for_each_intel_crtc(dev, crtc) {
 572                 const char pipe = pipe_name(crtc->pipe);
 573                 const char plane = plane_name(crtc->plane);
 574                 struct intel_unpin_work *work;
 575
 576                 spin_lock_irq(&dev->event_lock);
 577                 work = crtc->unpin_work;
 578                 if (work == NULL) {
 579                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 580                                    pipe, plane);
 581                 } else {
 582                         u32 addr;
 583
 584                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 585                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 586                                            pipe, plane);
 587                         } else {
 588                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 589                                            pipe, plane);
 590                         }
 591                         if (work->flip_queued_req) {
 592                                 struct intel_engine_cs *ring =
 593                                         i915_gem_request_get_ring(work->flip_queued_req);
 594
 595                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 596                                            ring->name,
 597                                            i915_gem_request_get_seqno(work->flip_queued_req),
 598                                            dev_priv->next_seqno,
 599                                            ring->get_seqno(ring, true),
 600                                            i915_gem_request_completed(work->flip_queued_req, true));
 601                         } else
 602                                 seq_printf(m, "Flip not associated with any ring\n");
 603                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 604                                    work->flip_queued_vblank,
 605                                    work->flip_ready_vblank,
 606                                    drm_crtc_vblank_count(&crtc->base));
 607                         if (work->enable_stall_check)
 608                                 seq_puts(m, "Stall check enabled, ");
 609                         else
 610                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 611                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 612
 613                         if (INTEL_INFO(dev)->gen >= 4)
 614                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 615                         else
 616                                 addr = I915_READ(DSPADDR(crtc->plane));
 617                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 618
 619                         if (work->pending_flip_obj) {
 620                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 621                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 622                         }
 623                 }
 624                 spin_unlock_irq(&dev->event_lock);
 625         }
 626
 627         mutex_unlock(&dev->struct_mutex);
 628
 629         return 0;
 630 }
 631
 632 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 633 {
 634         struct drm_info_node *node = m->private;
 635         struct drm_device *dev = node->minor->dev;
 636         struct drm_i915_private *dev_priv = dev->dev_private;
 637         struct drm_i915_gem_object *obj;
 638         struct intel_engine_cs *ring;
 639         int total = 0;
 640         int ret, i, j;
 641
 642         ret = mutex_lock_interruptible(&dev->struct_mutex);
 643         if (ret)
 644                 return ret;
 645
 646         for_each_ring(ring, dev_priv, i) {
 647                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 648                         int count;
 649
 650                         count = 0;
 651                         list_for_each_entry(obj,
 652                                             &ring->batch_pool.cache_list[j],
 653                                             batch_pool_link)
 654                                 count++;
 655                         seq_printf(m, "%s cache[%d]: %d objects\n",
 656                                    ring->name, j, count);
 657
 658                         list_for_each_entry(obj,
 659                                             &ring->batch_pool.cache_list[j],
 660                                             batch_pool_link) {
 661                                 seq_puts(m, "   ");
 662                                 describe_obj(m, obj);
 663                                 seq_putc(m, '\n');
 664                         }
 665
 666                         total += count;
 667                 }
 668         }
 669
 670         seq_printf(m, "total: %d\n", total);
 671
 672         mutex_unlock(&dev->struct_mutex);
 673
 674         return 0;
 675 }
 676
 677 static int i915_gem_request_info(struct seq_file *m, void *data)
 678 {
 679         struct drm_info_node *node = m->private;
 680         struct drm_device *dev = node->minor->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         struct intel_engine_cs *ring;
 683         struct drm_i915_gem_request *req;
 684         int ret, any, i;
 685
 686         ret = mutex_lock_interruptible(&dev->struct_mutex);
 687         if (ret)
 688                 return ret;
 689
 690         any = 0;
 691         for_each_ring(ring, dev_priv, i) {
 692                 int count;
 693
 694                 count = 0;
 695                 list_for_each_entry(req, &ring->request_list, list)
 696                         count++;
 697                 if (count == 0)
 698                         continue;
 699
 700                 seq_printf(m, "%s requests: %d\n", ring->name, count);
 701                 list_for_each_entry(req, &ring->request_list, list) {
 702                         struct task_struct *task;
 703
 704                         rcu_read_lock();
 705                         task = NULL;
 706                         if (req->pid)
 707                                 task = pid_task(req->pid, PIDTYPE_PID);
 708                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 709                                    req->seqno,
 710                                    (int) (jiffies - req->emitted_jiffies),
 711                                    task ? task->comm : "<unknown>",
 712                                    task ? task->pid : -1);
 713                         rcu_read_unlock();
 714                 }
 715
 716                 any++;
 717         }
 718         mutex_unlock(&dev->struct_mutex);
 719
 720         if (any == 0)
 721                 seq_puts(m, "No requests\n");
 722
 723         return 0;
 724 }
 725
 726 static void i915_ring_seqno_info(struct seq_file *m,
 727                                  struct intel_engine_cs *ring)
 728 {
 729         if (ring->get_seqno) {
 730                 seq_printf(m, "Current sequence (%s): %x\n",
 731                            ring->name, ring->get_seqno(ring, false));
 732         }
 733 }
 734
 735 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 736 {
 737         struct drm_info_node *node = m->private;
 738         struct drm_device *dev = node->minor->dev;
 739         struct drm_i915_private *dev_priv = dev->dev_private;
 740         struct intel_engine_cs *ring;
 741         int ret, i;
 742
 743         ret = mutex_lock_interruptible(&dev->struct_mutex);
 744         if (ret)
 745                 return ret;
 746         intel_runtime_pm_get(dev_priv);
 747
 748         for_each_ring(ring, dev_priv, i)
 749                 i915_ring_seqno_info(m, ring);
 750
 751         intel_runtime_pm_put(dev_priv);
 752         mutex_unlock(&dev->struct_mutex);
 753
 754         return 0;
 755 }
 756
 757
 758 static int i915_interrupt_info(struct seq_file *m, void *data)
 759 {
 760         struct drm_info_node *node = m->private;
 761         struct drm_device *dev = node->minor->dev;
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         struct intel_engine_cs *ring;
 764         int ret, i, pipe;
 765
 766         ret = mutex_lock_interruptible(&dev->struct_mutex);
 767         if (ret)
 768                 return ret;
 769         intel_runtime_pm_get(dev_priv);
 770
 771         if (IS_CHERRYVIEW(dev)) {
 772                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 773                            I915_READ(GEN8_MASTER_IRQ));
 774
 775                 seq_printf(m, "Display IER:\t%08x\n",
 776                            I915_READ(VLV_IER));
 777                 seq_printf(m, "Display IIR:\t%08x\n",
 778                            I915_READ(VLV_IIR));
 779                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 780                            I915_READ(VLV_IIR_RW));
 781                 seq_printf(m, "Display IMR:\t%08x\n",
 782                            I915_READ(VLV_IMR));
 783                 for_each_pipe(dev_priv, pipe)
 784                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 785                                    pipe_name(pipe),
 786                                    I915_READ(PIPESTAT(pipe)));
 787
 788                 seq_printf(m, "Port hotplug:\t%08x\n",
 789                            I915_READ(PORT_HOTPLUG_EN));
 790                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 791                            I915_READ(VLV_DPFLIPSTAT));
 792                 seq_printf(m, "DPINVGTT:\t%08x\n",
 793                            I915_READ(DPINVGTT));
 794
 795                 for (i = 0; i < 4; i++) {
 796                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 797                                    i, I915_READ(GEN8_GT_IMR(i)));
 798                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 799                                    i, I915_READ(GEN8_GT_IIR(i)));
 800                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 801                                    i, I915_READ(GEN8_GT_IER(i)));
 802                 }
 803
 804                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 805                            I915_READ(GEN8_PCU_IMR));
 806                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 807                            I915_READ(GEN8_PCU_IIR));
 808                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 809                            I915_READ(GEN8_PCU_IER));
 810         } else if (INTEL_INFO(dev)->gen >= 8) {
 811                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 812                            I915_READ(GEN8_MASTER_IRQ));
 813
 814                 for (i = 0; i < 4; i++) {
 815                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 816                                    i, I915_READ(GEN8_GT_IMR(i)));
 817                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 818                                    i, I915_READ(GEN8_GT_IIR(i)));
 819                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 820                                    i, I915_READ(GEN8_GT_IER(i)));
 821                 }
 822
 823                 for_each_pipe(dev_priv, pipe) {
 824                         if (!intel_display_power_is_enabled(dev_priv,
 825                                                 POWER_DOMAIN_PIPE(pipe))) {
 826                                 seq_printf(m, "Pipe %c power disabled\n",
 827                                            pipe_name(pipe));
 828                                 continue;
 829                         }
 830                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 831                                    pipe_name(pipe),
 832                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 833                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 834                                    pipe_name(pipe),
 835                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 836                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 837                                    pipe_name(pipe),
 838                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 839                 }
 840
 841                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 842                            I915_READ(GEN8_DE_PORT_IMR));
 843                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 844                            I915_READ(GEN8_DE_PORT_IIR));
 845                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 846                            I915_READ(GEN8_DE_PORT_IER));
 847
 848                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 849                            I915_READ(GEN8_DE_MISC_IMR));
 850                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 851                            I915_READ(GEN8_DE_MISC_IIR));
 852                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 853                            I915_READ(GEN8_DE_MISC_IER));
 854
 855                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 856                            I915_READ(GEN8_PCU_IMR));
 857                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 858                            I915_READ(GEN8_PCU_IIR));
 859                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 860                            I915_READ(GEN8_PCU_IER));
 861         } else if (IS_VALLEYVIEW(dev)) {
 862                 seq_printf(m, "Display IER:\t%08x\n",
 863                            I915_READ(VLV_IER));
 864                 seq_printf(m, "Display IIR:\t%08x\n",
 865                            I915_READ(VLV_IIR));
 866                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 867                            I915_READ(VLV_IIR_RW));
 868                 seq_printf(m, "Display IMR:\t%08x\n",
 869                            I915_READ(VLV_IMR));
 870                 for_each_pipe(dev_priv, pipe)
 871                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 872                                    pipe_name(pipe),
 873                                    I915_READ(PIPESTAT(pipe)));
 874
 875                 seq_printf(m, "Master IER:\t%08x\n",
 876                            I915_READ(VLV_MASTER_IER));
 877
 878                 seq_printf(m, "Render IER:\t%08x\n",
 879                            I915_READ(GTIER));
 880                 seq_printf(m, "Render IIR:\t%08x\n",
 881                            I915_READ(GTIIR));
 882                 seq_printf(m, "Render IMR:\t%08x\n",
 883                            I915_READ(GTIMR));
 884
 885                 seq_printf(m, "PM IER:\t\t%08x\n",
 886                            I915_READ(GEN6_PMIER));
 887                 seq_printf(m, "PM IIR:\t\t%08x\n",
 888                            I915_READ(GEN6_PMIIR));
 889                 seq_printf(m, "PM IMR:\t\t%08x\n",
 890                            I915_READ(GEN6_PMIMR));
 891
 892                 seq_printf(m, "Port hotplug:\t%08x\n",
 893                            I915_READ(PORT_HOTPLUG_EN));
 894                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 895                            I915_READ(VLV_DPFLIPSTAT));
 896                 seq_printf(m, "DPINVGTT:\t%08x\n",
 897                            I915_READ(DPINVGTT));
 898
 899         } else if (!HAS_PCH_SPLIT(dev)) {
 900                 seq_printf(m, "Interrupt enable:    %08x\n",
 901                            I915_READ(IER));
 902                 seq_printf(m, "Interrupt identity:  %08x\n",
 903                            I915_READ(IIR));
 904                 seq_printf(m, "Interrupt mask:      %08x\n",
 905                            I915_READ(IMR));
 906                 for_each_pipe(dev_priv, pipe)
 907                         seq_printf(m, "Pipe %c stat:         %08x\n",
 908                                    pipe_name(pipe),
 909                                    I915_READ(PIPESTAT(pipe)));
 910         } else {
 911                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 912                            I915_READ(DEIER));
 913                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 914                            I915_READ(DEIIR));
 915                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 916                            I915_READ(DEIMR));
 917                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 918                            I915_READ(SDEIER));
 919                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 920                            I915_READ(SDEIIR));
 921                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 922                            I915_READ(SDEIMR));
 923                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 924                            I915_READ(GTIER));
 925                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 926                            I915_READ(GTIIR));
 927                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 928                            I915_READ(GTIMR));
 929         }
 930         for_each_ring(ring, dev_priv, i) {
 931                 if (INTEL_INFO(dev)->gen >= 6) {
 932                         seq_printf(m,
 933                                    "Graphics Interrupt mask (%s):       %08x\n",
 934                                    ring->name, I915_READ_IMR(ring));
 935                 }
 936                 i915_ring_seqno_info(m, ring);
 937         }
 938         intel_runtime_pm_put(dev_priv);
 939         mutex_unlock(&dev->struct_mutex);
 940
 941         return 0;
 942 }
 943
 944 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 945 {
 946         struct drm_info_node *node = m->private;
 947         struct drm_device *dev = node->minor->dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         int i, ret;
 950
 951         ret = mutex_lock_interruptible(&dev->struct_mutex);
 952         if (ret)
 953                 return ret;
 954
 955         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 956         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 957                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 958
 959                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 960                            i, dev_priv->fence_regs[i].pin_count);
 961                 if (obj == NULL)
 962                         seq_puts(m, "unused");
 963                 else
 964                         describe_obj(m, obj);
 965                 seq_putc(m, '\n');
 966         }
 967
 968         mutex_unlock(&dev->struct_mutex);
 969         return 0;
 970 }
 971
 972 static int i915_hws_info(struct seq_file *m, void *data)
 973 {
 974         struct drm_info_node *node = m->private;
 975         struct drm_device *dev = node->minor->dev;
 976         struct drm_i915_private *dev_priv = dev->dev_private;
 977         struct intel_engine_cs *ring;
 978         const u32 *hws;
 979         int i;
 980
 981         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 982         hws = ring->status_page.page_addr;
 983         if (hws == NULL)
 984                 return 0;
 985
 986         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 987                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 988                            i * 4,
 989                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 990         }
 991         return 0;
 992 }
 993
 994 static ssize_t
 995 i915_error_state_write(struct file *filp,
 996                        const char __user *ubuf,
 997                        size_t cnt,
 998                        loff_t *ppos)
 999 {
1000         struct i915_error_state_file_priv *error_priv = filp->private_data;
1001         struct drm_device *dev = error_priv->dev;
1002         int ret;
1003
1004         DRM_DEBUG_DRIVER("Resetting error state\n");
1005
1006         ret = mutex_lock_interruptible(&dev->struct_mutex);
1007         if (ret)
1008                 return ret;
1009
1010         i915_destroy_error_state(dev);
1011         mutex_unlock(&dev->struct_mutex);
1012
1013         return cnt;
1014 }
1015
1016 static int i915_error_state_open(struct inode *inode, struct file *file)
1017 {
1018         struct drm_device *dev = inode->i_private;
1019         struct i915_error_state_file_priv *error_priv;
1020
1021         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1022         if (!error_priv)
1023                 return -ENOMEM;
1024
1025         error_priv->dev = dev;
1026
1027         i915_error_state_get(dev, error_priv);
1028
1029         file->private_data = error_priv;
1030
1031         return 0;
1032 }
1033
1034 static int i915_error_state_release(struct inode *inode, struct file *file)
1035 {
1036         struct i915_error_state_file_priv *error_priv = file->private_data;
1037
1038         i915_error_state_put(error_priv);
1039         kfree(error_priv);
1040
1041         return 0;
1042 }
1043
1044 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1045                                      size_t count, loff_t *pos)
1046 {
1047         struct i915_error_state_file_priv *error_priv = file->private_data;
1048         struct drm_i915_error_state_buf error_str;
1049         loff_t tmp_pos = 0;
1050         ssize_t ret_count = 0;
1051         int ret;
1052
1053         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1054         if (ret)
1055                 return ret;
1056
1057         ret = i915_error_state_to_str(&error_str, error_priv);
1058         if (ret)
1059                 goto out;
1060
1061         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1062                                             error_str.buf,
1063                                             error_str.bytes);
1064
1065         if (ret_count < 0)
1066                 ret = ret_count;
1067         else
1068                 *pos = error_str.start + ret_count;
1069 out:
1070         i915_error_state_buf_release(&error_str);
1071         return ret ?: ret_count;
1072 }
1073
1074 static const struct file_operations i915_error_state_fops = {
1075         .owner = THIS_MODULE,
1076         .open = i915_error_state_open,
1077         .read = i915_error_state_read,
1078         .write = i915_error_state_write,
1079         .llseek = default_llseek,
1080         .release = i915_error_state_release,
1081 };
1082
1083 static int
1084 i915_next_seqno_get(void *data, u64 *val)
1085 {
1086         struct drm_device *dev = data;
1087         struct drm_i915_private *dev_priv = dev->dev_private;
1088         int ret;
1089
1090         ret = mutex_lock_interruptible(&dev->struct_mutex);
1091         if (ret)
1092                 return ret;
1093
1094         *val = dev_priv->next_seqno;
1095         mutex_unlock(&dev->struct_mutex);
1096
1097         return 0;
1098 }
1099
1100 static int
1101 i915_next_seqno_set(void *data, u64 val)
1102 {
1103         struct drm_device *dev = data;
1104         int ret;
1105
1106         ret = mutex_lock_interruptible(&dev->struct_mutex);
1107         if (ret)
1108                 return ret;
1109
1110         ret = i915_gem_set_seqno(dev, val);
1111         mutex_unlock(&dev->struct_mutex);
1112
1113         return ret;
1114 }
1115
1116 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1117                         i915_next_seqno_get, i915_next_seqno_set,
1118                         "0x%llx\n");
1119
1120 static int i915_frequency_info(struct seq_file *m, void *unused)
1121 {
1122         struct drm_info_node *node = m->private;
1123         struct drm_device *dev = node->minor->dev;
1124         struct drm_i915_private *dev_priv = dev->dev_private;
1125         int ret = 0;
1126
1127         intel_runtime_pm_get(dev_priv);
1128
1129         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1130
1131         if (IS_GEN5(dev)) {
1132                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1133                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1134
1135                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1136                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1137                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1138                            MEMSTAT_VID_SHIFT);
1139                 seq_printf(m, "Current P-state: %d\n",
1140                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1141         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1142                    IS_BROADWELL(dev) || IS_GEN9(dev)) {
1143                 u32 rp_state_limits;
1144                 u32 gt_perf_status;
1145                 u32 rp_state_cap;
1146                 u32 rpmodectl, rpinclimit, rpdeclimit;
1147                 u32 rpstat, cagf, reqf;
1148                 u32 rpupei, rpcurup, rpprevup;
1149                 u32 rpdownei, rpcurdown, rpprevdown;
1150                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1151                 int max_freq;
1152
1153                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1154                 if (IS_BROXTON(dev)) {
1155                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1156                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1157                 } else {
1158                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1159                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1160                 }
1161
1162                 /* RPSTAT1 is in the GT power well */
1163                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1164                 if (ret)
1165                         goto out;
1166
1167                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1168
1169                 reqf = I915_READ(GEN6_RPNSWREQ);
1170                 if (IS_GEN9(dev))
1171                         reqf >>= 23;
1172                 else {
1173                         reqf &= ~GEN6_TURBO_DISABLE;
1174                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1175                                 reqf >>= 24;
1176                         else
1177                                 reqf >>= 25;
1178                 }
1179                 reqf = intel_gpu_freq(dev_priv, reqf);
1180
1181                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1182                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1183                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1184
1185                 rpstat = I915_READ(GEN6_RPSTAT1);
1186                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1187                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1188                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1189                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1190                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1191                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1192                 if (IS_GEN9(dev))
1193                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1194                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1195                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1196                 else
1197                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1198                 cagf = intel_gpu_freq(dev_priv, cagf);
1199
1200                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1201                 mutex_unlock(&dev->struct_mutex);
1202
1203                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1204                         pm_ier = I915_READ(GEN6_PMIER);
1205                         pm_imr = I915_READ(GEN6_PMIMR);
1206                         pm_isr = I915_READ(GEN6_PMISR);
1207                         pm_iir = I915_READ(GEN6_PMIIR);
1208                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1209                 } else {
1210                         pm_ier = I915_READ(GEN8_GT_IER(2));
1211                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1212                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1213                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1214                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1215                 }
1216                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1217                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1218                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1219                 seq_printf(m, "Render p-state ratio: %d\n",
1220                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1221                 seq_printf(m, "Render p-state VID: %d\n",
1222                            gt_perf_status & 0xff);
1223                 seq_printf(m, "Render p-state limit: %d\n",
1224                            rp_state_limits & 0xff);
1225                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1226                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1227                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1228                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1229                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1230                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1231                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1232                            GEN6_CURICONT_MASK);
1233                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1234                            GEN6_CURBSYTAVG_MASK);
1235                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1236                            GEN6_CURBSYTAVG_MASK);
1237                 seq_printf(m, "Up threshold: %d%%\n",
1238                            dev_priv->rps.up_threshold);
1239
1240                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1241                            GEN6_CURIAVG_MASK);
1242                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1243                            GEN6_CURBSYTAVG_MASK);
1244                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1245                            GEN6_CURBSYTAVG_MASK);
1246                 seq_printf(m, "Down threshold: %d%%\n",
1247                            dev_priv->rps.down_threshold);
1248
1249                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1250                             rp_state_cap >> 16) & 0xff;
1251                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1252                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1253                            intel_gpu_freq(dev_priv, max_freq));
1254
1255                 max_freq = (rp_state_cap & 0xff00) >> 8;
1256                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1257                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1258                            intel_gpu_freq(dev_priv, max_freq));
1259
1260                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1261                             rp_state_cap >> 0) & 0xff;
1262                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1263                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1264                            intel_gpu_freq(dev_priv, max_freq));
1265                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1266                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1267
1268                 seq_printf(m, "Current freq: %d MHz\n",
1269                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1270                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1271                 seq_printf(m, "Idle freq: %d MHz\n",
1272                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1273                 seq_printf(m, "Min freq: %d MHz\n",
1274                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1275                 seq_printf(m, "Max freq: %d MHz\n",
1276                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1277                 seq_printf(m,
1278                            "efficient (RPe) frequency: %d MHz\n",
1279                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1280         } else if (IS_VALLEYVIEW(dev)) {
1281                 u32 freq_sts;
1282
1283                 mutex_lock(&dev_priv->rps.hw_lock);
1284                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1285                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1286                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1287
1288                 seq_printf(m, "actual GPU freq: %d MHz\n",
1289                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1290
1291                 seq_printf(m, "current GPU freq: %d MHz\n",
1292                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1293
1294                 seq_printf(m, "max GPU freq: %d MHz\n",
1295                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1296
1297                 seq_printf(m, "min GPU freq: %d MHz\n",
1298                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1299
1300                 seq_printf(m, "idle GPU freq: %d MHz\n",
1301                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1302
1303                 seq_printf(m,
1304                            "efficient (RPe) frequency: %d MHz\n",
1305                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1306                 mutex_unlock(&dev_priv->rps.hw_lock);
1307         } else {
1308                 seq_puts(m, "no P-state info available\n");
1309         }
1310
1311 out:
1312         intel_runtime_pm_put(dev_priv);
1313         return ret;
1314 }
1315
1316 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1317 {
1318         struct drm_info_node *node = m->private;
1319         struct drm_device *dev = node->minor->dev;
1320         struct drm_i915_private *dev_priv = dev->dev_private;
1321         struct intel_engine_cs *ring;
1322         u64 acthd[I915_NUM_RINGS];
1323         u32 seqno[I915_NUM_RINGS];
1324         int i;
1325
1326         if (!i915.enable_hangcheck) {
1327                 seq_printf(m, "Hangcheck disabled\n");
1328                 return 0;
1329         }
1330
1331         intel_runtime_pm_get(dev_priv);
1332
1333         for_each_ring(ring, dev_priv, i) {
1334                 seqno[i] = ring->get_seqno(ring, false);
1335                 acthd[i] = intel_ring_get_active_head(ring);
1336         }
1337
1338         intel_runtime_pm_put(dev_priv);
1339
1340         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1341                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1342                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1343                                             jiffies));
1344         } else
1345                 seq_printf(m, "Hangcheck inactive\n");
1346
1347         for_each_ring(ring, dev_priv, i) {
1348                 seq_printf(m, "%s:\n", ring->name);
1349                 seq_printf(m, "\tseqno = %x [current %x]\n",
1350                            ring->hangcheck.seqno, seqno[i]);
1351                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1352                            (long long)ring->hangcheck.acthd,
1353                            (long long)acthd[i]);
1354                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1355                            (long long)ring->hangcheck.max_acthd);
1356                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1357                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1358         }
1359
1360         return 0;
1361 }
1362
1363 static int ironlake_drpc_info(struct seq_file *m)
1364 {
1365         struct drm_info_node *node = m->private;
1366         struct drm_device *dev = node->minor->dev;
1367         struct drm_i915_private *dev_priv = dev->dev_private;
1368         u32 rgvmodectl, rstdbyctl;
1369         u16 crstandvid;
1370         int ret;
1371
1372         ret = mutex_lock_interruptible(&dev->struct_mutex);
1373         if (ret)
1374                 return ret;
1375         intel_runtime_pm_get(dev_priv);
1376
1377         rgvmodectl = I915_READ(MEMMODECTL);
1378         rstdbyctl = I915_READ(RSTDBYCTL);
1379         crstandvid = I915_READ16(CRSTANDVID);
1380
1381         intel_runtime_pm_put(dev_priv);
1382         mutex_unlock(&dev->struct_mutex);
1383
1384         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1385         seq_printf(m, "Boost freq: %d\n",
1386                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1387                    MEMMODE_BOOST_FREQ_SHIFT);
1388         seq_printf(m, "HW control enabled: %s\n",
1389                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1390         seq_printf(m, "SW control enabled: %s\n",
1391                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1392         seq_printf(m, "Gated voltage change: %s\n",
1393                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1394         seq_printf(m, "Starting frequency: P%d\n",
1395                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1396         seq_printf(m, "Max P-state: P%d\n",
1397                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1398         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1399         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1400         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1401         seq_printf(m, "Render standby enabled: %s\n",
1402                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1403         seq_puts(m, "Current RS state: ");
1404         switch (rstdbyctl & RSX_STATUS_MASK) {
1405         case RSX_STATUS_ON:
1406                 seq_puts(m, "on\n");
1407                 break;
1408         case RSX_STATUS_RC1:
1409                 seq_puts(m, "RC1\n");
1410                 break;
1411         case RSX_STATUS_RC1E:
1412                 seq_puts(m, "RC1E\n");
1413                 break;
1414         case RSX_STATUS_RS1:
1415                 seq_puts(m, "RS1\n");
1416                 break;
1417         case RSX_STATUS_RS2:
1418                 seq_puts(m, "RS2 (RC6)\n");
1419                 break;
1420         case RSX_STATUS_RS3:
1421                 seq_puts(m, "RC3 (RC6+)\n");
1422                 break;
1423         default:
1424                 seq_puts(m, "unknown\n");
1425                 break;
1426         }
1427
1428         return 0;
1429 }
1430
1431 static int i915_forcewake_domains(struct seq_file *m, void *data)
1432 {
1433         struct drm_info_node *node = m->private;
1434         struct drm_device *dev = node->minor->dev;
1435         struct drm_i915_private *dev_priv = dev->dev_private;
1436         struct intel_uncore_forcewake_domain *fw_domain;
1437         int i;
1438
1439         spin_lock_irq(&dev_priv->uncore.lock);
1440         for_each_fw_domain(fw_domain, dev_priv, i) {
1441                 seq_printf(m, "%s.wake_count = %u\n",
1442                            intel_uncore_forcewake_domain_to_str(i),
1443                            fw_domain->wake_count);
1444         }
1445         spin_unlock_irq(&dev_priv->uncore.lock);
1446
1447         return 0;
1448 }
1449
1450 static int vlv_drpc_info(struct seq_file *m)
1451 {
1452         struct drm_info_node *node = m->private;
1453         struct drm_device *dev = node->minor->dev;
1454         struct drm_i915_private *dev_priv = dev->dev_private;
1455         u32 rpmodectl1, rcctl1, pw_status;
1456
1457         intel_runtime_pm_get(dev_priv);
1458
1459         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1460         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1461         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1462
1463         intel_runtime_pm_put(dev_priv);
1464
1465         seq_printf(m, "Video Turbo Mode: %s\n",
1466                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1467         seq_printf(m, "Turbo enabled: %s\n",
1468                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1469         seq_printf(m, "HW control enabled: %s\n",
1470                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1471         seq_printf(m, "SW control enabled: %s\n",
1472                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1473                           GEN6_RP_MEDIA_SW_MODE));
1474         seq_printf(m, "RC6 Enabled: %s\n",
1475                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1476                                         GEN6_RC_CTL_EI_MODE(1))));
1477         seq_printf(m, "Render Power Well: %s\n",
1478                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1479         seq_printf(m, "Media Power Well: %s\n",
1480                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1481
1482         seq_printf(m, "Render RC6 residency since boot: %u\n",
1483                    I915_READ(VLV_GT_RENDER_RC6));
1484         seq_printf(m, "Media RC6 residency since boot: %u\n",
1485                    I915_READ(VLV_GT_MEDIA_RC6));
1486
1487         return i915_forcewake_domains(m, NULL);
1488 }
1489
1490 static int gen6_drpc_info(struct seq_file *m)
1491 {
1492         struct drm_info_node *node = m->private;
1493         struct drm_device *dev = node->minor->dev;
1494         struct drm_i915_private *dev_priv = dev->dev_private;
1495         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1496         unsigned forcewake_count;
1497         int count = 0, ret;
1498
1499         ret = mutex_lock_interruptible(&dev->struct_mutex);
1500         if (ret)
1501                 return ret;
1502         intel_runtime_pm_get(dev_priv);
1503
1504         spin_lock_irq(&dev_priv->uncore.lock);
1505         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1506         spin_unlock_irq(&dev_priv->uncore.lock);
1507
1508         if (forcewake_count) {
1509                 seq_puts(m, "RC information inaccurate because somebody "
1510                             "holds a forcewake reference \n");
1511         } else {
1512                 /* NB: we cannot use forcewake, else we read the wrong values */
1513                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1514                         udelay(10);
1515                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1516         }
1517
1518         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1519         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1520
1521         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1522         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1523         mutex_unlock(&dev->struct_mutex);
1524         mutex_lock(&dev_priv->rps.hw_lock);
1525         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1526         mutex_unlock(&dev_priv->rps.hw_lock);
1527
1528         intel_runtime_pm_put(dev_priv);
1529
1530         seq_printf(m, "Video Turbo Mode: %s\n",
1531                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1532         seq_printf(m, "HW control enabled: %s\n",
1533                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1534         seq_printf(m, "SW control enabled: %s\n",
1535                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1536                           GEN6_RP_MEDIA_SW_MODE));
1537         seq_printf(m, "RC1e Enabled: %s\n",
1538                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1539         seq_printf(m, "RC6 Enabled: %s\n",
1540                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1541         seq_printf(m, "Deep RC6 Enabled: %s\n",
1542                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1543         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1544                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1545         seq_puts(m, "Current RC state: ");
1546         switch (gt_core_status & GEN6_RCn_MASK) {
1547         case GEN6_RC0:
1548                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1549                         seq_puts(m, "Core Power Down\n");
1550                 else
1551                         seq_puts(m, "on\n");
1552                 break;
1553         case GEN6_RC3:
1554                 seq_puts(m, "RC3\n");
1555                 break;
1556         case GEN6_RC6:
1557                 seq_puts(m, "RC6\n");
1558                 break;
1559         case GEN6_RC7:
1560                 seq_puts(m, "RC7\n");
1561                 break;
1562         default:
1563                 seq_puts(m, "Unknown\n");
1564                 break;
1565         }
1566
1567         seq_printf(m, "Core Power Down: %s\n",
1568                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1569
1570         /* Not exactly sure what this is */
1571         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1572                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1573         seq_printf(m, "RC6 residency since boot: %u\n",
1574                    I915_READ(GEN6_GT_GFX_RC6));
1575         seq_printf(m, "RC6+ residency since boot: %u\n",
1576                    I915_READ(GEN6_GT_GFX_RC6p));
1577         seq_printf(m, "RC6++ residency since boot: %u\n",
1578                    I915_READ(GEN6_GT_GFX_RC6pp));
1579
1580         seq_printf(m, "RC6   voltage: %dmV\n",
1581                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1582         seq_printf(m, "RC6+  voltage: %dmV\n",
1583                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1584         seq_printf(m, "RC6++ voltage: %dmV\n",
1585                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1586         return 0;
1587 }
1588
1589 static int i915_drpc_info(struct seq_file *m, void *unused)
1590 {
1591         struct drm_info_node *node = m->private;
1592         struct drm_device *dev = node->minor->dev;
1593
1594         if (IS_VALLEYVIEW(dev))
1595                 return vlv_drpc_info(m);
1596         else if (INTEL_INFO(dev)->gen >= 6)
1597                 return gen6_drpc_info(m);
1598         else
1599                 return ironlake_drpc_info(m);
1600 }
1601
1602 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1603 {
1604         struct drm_info_node *node = m->private;
1605         struct drm_device *dev = node->minor->dev;
1606         struct drm_i915_private *dev_priv = dev->dev_private;
1607
1608         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1609                    dev_priv->fb_tracking.busy_bits);
1610
1611         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1612                    dev_priv->fb_tracking.flip_bits);
1613
1614         return 0;
1615 }
1616
1617 static int i915_fbc_status(struct seq_file *m, void *unused)
1618 {
1619         struct drm_info_node *node = m->private;
1620         struct drm_device *dev = node->minor->dev;
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622
1623         if (!HAS_FBC(dev)) {
1624                 seq_puts(m, "FBC unsupported on this chipset\n");
1625                 return 0;
1626         }
1627
1628         intel_runtime_pm_get(dev_priv);
1629         mutex_lock(&dev_priv->fbc.lock);
1630
1631         if (intel_fbc_enabled(dev_priv))
1632                 seq_puts(m, "FBC enabled\n");
1633         else
1634                 seq_printf(m, "FBC disabled: %s\n",
1635                           intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
1636
1637         if (INTEL_INFO(dev_priv)->gen >= 7)
1638                 seq_printf(m, "Compressing: %s\n",
1639                            yesno(I915_READ(FBC_STATUS2) &
1640                                  FBC_COMPRESSION_MASK));
1641
1642         mutex_unlock(&dev_priv->fbc.lock);
1643         intel_runtime_pm_put(dev_priv);
1644
1645         return 0;
1646 }
1647
1648 static int i915_fbc_fc_get(void *data, u64 *val)
1649 {
1650         struct drm_device *dev = data;
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652
1653         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1654                 return -ENODEV;
1655
1656         *val = dev_priv->fbc.false_color;
1657
1658         return 0;
1659 }
1660
1661 static int i915_fbc_fc_set(void *data, u64 val)
1662 {
1663         struct drm_device *dev = data;
1664         struct drm_i915_private *dev_priv = dev->dev_private;
1665         u32 reg;
1666
1667         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1668                 return -ENODEV;
1669
1670         mutex_lock(&dev_priv->fbc.lock);
1671
1672         reg = I915_READ(ILK_DPFC_CONTROL);
1673         dev_priv->fbc.false_color = val;
1674
1675         I915_WRITE(ILK_DPFC_CONTROL, val ?
1676                    (reg | FBC_CTL_FALSE_COLOR) :
1677                    (reg & ~FBC_CTL_FALSE_COLOR));
1678
1679         mutex_unlock(&dev_priv->fbc.lock);
1680         return 0;
1681 }
1682
1683 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1684                         i915_fbc_fc_get, i915_fbc_fc_set,
1685                         "%llu\n");
1686
1687 static int i915_ips_status(struct seq_file *m, void *unused)
1688 {
1689         struct drm_info_node *node = m->private;
1690         struct drm_device *dev = node->minor->dev;
1691         struct drm_i915_private *dev_priv = dev->dev_private;
1692
1693         if (!HAS_IPS(dev)) {
1694                 seq_puts(m, "not supported\n");
1695                 return 0;
1696         }
1697
1698         intel_runtime_pm_get(dev_priv);
1699
1700         seq_printf(m, "Enabled by kernel parameter: %s\n",
1701                    yesno(i915.enable_ips));
1702
1703         if (INTEL_INFO(dev)->gen >= 8) {
1704                 seq_puts(m, "Currently: unknown\n");
1705         } else {
1706                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1707                         seq_puts(m, "Currently: enabled\n");
1708                 else
1709                         seq_puts(m, "Currently: disabled\n");
1710         }
1711
1712         intel_runtime_pm_put(dev_priv);
1713
1714         return 0;
1715 }
1716
1717 static int i915_sr_status(struct seq_file *m, void *unused)
1718 {
1719         struct drm_info_node *node = m->private;
1720         struct drm_device *dev = node->minor->dev;
1721         struct drm_i915_private *dev_priv = dev->dev_private;
1722         bool sr_enabled = false;
1723
1724         intel_runtime_pm_get(dev_priv);
1725
1726         if (HAS_PCH_SPLIT(dev))
1727                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1728         else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1729                  IS_I945G(dev) || IS_I945GM(dev))
1730                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1731         else if (IS_I915GM(dev))
1732                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1733         else if (IS_PINEVIEW(dev))
1734                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1735         else if (IS_VALLEYVIEW(dev))
1736                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1737
1738         intel_runtime_pm_put(dev_priv);
1739
1740         seq_printf(m, "self-refresh: %s\n",
1741                    sr_enabled ? "enabled" : "disabled");
1742
1743         return 0;
1744 }
1745
1746 static int i915_emon_status(struct seq_file *m, void *unused)
1747 {
1748         struct drm_info_node *node = m->private;
1749         struct drm_device *dev = node->minor->dev;
1750         struct drm_i915_private *dev_priv = dev->dev_private;
1751         unsigned long temp, chipset, gfx;
1752         int ret;
1753
1754         if (!IS_GEN5(dev))
1755                 return -ENODEV;
1756
1757         ret = mutex_lock_interruptible(&dev->struct_mutex);
1758         if (ret)
1759                 return ret;
1760
1761         temp = i915_mch_val(dev_priv);
1762         chipset = i915_chipset_val(dev_priv);
1763         gfx = i915_gfx_val(dev_priv);
1764         mutex_unlock(&dev->struct_mutex);
1765
1766         seq_printf(m, "GMCH temp: %ld\n", temp);
1767         seq_printf(m, "Chipset power: %ld\n", chipset);
1768         seq_printf(m, "GFX power: %ld\n", gfx);
1769         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1770
1771         return 0;
1772 }
1773
1774 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1775 {
1776         struct drm_info_node *node = m->private;
1777         struct drm_device *dev = node->minor->dev;
1778         struct drm_i915_private *dev_priv = dev->dev_private;
1779         int ret = 0;
1780         int gpu_freq, ia_freq;
1781         unsigned int max_gpu_freq, min_gpu_freq;
1782
1783         if (!HAS_CORE_RING_FREQ(dev)) {
1784                 seq_puts(m, "unsupported on this chipset\n");
1785                 return 0;
1786         }
1787
1788         intel_runtime_pm_get(dev_priv);
1789
1790         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1791
1792         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1793         if (ret)
1794                 goto out;
1795
1796         if (IS_SKYLAKE(dev)) {
1797                 /* Convert GT frequency to 50 HZ units */
1798                 min_gpu_freq =
1799                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1800                 max_gpu_freq =
1801                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1802         } else {
1803                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1804                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1805         }
1806
1807         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1808
1809         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1810                 ia_freq = gpu_freq;
1811                 sandybridge_pcode_read(dev_priv,
1812                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1813                                        &ia_freq);
1814                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1815                            intel_gpu_freq(dev_priv, (gpu_freq *
1816                                 (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
1817                            ((ia_freq >> 0) & 0xff) * 100,
1818                            ((ia_freq >> 8) & 0xff) * 100);
1819         }
1820
1821         mutex_unlock(&dev_priv->rps.hw_lock);
1822
1823 out:
1824         intel_runtime_pm_put(dev_priv);
1825         return ret;
1826 }
1827
1828 static int i915_opregion(struct seq_file *m, void *unused)
1829 {
1830         struct drm_info_node *node = m->private;
1831         struct drm_device *dev = node->minor->dev;
1832         struct drm_i915_private *dev_priv = dev->dev_private;
1833         struct intel_opregion *opregion = &dev_priv->opregion;
1834         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1835         int ret;
1836
1837         if (data == NULL)
1838                 return -ENOMEM;
1839
1840         ret = mutex_lock_interruptible(&dev->struct_mutex);
1841         if (ret)
1842                 goto out;
1843
1844         if (opregion->header) {
1845                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1846                 seq_write(m, data, OPREGION_SIZE);
1847         }
1848
1849         mutex_unlock(&dev->struct_mutex);
1850
1851 out:
1852         kfree(data);
1853         return 0;
1854 }
1855
1856 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1857 {
1858         struct drm_info_node *node = m->private;
1859         struct drm_device *dev = node->minor->dev;
1860         struct intel_fbdev *ifbdev = NULL;
1861         struct intel_framebuffer *fb;
1862         struct drm_framebuffer *drm_fb;
1863
1864 #ifdef CONFIG_DRM_FBDEV_EMULATION
1865         struct drm_i915_private *dev_priv = dev->dev_private;
1866
1867         ifbdev = dev_priv->fbdev;
1868         fb = to_intel_framebuffer(ifbdev->helper.fb);
1869
1870         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1871                    fb->base.width,
1872                    fb->base.height,
1873                    fb->base.depth,
1874                    fb->base.bits_per_pixel,
1875                    fb->base.modifier[0],
1876                    atomic_read(&fb->base.refcount.refcount));
1877         describe_obj(m, fb->obj);
1878         seq_putc(m, '\n');
1879 #endif
1880
1881         mutex_lock(&dev->mode_config.fb_lock);
1882         drm_for_each_fb(drm_fb, dev) {
1883                 fb = to_intel_framebuffer(drm_fb);
1884                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1885                         continue;
1886
1887                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1888                            fb->base.width,
1889                            fb->base.height,
1890                            fb->base.depth,
1891                            fb->base.bits_per_pixel,
1892                            fb->base.modifier[0],
1893                            atomic_read(&fb->base.refcount.refcount));
1894                 describe_obj(m, fb->obj);
1895                 seq_putc(m, '\n');
1896         }
1897         mutex_unlock(&dev->mode_config.fb_lock);
1898
1899         return 0;
1900 }
1901
1902 static void describe_ctx_ringbuf(struct seq_file *m,
1903                                  struct intel_ringbuffer *ringbuf)
1904 {
1905         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1906                    ringbuf->space, ringbuf->head, ringbuf->tail,
1907                    ringbuf->last_retired_head);
1908 }
1909
1910 static int i915_context_status(struct seq_file *m, void *unused)
1911 {
1912         struct drm_info_node *node = m->private;
1913         struct drm_device *dev = node->minor->dev;
1914         struct drm_i915_private *dev_priv = dev->dev_private;
1915         struct intel_engine_cs *ring;
1916         struct intel_context *ctx;
1917         int ret, i;
1918
1919         ret = mutex_lock_interruptible(&dev->struct_mutex);
1920         if (ret)
1921                 return ret;
1922
1923         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1924                 if (!i915.enable_execlists &&
1925                     ctx->legacy_hw_ctx.rcs_state == NULL)
1926                         continue;
1927
1928                 seq_puts(m, "HW context ");
1929                 describe_ctx(m, ctx);
1930                 for_each_ring(ring, dev_priv, i) {
1931                         if (ring->default_context == ctx)
1932                                 seq_printf(m, "(default context %s) ",
1933                                            ring->name);
1934                 }
1935
1936                 if (i915.enable_execlists) {
1937                         seq_putc(m, '\n');
1938                         for_each_ring(ring, dev_priv, i) {
1939                                 struct drm_i915_gem_object *ctx_obj =
1940                                         ctx->engine[i].state;
1941                                 struct intel_ringbuffer *ringbuf =
1942                                         ctx->engine[i].ringbuf;
1943
1944                                 seq_printf(m, "%s: ", ring->name);
1945                                 if (ctx_obj)
1946                                         describe_obj(m, ctx_obj);
1947                                 if (ringbuf)
1948                                         describe_ctx_ringbuf(m, ringbuf);
1949                                 seq_putc(m, '\n');
1950                         }
1951                 } else {
1952                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1953                 }
1954
1955                 seq_putc(m, '\n');
1956         }
1957
1958         mutex_unlock(&dev->struct_mutex);
1959
1960         return 0;
1961 }
1962
1963 static void i915_dump_lrc_obj(struct seq_file *m,
1964                               struct intel_engine_cs *ring,
1965                               struct drm_i915_gem_object *ctx_obj)
1966 {
1967         struct page *page;
1968         uint32_t *reg_state;
1969         int j;
1970         unsigned long ggtt_offset = 0;
1971
1972         if (ctx_obj == NULL) {
1973                 seq_printf(m, "Context on %s with no gem object\n",
1974                            ring->name);
1975                 return;
1976         }
1977
1978         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1979                    intel_execlists_ctx_id(ctx_obj));
1980
1981         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1982                 seq_puts(m, "\tNot bound in GGTT\n");
1983         else
1984                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1985
1986         if (i915_gem_object_get_pages(ctx_obj)) {
1987                 seq_puts(m, "\tFailed to get pages for context object\n");
1988                 return;
1989         }
1990
1991         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
1992         if (!WARN_ON(page == NULL)) {
1993                 reg_state = kmap_atomic(page);
1994
1995                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1996                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1997                                    ggtt_offset + 4096 + (j * 4),
1998                                    reg_state[j], reg_state[j + 1],
1999                                    reg_state[j + 2], reg_state[j + 3]);
2000                 }
2001                 kunmap_atomic(reg_state);
2002         }
2003
2004         seq_putc(m, '\n');
2005 }
2006
2007 static int i915_dump_lrc(struct seq_file *m, void *unused)
2008 {
2009         struct drm_info_node *node = (struct drm_info_node *) m->private;
2010         struct drm_device *dev = node->minor->dev;
2011         struct drm_i915_private *dev_priv = dev->dev_private;
2012         struct intel_engine_cs *ring;
2013         struct intel_context *ctx;
2014         int ret, i;
2015
2016         if (!i915.enable_execlists) {
2017                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2018                 return 0;
2019         }
2020
2021         ret = mutex_lock_interruptible(&dev->struct_mutex);
2022         if (ret)
2023                 return ret;
2024
2025         list_for_each_entry(ctx, &dev_priv->context_list, link) {
2026                 for_each_ring(ring, dev_priv, i) {
2027                         if (ring->default_context != ctx)
2028                                 i915_dump_lrc_obj(m, ring,
2029                                                   ctx->engine[i].state);
2030                 }
2031         }
2032
2033         mutex_unlock(&dev->struct_mutex);
2034
2035         return 0;
2036 }
2037
2038 static int i915_execlists(struct seq_file *m, void *data)
2039 {
2040         struct drm_info_node *node = (struct drm_info_node *)m->private;
2041         struct drm_device *dev = node->minor->dev;
2042         struct drm_i915_private *dev_priv = dev->dev_private;
2043         struct intel_engine_cs *ring;
2044         u32 status_pointer;
2045         u8 read_pointer;
2046         u8 write_pointer;
2047         u32 status;
2048         u32 ctx_id;
2049         struct list_head *cursor;
2050         int ring_id, i;
2051         int ret;
2052
2053         if (!i915.enable_execlists) {
2054                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2055                 return 0;
2056         }
2057
2058         ret = mutex_lock_interruptible(&dev->struct_mutex);
2059         if (ret)
2060                 return ret;
2061
2062         intel_runtime_pm_get(dev_priv);
2063
2064         for_each_ring(ring, dev_priv, ring_id) {
2065                 struct drm_i915_gem_request *head_req = NULL;
2066                 int count = 0;
2067                 unsigned long flags;
2068
2069                 seq_printf(m, "%s\n", ring->name);
2070
2071                 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2072                 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
2073                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2074                            status, ctx_id);
2075
2076                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2077                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2078
2079                 read_pointer = ring->next_context_status_buffer;
2080                 write_pointer = status_pointer & 0x07;
2081                 if (read_pointer > write_pointer)
2082                         write_pointer += 6;
2083                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2084                            read_pointer, write_pointer);
2085
2086                 for (i = 0; i < 6; i++) {
2087                         status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2088                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
2089
2090                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2091                                    i, status, ctx_id);
2092                 }
2093
2094                 spin_lock_irqsave(&ring->execlist_lock, flags);
2095                 list_for_each(cursor, &ring->execlist_queue)
2096                         count++;
2097                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2098                                 struct drm_i915_gem_request, execlist_link);
2099                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2100
2101                 seq_printf(m, "\t%d requests in queue\n", count);
2102                 if (head_req) {
2103                         struct drm_i915_gem_object *ctx_obj;
2104
2105                         ctx_obj = head_req->ctx->engine[ring_id].state;
2106                         seq_printf(m, "\tHead request id: %u\n",
2107                                    intel_execlists_ctx_id(ctx_obj));
2108                         seq_printf(m, "\tHead request tail: %u\n",
2109                                    head_req->tail);
2110                 }
2111
2112                 seq_putc(m, '\n');
2113         }
2114
2115         intel_runtime_pm_put(dev_priv);
2116         mutex_unlock(&dev->struct_mutex);
2117
2118         return 0;
2119 }
2120
2121 static const char *swizzle_string(unsigned swizzle)
2122 {
2123         switch (swizzle) {
2124         case I915_BIT_6_SWIZZLE_NONE:
2125                 return "none";
2126         case I915_BIT_6_SWIZZLE_9:
2127                 return "bit9";
2128         case I915_BIT_6_SWIZZLE_9_10:
2129                 return "bit9/bit10";
2130         case I915_BIT_6_SWIZZLE_9_11:
2131                 return "bit9/bit11";
2132         case I915_BIT_6_SWIZZLE_9_10_11:
2133                 return "bit9/bit10/bit11";
2134         case I915_BIT_6_SWIZZLE_9_17:
2135                 return "bit9/bit17";
2136         case I915_BIT_6_SWIZZLE_9_10_17:
2137                 return "bit9/bit10/bit17";
2138         case I915_BIT_6_SWIZZLE_UNKNOWN:
2139                 return "unknown";
2140         }
2141
2142         return "bug";
2143 }
2144
2145 static int i915_swizzle_info(struct seq_file *m, void *data)
2146 {
2147         struct drm_info_node *node = m->private;
2148         struct drm_device *dev = node->minor->dev;
2149         struct drm_i915_private *dev_priv = dev->dev_private;
2150         int ret;
2151
2152         ret = mutex_lock_interruptible(&dev->struct_mutex);
2153         if (ret)
2154                 return ret;
2155         intel_runtime_pm_get(dev_priv);
2156
2157         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2158                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2159         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2160                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2161
2162         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2163                 seq_printf(m, "DDC = 0x%08x\n",
2164                            I915_READ(DCC));
2165                 seq_printf(m, "DDC2 = 0x%08x\n",
2166                            I915_READ(DCC2));
2167                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2168                            I915_READ16(C0DRB3));
2169                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2170                            I915_READ16(C1DRB3));
2171         } else if (INTEL_INFO(dev)->gen >= 6) {
2172                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2173                            I915_READ(MAD_DIMM_C0));
2174                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2175                            I915_READ(MAD_DIMM_C1));
2176                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2177                            I915_READ(MAD_DIMM_C2));
2178                 seq_printf(m, "TILECTL = 0x%08x\n",
2179                            I915_READ(TILECTL));
2180                 if (INTEL_INFO(dev)->gen >= 8)
2181                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2182                                    I915_READ(GAMTARBMODE));
2183                 else
2184                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2185                                    I915_READ(ARB_MODE));
2186                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2187                            I915_READ(DISP_ARB_CTL));
2188         }
2189
2190         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2191                 seq_puts(m, "L-shaped memory detected\n");
2192
2193         intel_runtime_pm_put(dev_priv);
2194         mutex_unlock(&dev->struct_mutex);
2195
2196         return 0;
2197 }
2198
2199 static int per_file_ctx(int id, void *ptr, void *data)
2200 {
2201         struct intel_context *ctx = ptr;
2202         struct seq_file *m = data;
2203         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2204
2205         if (!ppgtt) {
2206                 seq_printf(m, "  no ppgtt for context %d\n",
2207                            ctx->user_handle);
2208                 return 0;
2209         }
2210
2211         if (i915_gem_context_is_default(ctx))
2212                 seq_puts(m, "  default context:\n");
2213         else
2214                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2215         ppgtt->debug_dump(ppgtt, m);
2216
2217         return 0;
2218 }
2219
2220 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2221 {
2222         struct drm_i915_private *dev_priv = dev->dev_private;
2223         struct intel_engine_cs *ring;
2224         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2225         int unused, i;
2226
2227         if (!ppgtt)
2228                 return;
2229
2230         for_each_ring(ring, dev_priv, unused) {
2231                 seq_printf(m, "%s\n", ring->name);
2232                 for (i = 0; i < 4; i++) {
2233                         u32 offset = 0x270 + i * 8;
2234                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2235                         pdp <<= 32;
2236                         pdp |= I915_READ(ring->mmio_base + offset);
2237                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2238                 }
2239         }
2240 }
2241
2242 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2243 {
2244         struct drm_i915_private *dev_priv = dev->dev_private;
2245         struct intel_engine_cs *ring;
2246         int i;
2247
2248         if (INTEL_INFO(dev)->gen == 6)
2249                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2250
2251         for_each_ring(ring, dev_priv, i) {
2252                 seq_printf(m, "%s\n", ring->name);
2253                 if (INTEL_INFO(dev)->gen == 7)
2254                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2255                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2256                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2257                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2258         }
2259         if (dev_priv->mm.aliasing_ppgtt) {
2260                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2261
2262                 seq_puts(m, "aliasing PPGTT:\n");
2263                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2264
2265                 ppgtt->debug_dump(ppgtt, m);
2266         }
2267
2268         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2269 }
2270
2271 static int i915_ppgtt_info(struct seq_file *m, void *data)
2272 {
2273         struct drm_info_node *node = m->private;
2274         struct drm_device *dev = node->minor->dev;
2275         struct drm_i915_private *dev_priv = dev->dev_private;
2276         struct drm_file *file;
2277
2278         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2279         if (ret)
2280                 return ret;
2281         intel_runtime_pm_get(dev_priv);
2282
2283         if (INTEL_INFO(dev)->gen >= 8)
2284                 gen8_ppgtt_info(m, dev);
2285         else if (INTEL_INFO(dev)->gen >= 6)
2286                 gen6_ppgtt_info(m, dev);
2287
2288         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2289                 struct drm_i915_file_private *file_priv = file->driver_priv;
2290                 struct task_struct *task;
2291
2292                 task = get_pid_task(file->pid, PIDTYPE_PID);
2293                 if (!task)
2294                         return -ESRCH;
2295                 seq_printf(m, "\nproc: %s\n", task->comm);
2296                 put_task_struct(task);
2297                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2298                              (void *)(unsigned long)m);
2299         }
2300
2301         intel_runtime_pm_put(dev_priv);
2302         mutex_unlock(&dev->struct_mutex);
2303
2304         return 0;
2305 }
2306
2307 static int count_irq_waiters(struct drm_i915_private *i915)
2308 {
2309         struct intel_engine_cs *ring;
2310         int count = 0;
2311         int i;
2312
2313         for_each_ring(ring, i915, i)
2314                 count += ring->irq_refcount;
2315
2316         return count;
2317 }
2318
2319 static int i915_rps_boost_info(struct seq_file *m, void *data)
2320 {
2321         struct drm_info_node *node = m->private;
2322         struct drm_device *dev = node->minor->dev;
2323         struct drm_i915_private *dev_priv = dev->dev_private;
2324         struct drm_file *file;
2325
2326         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2327         seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2328         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2329         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2330                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2331                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2332                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2333                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2334                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2335         spin_lock(&dev_priv->rps.client_lock);
2336         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2337                 struct drm_i915_file_private *file_priv = file->driver_priv;
2338                 struct task_struct *task;
2339
2340                 rcu_read_lock();
2341                 task = pid_task(file->pid, PIDTYPE_PID);
2342                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2343                            task ? task->comm : "<unknown>",
2344                            task ? task->pid : -1,
2345                            file_priv->rps.boosts,
2346                            list_empty(&file_priv->rps.link) ? "" : ", active");
2347                 rcu_read_unlock();
2348         }
2349         seq_printf(m, "Semaphore boosts: %d%s\n",
2350                    dev_priv->rps.semaphores.boosts,
2351                    list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2352         seq_printf(m, "MMIO flip boosts: %d%s\n",
2353                    dev_priv->rps.mmioflips.boosts,
2354                    list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2355         seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2356         spin_unlock(&dev_priv->rps.client_lock);
2357
2358         return 0;
2359 }
2360
2361 static int i915_llc(struct seq_file *m, void *data)
2362 {
2363         struct drm_info_node *node = m->private;
2364         struct drm_device *dev = node->minor->dev;
2365         struct drm_i915_private *dev_priv = dev->dev_private;
2366
2367         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2368         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2369         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2370
2371         return 0;
2372 }
2373
2374 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2375 {
2376         struct drm_info_node *node = m->private;
2377         struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2378         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2379         u32 tmp, i;
2380
2381         if (!HAS_GUC_UCODE(dev_priv->dev))
2382                 return 0;
2383
2384         seq_printf(m, "GuC firmware status:\n");
2385         seq_printf(m, "\tpath: %s\n",
2386                 guc_fw->guc_fw_path);
2387         seq_printf(m, "\tfetch: %s\n",
2388                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2389         seq_printf(m, "\tload: %s\n",
2390                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2391         seq_printf(m, "\tversion wanted: %d.%d\n",
2392                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2393         seq_printf(m, "\tversion found: %d.%d\n",
2394                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2395
2396         tmp = I915_READ(GUC_STATUS);
2397
2398         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2399         seq_printf(m, "\tBootrom status = 0x%x\n",
2400                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2401         seq_printf(m, "\tuKernel status = 0x%x\n",
2402                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2403         seq_printf(m, "\tMIA Core status = 0x%x\n",
2404                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2405         seq_puts(m, "\nScratch registers:\n");
2406         for (i = 0; i < 16; i++)
2407                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2408
2409         return 0;
2410 }
2411
2412 static void i915_guc_client_info(struct seq_file *m,
2413                                  struct drm_i915_private *dev_priv,
2414                                  struct i915_guc_client *client)
2415 {
2416         struct intel_engine_cs *ring;
2417         uint64_t tot = 0;
2418         uint32_t i;
2419
2420         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2421                 client->priority, client->ctx_index, client->proc_desc_offset);
2422         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2423                 client->doorbell_id, client->doorbell_offset, client->cookie);
2424         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2425                 client->wq_size, client->wq_offset, client->wq_tail);
2426
2427         seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2428         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2429         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2430
2431         for_each_ring(ring, dev_priv, i) {
2432                 seq_printf(m, "\tSubmissions: %llu %s\n",
2433                                 client->submissions[i],
2434                                 ring->name);
2435                 tot += client->submissions[i];
2436         }
2437         seq_printf(m, "\tTotal: %llu\n", tot);
2438 }
2439
2440 static int i915_guc_info(struct seq_file *m, void *data)
2441 {
2442         struct drm_info_node *node = m->private;
2443         struct drm_device *dev = node->minor->dev;
2444         struct drm_i915_private *dev_priv = dev->dev_private;
2445         struct intel_guc guc;
2446         struct i915_guc_client client = {};
2447         struct intel_engine_cs *ring;
2448         enum intel_ring_id i;
2449         u64 total = 0;
2450
2451         if (!HAS_GUC_SCHED(dev_priv->dev))
2452                 return 0;
2453
2454         /* Take a local copy of the GuC data, so we can dump it at leisure */
2455         spin_lock(&dev_priv->guc.host2guc_lock);
2456         guc = dev_priv->guc;
2457         if (guc.execbuf_client) {
2458                 spin_lock(&guc.execbuf_client->wq_lock);
2459                 client = *guc.execbuf_client;
2460                 spin_unlock(&guc.execbuf_client->wq_lock);
2461         }
2462         spin_unlock(&dev_priv->guc.host2guc_lock);
2463
2464         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2465         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2466         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2467         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2468         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2469
2470         seq_printf(m, "\nGuC submissions:\n");
2471         for_each_ring(ring, dev_priv, i) {
2472                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2473                         ring->name, guc.submissions[i],
2474                         guc.last_seqno[i], guc.last_seqno[i]);
2475                 total += guc.submissions[i];
2476         }
2477         seq_printf(m, "\t%s: %llu\n", "Total", total);
2478
2479         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2480         i915_guc_client_info(m, dev_priv, &client);
2481
2482         /* Add more as required ... */
2483
2484         return 0;
2485 }
2486
2487 static int i915_guc_log_dump(struct seq_file *m, void *data)
2488 {
2489         struct drm_info_node *node = m->private;
2490         struct drm_device *dev = node->minor->dev;
2491         struct drm_i915_private *dev_priv = dev->dev_private;
2492         struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2493         u32 *log;
2494         int i = 0, pg;
2495
2496         if (!log_obj)
2497                 return 0;
2498
2499         for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2500                 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2501
2502                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2503                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2504                                    *(log + i), *(log + i + 1),
2505                                    *(log + i + 2), *(log + i + 3));
2506
2507                 kunmap_atomic(log);
2508         }
2509
2510         seq_putc(m, '\n');
2511
2512         return 0;
2513 }
2514
2515 static int i915_edp_psr_status(struct seq_file *m, void *data)
2516 {
2517         struct drm_info_node *node = m->private;
2518         struct drm_device *dev = node->minor->dev;
2519         struct drm_i915_private *dev_priv = dev->dev_private;
2520         u32 psrperf = 0;
2521         u32 stat[3];
2522         enum pipe pipe;
2523         bool enabled = false;
2524
2525         if (!HAS_PSR(dev)) {
2526                 seq_puts(m, "PSR not supported\n");
2527                 return 0;
2528         }
2529
2530         intel_runtime_pm_get(dev_priv);
2531
2532         mutex_lock(&dev_priv->psr.lock);
2533         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2534         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2535         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2536         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2537         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2538                    dev_priv->psr.busy_frontbuffer_bits);
2539         seq_printf(m, "Re-enable work scheduled: %s\n",
2540                    yesno(work_busy(&dev_priv->psr.work.work)));
2541
2542         if (HAS_DDI(dev))
2543                 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2544         else {
2545                 for_each_pipe(dev_priv, pipe) {
2546                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2547                                 VLV_EDP_PSR_CURR_STATE_MASK;
2548                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2549                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2550                                 enabled = true;
2551                 }
2552         }
2553         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2554
2555         if (!HAS_DDI(dev))
2556                 for_each_pipe(dev_priv, pipe) {
2557                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2558                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2559                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2560                 }
2561         seq_puts(m, "\n");
2562
2563         /* CHV PSR has no kind of performance counter */
2564         if (HAS_DDI(dev)) {
2565                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2566                         EDP_PSR_PERF_CNT_MASK;
2567
2568                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2569         }
2570         mutex_unlock(&dev_priv->psr.lock);
2571
2572         intel_runtime_pm_put(dev_priv);
2573         return 0;
2574 }
2575
2576 static int i915_sink_crc(struct seq_file *m, void *data)
2577 {
2578         struct drm_info_node *node = m->private;
2579         struct drm_device *dev = node->minor->dev;
2580         struct intel_encoder *encoder;
2581         struct intel_connector *connector;
2582         struct intel_dp *intel_dp = NULL;
2583         int ret;
2584         u8 crc[6];
2585
2586         drm_modeset_lock_all(dev);
2587         for_each_intel_connector(dev, connector) {
2588
2589                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2590                         continue;
2591
2592                 if (!connector->base.encoder)
2593                         continue;
2594
2595                 encoder = to_intel_encoder(connector->base.encoder);
2596                 if (encoder->type != INTEL_OUTPUT_EDP)
2597                         continue;
2598
2599                 intel_dp = enc_to_intel_dp(&encoder->base);
2600
2601                 ret = intel_dp_sink_crc(intel_dp, crc);
2602                 if (ret)
2603                         goto out;
2604
2605                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2606                            crc[0], crc[1], crc[2],
2607                            crc[3], crc[4], crc[5]);
2608                 goto out;
2609         }
2610         ret = -ENODEV;
2611 out:
2612         drm_modeset_unlock_all(dev);
2613         return ret;
2614 }
2615
2616 static int i915_energy_uJ(struct seq_file *m, void *data)
2617 {
2618         struct drm_info_node *node = m->private;
2619         struct drm_device *dev = node->minor->dev;
2620         struct drm_i915_private *dev_priv = dev->dev_private;
2621         u64 power;
2622         u32 units;
2623
2624         if (INTEL_INFO(dev)->gen < 6)
2625                 return -ENODEV;
2626
2627         intel_runtime_pm_get(dev_priv);
2628
2629         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2630         power = (power & 0x1f00) >> 8;
2631         units = 1000000 / (1 << power); /* convert to uJ */
2632         power = I915_READ(MCH_SECP_NRG_STTS);
2633         power *= units;
2634
2635         intel_runtime_pm_put(dev_priv);
2636
2637         seq_printf(m, "%llu", (long long unsigned)power);
2638
2639         return 0;
2640 }
2641
2642 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2643 {
2644         struct drm_info_node *node = m->private;
2645         struct drm_device *dev = node->minor->dev;
2646         struct drm_i915_private *dev_priv = dev->dev_private;
2647
2648         if (!HAS_RUNTIME_PM(dev)) {
2649                 seq_puts(m, "not supported\n");
2650                 return 0;
2651         }
2652
2653         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2654         seq_printf(m, "IRQs disabled: %s\n",
2655                    yesno(!intel_irqs_enabled(dev_priv)));
2656 #ifdef CONFIG_PM
2657         seq_printf(m, "Usage count: %d\n",
2658                    atomic_read(&dev->dev->power.usage_count));
2659 #else
2660         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2661 #endif
2662
2663         return 0;
2664 }
2665
2666 static const char *power_domain_str(enum intel_display_power_domain domain)
2667 {
2668         switch (domain) {
2669         case POWER_DOMAIN_PIPE_A:
2670                 return "PIPE_A";
2671         case POWER_DOMAIN_PIPE_B:
2672                 return "PIPE_B";
2673         case POWER_DOMAIN_PIPE_C:
2674                 return "PIPE_C";
2675         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2676                 return "PIPE_A_PANEL_FITTER";
2677         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2678                 return "PIPE_B_PANEL_FITTER";
2679         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2680                 return "PIPE_C_PANEL_FITTER";
2681         case POWER_DOMAIN_TRANSCODER_A:
2682                 return "TRANSCODER_A";
2683         case POWER_DOMAIN_TRANSCODER_B:
2684                 return "TRANSCODER_B";
2685         case POWER_DOMAIN_TRANSCODER_C:
2686                 return "TRANSCODER_C";
2687         case POWER_DOMAIN_TRANSCODER_EDP:
2688                 return "TRANSCODER_EDP";
2689         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2690                 return "PORT_DDI_A_2_LANES";
2691         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2692                 return "PORT_DDI_A_4_LANES";
2693         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2694                 return "PORT_DDI_B_2_LANES";
2695         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2696                 return "PORT_DDI_B_4_LANES";
2697         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2698                 return "PORT_DDI_C_2_LANES";
2699         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2700                 return "PORT_DDI_C_4_LANES";
2701         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2702                 return "PORT_DDI_D_2_LANES";
2703         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2704                 return "PORT_DDI_D_4_LANES";
2705         case POWER_DOMAIN_PORT_DDI_E_2_LANES:
2706                 return "PORT_DDI_E_2_LANES";
2707         case POWER_DOMAIN_PORT_DSI:
2708                 return "PORT_DSI";
2709         case POWER_DOMAIN_PORT_CRT:
2710                 return "PORT_CRT";
2711         case POWER_DOMAIN_PORT_OTHER:
2712                 return "PORT_OTHER";
2713         case POWER_DOMAIN_VGA:
2714                 return "VGA";
2715         case POWER_DOMAIN_AUDIO:
2716                 return "AUDIO";
2717         case POWER_DOMAIN_PLLS:
2718                 return "PLLS";
2719         case POWER_DOMAIN_AUX_A:
2720                 return "AUX_A";
2721         case POWER_DOMAIN_AUX_B:
2722                 return "AUX_B";
2723         case POWER_DOMAIN_AUX_C:
2724                 return "AUX_C";
2725         case POWER_DOMAIN_AUX_D:
2726                 return "AUX_D";
2727         case POWER_DOMAIN_INIT:
2728                 return "INIT";
2729         default:
2730                 MISSING_CASE(domain);
2731                 return "?";
2732         }
2733 }
2734
2735 static int i915_power_domain_info(struct seq_file *m, void *unused)
2736 {
2737         struct drm_info_node *node = m->private;
2738         struct drm_device *dev = node->minor->dev;
2739         struct drm_i915_private *dev_priv = dev->dev_private;
2740         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2741         int i;
2742
2743         mutex_lock(&power_domains->lock);
2744
2745         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2746         for (i = 0; i < power_domains->power_well_count; i++) {
2747                 struct i915_power_well *power_well;
2748                 enum intel_display_power_domain power_domain;
2749
2750                 power_well = &power_domains->power_wells[i];
2751                 seq_printf(m, "%-25s %d\n", power_well->name,
2752                            power_well->count);
2753
2754                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2755                      power_domain++) {
2756                         if (!(BIT(power_domain) & power_well->domains))
2757                                 continue;
2758
2759                         seq_printf(m, "  %-23s %d\n",
2760                                  power_domain_str(power_domain),
2761                                  power_domains->domain_use_count[power_domain]);
2762                 }
2763         }
2764
2765         mutex_unlock(&power_domains->lock);
2766
2767         return 0;
2768 }
2769
2770 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2771                                  struct drm_display_mode *mode)
2772 {
2773         int i;
2774
2775         for (i = 0; i < tabs; i++)
2776                 seq_putc(m, '\t');
2777
2778         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2779                    mode->base.id, mode->name,
2780                    mode->vrefresh, mode->clock,
2781                    mode->hdisplay, mode->hsync_start,
2782                    mode->hsync_end, mode->htotal,
2783                    mode->vdisplay, mode->vsync_start,
2784                    mode->vsync_end, mode->vtotal,
2785                    mode->type, mode->flags);
2786 }
2787
2788 static void intel_encoder_info(struct seq_file *m,
2789                                struct intel_crtc *intel_crtc,
2790                                struct intel_encoder *intel_encoder)
2791 {
2792         struct drm_info_node *node = m->private;
2793         struct drm_device *dev = node->minor->dev;
2794         struct drm_crtc *crtc = &intel_crtc->base;
2795         struct intel_connector *intel_connector;
2796         struct drm_encoder *encoder;
2797
2798         encoder = &intel_encoder->base;
2799         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2800                    encoder->base.id, encoder->name);
2801         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2802                 struct drm_connector *connector = &intel_connector->base;
2803                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2804                            connector->base.id,
2805                            connector->name,
2806                            drm_get_connector_status_name(connector->status));
2807                 if (connector->status == connector_status_connected) {
2808                         struct drm_display_mode *mode = &crtc->mode;
2809                         seq_printf(m, ", mode:\n");
2810                         intel_seq_print_mode(m, 2, mode);
2811                 } else {
2812                         seq_putc(m, '\n');
2813                 }
2814         }
2815 }
2816
2817 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2818 {
2819         struct drm_info_node *node = m->private;
2820         struct drm_device *dev = node->minor->dev;
2821         struct drm_crtc *crtc = &intel_crtc->base;
2822         struct intel_encoder *intel_encoder;
2823         struct drm_plane_state *plane_state = crtc->primary->state;
2824         struct drm_framebuffer *fb = plane_state->fb;
2825
2826         if (fb)
2827                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2828                            fb->base.id, plane_state->src_x >> 16,
2829                            plane_state->src_y >> 16, fb->width, fb->height);
2830         else
2831                 seq_puts(m, "\tprimary plane disabled\n");
2832         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2833                 intel_encoder_info(m, intel_crtc, intel_encoder);
2834 }
2835
2836 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2837 {
2838         struct drm_display_mode *mode = panel->fixed_mode;
2839
2840         seq_printf(m, "\tfixed mode:\n");
2841         intel_seq_print_mode(m, 2, mode);
2842 }
2843
2844 static void intel_dp_info(struct seq_file *m,
2845                           struct intel_connector *intel_connector)
2846 {
2847         struct intel_encoder *intel_encoder = intel_connector->encoder;
2848         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2849
2850         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2851         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2852         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2853                 intel_panel_info(m, &intel_connector->panel);
2854 }
2855
2856 static void intel_hdmi_info(struct seq_file *m,
2857                             struct intel_connector *intel_connector)
2858 {
2859         struct intel_encoder *intel_encoder = intel_connector->encoder;
2860         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2861
2862         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2863 }
2864
2865 static void intel_lvds_info(struct seq_file *m,
2866                             struct intel_connector *intel_connector)
2867 {
2868         intel_panel_info(m, &intel_connector->panel);
2869 }
2870
2871 static void intel_connector_info(struct seq_file *m,
2872                                  struct drm_connector *connector)
2873 {
2874         struct intel_connector *intel_connector = to_intel_connector(connector);
2875         struct intel_encoder *intel_encoder = intel_connector->encoder;
2876         struct drm_display_mode *mode;
2877
2878         seq_printf(m, "connector %d: type %s, status: %s\n",
2879                    connector->base.id, connector->name,
2880                    drm_get_connector_status_name(connector->status));
2881         if (connector->status == connector_status_connected) {
2882                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2883                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2884                            connector->display_info.width_mm,
2885                            connector->display_info.height_mm);
2886                 seq_printf(m, "\tsubpixel order: %s\n",
2887                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2888                 seq_printf(m, "\tCEA rev: %d\n",
2889                            connector->display_info.cea_rev);
2890         }
2891         if (intel_encoder) {
2892                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2893                     intel_encoder->type == INTEL_OUTPUT_EDP)
2894                         intel_dp_info(m, intel_connector);
2895                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2896                         intel_hdmi_info(m, intel_connector);
2897                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2898                         intel_lvds_info(m, intel_connector);
2899         }
2900
2901         seq_printf(m, "\tmodes:\n");
2902         list_for_each_entry(mode, &connector->modes, head)
2903                 intel_seq_print_mode(m, 2, mode);
2904 }
2905
2906 static bool cursor_active(struct drm_device *dev, int pipe)
2907 {
2908         struct drm_i915_private *dev_priv = dev->dev_private;
2909         u32 state;
2910
2911         if (IS_845G(dev) || IS_I865G(dev))
2912                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2913         else
2914                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2915
2916         return state;
2917 }
2918
2919 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2920 {
2921         struct drm_i915_private *dev_priv = dev->dev_private;
2922         u32 pos;
2923
2924         pos = I915_READ(CURPOS(pipe));
2925
2926         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2927         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2928                 *x = -*x;
2929
2930         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2931         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2932                 *y = -*y;
2933
2934         return cursor_active(dev, pipe);
2935 }
2936
2937 static int i915_display_info(struct seq_file *m, void *unused)
2938 {
2939         struct drm_info_node *node = m->private;
2940         struct drm_device *dev = node->minor->dev;
2941         struct drm_i915_private *dev_priv = dev->dev_private;
2942         struct intel_crtc *crtc;
2943         struct drm_connector *connector;
2944
2945         intel_runtime_pm_get(dev_priv);
2946         drm_modeset_lock_all(dev);
2947         seq_printf(m, "CRTC info\n");
2948         seq_printf(m, "---------\n");
2949         for_each_intel_crtc(dev, crtc) {
2950                 bool active;
2951                 struct intel_crtc_state *pipe_config;
2952                 int x, y;
2953
2954                 pipe_config = to_intel_crtc_state(crtc->base.state);
2955
2956                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2957                            crtc->base.base.id, pipe_name(crtc->pipe),
2958                            yesno(pipe_config->base.active),
2959                            pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2960                 if (pipe_config->base.active) {
2961                         intel_crtc_info(m, crtc);
2962
2963                         active = cursor_position(dev, crtc->pipe, &x, &y);
2964                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2965                                    yesno(crtc->cursor_base),
2966                                    x, y, crtc->base.cursor->state->crtc_w,
2967                                    crtc->base.cursor->state->crtc_h,
2968                                    crtc->cursor_addr, yesno(active));
2969                 }
2970
2971                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2972                            yesno(!crtc->cpu_fifo_underrun_disabled),
2973                            yesno(!crtc->pch_fifo_underrun_disabled));
2974         }
2975
2976         seq_printf(m, "\n");
2977         seq_printf(m, "Connector info\n");
2978         seq_printf(m, "--------------\n");
2979         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2980                 intel_connector_info(m, connector);
2981         }
2982         drm_modeset_unlock_all(dev);
2983         intel_runtime_pm_put(dev_priv);
2984
2985         return 0;
2986 }
2987
2988 static int i915_semaphore_status(struct seq_file *m, void *unused)
2989 {
2990         struct drm_info_node *node = (struct drm_info_node *) m->private;
2991         struct drm_device *dev = node->minor->dev;
2992         struct drm_i915_private *dev_priv = dev->dev_private;
2993         struct intel_engine_cs *ring;
2994         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2995         int i, j, ret;
2996
2997         if (!i915_semaphore_is_enabled(dev)) {
2998                 seq_puts(m, "Semaphores are disabled\n");
2999                 return 0;
3000         }
3001
3002         ret = mutex_lock_interruptible(&dev->struct_mutex);
3003         if (ret)
3004                 return ret;
3005         intel_runtime_pm_get(dev_priv);
3006
3007         if (IS_BROADWELL(dev)) {
3008                 struct page *page;
3009                 uint64_t *seqno;
3010
3011                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3012
3013                 seqno = (uint64_t *)kmap_atomic(page);
3014                 for_each_ring(ring, dev_priv, i) {
3015                         uint64_t offset;
3016
3017                         seq_printf(m, "%s\n", ring->name);
3018
3019                         seq_puts(m, "  Last signal:");
3020                         for (j = 0; j < num_rings; j++) {
3021                                 offset = i * I915_NUM_RINGS + j;
3022                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3023                                            seqno[offset], offset * 8);
3024                         }
3025                         seq_putc(m, '\n');
3026
3027                         seq_puts(m, "  Last wait:  ");
3028                         for (j = 0; j < num_rings; j++) {
3029                                 offset = i + (j * I915_NUM_RINGS);
3030                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3031                                            seqno[offset], offset * 8);
3032                         }
3033                         seq_putc(m, '\n');
3034
3035                 }
3036                 kunmap_atomic(seqno);
3037         } else {
3038                 seq_puts(m, "  Last signal:");
3039                 for_each_ring(ring, dev_priv, i)
3040                         for (j = 0; j < num_rings; j++)
3041                                 seq_printf(m, "0x%08x\n",
3042                                            I915_READ(ring->semaphore.mbox.signal[j]));
3043                 seq_putc(m, '\n');
3044         }
3045
3046         seq_puts(m, "\nSync seqno:\n");
3047         for_each_ring(ring, dev_priv, i) {
3048                 for (j = 0; j < num_rings; j++) {
3049                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
3050                 }
3051                 seq_putc(m, '\n');
3052         }
3053         seq_putc(m, '\n');
3054
3055         intel_runtime_pm_put(dev_priv);
3056         mutex_unlock(&dev->struct_mutex);
3057         return 0;
3058 }
3059
3060 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3061 {
3062         struct drm_info_node *node = (struct drm_info_node *) m->private;
3063         struct drm_device *dev = node->minor->dev;
3064         struct drm_i915_private *dev_priv = dev->dev_private;
3065         int i;
3066
3067         drm_modeset_lock_all(dev);
3068         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3069                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3070
3071                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3072                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3073                            pll->config.crtc_mask, pll->active, yesno(pll->on));
3074                 seq_printf(m, " tracked hardware state:\n");
3075                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3076                 seq_printf(m, " dpll_md: 0x%08x\n",
3077                            pll->config.hw_state.dpll_md);
3078                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3079                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3080                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3081         }
3082         drm_modeset_unlock_all(dev);
3083
3084         return 0;
3085 }
3086
3087 static int i915_wa_registers(struct seq_file *m, void *unused)
3088 {
3089         int i;
3090         int ret;
3091         struct drm_info_node *node = (struct drm_info_node *) m->private;
3092         struct drm_device *dev = node->minor->dev;
3093         struct drm_i915_private *dev_priv = dev->dev_private;
3094
3095         ret = mutex_lock_interruptible(&dev->struct_mutex);
3096         if (ret)
3097                 return ret;
3098
3099         intel_runtime_pm_get(dev_priv);
3100
3101         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3102         for (i = 0; i < dev_priv->workarounds.count; ++i) {
3103                 u32 addr, mask, value, read;
3104                 bool ok;
3105
3106                 addr = dev_priv->workarounds.reg[i].addr;
3107                 mask = dev_priv->workarounds.reg[i].mask;
3108                 value = dev_priv->workarounds.reg[i].value;
3109                 read = I915_READ(addr);
3110                 ok = (value & mask) == (read & mask);
3111                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3112                            addr, value, mask, read, ok ? "OK" : "FAIL");
3113         }
3114
3115         intel_runtime_pm_put(dev_priv);
3116         mutex_unlock(&dev->struct_mutex);
3117
3118         return 0;
3119 }
3120
3121 static int i915_ddb_info(struct seq_file *m, void *unused)
3122 {
3123         struct drm_info_node *node = m->private;
3124         struct drm_device *dev = node->minor->dev;
3125         struct drm_i915_private *dev_priv = dev->dev_private;
3126         struct skl_ddb_allocation *ddb;
3127         struct skl_ddb_entry *entry;
3128         enum pipe pipe;
3129         int plane;
3130
3131         if (INTEL_INFO(dev)->gen < 9)
3132                 return 0;
3133
3134         drm_modeset_lock_all(dev);
3135
3136         ddb = &dev_priv->wm.skl_hw.ddb;
3137
3138         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3139
3140         for_each_pipe(dev_priv, pipe) {
3141                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3142
3143                 for_each_plane(dev_priv, pipe, plane) {
3144                         entry = &ddb->plane[pipe][plane];
3145                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3146                                    entry->start, entry->end,
3147                                    skl_ddb_entry_size(entry));
3148                 }
3149
3150                 entry = &ddb->cursor[pipe];
3151                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3152                            entry->end, skl_ddb_entry_size(entry));
3153         }
3154
3155         drm_modeset_unlock_all(dev);
3156
3157         return 0;
3158 }
3159
3160 static void drrs_status_per_crtc(struct seq_file *m,
3161                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3162 {
3163         struct intel_encoder *intel_encoder;
3164         struct drm_i915_private *dev_priv = dev->dev_private;
3165         struct i915_drrs *drrs = &dev_priv->drrs;
3166         int vrefresh = 0;
3167
3168         for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3169                 /* Encoder connected on this CRTC */
3170                 switch (intel_encoder->type) {
3171                 case INTEL_OUTPUT_EDP:
3172                         seq_puts(m, "eDP:\n");
3173                         break;
3174                 case INTEL_OUTPUT_DSI:
3175                         seq_puts(m, "DSI:\n");
3176                         break;
3177                 case INTEL_OUTPUT_HDMI:
3178                         seq_puts(m, "HDMI:\n");
3179                         break;
3180                 case INTEL_OUTPUT_DISPLAYPORT:
3181                         seq_puts(m, "DP:\n");
3182                         break;
3183                 default:
3184                         seq_printf(m, "Other encoder (id=%d).\n",
3185                                                 intel_encoder->type);
3186                         return;
3187                 }
3188         }
3189
3190         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3191                 seq_puts(m, "\tVBT: DRRS_type: Static");
3192         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3193                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3194         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3195                 seq_puts(m, "\tVBT: DRRS_type: None");
3196         else
3197                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3198
3199         seq_puts(m, "\n\n");
3200
3201         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3202                 struct intel_panel *panel;
3203
3204                 mutex_lock(&drrs->mutex);
3205                 /* DRRS Supported */
3206                 seq_puts(m, "\tDRRS Supported: Yes\n");
3207
3208                 /* disable_drrs() will make drrs->dp NULL */
3209                 if (!drrs->dp) {
3210                         seq_puts(m, "Idleness DRRS: Disabled");
3211                         mutex_unlock(&drrs->mutex);
3212                         return;
3213                 }
3214
3215                 panel = &drrs->dp->attached_connector->panel;
3216                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3217                                         drrs->busy_frontbuffer_bits);
3218
3219                 seq_puts(m, "\n\t\t");
3220                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3221                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3222                         vrefresh = panel->fixed_mode->vrefresh;
3223                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3224                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3225                         vrefresh = panel->downclock_mode->vrefresh;
3226                 } else {
3227                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3228                                                 drrs->refresh_rate_type);
3229                         mutex_unlock(&drrs->mutex);
3230                         return;
3231                 }
3232                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3233
3234                 seq_puts(m, "\n\t\t");
3235                 mutex_unlock(&drrs->mutex);
3236         } else {
3237                 /* DRRS not supported. Print the VBT parameter*/
3238                 seq_puts(m, "\tDRRS Supported : No");
3239         }
3240         seq_puts(m, "\n");
3241 }
3242
3243 static int i915_drrs_status(struct seq_file *m, void *unused)
3244 {
3245         struct drm_info_node *node = m->private;
3246         struct drm_device *dev = node->minor->dev;
3247         struct intel_crtc *intel_crtc;
3248         int active_crtc_cnt = 0;
3249
3250         for_each_intel_crtc(dev, intel_crtc) {
3251                 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3252
3253                 if (intel_crtc->base.state->active) {
3254                         active_crtc_cnt++;
3255                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3256
3257                         drrs_status_per_crtc(m, dev, intel_crtc);
3258                 }
3259
3260                 drm_modeset_unlock(&intel_crtc->base.mutex);
3261         }
3262
3263         if (!active_crtc_cnt)
3264                 seq_puts(m, "No active crtc found\n");
3265
3266         return 0;
3267 }
3268
3269 struct pipe_crc_info {
3270         const char *name;
3271         struct drm_device *dev;
3272         enum pipe pipe;
3273 };
3274
3275 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3276 {
3277         struct drm_info_node *node = (struct drm_info_node *) m->private;
3278         struct drm_device *dev = node->minor->dev;
3279         struct drm_encoder *encoder;
3280         struct intel_encoder *intel_encoder;
3281         struct intel_digital_port *intel_dig_port;
3282         drm_modeset_lock_all(dev);
3283         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3284                 intel_encoder = to_intel_encoder(encoder);
3285                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3286                         continue;
3287                 intel_dig_port = enc_to_dig_port(encoder);
3288                 if (!intel_dig_port->dp.can_mst)
3289                         continue;
3290
3291                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3292         }
3293         drm_modeset_unlock_all(dev);
3294         return 0;
3295 }
3296
3297 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3298 {
3299         struct pipe_crc_info *info = inode->i_private;
3300         struct drm_i915_private *dev_priv = info->dev->dev_private;
3301         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3302
3303         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3304                 return -ENODEV;
3305
3306         spin_lock_irq(&pipe_crc->lock);
3307
3308         if (pipe_crc->opened) {
3309                 spin_unlock_irq(&pipe_crc->lock);
3310                 return -EBUSY; /* already open */
3311         }
3312
3313         pipe_crc->opened = true;
3314         filep->private_data = inode->i_private;
3315
3316         spin_unlock_irq(&pipe_crc->lock);
3317
3318         return 0;
3319 }
3320
3321 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3322 {
3323         struct pipe_crc_info *info = inode->i_private;
3324         struct drm_i915_private *dev_priv = info->dev->dev_private;
3325         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3326
3327         spin_lock_irq(&pipe_crc->lock);
3328         pipe_crc->opened = false;
3329         spin_unlock_irq(&pipe_crc->lock);
3330
3331         return 0;
3332 }
3333
3334 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3335 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3336 /* account for \'0' */
3337 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3338
3339 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3340 {
3341         assert_spin_locked(&pipe_crc->lock);
3342         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3343                         INTEL_PIPE_CRC_ENTRIES_NR);
3344 }
3345
3346 static ssize_t
3347 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3348                    loff_t *pos)
3349 {
3350         struct pipe_crc_info *info = filep->private_data;
3351         struct drm_device *dev = info->dev;
3352         struct drm_i915_private *dev_priv = dev->dev_private;
3353         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3354         char buf[PIPE_CRC_BUFFER_LEN];
3355         int n_entries;
3356         ssize_t bytes_read;
3357
3358         /*
3359          * Don't allow user space to provide buffers not big enough to hold
3360          * a line of data.
3361          */
3362         if (count < PIPE_CRC_LINE_LEN)
3363                 return -EINVAL;
3364
3365         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3366                 return 0;
3367
3368         /* nothing to read */
3369         spin_lock_irq(&pipe_crc->lock);
3370         while (pipe_crc_data_count(pipe_crc) == 0) {
3371                 int ret;
3372
3373                 if (filep->f_flags & O_NONBLOCK) {
3374                         spin_unlock_irq(&pipe_crc->lock);
3375                         return -EAGAIN;
3376                 }
3377
3378                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3379                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3380                 if (ret) {
3381                         spin_unlock_irq(&pipe_crc->lock);
3382                         return ret;
3383                 }
3384         }
3385
3386         /* We now have one or more entries to read */
3387         n_entries = count / PIPE_CRC_LINE_LEN;
3388
3389         bytes_read = 0;
3390         while (n_entries > 0) {
3391                 struct intel_pipe_crc_entry *entry =
3392                         &pipe_crc->entries[pipe_crc->tail];
3393                 int ret;
3394
3395                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3396                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3397                         break;
3398
3399                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3400                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3401
3402                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3403                                        "%8u %8x %8x %8x %8x %8x\n",
3404                                        entry->frame, entry->crc[0],
3405                                        entry->crc[1], entry->crc[2],
3406                                        entry->crc[3], entry->crc[4]);
3407
3408                 spin_unlock_irq(&pipe_crc->lock);
3409
3410                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3411                 if (ret == PIPE_CRC_LINE_LEN)
3412                         return -EFAULT;
3413
3414                 user_buf += PIPE_CRC_LINE_LEN;
3415                 n_entries--;
3416
3417                 spin_lock_irq(&pipe_crc->lock);
3418         }
3419
3420         spin_unlock_irq(&pipe_crc->lock);
3421
3422         return bytes_read;
3423 }
3424
3425 static const struct file_operations i915_pipe_crc_fops = {
3426         .owner = THIS_MODULE,
3427         .open = i915_pipe_crc_open,
3428         .read = i915_pipe_crc_read,
3429         .release = i915_pipe_crc_release,
3430 };
3431
3432 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3433         {
3434                 .name = "i915_pipe_A_crc",
3435                 .pipe = PIPE_A,
3436         },
3437         {
3438                 .name = "i915_pipe_B_crc",
3439                 .pipe = PIPE_B,
3440         },
3441         {
3442                 .name = "i915_pipe_C_crc",
3443                 .pipe = PIPE_C,
3444         },
3445 };
3446
3447 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3448                                 enum pipe pipe)
3449 {
3450         struct drm_device *dev = minor->dev;
3451         struct dentry *ent;
3452         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3453
3454         info->dev = dev;
3455         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3456                                   &i915_pipe_crc_fops);
3457         if (!ent)
3458                 return -ENOMEM;
3459
3460         return drm_add_fake_info_node(minor, ent, info);
3461 }
3462
3463 static const char * const pipe_crc_sources[] = {
3464         "none",
3465         "plane1",
3466         "plane2",
3467         "pf",
3468         "pipe",
3469         "TV",
3470         "DP-B",
3471         "DP-C",
3472         "DP-D",
3473         "auto",
3474 };
3475
3476 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3477 {
3478         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3479         return pipe_crc_sources[source];
3480 }
3481
3482 static int display_crc_ctl_show(struct seq_file *m, void *data)
3483 {
3484         struct drm_device *dev = m->private;
3485         struct drm_i915_private *dev_priv = dev->dev_private;
3486         int i;
3487
3488         for (i = 0; i < I915_MAX_PIPES; i++)
3489                 seq_printf(m, "%c %s\n", pipe_name(i),
3490                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3491
3492         return 0;
3493 }
3494
3495 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3496 {
3497         struct drm_device *dev = inode->i_private;
3498
3499         return single_open(file, display_crc_ctl_show, dev);
3500 }
3501
3502 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3503                                  uint32_t *val)
3504 {
3505         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3506                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3507
3508         switch (*source) {
3509         case INTEL_PIPE_CRC_SOURCE_PIPE:
3510                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3511                 break;
3512         case INTEL_PIPE_CRC_SOURCE_NONE:
3513                 *val = 0;
3514                 break;
3515         default:
3516                 return -EINVAL;
3517         }
3518
3519         return 0;
3520 }
3521
3522 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3523                                      enum intel_pipe_crc_source *source)
3524 {
3525         struct intel_encoder *encoder;
3526         struct intel_crtc *crtc;
3527         struct intel_digital_port *dig_port;
3528         int ret = 0;
3529
3530         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3531
3532         drm_modeset_lock_all(dev);
3533         for_each_intel_encoder(dev, encoder) {
3534                 if (!encoder->base.crtc)
3535                         continue;
3536
3537                 crtc = to_intel_crtc(encoder->base.crtc);
3538
3539                 if (crtc->pipe != pipe)
3540                         continue;
3541
3542                 switch (encoder->type) {
3543                 case INTEL_OUTPUT_TVOUT:
3544                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3545                         break;
3546                 case INTEL_OUTPUT_DISPLAYPORT:
3547                 case INTEL_OUTPUT_EDP:
3548                         dig_port = enc_to_dig_port(&encoder->base);
3549                         switch (dig_port->port) {
3550                         case PORT_B:
3551                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3552                                 break;
3553                         case PORT_C:
3554                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3555                                 break;
3556                         case PORT_D:
3557                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3558                                 break;
3559                         default:
3560                                 WARN(1, "nonexisting DP port %c\n",
3561                                      port_name(dig_port->port));
3562                                 break;
3563                         }
3564                         break;
3565                 default:
3566                         break;
3567                 }
3568         }
3569         drm_modeset_unlock_all(dev);
3570
3571         return ret;
3572 }
3573
3574 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3575                                 enum pipe pipe,
3576                                 enum intel_pipe_crc_source *source,
3577                                 uint32_t *val)
3578 {
3579         struct drm_i915_private *dev_priv = dev->dev_private;
3580         bool need_stable_symbols = false;
3581
3582         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3583                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3584                 if (ret)
3585                         return ret;
3586         }
3587
3588         switch (*source) {
3589         case INTEL_PIPE_CRC_SOURCE_PIPE:
3590                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3591                 break;
3592         case INTEL_PIPE_CRC_SOURCE_DP_B:
3593                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3594                 need_stable_symbols = true;
3595                 break;
3596         case INTEL_PIPE_CRC_SOURCE_DP_C:
3597                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3598                 need_stable_symbols = true;
3599                 break;
3600         case INTEL_PIPE_CRC_SOURCE_DP_D:
3601                 if (!IS_CHERRYVIEW(dev))
3602                         return -EINVAL;
3603                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3604                 need_stable_symbols = true;
3605                 break;
3606         case INTEL_PIPE_CRC_SOURCE_NONE:
3607                 *val = 0;
3608                 break;
3609         default:
3610                 return -EINVAL;
3611         }
3612
3613         /*
3614          * When the pipe CRC tap point is after the transcoders we need
3615          * to tweak symbol-level features to produce a deterministic series of
3616          * symbols for a given frame. We need to reset those features only once
3617          * a frame (instead of every nth symbol):
3618          *   - DC-balance: used to ensure a better clock recovery from the data
3619          *     link (SDVO)
3620          *   - DisplayPort scrambling: used for EMI reduction
3621          */
3622         if (need_stable_symbols) {
3623                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3624
3625                 tmp |= DC_BALANCE_RESET_VLV;
3626                 switch (pipe) {
3627                 case PIPE_A:
3628                         tmp |= PIPE_A_SCRAMBLE_RESET;
3629                         break;
3630                 case PIPE_B:
3631                         tmp |= PIPE_B_SCRAMBLE_RESET;
3632                         break;
3633                 case PIPE_C:
3634                         tmp |= PIPE_C_SCRAMBLE_RESET;
3635                         break;
3636                 default:
3637                         return -EINVAL;
3638                 }
3639                 I915_WRITE(PORT_DFT2_G4X, tmp);
3640         }
3641
3642         return 0;
3643 }
3644
3645 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3646                                  enum pipe pipe,
3647                                  enum intel_pipe_crc_source *source,
3648                                  uint32_t *val)
3649 {
3650         struct drm_i915_private *dev_priv = dev->dev_private;
3651         bool need_stable_symbols = false;
3652
3653         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3654                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3655                 if (ret)
3656                         return ret;
3657         }
3658
3659         switch (*source) {
3660         case INTEL_PIPE_CRC_SOURCE_PIPE:
3661                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3662                 break;
3663         case INTEL_PIPE_CRC_SOURCE_TV:
3664                 if (!SUPPORTS_TV(dev))
3665                         return -EINVAL;
3666                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3667                 break;
3668         case INTEL_PIPE_CRC_SOURCE_DP_B:
3669                 if (!IS_G4X(dev))
3670                         return -EINVAL;
3671                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3672                 need_stable_symbols = true;
3673                 break;
3674         case INTEL_PIPE_CRC_SOURCE_DP_C:
3675                 if (!IS_G4X(dev))
3676                         return -EINVAL;
3677                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3678                 need_stable_symbols = true;
3679                 break;
3680         case INTEL_PIPE_CRC_SOURCE_DP_D:
3681                 if (!IS_G4X(dev))
3682                         return -EINVAL;
3683                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3684                 need_stable_symbols = true;
3685                 break;
3686         case INTEL_PIPE_CRC_SOURCE_NONE:
3687                 *val = 0;
3688                 break;
3689         default:
3690                 return -EINVAL;
3691         }
3692
3693         /*
3694          * When the pipe CRC tap point is after the transcoders we need
3695          * to tweak symbol-level features to produce a deterministic series of
3696          * symbols for a given frame. We need to reset those features only once
3697          * a frame (instead of every nth symbol):
3698          *   - DC-balance: used to ensure a better clock recovery from the data
3699          *     link (SDVO)
3700          *   - DisplayPort scrambling: used for EMI reduction
3701          */
3702         if (need_stable_symbols) {
3703                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3704
3705                 WARN_ON(!IS_G4X(dev));
3706
3707                 I915_WRITE(PORT_DFT_I9XX,
3708                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3709
3710                 if (pipe == PIPE_A)
3711                         tmp |= PIPE_A_SCRAMBLE_RESET;
3712                 else
3713                         tmp |= PIPE_B_SCRAMBLE_RESET;
3714
3715                 I915_WRITE(PORT_DFT2_G4X, tmp);
3716         }
3717
3718         return 0;
3719 }
3720
3721 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3722                                          enum pipe pipe)
3723 {
3724         struct drm_i915_private *dev_priv = dev->dev_private;
3725         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3726
3727         switch (pipe) {
3728         case PIPE_A:
3729                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3730                 break;
3731         case PIPE_B:
3732                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3733                 break;
3734         case PIPE_C:
3735                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3736                 break;
3737         default:
3738                 return;
3739         }
3740         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3741                 tmp &= ~DC_BALANCE_RESET_VLV;
3742         I915_WRITE(PORT_DFT2_G4X, tmp);
3743
3744 }
3745
3746 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3747                                          enum pipe pipe)
3748 {
3749         struct drm_i915_private *dev_priv = dev->dev_private;
3750         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3751
3752         if (pipe == PIPE_A)
3753                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3754         else
3755                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3756         I915_WRITE(PORT_DFT2_G4X, tmp);
3757
3758         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3759                 I915_WRITE(PORT_DFT_I9XX,
3760                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3761         }
3762 }
3763
3764 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3765                                 uint32_t *val)
3766 {
3767         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3768                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3769
3770         switch (*source) {
3771         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3772                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3773                 break;
3774         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3775                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3776                 break;
3777         case INTEL_PIPE_CRC_SOURCE_PIPE:
3778                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3779                 break;
3780         case INTEL_PIPE_CRC_SOURCE_NONE:
3781                 *val = 0;
3782                 break;
3783         default:
3784                 return -EINVAL;
3785         }
3786
3787         return 0;
3788 }
3789
3790 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3791 {
3792         struct drm_i915_private *dev_priv = dev->dev_private;
3793         struct intel_crtc *crtc =
3794                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3795         struct intel_crtc_state *pipe_config;
3796         struct drm_atomic_state *state;
3797         int ret = 0;
3798
3799         drm_modeset_lock_all(dev);
3800         state = drm_atomic_state_alloc(dev);
3801         if (!state) {
3802                 ret = -ENOMEM;
3803                 goto out;
3804         }
3805
3806         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3807         pipe_config = intel_atomic_get_crtc_state(state, crtc);
3808         if (IS_ERR(pipe_config)) {
3809                 ret = PTR_ERR(pipe_config);
3810                 goto out;
3811         }
3812
3813         pipe_config->pch_pfit.force_thru = enable;
3814         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3815             pipe_config->pch_pfit.enabled != enable)
3816                 pipe_config->base.connectors_changed = true;
3817
3818         ret = drm_atomic_commit(state);
3819 out:
3820         drm_modeset_unlock_all(dev);
3821         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3822         if (ret)
3823                 drm_atomic_state_free(state);
3824 }
3825
3826 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3827                                 enum pipe pipe,
3828                                 enum intel_pipe_crc_source *source,
3829                                 uint32_t *val)
3830 {
3831         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3832                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3833
3834         switch (*source) {
3835         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3836                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3837                 break;
3838         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3839                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3840                 break;
3841         case INTEL_PIPE_CRC_SOURCE_PF:
3842                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3843                         hsw_trans_edp_pipe_A_crc_wa(dev, true);
3844
3845                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3846                 break;
3847         case INTEL_PIPE_CRC_SOURCE_NONE:
3848                 *val = 0;
3849                 break;
3850         default:
3851                 return -EINVAL;
3852         }
3853
3854         return 0;
3855 }
3856
3857 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3858                                enum intel_pipe_crc_source source)
3859 {
3860         struct drm_i915_private *dev_priv = dev->dev_private;
3861         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3862         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3863                                                                         pipe));
3864         u32 val = 0; /* shut up gcc */
3865         int ret;
3866
3867         if (pipe_crc->source == source)
3868                 return 0;
3869
3870         /* forbid changing the source without going back to 'none' */
3871         if (pipe_crc->source && source)
3872                 return -EINVAL;
3873
3874         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3875                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3876                 return -EIO;
3877         }
3878
3879         if (IS_GEN2(dev))
3880                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3881         else if (INTEL_INFO(dev)->gen < 5)
3882                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3883         else if (IS_VALLEYVIEW(dev))
3884                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3885         else if (IS_GEN5(dev) || IS_GEN6(dev))
3886                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3887         else
3888                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3889
3890         if (ret != 0)
3891                 return ret;
3892
3893         /* none -> real source transition */
3894         if (source) {
3895                 struct intel_pipe_crc_entry *entries;
3896
3897                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3898                                  pipe_name(pipe), pipe_crc_source_name(source));
3899
3900                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3901                                   sizeof(pipe_crc->entries[0]),
3902                                   GFP_KERNEL);
3903                 if (!entries)
3904                         return -ENOMEM;
3905
3906                 /*
3907                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3908                  * enabled and disabled dynamically based on package C states,
3909                  * user space can't make reliable use of the CRCs, so let's just
3910                  * completely disable it.
3911                  */
3912                 hsw_disable_ips(crtc);
3913
3914                 spin_lock_irq(&pipe_crc->lock);
3915                 kfree(pipe_crc->entries);
3916                 pipe_crc->entries = entries;
3917                 pipe_crc->head = 0;
3918                 pipe_crc->tail = 0;
3919                 spin_unlock_irq(&pipe_crc->lock);
3920         }
3921
3922         pipe_crc->source = source;
3923
3924         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3925         POSTING_READ(PIPE_CRC_CTL(pipe));
3926
3927         /* real source -> none transition */
3928         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3929                 struct intel_pipe_crc_entry *entries;
3930                 struct intel_crtc *crtc =
3931                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3932
3933                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3934                                  pipe_name(pipe));
3935
3936                 drm_modeset_lock(&crtc->base.mutex, NULL);
3937                 if (crtc->base.state->active)
3938                         intel_wait_for_vblank(dev, pipe);
3939                 drm_modeset_unlock(&crtc->base.mutex);
3940
3941                 spin_lock_irq(&pipe_crc->lock);
3942                 entries = pipe_crc->entries;
3943                 pipe_crc->entries = NULL;
3944                 pipe_crc->head = 0;
3945                 pipe_crc->tail = 0;
3946                 spin_unlock_irq(&pipe_crc->lock);
3947
3948                 kfree(entries);
3949
3950                 if (IS_G4X(dev))
3951                         g4x_undo_pipe_scramble_reset(dev, pipe);
3952                 else if (IS_VALLEYVIEW(dev))
3953                         vlv_undo_pipe_scramble_reset(dev, pipe);
3954                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3955                         hsw_trans_edp_pipe_A_crc_wa(dev, false);
3956
3957                 hsw_enable_ips(crtc);
3958         }
3959
3960         return 0;
3961 }
3962
3963 /*
3964  * Parse pipe CRC command strings:
3965  *   command: wsp* object wsp+ name wsp+ source wsp*
3966  *   object: 'pipe'
3967  *   name: (A | B | C)
3968  *   source: (none | plane1 | plane2 | pf)
3969  *   wsp: (#0x20 | #0x9 | #0xA)+
3970  *
3971  * eg.:
3972  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3973  *  "pipe A none"    ->  Stop CRC
3974  */
3975 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3976 {
3977         int n_words = 0;
3978
3979         while (*buf) {
3980                 char *end;
3981
3982                 /* skip leading white space */
3983                 buf = skip_spaces(buf);
3984                 if (!*buf)
3985                         break;  /* end of buffer */
3986
3987                 /* find end of word */
3988                 for (end = buf; *end && !isspace(*end); end++)
3989                         ;
3990
3991                 if (n_words == max_words) {
3992                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3993                                          max_words);
3994                         return -EINVAL; /* ran out of words[] before bytes */
3995                 }
3996
3997                 if (*end)
3998                         *end++ = '\0';
3999                 words[n_words++] = buf;
4000                 buf = end;
4001         }
4002
4003         return n_words;
4004 }
4005
4006 enum intel_pipe_crc_object {
4007         PIPE_CRC_OBJECT_PIPE,
4008 };
4009
4010 static const char * const pipe_crc_objects[] = {
4011         "pipe",
4012 };
4013
4014 static int
4015 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4016 {
4017         int i;
4018
4019         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4020                 if (!strcmp(buf, pipe_crc_objects[i])) {
4021                         *o = i;
4022                         return 0;
4023                     }
4024
4025         return -EINVAL;
4026 }
4027
4028 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4029 {
4030         const char name = buf[0];
4031
4032         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4033                 return -EINVAL;
4034
4035         *pipe = name - 'A';
4036
4037         return 0;
4038 }
4039
4040 static int
4041 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4042 {
4043         int i;
4044
4045         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4046                 if (!strcmp(buf, pipe_crc_sources[i])) {
4047                         *s = i;
4048                         return 0;
4049                     }
4050
4051         return -EINVAL;
4052 }
4053
4054 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4055 {
4056 #define N_WORDS 3
4057         int n_words;
4058         char *words[N_WORDS];
4059         enum pipe pipe;
4060         enum intel_pipe_crc_object object;
4061         enum intel_pipe_crc_source source;
4062
4063         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4064         if (n_words != N_WORDS) {
4065                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4066                                  N_WORDS);
4067                 return -EINVAL;
4068         }
4069
4070         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4071                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4072                 return -EINVAL;
4073         }
4074
4075         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4076                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4077                 return -EINVAL;
4078         }
4079
4080         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4081                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4082                 return -EINVAL;
4083         }
4084
4085         return pipe_crc_set_source(dev, pipe, source);
4086 }
4087
4088 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4089                                      size_t len, loff_t *offp)
4090 {
4091         struct seq_file *m = file->private_data;
4092         struct drm_device *dev = m->private;
4093         char *tmpbuf;
4094         int ret;
4095
4096         if (len == 0)
4097                 return 0;
4098
4099         if (len > PAGE_SIZE - 1) {
4100                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4101                                  PAGE_SIZE);
4102                 return -E2BIG;
4103         }
4104
4105         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4106         if (!tmpbuf)
4107                 return -ENOMEM;
4108
4109         if (copy_from_user(tmpbuf, ubuf, len)) {
4110                 ret = -EFAULT;
4111                 goto out;
4112         }
4113         tmpbuf[len] = '\0';
4114
4115         ret = display_crc_ctl_parse(dev, tmpbuf, len);
4116
4117 out:
4118         kfree(tmpbuf);
4119         if (ret < 0)
4120                 return ret;
4121
4122         *offp += len;
4123         return len;
4124 }
4125
4126 static const struct file_operations i915_display_crc_ctl_fops = {
4127         .owner = THIS_MODULE,
4128         .open = display_crc_ctl_open,
4129         .read = seq_read,
4130         .llseek = seq_lseek,
4131         .release = single_release,
4132         .write = display_crc_ctl_write
4133 };
4134
4135 static ssize_t i915_displayport_test_active_write(struct file *file,
4136                                             const char __user *ubuf,
4137                                             size_t len, loff_t *offp)
4138 {
4139         char *input_buffer;
4140         int status = 0;
4141         struct drm_device *dev;
4142         struct drm_connector *connector;
4143         struct list_head *connector_list;
4144         struct intel_dp *intel_dp;
4145         int val = 0;
4146
4147         dev = ((struct seq_file *)file->private_data)->private;
4148
4149         connector_list = &dev->mode_config.connector_list;
4150
4151         if (len == 0)
4152                 return 0;
4153
4154         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4155         if (!input_buffer)
4156                 return -ENOMEM;
4157
4158         if (copy_from_user(input_buffer, ubuf, len)) {
4159                 status = -EFAULT;
4160                 goto out;
4161         }
4162
4163         input_buffer[len] = '\0';
4164         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4165
4166         list_for_each_entry(connector, connector_list, head) {
4167
4168                 if (connector->connector_type !=
4169                     DRM_MODE_CONNECTOR_DisplayPort)
4170                         continue;
4171
4172                 if (connector->status == connector_status_connected &&
4173                     connector->encoder != NULL) {
4174                         intel_dp = enc_to_intel_dp(connector->encoder);
4175                         status = kstrtoint(input_buffer, 10, &val);
4176                         if (status < 0)
4177                                 goto out;
4178                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4179                         /* To prevent erroneous activation of the compliance
4180                          * testing code, only accept an actual value of 1 here
4181                          */
4182                         if (val == 1)
4183                                 intel_dp->compliance_test_active = 1;
4184                         else
4185                                 intel_dp->compliance_test_active = 0;
4186                 }
4187         }
4188 out:
4189         kfree(input_buffer);
4190         if (status < 0)
4191                 return status;
4192
4193         *offp += len;
4194         return len;
4195 }
4196
4197 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4198 {
4199         struct drm_device *dev = m->private;
4200         struct drm_connector *connector;
4201         struct list_head *connector_list = &dev->mode_config.connector_list;
4202         struct intel_dp *intel_dp;
4203
4204         list_for_each_entry(connector, connector_list, head) {
4205
4206                 if (connector->connector_type !=
4207                     DRM_MODE_CONNECTOR_DisplayPort)
4208                         continue;
4209
4210                 if (connector->status == connector_status_connected &&
4211                     connector->encoder != NULL) {
4212                         intel_dp = enc_to_intel_dp(connector->encoder);
4213                         if (intel_dp->compliance_test_active)
4214                                 seq_puts(m, "1");
4215                         else
4216                                 seq_puts(m, "0");
4217                 } else
4218                         seq_puts(m, "0");
4219         }
4220
4221         return 0;
4222 }
4223
4224 static int i915_displayport_test_active_open(struct inode *inode,
4225                                        struct file *file)
4226 {
4227         struct drm_device *dev = inode->i_private;
4228
4229         return single_open(file, i915_displayport_test_active_show, dev);
4230 }
4231
4232 static const struct file_operations i915_displayport_test_active_fops = {
4233         .owner = THIS_MODULE,
4234         .open = i915_displayport_test_active_open,
4235         .read = seq_read,
4236         .llseek = seq_lseek,
4237         .release = single_release,
4238         .write = i915_displayport_test_active_write
4239 };
4240
4241 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4242 {
4243         struct drm_device *dev = m->private;
4244         struct drm_connector *connector;
4245         struct list_head *connector_list = &dev->mode_config.connector_list;
4246         struct intel_dp *intel_dp;
4247
4248         list_for_each_entry(connector, connector_list, head) {
4249
4250                 if (connector->connector_type !=
4251                     DRM_MODE_CONNECTOR_DisplayPort)
4252                         continue;
4253
4254                 if (connector->status == connector_status_connected &&
4255                     connector->encoder != NULL) {
4256                         intel_dp = enc_to_intel_dp(connector->encoder);
4257                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4258                 } else
4259                         seq_puts(m, "0");
4260         }
4261
4262         return 0;
4263 }
4264 static int i915_displayport_test_data_open(struct inode *inode,
4265                                        struct file *file)
4266 {
4267         struct drm_device *dev = inode->i_private;
4268
4269         return single_open(file, i915_displayport_test_data_show, dev);
4270 }
4271
4272 static const struct file_operations i915_displayport_test_data_fops = {
4273         .owner = THIS_MODULE,
4274         .open = i915_displayport_test_data_open,
4275         .read = seq_read,
4276         .llseek = seq_lseek,
4277         .release = single_release
4278 };
4279
4280 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4281 {
4282         struct drm_device *dev = m->private;
4283         struct drm_connector *connector;
4284         struct list_head *connector_list = &dev->mode_config.connector_list;
4285         struct intel_dp *intel_dp;
4286
4287         list_for_each_entry(connector, connector_list, head) {
4288
4289                 if (connector->connector_type !=
4290                     DRM_MODE_CONNECTOR_DisplayPort)
4291                         continue;
4292
4293                 if (connector->status == connector_status_connected &&
4294                     connector->encoder != NULL) {
4295                         intel_dp = enc_to_intel_dp(connector->encoder);
4296                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4297                 } else
4298                         seq_puts(m, "0");
4299         }
4300
4301         return 0;
4302 }
4303
4304 static int i915_displayport_test_type_open(struct inode *inode,
4305                                        struct file *file)
4306 {
4307         struct drm_device *dev = inode->i_private;
4308
4309         return single_open(file, i915_displayport_test_type_show, dev);
4310 }
4311
4312 static const struct file_operations i915_displayport_test_type_fops = {
4313         .owner = THIS_MODULE,
4314         .open = i915_displayport_test_type_open,
4315         .read = seq_read,
4316         .llseek = seq_lseek,
4317         .release = single_release
4318 };
4319
4320 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4321 {
4322         struct drm_device *dev = m->private;
4323         int level;
4324         int num_levels;
4325
4326         if (IS_CHERRYVIEW(dev))
4327                 num_levels = 3;
4328         else if (IS_VALLEYVIEW(dev))
4329                 num_levels = 1;
4330         else
4331                 num_levels = ilk_wm_max_level(dev) + 1;
4332
4333         drm_modeset_lock_all(dev);
4334
4335         for (level = 0; level < num_levels; level++) {
4336                 unsigned int latency = wm[level];
4337
4338                 /*
4339                  * - WM1+ latency values in 0.5us units
4340                  * - latencies are in us on gen9/vlv/chv
4341                  */
4342                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4343                         latency *= 10;
4344                 else if (level > 0)
4345                         latency *= 5;
4346
4347                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4348                            level, wm[level], latency / 10, latency % 10);
4349         }
4350
4351         drm_modeset_unlock_all(dev);
4352 }
4353
4354 static int pri_wm_latency_show(struct seq_file *m, void *data)
4355 {
4356         struct drm_device *dev = m->private;
4357         struct drm_i915_private *dev_priv = dev->dev_private;
4358         const uint16_t *latencies;
4359
4360         if (INTEL_INFO(dev)->gen >= 9)
4361                 latencies = dev_priv->wm.skl_latency;
4362         else
4363                 latencies = to_i915(dev)->wm.pri_latency;
4364
4365         wm_latency_show(m, latencies);
4366
4367         return 0;
4368 }
4369
4370 static int spr_wm_latency_show(struct seq_file *m, void *data)
4371 {
4372         struct drm_device *dev = m->private;
4373         struct drm_i915_private *dev_priv = dev->dev_private;
4374         const uint16_t *latencies;
4375
4376         if (INTEL_INFO(dev)->gen >= 9)
4377                 latencies = dev_priv->wm.skl_latency;
4378         else
4379                 latencies = to_i915(dev)->wm.spr_latency;
4380
4381         wm_latency_show(m, latencies);
4382
4383         return 0;
4384 }
4385
4386 static int cur_wm_latency_show(struct seq_file *m, void *data)
4387 {
4388         struct drm_device *dev = m->private;
4389         struct drm_i915_private *dev_priv = dev->dev_private;
4390         const uint16_t *latencies;
4391
4392         if (INTEL_INFO(dev)->gen >= 9)
4393                 latencies = dev_priv->wm.skl_latency;
4394         else
4395                 latencies = to_i915(dev)->wm.cur_latency;
4396
4397         wm_latency_show(m, latencies);
4398
4399         return 0;
4400 }
4401
4402 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4403 {
4404         struct drm_device *dev = inode->i_private;
4405
4406         if (INTEL_INFO(dev)->gen < 5)
4407                 return -ENODEV;
4408
4409         return single_open(file, pri_wm_latency_show, dev);
4410 }
4411
4412 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4413 {
4414         struct drm_device *dev = inode->i_private;
4415
4416         if (HAS_GMCH_DISPLAY(dev))
4417                 return -ENODEV;
4418
4419         return single_open(file, spr_wm_latency_show, dev);
4420 }
4421
4422 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4423 {
4424         struct drm_device *dev = inode->i_private;
4425
4426         if (HAS_GMCH_DISPLAY(dev))
4427                 return -ENODEV;
4428
4429         return single_open(file, cur_wm_latency_show, dev);
4430 }
4431
4432 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4433                                 size_t len, loff_t *offp, uint16_t wm[8])
4434 {
4435         struct seq_file *m = file->private_data;
4436         struct drm_device *dev = m->private;
4437         uint16_t new[8] = { 0 };
4438         int num_levels;
4439         int level;
4440         int ret;
4441         char tmp[32];
4442
4443         if (IS_CHERRYVIEW(dev))
4444                 num_levels = 3;
4445         else if (IS_VALLEYVIEW(dev))
4446                 num_levels = 1;
4447         else
4448                 num_levels = ilk_wm_max_level(dev) + 1;
4449
4450         if (len >= sizeof(tmp))
4451                 return -EINVAL;
4452
4453         if (copy_from_user(tmp, ubuf, len))
4454                 return -EFAULT;
4455
4456         tmp[len] = '\0';
4457
4458         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4459                      &new[0], &new[1], &new[2], &new[3],
4460                      &new[4], &new[5], &new[6], &new[7]);
4461         if (ret != num_levels)
4462                 return -EINVAL;
4463
4464         drm_modeset_lock_all(dev);
4465
4466         for (level = 0; level < num_levels; level++)
4467                 wm[level] = new[level];
4468
4469         drm_modeset_unlock_all(dev);
4470
4471         return len;
4472 }
4473
4474
4475 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4476                                     size_t len, loff_t *offp)
4477 {
4478         struct seq_file *m = file->private_data;
4479         struct drm_device *dev = m->private;
4480         struct drm_i915_private *dev_priv = dev->dev_private;
4481         uint16_t *latencies;
4482
4483         if (INTEL_INFO(dev)->gen >= 9)
4484                 latencies = dev_priv->wm.skl_latency;
4485         else
4486                 latencies = to_i915(dev)->wm.pri_latency;
4487
4488         return wm_latency_write(file, ubuf, len, offp, latencies);
4489 }
4490
4491 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4492                                     size_t len, loff_t *offp)
4493 {
4494         struct seq_file *m = file->private_data;
4495         struct drm_device *dev = m->private;
4496         struct drm_i915_private *dev_priv = dev->dev_private;
4497         uint16_t *latencies;
4498
4499         if (INTEL_INFO(dev)->gen >= 9)
4500                 latencies = dev_priv->wm.skl_latency;
4501         else
4502                 latencies = to_i915(dev)->wm.spr_latency;
4503
4504         return wm_latency_write(file, ubuf, len, offp, latencies);
4505 }
4506
4507 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4508                                     size_t len, loff_t *offp)
4509 {
4510         struct seq_file *m = file->private_data;
4511         struct drm_device *dev = m->private;
4512         struct drm_i915_private *dev_priv = dev->dev_private;
4513         uint16_t *latencies;
4514
4515         if (INTEL_INFO(dev)->gen >= 9)
4516                 latencies = dev_priv->wm.skl_latency;
4517         else
4518                 latencies = to_i915(dev)->wm.cur_latency;
4519
4520         return wm_latency_write(file, ubuf, len, offp, latencies);
4521 }
4522
4523 static const struct file_operations i915_pri_wm_latency_fops = {
4524         .owner = THIS_MODULE,
4525         .open = pri_wm_latency_open,
4526         .read = seq_read,
4527         .llseek = seq_lseek,
4528         .release = single_release,
4529         .write = pri_wm_latency_write
4530 };
4531
4532 static const struct file_operations i915_spr_wm_latency_fops = {
4533         .owner = THIS_MODULE,
4534         .open = spr_wm_latency_open,
4535         .read = seq_read,
4536         .llseek = seq_lseek,
4537         .release = single_release,
4538         .write = spr_wm_latency_write
4539 };
4540
4541 static const struct file_operations i915_cur_wm_latency_fops = {
4542         .owner = THIS_MODULE,
4543         .open = cur_wm_latency_open,
4544         .read = seq_read,
4545         .llseek = seq_lseek,
4546         .release = single_release,
4547         .write = cur_wm_latency_write
4548 };
4549
4550 static int
4551 i915_wedged_get(void *data, u64 *val)
4552 {
4553         struct drm_device *dev = data;
4554         struct drm_i915_private *dev_priv = dev->dev_private;
4555
4556         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4557
4558         return 0;
4559 }
4560
4561 static int
4562 i915_wedged_set(void *data, u64 val)
4563 {
4564         struct drm_device *dev = data;
4565         struct drm_i915_private *dev_priv = dev->dev_private;
4566
4567         /*
4568          * There is no safeguard against this debugfs entry colliding
4569          * with the hangcheck calling same i915_handle_error() in
4570          * parallel, causing an explosion. For now we assume that the
4571          * test harness is responsible enough not to inject gpu hangs
4572          * while it is writing to 'i915_wedged'
4573          */
4574
4575         if (i915_reset_in_progress(&dev_priv->gpu_error))
4576                 return -EAGAIN;
4577
4578         intel_runtime_pm_get(dev_priv);
4579
4580         i915_handle_error(dev, val,
4581                           "Manually setting wedged to %llu", val);
4582
4583         intel_runtime_pm_put(dev_priv);
4584
4585         return 0;
4586 }
4587
4588 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4589                         i915_wedged_get, i915_wedged_set,
4590                         "%llu\n");
4591
4592 static int
4593 i915_ring_stop_get(void *data, u64 *val)
4594 {
4595         struct drm_device *dev = data;
4596         struct drm_i915_private *dev_priv = dev->dev_private;
4597
4598         *val = dev_priv->gpu_error.stop_rings;
4599
4600         return 0;
4601 }
4602
4603 static int
4604 i915_ring_stop_set(void *data, u64 val)
4605 {
4606         struct drm_device *dev = data;
4607         struct drm_i915_private *dev_priv = dev->dev_private;
4608         int ret;
4609
4610         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4611
4612         ret = mutex_lock_interruptible(&dev->struct_mutex);
4613         if (ret)
4614                 return ret;
4615
4616         dev_priv->gpu_error.stop_rings = val;
4617         mutex_unlock(&dev->struct_mutex);
4618
4619         return 0;
4620 }
4621
4622 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4623                         i915_ring_stop_get, i915_ring_stop_set,
4624                         "0x%08llx\n");
4625
4626 static int
4627 i915_ring_missed_irq_get(void *data, u64 *val)
4628 {
4629         struct drm_device *dev = data;
4630         struct drm_i915_private *dev_priv = dev->dev_private;
4631
4632         *val = dev_priv->gpu_error.missed_irq_rings;
4633         return 0;
4634 }
4635
4636 static int
4637 i915_ring_missed_irq_set(void *data, u64 val)
4638 {
4639         struct drm_device *dev = data;
4640         struct drm_i915_private *dev_priv = dev->dev_private;
4641         int ret;
4642
4643         /* Lock against concurrent debugfs callers */
4644         ret = mutex_lock_interruptible(&dev->struct_mutex);
4645         if (ret)
4646                 return ret;
4647         dev_priv->gpu_error.missed_irq_rings = val;
4648         mutex_unlock(&dev->struct_mutex);
4649
4650         return 0;
4651 }
4652
4653 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4654                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4655                         "0x%08llx\n");
4656
4657 static int
4658 i915_ring_test_irq_get(void *data, u64 *val)
4659 {
4660         struct drm_device *dev = data;
4661         struct drm_i915_private *dev_priv = dev->dev_private;
4662
4663         *val = dev_priv->gpu_error.test_irq_rings;
4664
4665         return 0;
4666 }
4667
4668 static int
4669 i915_ring_test_irq_set(void *data, u64 val)
4670 {
4671         struct drm_device *dev = data;
4672         struct drm_i915_private *dev_priv = dev->dev_private;
4673         int ret;
4674
4675         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4676
4677         /* Lock against concurrent debugfs callers */
4678         ret = mutex_lock_interruptible(&dev->struct_mutex);
4679         if (ret)
4680                 return ret;
4681
4682         dev_priv->gpu_error.test_irq_rings = val;
4683         mutex_unlock(&dev->struct_mutex);
4684
4685         return 0;
4686 }
4687
4688 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4689                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4690                         "0x%08llx\n");
4691
4692 #define DROP_UNBOUND 0x1
4693 #define DROP_BOUND 0x2
4694 #define DROP_RETIRE 0x4
4695 #define DROP_ACTIVE 0x8
4696 #define DROP_ALL (DROP_UNBOUND | \
4697                   DROP_BOUND | \
4698                   DROP_RETIRE | \
4699                   DROP_ACTIVE)
4700 static int
4701 i915_drop_caches_get(void *data, u64 *val)
4702 {
4703         *val = DROP_ALL;
4704
4705         return 0;
4706 }
4707
4708 static int
4709 i915_drop_caches_set(void *data, u64 val)
4710 {
4711         struct drm_device *dev = data;
4712         struct drm_i915_private *dev_priv = dev->dev_private;
4713         int ret;
4714
4715         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4716
4717         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4718          * on ioctls on -EAGAIN. */
4719         ret = mutex_lock_interruptible(&dev->struct_mutex);
4720         if (ret)
4721                 return ret;
4722
4723         if (val & DROP_ACTIVE) {
4724                 ret = i915_gpu_idle(dev);
4725                 if (ret)
4726                         goto unlock;
4727         }
4728
4729         if (val & (DROP_RETIRE | DROP_ACTIVE))
4730                 i915_gem_retire_requests(dev);
4731
4732         if (val & DROP_BOUND)
4733                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4734
4735         if (val & DROP_UNBOUND)
4736                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4737
4738 unlock:
4739         mutex_unlock(&dev->struct_mutex);
4740
4741         return ret;
4742 }
4743
4744 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4745                         i915_drop_caches_get, i915_drop_caches_set,
4746                         "0x%08llx\n");
4747
4748 static int
4749 i915_max_freq_get(void *data, u64 *val)
4750 {
4751         struct drm_device *dev = data;
4752         struct drm_i915_private *dev_priv = dev->dev_private;
4753         int ret;
4754
4755         if (INTEL_INFO(dev)->gen < 6)
4756                 return -ENODEV;
4757
4758         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4759
4760         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4761         if (ret)
4762                 return ret;
4763
4764         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4765         mutex_unlock(&dev_priv->rps.hw_lock);
4766
4767         return 0;
4768 }
4769
4770 static int
4771 i915_max_freq_set(void *data, u64 val)
4772 {
4773         struct drm_device *dev = data;
4774         struct drm_i915_private *dev_priv = dev->dev_private;
4775         u32 hw_max, hw_min;
4776         int ret;
4777
4778         if (INTEL_INFO(dev)->gen < 6)
4779                 return -ENODEV;
4780
4781         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4782
4783         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4784
4785         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4786         if (ret)
4787                 return ret;
4788
4789         /*
4790          * Turbo will still be enabled, but won't go above the set value.
4791          */
4792         val = intel_freq_opcode(dev_priv, val);
4793
4794         hw_max = dev_priv->rps.max_freq;
4795         hw_min = dev_priv->rps.min_freq;
4796
4797         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4798                 mutex_unlock(&dev_priv->rps.hw_lock);
4799                 return -EINVAL;
4800         }
4801
4802         dev_priv->rps.max_freq_softlimit = val;
4803
4804         intel_set_rps(dev, val);
4805
4806         mutex_unlock(&dev_priv->rps.hw_lock);
4807
4808         return 0;
4809 }
4810
4811 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4812                         i915_max_freq_get, i915_max_freq_set,
4813                         "%llu\n");
4814
4815 static int
4816 i915_min_freq_get(void *data, u64 *val)
4817 {
4818         struct drm_device *dev = data;
4819         struct drm_i915_private *dev_priv = dev->dev_private;
4820         int ret;
4821
4822         if (INTEL_INFO(dev)->gen < 6)
4823                 return -ENODEV;
4824
4825         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4826
4827         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4828         if (ret)
4829                 return ret;
4830
4831         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4832         mutex_unlock(&dev_priv->rps.hw_lock);
4833
4834         return 0;
4835 }
4836
4837 static int
4838 i915_min_freq_set(void *data, u64 val)
4839 {
4840         struct drm_device *dev = data;
4841         struct drm_i915_private *dev_priv = dev->dev_private;
4842         u32 hw_max, hw_min;
4843         int ret;
4844
4845         if (INTEL_INFO(dev)->gen < 6)
4846                 return -ENODEV;
4847
4848         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4849
4850         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4851
4852         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4853         if (ret)
4854                 return ret;
4855
4856         /*
4857          * Turbo will still be enabled, but won't go below the set value.
4858          */
4859         val = intel_freq_opcode(dev_priv, val);
4860
4861         hw_max = dev_priv->rps.max_freq;
4862         hw_min = dev_priv->rps.min_freq;
4863
4864         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4865                 mutex_unlock(&dev_priv->rps.hw_lock);
4866                 return -EINVAL;
4867         }
4868
4869         dev_priv->rps.min_freq_softlimit = val;
4870
4871         intel_set_rps(dev, val);
4872
4873         mutex_unlock(&dev_priv->rps.hw_lock);
4874
4875         return 0;
4876 }
4877
4878 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4879                         i915_min_freq_get, i915_min_freq_set,
4880                         "%llu\n");
4881
4882 static int
4883 i915_cache_sharing_get(void *data, u64 *val)
4884 {
4885         struct drm_device *dev = data;
4886         struct drm_i915_private *dev_priv = dev->dev_private;
4887         u32 snpcr;
4888         int ret;
4889
4890         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4891                 return -ENODEV;
4892
4893         ret = mutex_lock_interruptible(&dev->struct_mutex);
4894         if (ret)
4895                 return ret;
4896         intel_runtime_pm_get(dev_priv);
4897
4898         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4899
4900         intel_runtime_pm_put(dev_priv);
4901         mutex_unlock(&dev_priv->dev->struct_mutex);
4902
4903         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4904
4905         return 0;
4906 }
4907
4908 static int
4909 i915_cache_sharing_set(void *data, u64 val)
4910 {
4911         struct drm_device *dev = data;
4912         struct drm_i915_private *dev_priv = dev->dev_private;
4913         u32 snpcr;
4914
4915         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4916                 return -ENODEV;
4917
4918         if (val > 3)
4919                 return -EINVAL;
4920
4921         intel_runtime_pm_get(dev_priv);
4922         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4923
4924         /* Update the cache sharing policy here as well */
4925         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4926         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4927         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4928         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4929
4930         intel_runtime_pm_put(dev_priv);
4931         return 0;
4932 }
4933
4934 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4935                         i915_cache_sharing_get, i915_cache_sharing_set,
4936                         "%llu\n");
4937
4938 struct sseu_dev_status {
4939         unsigned int slice_total;
4940         unsigned int subslice_total;
4941         unsigned int subslice_per_slice;
4942         unsigned int eu_total;
4943         unsigned int eu_per_subslice;
4944 };
4945
4946 static void cherryview_sseu_device_status(struct drm_device *dev,
4947                                           struct sseu_dev_status *stat)
4948 {
4949         struct drm_i915_private *dev_priv = dev->dev_private;
4950         int ss_max = 2;
4951         int ss;
4952         u32 sig1[ss_max], sig2[ss_max];
4953
4954         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4955         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4956         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4957         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4958
4959         for (ss = 0; ss < ss_max; ss++) {
4960                 unsigned int eu_cnt;
4961
4962                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4963                         /* skip disabled subslice */
4964                         continue;
4965
4966                 stat->slice_total = 1;
4967                 stat->subslice_per_slice++;
4968                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4969                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4970                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4971                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4972                 stat->eu_total += eu_cnt;
4973                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4974         }
4975         stat->subslice_total = stat->subslice_per_slice;
4976 }
4977
4978 static void gen9_sseu_device_status(struct drm_device *dev,
4979                                     struct sseu_dev_status *stat)
4980 {
4981         struct drm_i915_private *dev_priv = dev->dev_private;
4982         int s_max = 3, ss_max = 4;
4983         int s, ss;
4984         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4985
4986         /* BXT has a single slice and at most 3 subslices. */
4987         if (IS_BROXTON(dev)) {
4988                 s_max = 1;
4989                 ss_max = 3;
4990         }
4991
4992         for (s = 0; s < s_max; s++) {
4993                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4994                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4995                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4996         }
4997
4998         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4999                      GEN9_PGCTL_SSA_EU19_ACK |
5000                      GEN9_PGCTL_SSA_EU210_ACK |
5001                      GEN9_PGCTL_SSA_EU311_ACK;
5002         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5003                      GEN9_PGCTL_SSB_EU19_ACK |
5004                      GEN9_PGCTL_SSB_EU210_ACK |
5005                      GEN9_PGCTL_SSB_EU311_ACK;
5006
5007         for (s = 0; s < s_max; s++) {
5008                 unsigned int ss_cnt = 0;
5009
5010                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5011                         /* skip disabled slice */
5012                         continue;
5013
5014                 stat->slice_total++;
5015
5016                 if (IS_SKYLAKE(dev))
5017                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5018
5019                 for (ss = 0; ss < ss_max; ss++) {
5020                         unsigned int eu_cnt;
5021
5022                         if (IS_BROXTON(dev) &&
5023                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5024                                 /* skip disabled subslice */
5025                                 continue;
5026
5027                         if (IS_BROXTON(dev))
5028                                 ss_cnt++;
5029
5030                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5031                                                eu_mask[ss%2]);
5032                         stat->eu_total += eu_cnt;
5033                         stat->eu_per_subslice = max(stat->eu_per_subslice,
5034                                                     eu_cnt);
5035                 }
5036
5037                 stat->subslice_total += ss_cnt;
5038                 stat->subslice_per_slice = max(stat->subslice_per_slice,
5039                                                ss_cnt);
5040         }
5041 }
5042
5043 static int i915_sseu_status(struct seq_file *m, void *unused)
5044 {
5045         struct drm_info_node *node = (struct drm_info_node *) m->private;
5046         struct drm_device *dev = node->minor->dev;
5047         struct sseu_dev_status stat;
5048
5049         if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
5050                 return -ENODEV;
5051
5052         seq_puts(m, "SSEU Device Info\n");
5053         seq_printf(m, "  Available Slice Total: %u\n",
5054                    INTEL_INFO(dev)->slice_total);
5055         seq_printf(m, "  Available Subslice Total: %u\n",
5056                    INTEL_INFO(dev)->subslice_total);
5057         seq_printf(m, "  Available Subslice Per Slice: %u\n",
5058                    INTEL_INFO(dev)->subslice_per_slice);
5059         seq_printf(m, "  Available EU Total: %u\n",
5060                    INTEL_INFO(dev)->eu_total);
5061         seq_printf(m, "  Available EU Per Subslice: %u\n",
5062                    INTEL_INFO(dev)->eu_per_subslice);
5063         seq_printf(m, "  Has Slice Power Gating: %s\n",
5064                    yesno(INTEL_INFO(dev)->has_slice_pg));
5065         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5066                    yesno(INTEL_INFO(dev)->has_subslice_pg));
5067         seq_printf(m, "  Has EU Power Gating: %s\n",
5068                    yesno(INTEL_INFO(dev)->has_eu_pg));
5069
5070         seq_puts(m, "SSEU Device Status\n");
5071         memset(&stat, 0, sizeof(stat));
5072         if (IS_CHERRYVIEW(dev)) {
5073                 cherryview_sseu_device_status(dev, &stat);
5074         } else if (INTEL_INFO(dev)->gen >= 9) {
5075                 gen9_sseu_device_status(dev, &stat);
5076         }
5077         seq_printf(m, "  Enabled Slice Total: %u\n",
5078                    stat.slice_total);
5079         seq_printf(m, "  Enabled Subslice Total: %u\n",
5080                    stat.subslice_total);
5081         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
5082                    stat.subslice_per_slice);
5083         seq_printf(m, "  Enabled EU Total: %u\n",
5084                    stat.eu_total);
5085         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
5086                    stat.eu_per_subslice);
5087
5088         return 0;
5089 }
5090
5091 static int i915_forcewake_open(struct inode *inode, struct file *file)
5092 {
5093         struct drm_device *dev = inode->i_private;
5094         struct drm_i915_private *dev_priv = dev->dev_private;
5095
5096         if (INTEL_INFO(dev)->gen < 6)
5097                 return 0;
5098
5099         intel_runtime_pm_get(dev_priv);
5100         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5101
5102         return 0;
5103 }
5104
5105 static int i915_forcewake_release(struct inode *inode, struct file *file)
5106 {
5107         struct drm_device *dev = inode->i_private;
5108         struct drm_i915_private *dev_priv = dev->dev_private;
5109
5110         if (INTEL_INFO(dev)->gen < 6)
5111                 return 0;
5112
5113         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5114         intel_runtime_pm_put(dev_priv);
5115
5116         return 0;
5117 }
5118
5119 static const struct file_operations i915_forcewake_fops = {
5120         .owner = THIS_MODULE,
5121         .open = i915_forcewake_open,
5122         .release = i915_forcewake_release,
5123 };
5124
5125 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5126 {
5127         struct drm_device *dev = minor->dev;
5128         struct dentry *ent;
5129
5130         ent = debugfs_create_file("i915_forcewake_user",
5131                                   S_IRUSR,
5132                                   root, dev,
5133                                   &i915_forcewake_fops);
5134         if (!ent)
5135                 return -ENOMEM;
5136
5137         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5138 }
5139
5140 static int i915_debugfs_create(struct dentry *root,
5141                                struct drm_minor *minor,
5142                                const char *name,
5143                                const struct file_operations *fops)
5144 {
5145         struct drm_device *dev = minor->dev;
5146         struct dentry *ent;
5147
5148         ent = debugfs_create_file(name,
5149                                   S_IRUGO | S_IWUSR,
5150                                   root, dev,
5151                                   fops);
5152         if (!ent)
5153                 return -ENOMEM;
5154
5155         return drm_add_fake_info_node(minor, ent, fops);
5156 }
5157
5158 static const struct drm_info_list i915_debugfs_list[] = {
5159         {"i915_capabilities", i915_capabilities, 0},
5160         {"i915_gem_objects", i915_gem_object_info, 0},
5161         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5162         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5163         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5164         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5165         {"i915_gem_stolen", i915_gem_stolen_list_info },
5166         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5167         {"i915_gem_request", i915_gem_request_info, 0},
5168         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5169         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5170         {"i915_gem_interrupt", i915_interrupt_info, 0},
5171         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5172         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5173         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5174         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5175         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5176         {"i915_guc_info", i915_guc_info, 0},
5177         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5178         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5179         {"i915_frequency_info", i915_frequency_info, 0},
5180         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5181         {"i915_drpc_info", i915_drpc_info, 0},
5182         {"i915_emon_status", i915_emon_status, 0},
5183         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5184         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5185         {"i915_fbc_status", i915_fbc_status, 0},
5186         {"i915_ips_status", i915_ips_status, 0},
5187         {"i915_sr_status", i915_sr_status, 0},
5188         {"i915_opregion", i915_opregion, 0},
5189         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5190         {"i915_context_status", i915_context_status, 0},
5191         {"i915_dump_lrc", i915_dump_lrc, 0},
5192         {"i915_execlists", i915_execlists, 0},
5193         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5194         {"i915_swizzle_info", i915_swizzle_info, 0},
5195         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5196         {"i915_llc", i915_llc, 0},
5197         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5198         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5199         {"i915_energy_uJ", i915_energy_uJ, 0},
5200         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5201         {"i915_power_domain_info", i915_power_domain_info, 0},
5202         {"i915_display_info", i915_display_info, 0},
5203         {"i915_semaphore_status", i915_semaphore_status, 0},
5204         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5205         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5206         {"i915_wa_registers", i915_wa_registers, 0},
5207         {"i915_ddb_info", i915_ddb_info, 0},
5208         {"i915_sseu_status", i915_sseu_status, 0},
5209         {"i915_drrs_status", i915_drrs_status, 0},
5210         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5211 };
5212 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5213
5214 static const struct i915_debugfs_files {
5215         const char *name;
5216         const struct file_operations *fops;
5217 } i915_debugfs_files[] = {
5218         {"i915_wedged", &i915_wedged_fops},
5219         {"i915_max_freq", &i915_max_freq_fops},
5220         {"i915_min_freq", &i915_min_freq_fops},
5221         {"i915_cache_sharing", &i915_cache_sharing_fops},
5222         {"i915_ring_stop", &i915_ring_stop_fops},
5223         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5224         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5225         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5226         {"i915_error_state", &i915_error_state_fops},
5227         {"i915_next_seqno", &i915_next_seqno_fops},
5228         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5229         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5230         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5231         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5232         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5233         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5234         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5235         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5236 };
5237
5238 void intel_display_crc_init(struct drm_device *dev)
5239 {
5240         struct drm_i915_private *dev_priv = dev->dev_private;
5241         enum pipe pipe;
5242
5243         for_each_pipe(dev_priv, pipe) {
5244                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5245
5246                 pipe_crc->opened = false;
5247                 spin_lock_init(&pipe_crc->lock);
5248                 init_waitqueue_head(&pipe_crc->wq);
5249         }
5250 }
5251
5252 int i915_debugfs_init(struct drm_minor *minor)
5253 {
5254         int ret, i;
5255
5256         ret = i915_forcewake_create(minor->debugfs_root, minor);
5257         if (ret)
5258                 return ret;
5259
5260         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5261                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5262                 if (ret)
5263                         return ret;
5264         }
5265
5266         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5267                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5268                                           i915_debugfs_files[i].name,
5269                                           i915_debugfs_files[i].fops);
5270                 if (ret)
5271                         return ret;
5272         }
5273
5274         return drm_debugfs_create_files(i915_debugfs_list,
5275                                         I915_DEBUGFS_ENTRIES,
5276                                         minor->debugfs_root, minor);
5277 }
5278
5279 void i915_debugfs_cleanup(struct drm_minor *minor)
5280 {
5281         int i;
5282
5283         drm_debugfs_remove_files(i915_debugfs_list,
5284                                  I915_DEBUGFS_ENTRIES, minor);
5285
5286         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5287                                  1, minor);
5288
5289         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5290                 struct drm_info_list *info_list =
5291                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5292
5293                 drm_debugfs_remove_files(info_list, 1, minor);
5294         }
5295
5296         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5297                 struct drm_info_list *info_list =
5298                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5299
5300                 drm_debugfs_remove_files(info_list, 1, minor);
5301         }
5302 }
5303
5304 struct dpcd_block {
5305         /* DPCD dump start address. */
5306         unsigned int offset;
5307         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5308         unsigned int end;
5309         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5310         size_t size;
5311         /* Only valid for eDP. */
5312         bool edp;
5313 };
5314
5315 static const struct dpcd_block i915_dpcd_debug[] = {
5316         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5317         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5318         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5319         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5320         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5321         { .offset = DP_SET_POWER },
5322         { .offset = DP_EDP_DPCD_REV },
5323         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5324         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5325         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5326 };
5327
5328 static int i915_dpcd_show(struct seq_file *m, void *data)
5329 {
5330         struct drm_connector *connector = m->private;
5331         struct intel_dp *intel_dp =
5332                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5333         uint8_t buf[16];
5334         ssize_t err;
5335         int i;
5336
5337         if (connector->status != connector_status_connected)
5338                 return -ENODEV;
5339
5340         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5341                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5342                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5343
5344                 if (b->edp &&
5345                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5346                         continue;
5347
5348                 /* low tech for now */
5349                 if (WARN_ON(size > sizeof(buf)))
5350                         continue;
5351
5352                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5353                 if (err <= 0) {
5354                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5355                                   size, b->offset, err);
5356                         continue;
5357                 }
5358
5359                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5360         }
5361
5362         return 0;
5363 }
5364
5365 static int i915_dpcd_open(struct inode *inode, struct file *file)
5366 {
5367         return single_open(file, i915_dpcd_show, inode->i_private);
5368 }
5369
5370 static const struct file_operations i915_dpcd_fops = {
5371         .owner = THIS_MODULE,
5372         .open = i915_dpcd_open,
5373         .read = seq_read,
5374         .llseek = seq_lseek,
5375         .release = single_release,
5376 };
5377
5378 /**
5379  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5380  * @connector: pointer to a registered drm_connector
5381  *
5382  * Cleanup will be done by drm_connector_unregister() through a call to
5383  * drm_debugfs_connector_remove().
5384  *
5385  * Returns 0 on success, negative error codes on error.
5386  */
5387 int i915_debugfs_connector_add(struct drm_connector *connector)
5388 {
5389         struct dentry *root = connector->debugfs_entry;
5390
5391         /* The connector must have been registered beforehands. */
5392         if (!root)
5393                 return -ENODEV;
5394
5395         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5396             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5397                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5398                                     &i915_dpcd_fops);
5399
5400         return 0;
5401 }