2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_2_4_d.h"
33 #include "oss/oss_2_4_sh_mask.h"
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "iceland_sdma_pkt_open.h"
47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
57 SDMA0_REGISTER_OFFSET,
61 static const u32 golden_settings_iceland_a11[] =
63 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
64 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
65 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
66 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
69 static const u32 iceland_mgcg_cgcg_init[] =
71 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
72 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
77 * Starting with CIK, the GPU has new asynchronous
78 * DMA engines. These engines are used for compute
79 * and gfx. There are two DMA engines (SDMA0, SDMA1)
80 * and each one supports 1 ring buffer used for gfx
81 * and 2 queues used for compute.
83 * The programming model is very similar to the CP
84 * (ring buffer, IBs, etc.), but sDMA has it's own
85 * packet format that is different from the PM4 format
86 * used by the CP. sDMA supports copying data, writing
87 * embedded data, solid fills, and a number of other
88 * things. It also has support for tiling/detiling of
92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
94 switch (adev->asic_type) {
96 amdgpu_program_register_sequence(adev,
97 iceland_mgcg_cgcg_init,
98 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
99 amdgpu_program_register_sequence(adev,
100 golden_settings_iceland_a11,
101 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
109 * sdma_v2_4_init_microcode - load ucode images from disk
111 * @adev: amdgpu_device pointer
113 * Use the firmware interface to load the ucode images into
114 * the driver (not loaded into hw).
115 * Returns 0 on success, error on failure.
117 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
119 const char *chip_name;
122 struct amdgpu_firmware_info *info = NULL;
123 const struct common_firmware_header *header = NULL;
124 const struct sdma_firmware_header_v1_0 *hdr;
128 switch (adev->asic_type) {
135 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
137 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
139 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
140 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
143 err = amdgpu_ucode_validate(adev->sdma[i].fw);
146 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
147 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
148 adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
150 if (adev->firmware.smu_load) {
151 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
152 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
153 info->fw = adev->sdma[i].fw;
154 header = (const struct common_firmware_header *)info->fw->data;
155 adev->firmware.fw_size +=
156 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
163 "sdma_v2_4: Failed to load firmware \"%s\"\n",
165 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
166 release_firmware(adev->sdma[i].fw);
167 adev->sdma[i].fw = NULL;
174 * sdma_v2_4_ring_get_rptr - get the current read pointer
176 * @ring: amdgpu ring pointer
178 * Get the current rptr from the hardware (VI+).
180 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
184 /* XXX check if swapping is necessary on BE */
185 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
191 * sdma_v2_4_ring_get_wptr - get the current write pointer
193 * @ring: amdgpu ring pointer
195 * Get the current wptr from the hardware (VI+).
197 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
199 struct amdgpu_device *adev = ring->adev;
200 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
201 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
207 * sdma_v2_4_ring_set_wptr - commit the write pointer
209 * @ring: amdgpu ring pointer
211 * Write the wptr back to the hardware (VI+).
213 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
215 struct amdgpu_device *adev = ring->adev;
216 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
218 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
222 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
224 * @ring: amdgpu ring pointer
225 * @ib: IB object to schedule
227 * Schedule an IB in the DMA ring (VI).
229 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
230 struct amdgpu_ib *ib)
232 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
233 u32 next_rptr = ring->wptr + 5;
235 while ((next_rptr & 7) != 2)
240 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
241 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
242 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
243 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
244 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
245 amdgpu_ring_write(ring, next_rptr);
247 /* IB packet must end on a 8 DW boundary */
248 while ((ring->wptr & 7) != 2)
249 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP));
250 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
251 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
252 /* base must be 32 byte aligned */
253 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
254 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
255 amdgpu_ring_write(ring, ib->length_dw);
256 amdgpu_ring_write(ring, 0);
257 amdgpu_ring_write(ring, 0);
262 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
264 * @ring: amdgpu ring pointer
266 * Emit an hdp flush packet on the requested DMA ring.
268 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
270 u32 ref_and_mask = 0;
272 if (ring == &ring->adev->sdma[0].ring)
273 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
275 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
277 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
278 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
279 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
280 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
281 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
282 amdgpu_ring_write(ring, ref_and_mask); /* reference */
283 amdgpu_ring_write(ring, ref_and_mask); /* mask */
284 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
285 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
289 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
291 * @ring: amdgpu ring pointer
292 * @fence: amdgpu fence object
294 * Add a DMA fence packet to the ring to write
295 * the fence seq number and DMA trap packet to generate
296 * an interrupt if needed (VI).
298 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
301 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
302 /* write the fence */
303 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
304 amdgpu_ring_write(ring, lower_32_bits(addr));
305 amdgpu_ring_write(ring, upper_32_bits(addr));
306 amdgpu_ring_write(ring, lower_32_bits(seq));
308 /* optionally write high bits as well */
311 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
312 amdgpu_ring_write(ring, lower_32_bits(addr));
313 amdgpu_ring_write(ring, upper_32_bits(addr));
314 amdgpu_ring_write(ring, upper_32_bits(seq));
317 /* generate an interrupt */
318 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
319 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
323 * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring
325 * @ring: amdgpu_ring structure holding ring information
326 * @semaphore: amdgpu semaphore object
327 * @emit_wait: wait or signal semaphore
329 * Add a DMA semaphore packet to the ring wait on or signal
332 static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring,
333 struct amdgpu_semaphore *semaphore,
336 u64 addr = semaphore->gpu_addr;
337 u32 sig = emit_wait ? 0 : 1;
339 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
340 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
341 amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
342 amdgpu_ring_write(ring, upper_32_bits(addr));
348 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
350 * @adev: amdgpu_device pointer
352 * Stop the gfx async dma ring buffers (VI).
354 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
356 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
357 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
358 u32 rb_cntl, ib_cntl;
361 if ((adev->mman.buffer_funcs_ring == sdma0) ||
362 (adev->mman.buffer_funcs_ring == sdma1))
363 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
365 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
366 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
367 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
368 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
369 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
370 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
371 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
373 sdma0->ready = false;
374 sdma1->ready = false;
378 * sdma_v2_4_rlc_stop - stop the compute async dma engines
380 * @adev: amdgpu_device pointer
382 * Stop the compute async dma queues (VI).
384 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
390 * sdma_v2_4_enable - stop the async dma engines
392 * @adev: amdgpu_device pointer
393 * @enable: enable/disable the DMA MEs.
395 * Halt or unhalt the async dma engines (VI).
397 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
402 if (enable == false) {
403 sdma_v2_4_gfx_stop(adev);
404 sdma_v2_4_rlc_stop(adev);
407 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
408 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
410 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
412 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
413 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
418 * sdma_v2_4_gfx_resume - setup and start the async dma engines
420 * @adev: amdgpu_device pointer
422 * Set up the gfx DMA ring buffers and enable them (VI).
423 * Returns 0 for success, error for failure.
425 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
427 struct amdgpu_ring *ring;
428 u32 rb_cntl, ib_cntl;
433 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
434 ring = &adev->sdma[i].ring;
435 wb_offset = (ring->rptr_offs * 4);
437 mutex_lock(&adev->srbm_mutex);
438 for (j = 0; j < 16; j++) {
439 vi_srbm_select(adev, 0, 0, 0, j);
441 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
442 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
444 vi_srbm_select(adev, 0, 0, 0, 0);
445 mutex_unlock(&adev->srbm_mutex);
447 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
449 /* Set ring buffer size in dwords */
450 rb_bufsz = order_base_2(ring->ring_size / 4);
451 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
452 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
454 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
455 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
456 RPTR_WRITEBACK_SWAP_ENABLE, 1);
458 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
460 /* Initialize the ring buffer's read and write pointers */
461 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
462 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
464 /* set the wb address whether it's enabled or not */
465 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
466 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
467 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
468 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
470 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
472 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
473 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
476 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
479 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
480 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
482 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
483 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
485 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
488 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
492 r = amdgpu_ring_test_ring(ring);
498 if (adev->mman.buffer_funcs_ring == ring)
499 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
506 * sdma_v2_4_rlc_resume - setup and start the async dma engines
508 * @adev: amdgpu_device pointer
510 * Set up the compute DMA queues and enable them (VI).
511 * Returns 0 for success, error for failure.
513 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
520 * sdma_v2_4_load_microcode - load the sDMA ME ucode
522 * @adev: amdgpu_device pointer
524 * Loads the sDMA0/1 ucode.
525 * Returns 0 for success, -EINVAL if the ucode is not available.
527 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
529 const struct sdma_firmware_header_v1_0 *hdr;
530 const __le32 *fw_data;
533 bool smc_loads_fw = false; /* XXX fix me */
535 if (!adev->sdma[0].fw || !adev->sdma[1].fw)
539 sdma_v2_4_enable(adev, false);
542 /* XXX query SMC for fw load complete */
544 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
545 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
546 amdgpu_ucode_print_sdma_hdr(&hdr->header);
547 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
548 fw_data = (const __le32 *)
549 (adev->sdma[i].fw->data +
550 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
551 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
552 for (j = 0; j < fw_size; j++)
553 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
554 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
562 * sdma_v2_4_start - setup and start the async dma engines
564 * @adev: amdgpu_device pointer
566 * Set up the DMA engines and enable them (VI).
567 * Returns 0 for success, error for failure.
569 static int sdma_v2_4_start(struct amdgpu_device *adev)
573 if (!adev->firmware.smu_load) {
574 r = sdma_v2_4_load_microcode(adev);
578 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
579 AMDGPU_UCODE_ID_SDMA0);
582 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
583 AMDGPU_UCODE_ID_SDMA1);
589 sdma_v2_4_enable(adev, true);
591 /* start the gfx rings and rlc compute queues */
592 r = sdma_v2_4_gfx_resume(adev);
595 r = sdma_v2_4_rlc_resume(adev);
603 * sdma_v2_4_ring_test_ring - simple async dma engine test
605 * @ring: amdgpu_ring structure holding ring information
607 * Test the DMA engine by writing using it to write an
608 * value to memory. (VI).
609 * Returns 0 for success, error for failure.
611 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
613 struct amdgpu_device *adev = ring->adev;
620 r = amdgpu_wb_get(adev, &index);
622 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
626 gpu_addr = adev->wb.gpu_addr + (index * 4);
628 adev->wb.wb[index] = cpu_to_le32(tmp);
630 r = amdgpu_ring_lock(ring, 5);
632 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
633 amdgpu_wb_free(adev, index);
637 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
638 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
639 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
640 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
641 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
642 amdgpu_ring_write(ring, 0xDEADBEEF);
643 amdgpu_ring_unlock_commit(ring);
645 for (i = 0; i < adev->usec_timeout; i++) {
646 tmp = le32_to_cpu(adev->wb.wb[index]);
647 if (tmp == 0xDEADBEEF)
652 if (i < adev->usec_timeout) {
653 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
655 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
659 amdgpu_wb_free(adev, index);
665 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
667 * @ring: amdgpu_ring structure holding ring information
669 * Test a simple IB in the DMA ring (VI).
670 * Returns 0 on success, error on failure.
672 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
674 struct amdgpu_device *adev = ring->adev;
682 r = amdgpu_wb_get(adev, &index);
684 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
688 gpu_addr = adev->wb.gpu_addr + (index * 4);
690 adev->wb.wb[index] = cpu_to_le32(tmp);
692 r = amdgpu_ib_get(ring, NULL, 256, &ib);
694 amdgpu_wb_free(adev, index);
695 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
699 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
700 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
701 ib.ptr[1] = lower_32_bits(gpu_addr);
702 ib.ptr[2] = upper_32_bits(gpu_addr);
703 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
704 ib.ptr[4] = 0xDEADBEEF;
705 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
706 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
707 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
710 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
712 amdgpu_ib_free(adev, &ib);
713 amdgpu_wb_free(adev, index);
714 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
717 r = amdgpu_fence_wait(ib.fence, false);
719 amdgpu_ib_free(adev, &ib);
720 amdgpu_wb_free(adev, index);
721 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
724 for (i = 0; i < adev->usec_timeout; i++) {
725 tmp = le32_to_cpu(adev->wb.wb[index]);
726 if (tmp == 0xDEADBEEF)
730 if (i < adev->usec_timeout) {
731 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
732 ib.fence->ring->idx, i);
734 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
737 amdgpu_ib_free(adev, &ib);
738 amdgpu_wb_free(adev, index);
743 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
745 * @ib: indirect buffer to fill with commands
746 * @pe: addr of the page entry
747 * @src: src addr to copy from
748 * @count: number of page entries to update
750 * Update PTEs by copying them from the GART using sDMA (CIK).
752 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
753 uint64_t pe, uint64_t src,
757 unsigned bytes = count * 8;
758 if (bytes > 0x1FFFF8)
761 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
762 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
763 ib->ptr[ib->length_dw++] = bytes;
764 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
765 ib->ptr[ib->length_dw++] = lower_32_bits(src);
766 ib->ptr[ib->length_dw++] = upper_32_bits(src);
767 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
768 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
777 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
779 * @ib: indirect buffer to fill with commands
780 * @pe: addr of the page entry
781 * @addr: dst addr to write into pe
782 * @count: number of page entries to update
783 * @incr: increase next addr by incr bytes
784 * @flags: access flags
786 * Update PTEs by writing them manually using sDMA (CIK).
788 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
790 uint64_t addr, unsigned count,
791 uint32_t incr, uint32_t flags)
801 /* for non-physically contiguous pages (system) */
802 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
803 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
804 ib->ptr[ib->length_dw++] = pe;
805 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
806 ib->ptr[ib->length_dw++] = ndw;
807 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
808 if (flags & AMDGPU_PTE_SYSTEM) {
809 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
810 value &= 0xFFFFFFFFFFFFF000ULL;
811 } else if (flags & AMDGPU_PTE_VALID) {
818 ib->ptr[ib->length_dw++] = value;
819 ib->ptr[ib->length_dw++] = upper_32_bits(value);
825 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
827 * @ib: indirect buffer to fill with commands
828 * @pe: addr of the page entry
829 * @addr: dst addr to write into pe
830 * @count: number of page entries to update
831 * @incr: increase next addr by incr bytes
832 * @flags: access flags
834 * Update the page tables using sDMA (CIK).
836 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
838 uint64_t addr, unsigned count,
839 uint32_t incr, uint32_t flags)
849 if (flags & AMDGPU_PTE_VALID)
854 /* for physically contiguous pages (vram) */
855 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
856 ib->ptr[ib->length_dw++] = pe; /* dst addr */
857 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
858 ib->ptr[ib->length_dw++] = flags; /* mask */
859 ib->ptr[ib->length_dw++] = 0;
860 ib->ptr[ib->length_dw++] = value; /* value */
861 ib->ptr[ib->length_dw++] = upper_32_bits(value);
862 ib->ptr[ib->length_dw++] = incr; /* increment size */
863 ib->ptr[ib->length_dw++] = 0;
864 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
873 * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw
875 * @ib: indirect buffer to fill with padding
878 static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
880 while (ib->length_dw & 0x7)
881 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
885 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
887 * @ring: amdgpu_ring pointer
888 * @vm: amdgpu_vm pointer
890 * Update the page table base and flush the VM TLB
893 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
894 unsigned vm_id, uint64_t pd_addr)
896 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
897 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
899 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
901 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
903 amdgpu_ring_write(ring, pd_addr >> 12);
906 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
907 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
908 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
909 amdgpu_ring_write(ring, 1 << vm_id);
912 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
913 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
914 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
915 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
916 amdgpu_ring_write(ring, 0);
917 amdgpu_ring_write(ring, 0); /* reference */
918 amdgpu_ring_write(ring, 0); /* mask */
919 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
920 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
923 static int sdma_v2_4_early_init(void *handle)
925 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
927 sdma_v2_4_set_ring_funcs(adev);
928 sdma_v2_4_set_buffer_funcs(adev);
929 sdma_v2_4_set_vm_pte_funcs(adev);
930 sdma_v2_4_set_irq_funcs(adev);
935 static int sdma_v2_4_sw_init(void *handle)
937 struct amdgpu_ring *ring;
939 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
941 /* SDMA trap event */
942 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
946 /* SDMA Privileged inst */
947 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
951 /* SDMA Privileged inst */
952 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
956 r = sdma_v2_4_init_microcode(adev);
958 DRM_ERROR("Failed to load sdma firmware!\n");
962 ring = &adev->sdma[0].ring;
963 ring->ring_obj = NULL;
964 ring->use_doorbell = false;
966 ring = &adev->sdma[1].ring;
967 ring->ring_obj = NULL;
968 ring->use_doorbell = false;
970 ring = &adev->sdma[0].ring;
971 sprintf(ring->name, "sdma0");
972 r = amdgpu_ring_init(adev, ring, 256 * 1024,
973 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
974 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
975 AMDGPU_RING_TYPE_SDMA);
979 ring = &adev->sdma[1].ring;
980 sprintf(ring->name, "sdma1");
981 r = amdgpu_ring_init(adev, ring, 256 * 1024,
982 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
983 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
984 AMDGPU_RING_TYPE_SDMA);
991 static int sdma_v2_4_sw_fini(void *handle)
993 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
995 amdgpu_ring_fini(&adev->sdma[0].ring);
996 amdgpu_ring_fini(&adev->sdma[1].ring);
1001 static int sdma_v2_4_hw_init(void *handle)
1004 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1006 sdma_v2_4_init_golden_registers(adev);
1008 r = sdma_v2_4_start(adev);
1015 static int sdma_v2_4_hw_fini(void *handle)
1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1019 sdma_v2_4_enable(adev, false);
1024 static int sdma_v2_4_suspend(void *handle)
1026 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1028 return sdma_v2_4_hw_fini(adev);
1031 static int sdma_v2_4_resume(void *handle)
1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035 return sdma_v2_4_hw_init(adev);
1038 static bool sdma_v2_4_is_idle(void *handle)
1040 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041 u32 tmp = RREG32(mmSRBM_STATUS2);
1043 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1044 SRBM_STATUS2__SDMA1_BUSY_MASK))
1050 static int sdma_v2_4_wait_for_idle(void *handle)
1054 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1056 for (i = 0; i < adev->usec_timeout; i++) {
1057 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1058 SRBM_STATUS2__SDMA1_BUSY_MASK);
1067 static void sdma_v2_4_print_status(void *handle)
1070 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1072 dev_info(adev->dev, "VI SDMA registers\n");
1073 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1074 RREG32(mmSRBM_STATUS2));
1075 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1076 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1077 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1078 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
1079 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1080 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1081 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1082 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1083 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1084 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1085 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1086 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1087 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1088 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1089 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1090 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1091 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1092 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1093 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1094 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1095 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1096 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1097 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1098 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1099 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1100 mutex_lock(&adev->srbm_mutex);
1101 for (j = 0; j < 16; j++) {
1102 vi_srbm_select(adev, 0, 0, 0, j);
1103 dev_info(adev->dev, " VM %d:\n", j);
1104 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1105 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1106 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1107 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1109 vi_srbm_select(adev, 0, 0, 0, 0);
1110 mutex_unlock(&adev->srbm_mutex);
1114 static int sdma_v2_4_soft_reset(void *handle)
1116 u32 srbm_soft_reset = 0;
1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1118 u32 tmp = RREG32(mmSRBM_STATUS2);
1120 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1122 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1123 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1124 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1125 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1127 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1129 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1130 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1131 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1132 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1135 if (srbm_soft_reset) {
1136 sdma_v2_4_print_status((void *)adev);
1138 tmp = RREG32(mmSRBM_SOFT_RESET);
1139 tmp |= srbm_soft_reset;
1140 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1141 WREG32(mmSRBM_SOFT_RESET, tmp);
1142 tmp = RREG32(mmSRBM_SOFT_RESET);
1146 tmp &= ~srbm_soft_reset;
1147 WREG32(mmSRBM_SOFT_RESET, tmp);
1148 tmp = RREG32(mmSRBM_SOFT_RESET);
1150 /* Wait a little for things to settle down */
1153 sdma_v2_4_print_status((void *)adev);
1159 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1160 struct amdgpu_irq_src *src,
1162 enum amdgpu_interrupt_state state)
1167 case AMDGPU_SDMA_IRQ_TRAP0:
1169 case AMDGPU_IRQ_STATE_DISABLE:
1170 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1171 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1172 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1174 case AMDGPU_IRQ_STATE_ENABLE:
1175 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1176 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1177 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1183 case AMDGPU_SDMA_IRQ_TRAP1:
1185 case AMDGPU_IRQ_STATE_DISABLE:
1186 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1187 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1188 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1190 case AMDGPU_IRQ_STATE_ENABLE:
1191 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1192 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1193 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1205 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1206 struct amdgpu_irq_src *source,
1207 struct amdgpu_iv_entry *entry)
1209 u8 instance_id, queue_id;
1211 instance_id = (entry->ring_id & 0x3) >> 0;
1212 queue_id = (entry->ring_id & 0xc) >> 2;
1213 DRM_DEBUG("IH: SDMA trap\n");
1214 switch (instance_id) {
1218 amdgpu_fence_process(&adev->sdma[0].ring);
1231 amdgpu_fence_process(&adev->sdma[1].ring);
1245 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1246 struct amdgpu_irq_src *source,
1247 struct amdgpu_iv_entry *entry)
1249 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1250 schedule_work(&adev->reset_work);
1254 static int sdma_v2_4_set_clockgating_state(void *handle,
1255 enum amd_clockgating_state state)
1257 /* XXX handled via the smc on VI */
1261 static int sdma_v2_4_set_powergating_state(void *handle,
1262 enum amd_powergating_state state)
1267 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1268 .early_init = sdma_v2_4_early_init,
1270 .sw_init = sdma_v2_4_sw_init,
1271 .sw_fini = sdma_v2_4_sw_fini,
1272 .hw_init = sdma_v2_4_hw_init,
1273 .hw_fini = sdma_v2_4_hw_fini,
1274 .suspend = sdma_v2_4_suspend,
1275 .resume = sdma_v2_4_resume,
1276 .is_idle = sdma_v2_4_is_idle,
1277 .wait_for_idle = sdma_v2_4_wait_for_idle,
1278 .soft_reset = sdma_v2_4_soft_reset,
1279 .print_status = sdma_v2_4_print_status,
1280 .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1281 .set_powergating_state = sdma_v2_4_set_powergating_state,
1285 * sdma_v2_4_ring_is_lockup - Check if the DMA engine is locked up
1287 * @ring: amdgpu_ring structure holding ring information
1289 * Check if the async DMA engine is locked up (VI).
1290 * Returns true if the engine appears to be locked up, false if not.
1292 static bool sdma_v2_4_ring_is_lockup(struct amdgpu_ring *ring)
1295 if (sdma_v2_4_is_idle(ring->adev)) {
1296 amdgpu_ring_lockup_update(ring);
1299 return amdgpu_ring_test_lockup(ring);
1302 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1303 .get_rptr = sdma_v2_4_ring_get_rptr,
1304 .get_wptr = sdma_v2_4_ring_get_wptr,
1305 .set_wptr = sdma_v2_4_ring_set_wptr,
1307 .emit_ib = sdma_v2_4_ring_emit_ib,
1308 .emit_fence = sdma_v2_4_ring_emit_fence,
1309 .emit_semaphore = sdma_v2_4_ring_emit_semaphore,
1310 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1311 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1312 .test_ring = sdma_v2_4_ring_test_ring,
1313 .test_ib = sdma_v2_4_ring_test_ib,
1314 .is_lockup = sdma_v2_4_ring_is_lockup,
1317 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1319 adev->sdma[0].ring.funcs = &sdma_v2_4_ring_funcs;
1320 adev->sdma[1].ring.funcs = &sdma_v2_4_ring_funcs;
1323 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1324 .set = sdma_v2_4_set_trap_irq_state,
1325 .process = sdma_v2_4_process_trap_irq,
1328 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1329 .process = sdma_v2_4_process_illegal_inst_irq,
1332 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1334 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1335 adev->sdma_trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1336 adev->sdma_illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1340 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1342 * @ring: amdgpu_ring structure holding ring information
1343 * @src_offset: src GPU address
1344 * @dst_offset: dst GPU address
1345 * @byte_count: number of bytes to xfer
1347 * Copy GPU buffers using the DMA engine (VI).
1348 * Used by the amdgpu ttm implementation to move pages if
1349 * registered as the asic copy callback.
1351 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ring *ring,
1352 uint64_t src_offset,
1353 uint64_t dst_offset,
1354 uint32_t byte_count)
1356 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1357 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR));
1358 amdgpu_ring_write(ring, byte_count);
1359 amdgpu_ring_write(ring, 0); /* src/dst endian swap */
1360 amdgpu_ring_write(ring, lower_32_bits(src_offset));
1361 amdgpu_ring_write(ring, upper_32_bits(src_offset));
1362 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1363 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1367 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1369 * @ring: amdgpu_ring structure holding ring information
1370 * @src_data: value to write to buffer
1371 * @dst_offset: dst GPU address
1372 * @byte_count: number of bytes to xfer
1374 * Fill GPU buffers using the DMA engine (VI).
1376 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ring *ring,
1378 uint64_t dst_offset,
1379 uint32_t byte_count)
1381 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL));
1382 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1383 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1384 amdgpu_ring_write(ring, src_data);
1385 amdgpu_ring_write(ring, byte_count);
1388 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1389 .copy_max_bytes = 0x1fffff,
1391 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1393 .fill_max_bytes = 0x1fffff,
1395 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1398 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1400 if (adev->mman.buffer_funcs == NULL) {
1401 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1402 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1406 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1407 .copy_pte = sdma_v2_4_vm_copy_pte,
1408 .write_pte = sdma_v2_4_vm_write_pte,
1409 .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1410 .pad_ib = sdma_v2_4_vm_pad_ib,
1413 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1415 if (adev->vm_manager.vm_pte_funcs == NULL) {
1416 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1417 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;