2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_2_4_d.h"
33 #include "oss/oss_2_4_sh_mask.h"
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "iceland_sdma_pkt_open.h"
47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
57 SDMA0_REGISTER_OFFSET,
61 static const u32 golden_settings_iceland_a11[] =
63 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
64 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
65 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
66 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
69 static const u32 iceland_mgcg_cgcg_init[] =
71 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
72 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
77 * Starting with CIK, the GPU has new asynchronous
78 * DMA engines. These engines are used for compute
79 * and gfx. There are two DMA engines (SDMA0, SDMA1)
80 * and each one supports 1 ring buffer used for gfx
81 * and 2 queues used for compute.
83 * The programming model is very similar to the CP
84 * (ring buffer, IBs, etc.), but sDMA has it's own
85 * packet format that is different from the PM4 format
86 * used by the CP. sDMA supports copying data, writing
87 * embedded data, solid fills, and a number of other
88 * things. It also has support for tiling/detiling of
92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
94 switch (adev->asic_type) {
96 amdgpu_program_register_sequence(adev,
97 iceland_mgcg_cgcg_init,
98 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
99 amdgpu_program_register_sequence(adev,
100 golden_settings_iceland_a11,
101 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
109 * sdma_v2_4_init_microcode - load ucode images from disk
111 * @adev: amdgpu_device pointer
113 * Use the firmware interface to load the ucode images into
114 * the driver (not loaded into hw).
115 * Returns 0 on success, error on failure.
117 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
119 const char *chip_name;
122 struct amdgpu_firmware_info *info = NULL;
123 const struct common_firmware_header *header = NULL;
127 switch (adev->asic_type) {
134 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
136 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
138 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
139 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
142 err = amdgpu_ucode_validate(adev->sdma[i].fw);
146 if (adev->firmware.smu_load) {
147 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
148 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
149 info->fw = adev->sdma[i].fw;
150 header = (const struct common_firmware_header *)info->fw->data;
151 adev->firmware.fw_size +=
152 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
159 "sdma_v2_4: Failed to load firmware \"%s\"\n",
161 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
162 release_firmware(adev->sdma[i].fw);
163 adev->sdma[i].fw = NULL;
170 * sdma_v2_4_ring_get_rptr - get the current read pointer
172 * @ring: amdgpu ring pointer
174 * Get the current rptr from the hardware (VI+).
176 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
180 /* XXX check if swapping is necessary on BE */
181 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
187 * sdma_v2_4_ring_get_wptr - get the current write pointer
189 * @ring: amdgpu ring pointer
191 * Get the current wptr from the hardware (VI+).
193 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
195 struct amdgpu_device *adev = ring->adev;
196 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
197 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
203 * sdma_v2_4_ring_set_wptr - commit the write pointer
205 * @ring: amdgpu ring pointer
207 * Write the wptr back to the hardware (VI+).
209 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
211 struct amdgpu_device *adev = ring->adev;
212 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
214 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
218 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
220 * @ring: amdgpu ring pointer
221 * @ib: IB object to schedule
223 * Schedule an IB in the DMA ring (VI).
225 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
226 struct amdgpu_ib *ib)
228 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
229 u32 next_rptr = ring->wptr + 5;
231 while ((next_rptr & 7) != 2)
236 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
237 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
238 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
239 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
240 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
241 amdgpu_ring_write(ring, next_rptr);
243 /* IB packet must end on a 8 DW boundary */
244 while ((ring->wptr & 7) != 2)
245 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP));
246 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
247 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
248 /* base must be 32 byte aligned */
249 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
250 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
251 amdgpu_ring_write(ring, ib->length_dw);
252 amdgpu_ring_write(ring, 0);
253 amdgpu_ring_write(ring, 0);
258 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
260 * @ring: amdgpu ring pointer
262 * Emit an hdp flush packet on the requested DMA ring.
264 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
266 u32 ref_and_mask = 0;
268 if (ring == &ring->adev->sdma[0].ring)
269 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
271 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
273 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
274 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
275 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
276 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
277 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
278 amdgpu_ring_write(ring, ref_and_mask); /* reference */
279 amdgpu_ring_write(ring, ref_and_mask); /* mask */
280 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
281 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
285 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
287 * @ring: amdgpu ring pointer
288 * @fence: amdgpu fence object
290 * Add a DMA fence packet to the ring to write
291 * the fence seq number and DMA trap packet to generate
292 * an interrupt if needed (VI).
294 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
297 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
298 /* write the fence */
299 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
300 amdgpu_ring_write(ring, lower_32_bits(addr));
301 amdgpu_ring_write(ring, upper_32_bits(addr));
302 amdgpu_ring_write(ring, lower_32_bits(seq));
304 /* optionally write high bits as well */
307 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
308 amdgpu_ring_write(ring, lower_32_bits(addr));
309 amdgpu_ring_write(ring, upper_32_bits(addr));
310 amdgpu_ring_write(ring, upper_32_bits(seq));
313 /* generate an interrupt */
314 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
315 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
319 * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring
321 * @ring: amdgpu_ring structure holding ring information
322 * @semaphore: amdgpu semaphore object
323 * @emit_wait: wait or signal semaphore
325 * Add a DMA semaphore packet to the ring wait on or signal
328 static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring,
329 struct amdgpu_semaphore *semaphore,
332 u64 addr = semaphore->gpu_addr;
333 u32 sig = emit_wait ? 0 : 1;
335 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
336 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
337 amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
338 amdgpu_ring_write(ring, upper_32_bits(addr));
344 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
346 * @adev: amdgpu_device pointer
348 * Stop the gfx async dma ring buffers (VI).
350 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
352 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
353 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
354 u32 rb_cntl, ib_cntl;
357 if ((adev->mman.buffer_funcs_ring == sdma0) ||
358 (adev->mman.buffer_funcs_ring == sdma1))
359 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
361 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
362 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
363 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
364 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
365 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
366 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
367 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
369 sdma0->ready = false;
370 sdma1->ready = false;
374 * sdma_v2_4_rlc_stop - stop the compute async dma engines
376 * @adev: amdgpu_device pointer
378 * Stop the compute async dma queues (VI).
380 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
386 * sdma_v2_4_enable - stop the async dma engines
388 * @adev: amdgpu_device pointer
389 * @enable: enable/disable the DMA MEs.
391 * Halt or unhalt the async dma engines (VI).
393 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
398 if (enable == false) {
399 sdma_v2_4_gfx_stop(adev);
400 sdma_v2_4_rlc_stop(adev);
403 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
404 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
406 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
408 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
409 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
414 * sdma_v2_4_gfx_resume - setup and start the async dma engines
416 * @adev: amdgpu_device pointer
418 * Set up the gfx DMA ring buffers and enable them (VI).
419 * Returns 0 for success, error for failure.
421 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
423 struct amdgpu_ring *ring;
424 u32 rb_cntl, ib_cntl;
429 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
430 ring = &adev->sdma[i].ring;
431 wb_offset = (ring->rptr_offs * 4);
433 mutex_lock(&adev->srbm_mutex);
434 for (j = 0; j < 16; j++) {
435 vi_srbm_select(adev, 0, 0, 0, j);
437 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
438 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
440 vi_srbm_select(adev, 0, 0, 0, 0);
441 mutex_unlock(&adev->srbm_mutex);
443 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
445 /* Set ring buffer size in dwords */
446 rb_bufsz = order_base_2(ring->ring_size / 4);
447 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
448 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
450 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
451 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
452 RPTR_WRITEBACK_SWAP_ENABLE, 1);
454 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
456 /* Initialize the ring buffer's read and write pointers */
457 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
458 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
460 /* set the wb address whether it's enabled or not */
461 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
462 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
463 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
464 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
466 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
468 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
469 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
472 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
475 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
476 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
478 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
479 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
481 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
484 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
488 r = amdgpu_ring_test_ring(ring);
494 if (adev->mman.buffer_funcs_ring == ring)
495 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
502 * sdma_v2_4_rlc_resume - setup and start the async dma engines
504 * @adev: amdgpu_device pointer
506 * Set up the compute DMA queues and enable them (VI).
507 * Returns 0 for success, error for failure.
509 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
516 * sdma_v2_4_load_microcode - load the sDMA ME ucode
518 * @adev: amdgpu_device pointer
520 * Loads the sDMA0/1 ucode.
521 * Returns 0 for success, -EINVAL if the ucode is not available.
523 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
525 const struct sdma_firmware_header_v1_0 *hdr;
526 const __le32 *fw_data;
529 bool smc_loads_fw = false; /* XXX fix me */
531 if (!adev->sdma[0].fw || !adev->sdma[1].fw)
535 sdma_v2_4_enable(adev, false);
538 /* XXX query SMC for fw load complete */
540 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
541 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
542 amdgpu_ucode_print_sdma_hdr(&hdr->header);
543 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
544 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
546 fw_data = (const __le32 *)
547 (adev->sdma[i].fw->data +
548 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
549 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
550 for (j = 0; j < fw_size; j++)
551 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
552 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
560 * sdma_v2_4_start - setup and start the async dma engines
562 * @adev: amdgpu_device pointer
564 * Set up the DMA engines and enable them (VI).
565 * Returns 0 for success, error for failure.
567 static int sdma_v2_4_start(struct amdgpu_device *adev)
571 if (!adev->firmware.smu_load) {
572 r = sdma_v2_4_load_microcode(adev);
576 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
577 AMDGPU_UCODE_ID_SDMA0);
580 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
581 AMDGPU_UCODE_ID_SDMA1);
587 sdma_v2_4_enable(adev, true);
589 /* start the gfx rings and rlc compute queues */
590 r = sdma_v2_4_gfx_resume(adev);
593 r = sdma_v2_4_rlc_resume(adev);
601 * sdma_v2_4_ring_test_ring - simple async dma engine test
603 * @ring: amdgpu_ring structure holding ring information
605 * Test the DMA engine by writing using it to write an
606 * value to memory. (VI).
607 * Returns 0 for success, error for failure.
609 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
611 struct amdgpu_device *adev = ring->adev;
618 r = amdgpu_wb_get(adev, &index);
620 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
624 gpu_addr = adev->wb.gpu_addr + (index * 4);
626 adev->wb.wb[index] = cpu_to_le32(tmp);
628 r = amdgpu_ring_lock(ring, 5);
630 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
631 amdgpu_wb_free(adev, index);
635 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
636 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
637 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
638 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
639 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
640 amdgpu_ring_write(ring, 0xDEADBEEF);
641 amdgpu_ring_unlock_commit(ring);
643 for (i = 0; i < adev->usec_timeout; i++) {
644 tmp = le32_to_cpu(adev->wb.wb[index]);
645 if (tmp == 0xDEADBEEF)
650 if (i < adev->usec_timeout) {
651 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
653 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
657 amdgpu_wb_free(adev, index);
663 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
665 * @ring: amdgpu_ring structure holding ring information
667 * Test a simple IB in the DMA ring (VI).
668 * Returns 0 on success, error on failure.
670 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
672 struct amdgpu_device *adev = ring->adev;
680 r = amdgpu_wb_get(adev, &index);
682 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
686 gpu_addr = adev->wb.gpu_addr + (index * 4);
688 adev->wb.wb[index] = cpu_to_le32(tmp);
690 r = amdgpu_ib_get(ring, NULL, 256, &ib);
692 amdgpu_wb_free(adev, index);
693 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
697 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
698 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
699 ib.ptr[1] = lower_32_bits(gpu_addr);
700 ib.ptr[2] = upper_32_bits(gpu_addr);
701 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
702 ib.ptr[4] = 0xDEADBEEF;
703 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
704 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
705 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
708 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
710 amdgpu_ib_free(adev, &ib);
711 amdgpu_wb_free(adev, index);
712 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
715 r = amdgpu_fence_wait(ib.fence, false);
717 amdgpu_ib_free(adev, &ib);
718 amdgpu_wb_free(adev, index);
719 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
722 for (i = 0; i < adev->usec_timeout; i++) {
723 tmp = le32_to_cpu(adev->wb.wb[index]);
724 if (tmp == 0xDEADBEEF)
728 if (i < adev->usec_timeout) {
729 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
730 ib.fence->ring->idx, i);
732 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
735 amdgpu_ib_free(adev, &ib);
736 amdgpu_wb_free(adev, index);
741 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
743 * @ib: indirect buffer to fill with commands
744 * @pe: addr of the page entry
745 * @src: src addr to copy from
746 * @count: number of page entries to update
748 * Update PTEs by copying them from the GART using sDMA (CIK).
750 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
751 uint64_t pe, uint64_t src,
755 unsigned bytes = count * 8;
756 if (bytes > 0x1FFFF8)
759 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
760 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
761 ib->ptr[ib->length_dw++] = bytes;
762 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
763 ib->ptr[ib->length_dw++] = lower_32_bits(src);
764 ib->ptr[ib->length_dw++] = upper_32_bits(src);
765 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
766 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
775 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
777 * @ib: indirect buffer to fill with commands
778 * @pe: addr of the page entry
779 * @addr: dst addr to write into pe
780 * @count: number of page entries to update
781 * @incr: increase next addr by incr bytes
782 * @flags: access flags
784 * Update PTEs by writing them manually using sDMA (CIK).
786 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
788 uint64_t addr, unsigned count,
789 uint32_t incr, uint32_t flags)
799 /* for non-physically contiguous pages (system) */
800 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
801 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
802 ib->ptr[ib->length_dw++] = pe;
803 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
804 ib->ptr[ib->length_dw++] = ndw;
805 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
806 if (flags & AMDGPU_PTE_SYSTEM) {
807 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
808 value &= 0xFFFFFFFFFFFFF000ULL;
809 } else if (flags & AMDGPU_PTE_VALID) {
816 ib->ptr[ib->length_dw++] = value;
817 ib->ptr[ib->length_dw++] = upper_32_bits(value);
823 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
825 * @ib: indirect buffer to fill with commands
826 * @pe: addr of the page entry
827 * @addr: dst addr to write into pe
828 * @count: number of page entries to update
829 * @incr: increase next addr by incr bytes
830 * @flags: access flags
832 * Update the page tables using sDMA (CIK).
834 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
836 uint64_t addr, unsigned count,
837 uint32_t incr, uint32_t flags)
847 if (flags & AMDGPU_PTE_VALID)
852 /* for physically contiguous pages (vram) */
853 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
854 ib->ptr[ib->length_dw++] = pe; /* dst addr */
855 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
856 ib->ptr[ib->length_dw++] = flags; /* mask */
857 ib->ptr[ib->length_dw++] = 0;
858 ib->ptr[ib->length_dw++] = value; /* value */
859 ib->ptr[ib->length_dw++] = upper_32_bits(value);
860 ib->ptr[ib->length_dw++] = incr; /* increment size */
861 ib->ptr[ib->length_dw++] = 0;
862 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
871 * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw
873 * @ib: indirect buffer to fill with padding
876 static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
878 while (ib->length_dw & 0x7)
879 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
883 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
885 * @ring: amdgpu_ring pointer
886 * @vm: amdgpu_vm pointer
888 * Update the page table base and flush the VM TLB
891 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
892 unsigned vm_id, uint64_t pd_addr)
894 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
895 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
897 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
899 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
901 amdgpu_ring_write(ring, pd_addr >> 12);
904 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
905 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
906 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
907 amdgpu_ring_write(ring, 1 << vm_id);
910 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
911 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
912 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
913 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
914 amdgpu_ring_write(ring, 0);
915 amdgpu_ring_write(ring, 0); /* reference */
916 amdgpu_ring_write(ring, 0); /* mask */
917 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
918 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
921 static int sdma_v2_4_early_init(void *handle)
923 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
925 sdma_v2_4_set_ring_funcs(adev);
926 sdma_v2_4_set_buffer_funcs(adev);
927 sdma_v2_4_set_vm_pte_funcs(adev);
928 sdma_v2_4_set_irq_funcs(adev);
933 static int sdma_v2_4_sw_init(void *handle)
935 struct amdgpu_ring *ring;
937 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
939 /* SDMA trap event */
940 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
944 /* SDMA Privileged inst */
945 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
949 /* SDMA Privileged inst */
950 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
954 r = sdma_v2_4_init_microcode(adev);
956 DRM_ERROR("Failed to load sdma firmware!\n");
960 ring = &adev->sdma[0].ring;
961 ring->ring_obj = NULL;
962 ring->use_doorbell = false;
964 ring = &adev->sdma[1].ring;
965 ring->ring_obj = NULL;
966 ring->use_doorbell = false;
968 ring = &adev->sdma[0].ring;
969 sprintf(ring->name, "sdma0");
970 r = amdgpu_ring_init(adev, ring, 256 * 1024,
971 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
972 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
973 AMDGPU_RING_TYPE_SDMA);
977 ring = &adev->sdma[1].ring;
978 sprintf(ring->name, "sdma1");
979 r = amdgpu_ring_init(adev, ring, 256 * 1024,
980 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
981 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
982 AMDGPU_RING_TYPE_SDMA);
989 static int sdma_v2_4_sw_fini(void *handle)
991 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
993 amdgpu_ring_fini(&adev->sdma[0].ring);
994 amdgpu_ring_fini(&adev->sdma[1].ring);
999 static int sdma_v2_4_hw_init(void *handle)
1002 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1004 sdma_v2_4_init_golden_registers(adev);
1006 r = sdma_v2_4_start(adev);
1013 static int sdma_v2_4_hw_fini(void *handle)
1015 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1017 sdma_v2_4_enable(adev, false);
1022 static int sdma_v2_4_suspend(void *handle)
1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1026 return sdma_v2_4_hw_fini(adev);
1029 static int sdma_v2_4_resume(void *handle)
1031 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1033 return sdma_v2_4_hw_init(adev);
1036 static bool sdma_v2_4_is_idle(void *handle)
1038 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1039 u32 tmp = RREG32(mmSRBM_STATUS2);
1041 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1042 SRBM_STATUS2__SDMA1_BUSY_MASK))
1048 static int sdma_v2_4_wait_for_idle(void *handle)
1052 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1054 for (i = 0; i < adev->usec_timeout; i++) {
1055 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1056 SRBM_STATUS2__SDMA1_BUSY_MASK);
1065 static void sdma_v2_4_print_status(void *handle)
1068 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1070 dev_info(adev->dev, "VI SDMA registers\n");
1071 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1072 RREG32(mmSRBM_STATUS2));
1073 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1074 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1075 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1076 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
1077 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1078 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1079 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1080 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1081 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1082 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1083 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1084 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1085 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1086 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1087 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1088 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1089 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1090 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1091 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1092 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1093 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1094 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1095 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1096 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1097 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1098 mutex_lock(&adev->srbm_mutex);
1099 for (j = 0; j < 16; j++) {
1100 vi_srbm_select(adev, 0, 0, 0, j);
1101 dev_info(adev->dev, " VM %d:\n", j);
1102 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1103 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1104 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1105 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1107 vi_srbm_select(adev, 0, 0, 0, 0);
1108 mutex_unlock(&adev->srbm_mutex);
1112 static int sdma_v2_4_soft_reset(void *handle)
1114 u32 srbm_soft_reset = 0;
1115 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1116 u32 tmp = RREG32(mmSRBM_STATUS2);
1118 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1120 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1121 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1122 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1123 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1125 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1127 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1128 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1129 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1130 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1133 if (srbm_soft_reset) {
1134 sdma_v2_4_print_status((void *)adev);
1136 tmp = RREG32(mmSRBM_SOFT_RESET);
1137 tmp |= srbm_soft_reset;
1138 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1139 WREG32(mmSRBM_SOFT_RESET, tmp);
1140 tmp = RREG32(mmSRBM_SOFT_RESET);
1144 tmp &= ~srbm_soft_reset;
1145 WREG32(mmSRBM_SOFT_RESET, tmp);
1146 tmp = RREG32(mmSRBM_SOFT_RESET);
1148 /* Wait a little for things to settle down */
1151 sdma_v2_4_print_status((void *)adev);
1157 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1158 struct amdgpu_irq_src *src,
1160 enum amdgpu_interrupt_state state)
1165 case AMDGPU_SDMA_IRQ_TRAP0:
1167 case AMDGPU_IRQ_STATE_DISABLE:
1168 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1169 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1170 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1172 case AMDGPU_IRQ_STATE_ENABLE:
1173 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1174 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1175 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1181 case AMDGPU_SDMA_IRQ_TRAP1:
1183 case AMDGPU_IRQ_STATE_DISABLE:
1184 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1185 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1186 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1188 case AMDGPU_IRQ_STATE_ENABLE:
1189 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1190 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1191 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1203 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1204 struct amdgpu_irq_src *source,
1205 struct amdgpu_iv_entry *entry)
1207 u8 instance_id, queue_id;
1209 instance_id = (entry->ring_id & 0x3) >> 0;
1210 queue_id = (entry->ring_id & 0xc) >> 2;
1211 DRM_DEBUG("IH: SDMA trap\n");
1212 switch (instance_id) {
1216 amdgpu_fence_process(&adev->sdma[0].ring);
1229 amdgpu_fence_process(&adev->sdma[1].ring);
1243 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1244 struct amdgpu_irq_src *source,
1245 struct amdgpu_iv_entry *entry)
1247 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1248 schedule_work(&adev->reset_work);
1252 static int sdma_v2_4_set_clockgating_state(void *handle,
1253 enum amd_clockgating_state state)
1255 /* XXX handled via the smc on VI */
1259 static int sdma_v2_4_set_powergating_state(void *handle,
1260 enum amd_powergating_state state)
1265 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1266 .early_init = sdma_v2_4_early_init,
1268 .sw_init = sdma_v2_4_sw_init,
1269 .sw_fini = sdma_v2_4_sw_fini,
1270 .hw_init = sdma_v2_4_hw_init,
1271 .hw_fini = sdma_v2_4_hw_fini,
1272 .suspend = sdma_v2_4_suspend,
1273 .resume = sdma_v2_4_resume,
1274 .is_idle = sdma_v2_4_is_idle,
1275 .wait_for_idle = sdma_v2_4_wait_for_idle,
1276 .soft_reset = sdma_v2_4_soft_reset,
1277 .print_status = sdma_v2_4_print_status,
1278 .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1279 .set_powergating_state = sdma_v2_4_set_powergating_state,
1283 * sdma_v2_4_ring_is_lockup - Check if the DMA engine is locked up
1285 * @ring: amdgpu_ring structure holding ring information
1287 * Check if the async DMA engine is locked up (VI).
1288 * Returns true if the engine appears to be locked up, false if not.
1290 static bool sdma_v2_4_ring_is_lockup(struct amdgpu_ring *ring)
1293 if (sdma_v2_4_is_idle(ring->adev)) {
1294 amdgpu_ring_lockup_update(ring);
1297 return amdgpu_ring_test_lockup(ring);
1300 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1301 .get_rptr = sdma_v2_4_ring_get_rptr,
1302 .get_wptr = sdma_v2_4_ring_get_wptr,
1303 .set_wptr = sdma_v2_4_ring_set_wptr,
1305 .emit_ib = sdma_v2_4_ring_emit_ib,
1306 .emit_fence = sdma_v2_4_ring_emit_fence,
1307 .emit_semaphore = sdma_v2_4_ring_emit_semaphore,
1308 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1309 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1310 .test_ring = sdma_v2_4_ring_test_ring,
1311 .test_ib = sdma_v2_4_ring_test_ib,
1312 .is_lockup = sdma_v2_4_ring_is_lockup,
1315 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1317 adev->sdma[0].ring.funcs = &sdma_v2_4_ring_funcs;
1318 adev->sdma[1].ring.funcs = &sdma_v2_4_ring_funcs;
1321 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1322 .set = sdma_v2_4_set_trap_irq_state,
1323 .process = sdma_v2_4_process_trap_irq,
1326 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1327 .process = sdma_v2_4_process_illegal_inst_irq,
1330 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1332 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1333 adev->sdma_trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1334 adev->sdma_illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1338 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1340 * @ring: amdgpu_ring structure holding ring information
1341 * @src_offset: src GPU address
1342 * @dst_offset: dst GPU address
1343 * @byte_count: number of bytes to xfer
1345 * Copy GPU buffers using the DMA engine (VI).
1346 * Used by the amdgpu ttm implementation to move pages if
1347 * registered as the asic copy callback.
1349 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ring *ring,
1350 uint64_t src_offset,
1351 uint64_t dst_offset,
1352 uint32_t byte_count)
1354 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1355 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR));
1356 amdgpu_ring_write(ring, byte_count);
1357 amdgpu_ring_write(ring, 0); /* src/dst endian swap */
1358 amdgpu_ring_write(ring, lower_32_bits(src_offset));
1359 amdgpu_ring_write(ring, upper_32_bits(src_offset));
1360 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1361 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1365 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1367 * @ring: amdgpu_ring structure holding ring information
1368 * @src_data: value to write to buffer
1369 * @dst_offset: dst GPU address
1370 * @byte_count: number of bytes to xfer
1372 * Fill GPU buffers using the DMA engine (VI).
1374 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ring *ring,
1376 uint64_t dst_offset,
1377 uint32_t byte_count)
1379 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL));
1380 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1381 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1382 amdgpu_ring_write(ring, src_data);
1383 amdgpu_ring_write(ring, byte_count);
1386 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1387 .copy_max_bytes = 0x1fffff,
1389 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1391 .fill_max_bytes = 0x1fffff,
1393 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1396 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1398 if (adev->mman.buffer_funcs == NULL) {
1399 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1400 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1404 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1405 .copy_pte = sdma_v2_4_vm_copy_pte,
1406 .write_pte = sdma_v2_4_vm_write_pte,
1407 .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1408 .pad_ib = sdma_v2_4_vm_pad_ib,
1411 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1413 if (adev->vm_manager.vm_pte_funcs == NULL) {
1414 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1415 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;