drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
  54
  55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  56 {
  57         SDMA0_REGISTER_OFFSET,
  58         SDMA1_REGISTER_OFFSET
  59 };
  60
  61 static const u32 golden_settings_iceland_a11[] =
  62 {
  63         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  64         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  65         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  66         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  67 };
  68
  69 static const u32 iceland_mgcg_cgcg_init[] =
  70 {
  71         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  72         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  73 };
  74
  75 /*
  76  * sDMA - System DMA
  77  * Starting with CIK, the GPU has new asynchronous
  78  * DMA engines.  These engines are used for compute
  79  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  80  * and each one supports 1 ring buffer used for gfx
  81  * and 2 queues used for compute.
  82  *
  83  * The programming model is very similar to the CP
  84  * (ring buffer, IBs, etc.), but sDMA has it's own
  85  * packet format that is different from the PM4 format
  86  * used by the CP. sDMA supports copying data, writing
  87  * embedded data, solid fills, and a number of other
  88  * things.  It also has support for tiling/detiling of
  89  * buffers.
  90  */
  91
  92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  93 {
  94         switch (adev->asic_type) {
  95         case CHIP_TOPAZ:
  96                 amdgpu_program_register_sequence(adev,
  97                                                  iceland_mgcg_cgcg_init,
  98                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  99                 amdgpu_program_register_sequence(adev,
 100                                                  golden_settings_iceland_a11,
 101                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 102                 break;
 103         default:
 104                 break;
 105         }
 106 }
 107
 108 /**
 109  * sdma_v2_4_init_microcode - load ucode images from disk
 110  *
 111  * @adev: amdgpu_device pointer
 112  *
 113  * Use the firmware interface to load the ucode images into
 114  * the driver (not loaded into hw).
 115  * Returns 0 on success, error on failure.
 116  */
 117 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 118 {
 119         const char *chip_name;
 120         char fw_name[30];
 121         int err, i;
 122         struct amdgpu_firmware_info *info = NULL;
 123         const struct common_firmware_header *header = NULL;
 124         const struct sdma_firmware_header_v1_0 *hdr;
 125
 126         DRM_DEBUG("\n");
 127
 128         switch (adev->asic_type) {
 129         case CHIP_TOPAZ:
 130                 chip_name = "topaz";
 131                 break;
 132         default: BUG();
 133         }
 134
 135         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 136                 if (i == 0)
 137                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 138                 else
 139                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 140                 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
 141                 if (err)
 142                         goto out;
 143                 err = amdgpu_ucode_validate(adev->sdma[i].fw);
 144                 if (err)
 145                         goto out;
 146                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
 147                 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 148                 adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 149                 if (adev->sdma[i].feature_version >= 20)
 150                         adev->sdma[i].burst_nop = true;
 151
 152                 if (adev->firmware.smu_load) {
 153                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 154                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 155                         info->fw = adev->sdma[i].fw;
 156                         header = (const struct common_firmware_header *)info->fw->data;
 157                         adev->firmware.fw_size +=
 158                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 159                 }
 160         }
 161
 162 out:
 163         if (err) {
 164                 printk(KERN_ERR
 165                        "sdma_v2_4: Failed to load firmware \"%s\"\n",
 166                        fw_name);
 167                 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 168                         release_firmware(adev->sdma[i].fw);
 169                         adev->sdma[i].fw = NULL;
 170                 }
 171         }
 172         return err;
 173 }
 174
 175 /**
 176  * sdma_v2_4_ring_get_rptr - get the current read pointer
 177  *
 178  * @ring: amdgpu ring pointer
 179  *
 180  * Get the current rptr from the hardware (VI+).
 181  */
 182 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 183 {
 184         u32 rptr;
 185
 186         /* XXX check if swapping is necessary on BE */
 187         rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
 188
 189         return rptr;
 190 }
 191
 192 /**
 193  * sdma_v2_4_ring_get_wptr - get the current write pointer
 194  *
 195  * @ring: amdgpu ring pointer
 196  *
 197  * Get the current wptr from the hardware (VI+).
 198  */
 199 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 200 {
 201         struct amdgpu_device *adev = ring->adev;
 202         int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
 203         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 204
 205         return wptr;
 206 }
 207
 208 /**
 209  * sdma_v2_4_ring_set_wptr - commit the write pointer
 210  *
 211  * @ring: amdgpu ring pointer
 212  *
 213  * Write the wptr back to the hardware (VI+).
 214  */
 215 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 216 {
 217         struct amdgpu_device *adev = ring->adev;
 218         int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
 219
 220         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 221 }
 222
 223 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 224 {
 225         struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ring);
 226         int i;
 227
 228         for (i = 0; i < count; i++)
 229                 if (sdma && sdma->burst_nop && (i == 0))
 230                         amdgpu_ring_write(ring, ring->nop |
 231                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 232                 else
 233                         amdgpu_ring_write(ring, ring->nop);
 234 }
 235
 236 /**
 237  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 238  *
 239  * @ring: amdgpu ring pointer
 240  * @ib: IB object to schedule
 241  *
 242  * Schedule an IB in the DMA ring (VI).
 243  */
 244 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 245                                    struct amdgpu_ib *ib)
 246 {
 247         u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
 248         u32 next_rptr = ring->wptr + 5;
 249
 250         while ((next_rptr & 7) != 2)
 251                 next_rptr++;
 252
 253         next_rptr += 6;
 254
 255         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 256                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 257         amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
 258         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
 259         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 260         amdgpu_ring_write(ring, next_rptr);
 261
 262         /* IB packet must end on a 8 DW boundary */
 263         sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 264
 265         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 266                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 267         /* base must be 32 byte aligned */
 268         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 269         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 270         amdgpu_ring_write(ring, ib->length_dw);
 271         amdgpu_ring_write(ring, 0);
 272         amdgpu_ring_write(ring, 0);
 273
 274 }
 275
 276 /**
 277  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 278  *
 279  * @ring: amdgpu ring pointer
 280  *
 281  * Emit an hdp flush packet on the requested DMA ring.
 282  */
 283 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 284 {
 285         u32 ref_and_mask = 0;
 286
 287         if (ring == &ring->adev->sdma[0].ring)
 288                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 289         else
 290                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 291
 292         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 293                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 294                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 295         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 296         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 297         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 298         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 299         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 300                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 301 }
 302
 303 /**
 304  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 305  *
 306  * @ring: amdgpu ring pointer
 307  * @fence: amdgpu fence object
 308  *
 309  * Add a DMA fence packet to the ring to write
 310  * the fence seq number and DMA trap packet to generate
 311  * an interrupt if needed (VI).
 312  */
 313 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 314                                       unsigned flags)
 315 {
 316         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 317         /* write the fence */
 318         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 319         amdgpu_ring_write(ring, lower_32_bits(addr));
 320         amdgpu_ring_write(ring, upper_32_bits(addr));
 321         amdgpu_ring_write(ring, lower_32_bits(seq));
 322
 323         /* optionally write high bits as well */
 324         if (write64bit) {
 325                 addr += 4;
 326                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 327                 amdgpu_ring_write(ring, lower_32_bits(addr));
 328                 amdgpu_ring_write(ring, upper_32_bits(addr));
 329                 amdgpu_ring_write(ring, upper_32_bits(seq));
 330         }
 331
 332         /* generate an interrupt */
 333         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 334         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 335 }
 336
 337 /**
 338  * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring
 339  *
 340  * @ring: amdgpu_ring structure holding ring information
 341  * @semaphore: amdgpu semaphore object
 342  * @emit_wait: wait or signal semaphore
 343  *
 344  * Add a DMA semaphore packet to the ring wait on or signal
 345  * other rings (VI).
 346  */
 347 static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring,
 348                                           struct amdgpu_semaphore *semaphore,
 349                                           bool emit_wait)
 350 {
 351         u64 addr = semaphore->gpu_addr;
 352         u32 sig = emit_wait ? 0 : 1;
 353
 354         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
 355                           SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
 356         amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
 357         amdgpu_ring_write(ring, upper_32_bits(addr));
 358
 359         return true;
 360 }
 361
 362 /**
 363  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 364  *
 365  * @adev: amdgpu_device pointer
 366  *
 367  * Stop the gfx async dma ring buffers (VI).
 368  */
 369 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 370 {
 371         struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
 372         struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
 373         u32 rb_cntl, ib_cntl;
 374         int i;
 375
 376         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 377             (adev->mman.buffer_funcs_ring == sdma1))
 378                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 379
 380         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 381                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 382                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 383                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 384                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 385                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 386                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 387         }
 388         sdma0->ready = false;
 389         sdma1->ready = false;
 390 }
 391
 392 /**
 393  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 394  *
 395  * @adev: amdgpu_device pointer
 396  *
 397  * Stop the compute async dma queues (VI).
 398  */
 399 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 400 {
 401         /* XXX todo */
 402 }
 403
 404 /**
 405  * sdma_v2_4_enable - stop the async dma engines
 406  *
 407  * @adev: amdgpu_device pointer
 408  * @enable: enable/disable the DMA MEs.
 409  *
 410  * Halt or unhalt the async dma engines (VI).
 411  */
 412 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 413 {
 414         u32 f32_cntl;
 415         int i;
 416
 417         if (enable == false) {
 418                 sdma_v2_4_gfx_stop(adev);
 419                 sdma_v2_4_rlc_stop(adev);
 420         }
 421
 422         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 423                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 424                 if (enable)
 425                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 426                 else
 427                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 428                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 429         }
 430 }
 431
 432 /**
 433  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 434  *
 435  * @adev: amdgpu_device pointer
 436  *
 437  * Set up the gfx DMA ring buffers and enable them (VI).
 438  * Returns 0 for success, error for failure.
 439  */
 440 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 441 {
 442         struct amdgpu_ring *ring;
 443         u32 rb_cntl, ib_cntl;
 444         u32 rb_bufsz;
 445         u32 wb_offset;
 446         int i, j, r;
 447
 448         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 449                 ring = &adev->sdma[i].ring;
 450                 wb_offset = (ring->rptr_offs * 4);
 451
 452                 mutex_lock(&adev->srbm_mutex);
 453                 for (j = 0; j < 16; j++) {
 454                         vi_srbm_select(adev, 0, 0, 0, j);
 455                         /* SDMA GFX */
 456                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 457                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 458                 }
 459                 vi_srbm_select(adev, 0, 0, 0, 0);
 460                 mutex_unlock(&adev->srbm_mutex);
 461
 462                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 463
 464                 /* Set ring buffer size in dwords */
 465                 rb_bufsz = order_base_2(ring->ring_size / 4);
 466                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 467                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 468 #ifdef __BIG_ENDIAN
 469                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 470                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 471                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 472 #endif
 473                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 474
 475                 /* Initialize the ring buffer's read and write pointers */
 476                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 477                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 478
 479                 /* set the wb address whether it's enabled or not */
 480                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 481                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 482                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 483                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 484
 485                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 486
 487                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 488                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 489
 490                 ring->wptr = 0;
 491                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 492
 493                 /* enable DMA RB */
 494                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 495                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 496
 497                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 498                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 499 #ifdef __BIG_ENDIAN
 500                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 501 #endif
 502                 /* enable DMA IBs */
 503                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 504
 505                 ring->ready = true;
 506
 507                 r = amdgpu_ring_test_ring(ring);
 508                 if (r) {
 509                         ring->ready = false;
 510                         return r;
 511                 }
 512
 513                 if (adev->mman.buffer_funcs_ring == ring)
 514                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 515         }
 516
 517         return 0;
 518 }
 519
 520 /**
 521  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 522  *
 523  * @adev: amdgpu_device pointer
 524  *
 525  * Set up the compute DMA queues and enable them (VI).
 526  * Returns 0 for success, error for failure.
 527  */
 528 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 529 {
 530         /* XXX todo */
 531         return 0;
 532 }
 533
 534 /**
 535  * sdma_v2_4_load_microcode - load the sDMA ME ucode
 536  *
 537  * @adev: amdgpu_device pointer
 538  *
 539  * Loads the sDMA0/1 ucode.
 540  * Returns 0 for success, -EINVAL if the ucode is not available.
 541  */
 542 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
 543 {
 544         const struct sdma_firmware_header_v1_0 *hdr;
 545         const __le32 *fw_data;
 546         u32 fw_size;
 547         int i, j;
 548         bool smc_loads_fw = false; /* XXX fix me */
 549
 550         if (!adev->sdma[0].fw || !adev->sdma[1].fw)
 551                 return -EINVAL;
 552
 553         /* halt the MEs */
 554         sdma_v2_4_enable(adev, false);
 555
 556         if (smc_loads_fw) {
 557                 /* XXX query SMC for fw load complete */
 558         } else {
 559                 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 560                         hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
 561                         amdgpu_ucode_print_sdma_hdr(&hdr->header);
 562                         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 563                         fw_data = (const __le32 *)
 564                                 (adev->sdma[i].fw->data +
 565                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 566                         WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 567                         for (j = 0; j < fw_size; j++)
 568                                 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 569                         WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
 570                 }
 571         }
 572
 573         return 0;
 574 }
 575
 576 /**
 577  * sdma_v2_4_start - setup and start the async dma engines
 578  *
 579  * @adev: amdgpu_device pointer
 580  *
 581  * Set up the DMA engines and enable them (VI).
 582  * Returns 0 for success, error for failure.
 583  */
 584 static int sdma_v2_4_start(struct amdgpu_device *adev)
 585 {
 586         int r;
 587
 588         if (!adev->firmware.smu_load) {
 589                 r = sdma_v2_4_load_microcode(adev);
 590                 if (r)
 591                         return r;
 592         } else {
 593                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 594                                                 AMDGPU_UCODE_ID_SDMA0);
 595                 if (r)
 596                         return -EINVAL;
 597                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 598                                                 AMDGPU_UCODE_ID_SDMA1);
 599                 if (r)
 600                         return -EINVAL;
 601         }
 602
 603         /* unhalt the MEs */
 604         sdma_v2_4_enable(adev, true);
 605
 606         /* start the gfx rings and rlc compute queues */
 607         r = sdma_v2_4_gfx_resume(adev);
 608         if (r)
 609                 return r;
 610         r = sdma_v2_4_rlc_resume(adev);
 611         if (r)
 612                 return r;
 613
 614         return 0;
 615 }
 616
 617 /**
 618  * sdma_v2_4_ring_test_ring - simple async dma engine test
 619  *
 620  * @ring: amdgpu_ring structure holding ring information
 621  *
 622  * Test the DMA engine by writing using it to write an
 623  * value to memory. (VI).
 624  * Returns 0 for success, error for failure.
 625  */
 626 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 627 {
 628         struct amdgpu_device *adev = ring->adev;
 629         unsigned i;
 630         unsigned index;
 631         int r;
 632         u32 tmp;
 633         u64 gpu_addr;
 634
 635         r = amdgpu_wb_get(adev, &index);
 636         if (r) {
 637                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 638                 return r;
 639         }
 640
 641         gpu_addr = adev->wb.gpu_addr + (index * 4);
 642         tmp = 0xCAFEDEAD;
 643         adev->wb.wb[index] = cpu_to_le32(tmp);
 644
 645         r = amdgpu_ring_lock(ring, 5);
 646         if (r) {
 647                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 648                 amdgpu_wb_free(adev, index);
 649                 return r;
 650         }
 651
 652         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 653                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 654         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 655         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 656         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 657         amdgpu_ring_write(ring, 0xDEADBEEF);
 658         amdgpu_ring_unlock_commit(ring);
 659
 660         for (i = 0; i < adev->usec_timeout; i++) {
 661                 tmp = le32_to_cpu(adev->wb.wb[index]);
 662                 if (tmp == 0xDEADBEEF)
 663                         break;
 664                 DRM_UDELAY(1);
 665         }
 666
 667         if (i < adev->usec_timeout) {
 668                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 669         } else {
 670                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 671                           ring->idx, tmp);
 672                 r = -EINVAL;
 673         }
 674         amdgpu_wb_free(adev, index);
 675
 676         return r;
 677 }
 678
 679 /**
 680  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 681  *
 682  * @ring: amdgpu_ring structure holding ring information
 683  *
 684  * Test a simple IB in the DMA ring (VI).
 685  * Returns 0 on success, error on failure.
 686  */
 687 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
 688 {
 689         struct amdgpu_device *adev = ring->adev;
 690         struct amdgpu_ib ib;
 691         struct fence *f = NULL;
 692         unsigned i;
 693         unsigned index;
 694         int r;
 695         u32 tmp = 0;
 696         u64 gpu_addr;
 697
 698         r = amdgpu_wb_get(adev, &index);
 699         if (r) {
 700                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 701                 return r;
 702         }
 703
 704         gpu_addr = adev->wb.gpu_addr + (index * 4);
 705         tmp = 0xCAFEDEAD;
 706         adev->wb.wb[index] = cpu_to_le32(tmp);
 707         memset(&ib, 0, sizeof(ib));
 708         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 709         if (r) {
 710                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 711                 goto err0;
 712         }
 713
 714         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 715                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 716         ib.ptr[1] = lower_32_bits(gpu_addr);
 717         ib.ptr[2] = upper_32_bits(gpu_addr);
 718         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 719         ib.ptr[4] = 0xDEADBEEF;
 720         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 721         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 722         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 723         ib.length_dw = 8;
 724
 725         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 726                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 727                                                  &f);
 728         if (r)
 729                 goto err1;
 730
 731         r = fence_wait(f, false);
 732         if (r) {
 733                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 734                 goto err1;
 735         }
 736         for (i = 0; i < adev->usec_timeout; i++) {
 737                 tmp = le32_to_cpu(adev->wb.wb[index]);
 738                 if (tmp == 0xDEADBEEF)
 739                         break;
 740                 DRM_UDELAY(1);
 741         }
 742         if (i < adev->usec_timeout) {
 743                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 744                          ring->idx, i);
 745                 goto err1;
 746         } else {
 747                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 748                 r = -EINVAL;
 749         }
 750
 751 err1:
 752         fence_put(f);
 753         amdgpu_ib_free(adev, &ib);
 754 err0:
 755         amdgpu_wb_free(adev, index);
 756         return r;
 757 }
 758
 759 /**
 760  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 761  *
 762  * @ib: indirect buffer to fill with commands
 763  * @pe: addr of the page entry
 764  * @src: src addr to copy from
 765  * @count: number of page entries to update
 766  *
 767  * Update PTEs by copying them from the GART using sDMA (CIK).
 768  */
 769 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 770                                   uint64_t pe, uint64_t src,
 771                                   unsigned count)
 772 {
 773         while (count) {
 774                 unsigned bytes = count * 8;
 775                 if (bytes > 0x1FFFF8)
 776                         bytes = 0x1FFFF8;
 777
 778                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 779                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 780                 ib->ptr[ib->length_dw++] = bytes;
 781                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 782                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 783                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 784                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 785                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 786
 787                 pe += bytes;
 788                 src += bytes;
 789                 count -= bytes / 8;
 790         }
 791 }
 792
 793 /**
 794  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 795  *
 796  * @ib: indirect buffer to fill with commands
 797  * @pe: addr of the page entry
 798  * @addr: dst addr to write into pe
 799  * @count: number of page entries to update
 800  * @incr: increase next addr by incr bytes
 801  * @flags: access flags
 802  *
 803  * Update PTEs by writing them manually using sDMA (CIK).
 804  */
 805 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
 806                                    uint64_t pe,
 807                                    uint64_t addr, unsigned count,
 808                                    uint32_t incr, uint32_t flags)
 809 {
 810         uint64_t value;
 811         unsigned ndw;
 812
 813         while (count) {
 814                 ndw = count * 2;
 815                 if (ndw > 0xFFFFE)
 816                         ndw = 0xFFFFE;
 817
 818                 /* for non-physically contiguous pages (system) */
 819                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 820                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 821                 ib->ptr[ib->length_dw++] = pe;
 822                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 823                 ib->ptr[ib->length_dw++] = ndw;
 824                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 825                         if (flags & AMDGPU_PTE_SYSTEM) {
 826                                 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
 827                                 value &= 0xFFFFFFFFFFFFF000ULL;
 828                         } else if (flags & AMDGPU_PTE_VALID) {
 829                                 value = addr;
 830                         } else {
 831                                 value = 0;
 832                         }
 833                         addr += incr;
 834                         value |= flags;
 835                         ib->ptr[ib->length_dw++] = value;
 836                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 837                 }
 838         }
 839 }
 840
 841 /**
 842  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 843  *
 844  * @ib: indirect buffer to fill with commands
 845  * @pe: addr of the page entry
 846  * @addr: dst addr to write into pe
 847  * @count: number of page entries to update
 848  * @incr: increase next addr by incr bytes
 849  * @flags: access flags
 850  *
 851  * Update the page tables using sDMA (CIK).
 852  */
 853 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
 854                                      uint64_t pe,
 855                                      uint64_t addr, unsigned count,
 856                                      uint32_t incr, uint32_t flags)
 857 {
 858         uint64_t value;
 859         unsigned ndw;
 860
 861         while (count) {
 862                 ndw = count;
 863                 if (ndw > 0x7FFFF)
 864                         ndw = 0x7FFFF;
 865
 866                 if (flags & AMDGPU_PTE_VALID)
 867                         value = addr;
 868                 else
 869                         value = 0;
 870
 871                 /* for physically contiguous pages (vram) */
 872                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 873                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 874                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 875                 ib->ptr[ib->length_dw++] = flags; /* mask */
 876                 ib->ptr[ib->length_dw++] = 0;
 877                 ib->ptr[ib->length_dw++] = value; /* value */
 878                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 879                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 880                 ib->ptr[ib->length_dw++] = 0;
 881                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 882
 883                 pe += ndw * 8;
 884                 addr += ndw * incr;
 885                 count -= ndw;
 886         }
 887 }
 888
 889 /**
 890  * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw
 891  *
 892  * @ib: indirect buffer to fill with padding
 893  *
 894  */
 895 static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
 896 {
 897         struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ib->ring);
 898         u32 pad_count;
 899         int i;
 900
 901         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 902         for (i = 0; i < pad_count; i++)
 903                 if (sdma && sdma->burst_nop && (i == 0))
 904                         ib->ptr[ib->length_dw++] =
 905                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 906                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 907                 else
 908                         ib->ptr[ib->length_dw++] =
 909                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 910 }
 911
 912 /**
 913  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 914  *
 915  * @ring: amdgpu_ring pointer
 916  * @vm: amdgpu_vm pointer
 917  *
 918  * Update the page table base and flush the VM TLB
 919  * using sDMA (VI).
 920  */
 921 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 922                                          unsigned vm_id, uint64_t pd_addr)
 923 {
 924         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 925                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 926         if (vm_id < 8) {
 927                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 928         } else {
 929                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 930         }
 931         amdgpu_ring_write(ring, pd_addr >> 12);
 932
 933         /* flush TLB */
 934         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 935                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 936         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 937         amdgpu_ring_write(ring, 1 << vm_id);
 938
 939         /* wait for flush */
 940         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 941                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 942                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 943         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 944         amdgpu_ring_write(ring, 0);
 945         amdgpu_ring_write(ring, 0); /* reference */
 946         amdgpu_ring_write(ring, 0); /* mask */
 947         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 948                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 949 }
 950
 951 static int sdma_v2_4_early_init(void *handle)
 952 {
 953         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 954
 955         sdma_v2_4_set_ring_funcs(adev);
 956         sdma_v2_4_set_buffer_funcs(adev);
 957         sdma_v2_4_set_vm_pte_funcs(adev);
 958         sdma_v2_4_set_irq_funcs(adev);
 959
 960         return 0;
 961 }
 962
 963 static int sdma_v2_4_sw_init(void *handle)
 964 {
 965         struct amdgpu_ring *ring;
 966         int r;
 967         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 968
 969         /* SDMA trap event */
 970         r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
 971         if (r)
 972                 return r;
 973
 974         /* SDMA Privileged inst */
 975         r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
 976         if (r)
 977                 return r;
 978
 979         /* SDMA Privileged inst */
 980         r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
 981         if (r)
 982                 return r;
 983
 984         r = sdma_v2_4_init_microcode(adev);
 985         if (r) {
 986                 DRM_ERROR("Failed to load sdma firmware!\n");
 987                 return r;
 988         }
 989
 990         ring = &adev->sdma[0].ring;
 991         ring->ring_obj = NULL;
 992         ring->use_doorbell = false;
 993
 994         ring = &adev->sdma[1].ring;
 995         ring->ring_obj = NULL;
 996         ring->use_doorbell = false;
 997
 998         ring = &adev->sdma[0].ring;
 999         sprintf(ring->name, "sdma0");
1000         r = amdgpu_ring_init(adev, ring, 256 * 1024,
1001                              SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1002                              &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
1003                              AMDGPU_RING_TYPE_SDMA);
1004         if (r)
1005                 return r;
1006
1007         ring = &adev->sdma[1].ring;
1008         sprintf(ring->name, "sdma1");
1009         r = amdgpu_ring_init(adev, ring, 256 * 1024,
1010                              SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1011                              &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
1012                              AMDGPU_RING_TYPE_SDMA);
1013         if (r)
1014                 return r;
1015
1016         return r;
1017 }
1018
1019 static int sdma_v2_4_sw_fini(void *handle)
1020 {
1021         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1022
1023         amdgpu_ring_fini(&adev->sdma[0].ring);
1024         amdgpu_ring_fini(&adev->sdma[1].ring);
1025
1026         return 0;
1027 }
1028
1029 static int sdma_v2_4_hw_init(void *handle)
1030 {
1031         int r;
1032         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1033
1034         sdma_v2_4_init_golden_registers(adev);
1035
1036         r = sdma_v2_4_start(adev);
1037         if (r)
1038                 return r;
1039
1040         return r;
1041 }
1042
1043 static int sdma_v2_4_hw_fini(void *handle)
1044 {
1045         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1046
1047         sdma_v2_4_enable(adev, false);
1048
1049         return 0;
1050 }
1051
1052 static int sdma_v2_4_suspend(void *handle)
1053 {
1054         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1055
1056         return sdma_v2_4_hw_fini(adev);
1057 }
1058
1059 static int sdma_v2_4_resume(void *handle)
1060 {
1061         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1062
1063         return sdma_v2_4_hw_init(adev);
1064 }
1065
1066 static bool sdma_v2_4_is_idle(void *handle)
1067 {
1068         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1069         u32 tmp = RREG32(mmSRBM_STATUS2);
1070
1071         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1072                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1073             return false;
1074
1075         return true;
1076 }
1077
1078 static int sdma_v2_4_wait_for_idle(void *handle)
1079 {
1080         unsigned i;
1081         u32 tmp;
1082         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1083
1084         for (i = 0; i < adev->usec_timeout; i++) {
1085                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1086                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1087
1088                 if (!tmp)
1089                         return 0;
1090                 udelay(1);
1091         }
1092         return -ETIMEDOUT;
1093 }
1094
1095 static void sdma_v2_4_print_status(void *handle)
1096 {
1097         int i, j;
1098         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1099
1100         dev_info(adev->dev, "VI SDMA registers\n");
1101         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1102                  RREG32(mmSRBM_STATUS2));
1103         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1104                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
1105                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1106                 dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
1107                          i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1108                 dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
1109                          i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1110                 dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1111                          i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1112                 dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
1113                          i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1114                 dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
1115                          i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1116                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
1117                          i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1118                 dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
1119                          i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1120                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1121                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1122                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1123                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1124                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
1125                          i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1126                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1127                          i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1128                 mutex_lock(&adev->srbm_mutex);
1129                 for (j = 0; j < 16; j++) {
1130                         vi_srbm_select(adev, 0, 0, 0, j);
1131                         dev_info(adev->dev, "  VM %d:\n", j);
1132                         dev_info(adev->dev, "  SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1133                                  i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1134                         dev_info(adev->dev, "  SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1135                                  i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1136                 }
1137                 vi_srbm_select(adev, 0, 0, 0, 0);
1138                 mutex_unlock(&adev->srbm_mutex);
1139         }
1140 }
1141
1142 static int sdma_v2_4_soft_reset(void *handle)
1143 {
1144         u32 srbm_soft_reset = 0;
1145         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1146         u32 tmp = RREG32(mmSRBM_STATUS2);
1147
1148         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1149                 /* sdma0 */
1150                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1151                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1152                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1153                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1154         }
1155         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1156                 /* sdma1 */
1157                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1158                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1159                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1160                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1161         }
1162
1163         if (srbm_soft_reset) {
1164                 sdma_v2_4_print_status((void *)adev);
1165
1166                 tmp = RREG32(mmSRBM_SOFT_RESET);
1167                 tmp |= srbm_soft_reset;
1168                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1169                 WREG32(mmSRBM_SOFT_RESET, tmp);
1170                 tmp = RREG32(mmSRBM_SOFT_RESET);
1171
1172                 udelay(50);
1173
1174                 tmp &= ~srbm_soft_reset;
1175                 WREG32(mmSRBM_SOFT_RESET, tmp);
1176                 tmp = RREG32(mmSRBM_SOFT_RESET);
1177
1178                 /* Wait a little for things to settle down */
1179                 udelay(50);
1180
1181                 sdma_v2_4_print_status((void *)adev);
1182         }
1183
1184         return 0;
1185 }
1186
1187 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1188                                         struct amdgpu_irq_src *src,
1189                                         unsigned type,
1190                                         enum amdgpu_interrupt_state state)
1191 {
1192         u32 sdma_cntl;
1193
1194         switch (type) {
1195         case AMDGPU_SDMA_IRQ_TRAP0:
1196                 switch (state) {
1197                 case AMDGPU_IRQ_STATE_DISABLE:
1198                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1199                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1200                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1201                         break;
1202                 case AMDGPU_IRQ_STATE_ENABLE:
1203                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1204                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1205                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1206                         break;
1207                 default:
1208                         break;
1209                 }
1210                 break;
1211         case AMDGPU_SDMA_IRQ_TRAP1:
1212                 switch (state) {
1213                 case AMDGPU_IRQ_STATE_DISABLE:
1214                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1215                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1216                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1217                         break;
1218                 case AMDGPU_IRQ_STATE_ENABLE:
1219                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1220                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1221                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1222                         break;
1223                 default:
1224                         break;
1225                 }
1226                 break;
1227         default:
1228                 break;
1229         }
1230         return 0;
1231 }
1232
1233 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1234                                       struct amdgpu_irq_src *source,
1235                                       struct amdgpu_iv_entry *entry)
1236 {
1237         u8 instance_id, queue_id;
1238
1239         instance_id = (entry->ring_id & 0x3) >> 0;
1240         queue_id = (entry->ring_id & 0xc) >> 2;
1241         DRM_DEBUG("IH: SDMA trap\n");
1242         switch (instance_id) {
1243         case 0:
1244                 switch (queue_id) {
1245                 case 0:
1246                         amdgpu_fence_process(&adev->sdma[0].ring);
1247                         break;
1248                 case 1:
1249                         /* XXX compute */
1250                         break;
1251                 case 2:
1252                         /* XXX compute */
1253                         break;
1254                 }
1255                 break;
1256         case 1:
1257                 switch (queue_id) {
1258                 case 0:
1259                         amdgpu_fence_process(&adev->sdma[1].ring);
1260                         break;
1261                 case 1:
1262                         /* XXX compute */
1263                         break;
1264                 case 2:
1265                         /* XXX compute */
1266                         break;
1267                 }
1268                 break;
1269         }
1270         return 0;
1271 }
1272
1273 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1274                                               struct amdgpu_irq_src *source,
1275                                               struct amdgpu_iv_entry *entry)
1276 {
1277         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1278         schedule_work(&adev->reset_work);
1279         return 0;
1280 }
1281
1282 static int sdma_v2_4_set_clockgating_state(void *handle,
1283                                           enum amd_clockgating_state state)
1284 {
1285         /* XXX handled via the smc on VI */
1286         return 0;
1287 }
1288
1289 static int sdma_v2_4_set_powergating_state(void *handle,
1290                                           enum amd_powergating_state state)
1291 {
1292         return 0;
1293 }
1294
1295 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1296         .early_init = sdma_v2_4_early_init,
1297         .late_init = NULL,
1298         .sw_init = sdma_v2_4_sw_init,
1299         .sw_fini = sdma_v2_4_sw_fini,
1300         .hw_init = sdma_v2_4_hw_init,
1301         .hw_fini = sdma_v2_4_hw_fini,
1302         .suspend = sdma_v2_4_suspend,
1303         .resume = sdma_v2_4_resume,
1304         .is_idle = sdma_v2_4_is_idle,
1305         .wait_for_idle = sdma_v2_4_wait_for_idle,
1306         .soft_reset = sdma_v2_4_soft_reset,
1307         .print_status = sdma_v2_4_print_status,
1308         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1309         .set_powergating_state = sdma_v2_4_set_powergating_state,
1310 };
1311
1312 /**
1313  * sdma_v2_4_ring_is_lockup - Check if the DMA engine is locked up
1314  *
1315  * @ring: amdgpu_ring structure holding ring information
1316  *
1317  * Check if the async DMA engine is locked up (VI).
1318  * Returns true if the engine appears to be locked up, false if not.
1319  */
1320 static bool sdma_v2_4_ring_is_lockup(struct amdgpu_ring *ring)
1321 {
1322
1323         if (sdma_v2_4_is_idle(ring->adev)) {
1324                 amdgpu_ring_lockup_update(ring);
1325                 return false;
1326         }
1327         return amdgpu_ring_test_lockup(ring);
1328 }
1329
1330 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1331         .get_rptr = sdma_v2_4_ring_get_rptr,
1332         .get_wptr = sdma_v2_4_ring_get_wptr,
1333         .set_wptr = sdma_v2_4_ring_set_wptr,
1334         .parse_cs = NULL,
1335         .emit_ib = sdma_v2_4_ring_emit_ib,
1336         .emit_fence = sdma_v2_4_ring_emit_fence,
1337         .emit_semaphore = sdma_v2_4_ring_emit_semaphore,
1338         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1339         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1340         .test_ring = sdma_v2_4_ring_test_ring,
1341         .test_ib = sdma_v2_4_ring_test_ib,
1342         .is_lockup = sdma_v2_4_ring_is_lockup,
1343         .insert_nop = sdma_v2_4_ring_insert_nop,
1344 };
1345
1346 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1347 {
1348         adev->sdma[0].ring.funcs = &sdma_v2_4_ring_funcs;
1349         adev->sdma[1].ring.funcs = &sdma_v2_4_ring_funcs;
1350 }
1351
1352 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1353         .set = sdma_v2_4_set_trap_irq_state,
1354         .process = sdma_v2_4_process_trap_irq,
1355 };
1356
1357 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1358         .process = sdma_v2_4_process_illegal_inst_irq,
1359 };
1360
1361 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1362 {
1363         adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1364         adev->sdma_trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1365         adev->sdma_illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1366 }
1367
1368 /**
1369  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1370  *
1371  * @ring: amdgpu_ring structure holding ring information
1372  * @src_offset: src GPU address
1373  * @dst_offset: dst GPU address
1374  * @byte_count: number of bytes to xfer
1375  *
1376  * Copy GPU buffers using the DMA engine (VI).
1377  * Used by the amdgpu ttm implementation to move pages if
1378  * registered as the asic copy callback.
1379  */
1380 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1381                                        uint64_t src_offset,
1382                                        uint64_t dst_offset,
1383                                        uint32_t byte_count)
1384 {
1385         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1386                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1387         ib->ptr[ib->length_dw++] = byte_count;
1388         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1389         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1390         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1391         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1392         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1393 }
1394
1395 /**
1396  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1397  *
1398  * @ring: amdgpu_ring structure holding ring information
1399  * @src_data: value to write to buffer
1400  * @dst_offset: dst GPU address
1401  * @byte_count: number of bytes to xfer
1402  *
1403  * Fill GPU buffers using the DMA engine (VI).
1404  */
1405 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1406                                        uint32_t src_data,
1407                                        uint64_t dst_offset,
1408                                        uint32_t byte_count)
1409 {
1410         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1411         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1412         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1413         ib->ptr[ib->length_dw++] = src_data;
1414         ib->ptr[ib->length_dw++] = byte_count;
1415 }
1416
1417 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1418         .copy_max_bytes = 0x1fffff,
1419         .copy_num_dw = 7,
1420         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1421
1422         .fill_max_bytes = 0x1fffff,
1423         .fill_num_dw = 7,
1424         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1425 };
1426
1427 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1428 {
1429         if (adev->mman.buffer_funcs == NULL) {
1430                 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1431                 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1432         }
1433 }
1434
1435 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1436         .copy_pte = sdma_v2_4_vm_copy_pte,
1437         .write_pte = sdma_v2_4_vm_write_pte,
1438         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1439         .pad_ib = sdma_v2_4_vm_pad_ib,
1440 };
1441
1442 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1443 {
1444         if (adev->vm_manager.vm_pte_funcs == NULL) {
1445                 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1446                 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
1447                 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
1448         }
1449 }