2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * See "enum e752x_chips" below for supported chipsets
9 * Written by Tom Zimmerman
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
20 #include <linux/config.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/pci_ids.h>
25 #include <linux/slab.h>
28 #define e752x_printk(level, fmt, arg...) \
29 edac_printk(level, "e752x", fmt, ##arg)
31 #define e752x_mc_printk(mci, level, fmt, arg...) \
32 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
34 #ifndef PCI_DEVICE_ID_INTEL_7520_0
35 #define PCI_DEVICE_ID_INTEL_7520_0 0x3590
36 #endif /* PCI_DEVICE_ID_INTEL_7520_0 */
38 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
39 #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
40 #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
42 #ifndef PCI_DEVICE_ID_INTEL_7525_0
43 #define PCI_DEVICE_ID_INTEL_7525_0 0x359E
44 #endif /* PCI_DEVICE_ID_INTEL_7525_0 */
46 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
47 #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
48 #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
50 #ifndef PCI_DEVICE_ID_INTEL_7320_0
51 #define PCI_DEVICE_ID_INTEL_7320_0 0x3592
52 #endif /* PCI_DEVICE_ID_INTEL_7320_0 */
54 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
55 #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
56 #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
58 #define E752X_NR_CSROWS 8 /* number of csrows */
60 /* E752X register addresses - device 0 function 0 */
61 #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
62 #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
64 * 31:30 Device width row 7
65 * 01=x8 10=x4 11=x8 DDR2
66 * 27:26 Device width row 6
67 * 23:22 Device width row 5
68 * 19:20 Device width row 4
69 * 15:14 Device width row 3
70 * 11:10 Device width row 2
71 * 7:6 Device width row 1
72 * 3:2 Device width row 0
74 #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
75 /* FIXME:IS THIS RIGHT? */
77 * 22 Number channels 0=1,1=2
78 * 19:18 DRB Granularity 32/64MB
80 #define E752X_DRM 0x80 /* Dimm mapping register */
81 #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
83 * 14:12 1 single A, 2 single B, 3 dual
85 #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
86 #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
87 #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
88 #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
90 /* E752X register addresses - device 0 function 1 */
91 #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
92 #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
93 #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
94 #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
95 #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
96 #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
97 #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
98 #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
99 #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
100 #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
101 #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
102 #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
103 #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
104 #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */
105 #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
106 #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
107 #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
108 #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
109 #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
110 #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
111 /* error address register (32b) */
114 * 30:2 CE address (64 byte block 34:6)
118 #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
119 /* error address register (32b) */
122 * 30:2 CE address (64 byte block 34:6)
126 #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
127 /* error address register (32b) */
130 * 30:2 CE address (64 byte block 34:6)
134 #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */
135 /* error address register (32b) */
138 * 30:2 CE address (64 byte block 34:6)
142 #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
143 /* error syndrome register (16b) */
144 #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
145 /* error syndrome register (16b) */
146 #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
148 /* ICH5R register addresses - device 30 function 0 */
149 #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
150 #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
151 #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
160 struct pci_dev *bridge_ck;
161 struct pci_dev *dev_d0f0;
162 struct pci_dev *dev_d0f1;
169 const struct e752x_dev_info *dev_info;
172 struct e752x_dev_info {
175 const char *ctl_name;
178 struct e752x_error_info {
191 u16 dram_sec1_syndrome;
192 u16 dram_sec2_syndrome;
198 static const struct e752x_dev_info e752x_devs[] = {
200 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
201 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
205 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
206 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
210 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
211 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
216 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
220 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
222 debugf3("%s()\n", __func__);
224 if (page < pvt->tolm)
227 if ((page >= 0x100000) && (page < pvt->remapbase))
230 remap = (page - pvt->tolm) + pvt->remapbase;
232 if (remap < pvt->remaplimit)
235 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
236 return pvt->tolm - 1;
239 static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
240 u32 sec1_add, u16 sec1_syndrome)
246 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
248 debugf3("%s()\n", __func__);
250 /* convert the addr to 4k page */
251 page = sec1_add >> (PAGE_SHIFT - 4);
253 /* FIXME - check for -1 */
254 if (pvt->mc_symmetric) {
255 /* chip select are bits 14 & 13 */
256 row = ((page >> 1) & 3);
257 e752x_printk(KERN_WARNING,
258 "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
259 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
260 pvt->map[4], pvt->map[5], pvt->map[6], pvt->map[7]);
262 /* test for channel remapping */
263 for (i = 0; i < 8; i++) {
264 if (pvt->map[i] == row)
268 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
273 e752x_mc_printk(mci, KERN_WARNING,
274 "row %d not found in remap table\n", row);
276 row = edac_mc_find_csrow_by_page(mci, page);
278 /* 0 = channel A, 1 = channel B */
279 channel = !(error_one & 1);
284 edac_mc_handle_ce(mci, page, 0, sec1_syndrome, row, channel,
288 static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
289 u32 sec1_add, u16 sec1_syndrome, int *error_found,
295 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
298 static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
299 u32 ded_add, u32 scrb_add)
301 u32 error_2b, block_page;
303 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
305 debugf3("%s()\n", __func__);
307 if (error_one & 0x0202) {
310 /* convert to 4k address */
311 block_page = error_2b >> (PAGE_SHIFT - 4);
313 row = pvt->mc_symmetric ?
314 /* chip select are bits 14 & 13 */
315 ((block_page >> 1) & 3) :
316 edac_mc_find_csrow_by_page(mci, block_page);
318 edac_mc_handle_ue(mci, block_page, 0, row,
319 "e752x UE from Read");
321 if (error_one & 0x0404) {
324 /* convert to 4k address */
325 block_page = error_2b >> (PAGE_SHIFT - 4);
327 row = pvt->mc_symmetric ?
328 /* chip select are bits 14 & 13 */
329 ((block_page >> 1) & 3) :
330 edac_mc_find_csrow_by_page(mci, block_page);
332 edac_mc_handle_ue(mci, block_page, 0, row,
333 "e752x UE from Scruber");
337 static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
338 u32 ded_add, u32 scrb_add, int *error_found, int handle_error)
343 do_process_ue(mci, error_one, ded_add, scrb_add);
346 static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
347 int *error_found, int handle_error)
354 debugf3("%s()\n", __func__);
355 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
358 static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
363 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
365 error_1b = retry_add;
366 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
367 row = pvt->mc_symmetric ?
368 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
369 edac_mc_find_csrow_by_page(mci, page);
370 e752x_mc_printk(mci, KERN_WARNING,
371 "CE page 0x%lx, row %d : Memory read retry\n",
372 (long unsigned int) page, row);
375 static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
376 u32 retry_add, int *error_found, int handle_error)
381 do_process_ded_retry(mci, error, retry_add);
384 static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
385 int *error_found, int handle_error)
390 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
393 static char *global_message[11] = {
394 "PCI Express C1", "PCI Express C", "PCI Express B1",
395 "PCI Express B", "PCI Express A1", "PCI Express A",
396 "DMA Controler", "HUB Interface", "System Bus",
397 "DRAM Controler", "Internal Buffer"
400 static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
402 static void do_global_error(int fatal, u32 errors)
406 for (i = 0; i < 11; i++) {
407 if (errors & (1 << i))
408 e752x_printk(KERN_WARNING, "%sError %s\n",
409 fatal_message[fatal], global_message[i]);
413 static inline void global_error(int fatal, u32 errors, int *error_found,
419 do_global_error(fatal, errors);
422 static char *hub_message[7] = {
423 "HI Address or Command Parity", "HI Illegal Access",
424 "HI Internal Parity", "Out of Range Access",
425 "HI Data Parity", "Enhanced Config Access",
426 "Hub Interface Target Abort"
429 static void do_hub_error(int fatal, u8 errors)
433 for (i = 0; i < 7; i++) {
434 if (errors & (1 << i))
435 e752x_printk(KERN_WARNING, "%sError %s\n",
436 fatal_message[fatal], hub_message[i]);
440 static inline void hub_error(int fatal, u8 errors, int *error_found,
446 do_hub_error(fatal, errors);
449 static char *membuf_message[4] = {
450 "Internal PMWB to DRAM parity",
451 "Internal PMWB to System Bus Parity",
452 "Internal System Bus or IO to PMWB Parity",
453 "Internal DRAM to PMWB Parity"
456 static void do_membuf_error(u8 errors)
460 for (i = 0; i < 4; i++) {
461 if (errors & (1 << i))
462 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
467 static inline void membuf_error(u8 errors, int *error_found, int handle_error)
472 do_membuf_error(errors);
476 char *sysbus_message[10] = {
477 "Addr or Request Parity",
478 "Data Strobe Glitch",
479 "Addr Strobe Glitch",
482 "Non DRAM Lock Error",
485 "IO Subsystem Parity"
489 static void do_sysbus_error(int fatal, u32 errors)
493 for (i = 0; i < 10; i++) {
494 if (errors & (1 << i))
495 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
496 fatal_message[fatal], global_message[i]);
500 static inline void sysbus_error(int fatal, u32 errors, int *error_found,
506 do_sysbus_error(fatal, errors);
509 static void e752x_check_hub_interface(struct e752x_error_info *info,
510 int *error_found, int handle_error)
514 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
516 stat8 = info->hi_ferr;
518 if(stat8 & 0x7f) { /* Error, so process */
522 hub_error(1, stat8 & 0x2b, error_found, handle_error);
525 hub_error(0, stat8 & 0x54, error_found, handle_error);
528 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
530 stat8 = info->hi_nerr;
532 if(stat8 & 0x7f) { /* Error, so process */
536 hub_error(1, stat8 & 0x2b, error_found, handle_error);
539 hub_error(0, stat8 & 0x54, error_found, handle_error);
543 static void e752x_check_sysbus(struct e752x_error_info *info,
544 int *error_found, int handle_error)
548 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
549 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
552 return; /* no errors */
554 error32 = (stat32 >> 16) & 0x3ff;
555 stat32 = stat32 & 0x3ff;
558 sysbus_error(1, stat32 & 0x083, error_found, handle_error);
561 sysbus_error(0, stat32 & 0x37c, error_found, handle_error);
564 sysbus_error(1, error32 & 0x083, error_found, handle_error);
567 sysbus_error(0, error32 & 0x37c, error_found, handle_error);
570 static void e752x_check_membuf (struct e752x_error_info *info,
571 int *error_found, int handle_error)
575 stat8 = info->buf_ferr;
577 if (stat8 & 0x0f) { /* Error, so process */
579 membuf_error(stat8, error_found, handle_error);
582 stat8 = info->buf_nerr;
584 if (stat8 & 0x0f) { /* Error, so process */
586 membuf_error(stat8, error_found, handle_error);
590 static void e752x_check_dram (struct mem_ctl_info *mci,
591 struct e752x_error_info *info, int *error_found,
594 u16 error_one, error_next;
596 error_one = info->dram_ferr;
597 error_next = info->dram_nerr;
599 /* decode and report errors */
600 if(error_one & 0x0101) /* check first error correctable */
601 process_ce(mci, error_one, info->dram_sec1_add,
602 info->dram_sec1_syndrome, error_found,
605 if(error_next & 0x0101) /* check next error correctable */
606 process_ce(mci, error_next, info->dram_sec2_add,
607 info->dram_sec2_syndrome, error_found,
610 if(error_one & 0x4040)
611 process_ue_no_info_wr(mci, error_found, handle_error);
613 if(error_next & 0x4040)
614 process_ue_no_info_wr(mci, error_found, handle_error);
616 if(error_one & 0x2020)
617 process_ded_retry(mci, error_one, info->dram_retr_add,
618 error_found, handle_error);
620 if(error_next & 0x2020)
621 process_ded_retry(mci, error_next, info->dram_retr_add,
622 error_found, handle_error);
624 if(error_one & 0x0808)
625 process_threshold_ce(mci, error_one, error_found,
628 if(error_next & 0x0808)
629 process_threshold_ce(mci, error_next, error_found,
632 if(error_one & 0x0606)
633 process_ue(mci, error_one, info->dram_ded_add,
634 info->dram_scrb_add, error_found, handle_error);
636 if(error_next & 0x0606)
637 process_ue(mci, error_next, info->dram_ded_add,
638 info->dram_scrb_add, error_found, handle_error);
641 static void e752x_get_error_info (struct mem_ctl_info *mci,
642 struct e752x_error_info *info)
645 struct e752x_pvt *pvt;
647 memset(info, 0, sizeof(*info));
648 pvt = (struct e752x_pvt *) mci->pvt_info;
650 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
652 if (info->ferr_global) {
653 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
654 pci_read_config_word(dev, E752X_SYSBUS_FERR,
656 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
657 pci_read_config_word(dev, E752X_DRAM_FERR,
659 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
660 &info->dram_sec1_add);
661 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
662 &info->dram_sec1_syndrome);
663 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
664 &info->dram_ded_add);
665 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
666 &info->dram_scrb_add);
667 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
668 &info->dram_retr_add);
670 if (info->hi_ferr & 0x7f)
671 pci_write_config_byte(dev, E752X_HI_FERR,
674 if (info->sysbus_ferr)
675 pci_write_config_word(dev, E752X_SYSBUS_FERR,
678 if (info->buf_ferr & 0x0f)
679 pci_write_config_byte(dev, E752X_BUF_FERR,
683 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
684 info->dram_ferr, info->dram_ferr);
686 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
690 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
692 if (info->nerr_global) {
693 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
694 pci_read_config_word(dev, E752X_SYSBUS_NERR,
696 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
697 pci_read_config_word(dev, E752X_DRAM_NERR,
699 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
700 &info->dram_sec2_add);
701 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
702 &info->dram_sec2_syndrome);
704 if (info->hi_nerr & 0x7f)
705 pci_write_config_byte(dev, E752X_HI_NERR,
708 if (info->sysbus_nerr)
709 pci_write_config_word(dev, E752X_SYSBUS_NERR,
712 if (info->buf_nerr & 0x0f)
713 pci_write_config_byte(dev, E752X_BUF_NERR,
717 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
718 info->dram_nerr, info->dram_nerr);
720 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
725 static int e752x_process_error_info (struct mem_ctl_info *mci,
726 struct e752x_error_info *info, int handle_errors)
732 error32 = (info->ferr_global >> 18) & 0x3ff;
733 stat32 = (info->ferr_global >> 4) & 0x7ff;
736 global_error(1, error32, &error_found, handle_errors);
739 global_error(0, stat32, &error_found, handle_errors);
741 error32 = (info->nerr_global >> 18) & 0x3ff;
742 stat32 = (info->nerr_global >> 4) & 0x7ff;
745 global_error(1, error32, &error_found, handle_errors);
748 global_error(0, stat32, &error_found, handle_errors);
750 e752x_check_hub_interface(info, &error_found, handle_errors);
751 e752x_check_sysbus(info, &error_found, handle_errors);
752 e752x_check_membuf(info, &error_found, handle_errors);
753 e752x_check_dram(mci, info, &error_found, handle_errors);
757 static void e752x_check(struct mem_ctl_info *mci)
759 struct e752x_error_info info;
761 debugf3("%s()\n", __func__);
762 e752x_get_error_info(mci, &info);
763 e752x_process_error_info(mci, &info, 1);
766 static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
772 struct mem_ctl_info *mci = NULL;
773 struct e752x_pvt *pvt = NULL;
776 int drc_chan; /* Number of channels 0=1chan,1=2chan */
777 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
778 int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
780 unsigned long last_cumul_size;
781 struct pci_dev *dev = NULL;
782 struct e752x_error_info discard;
784 debugf0("%s(): mci\n", __func__);
785 debugf0("Starting Probe1\n");
787 /* enable device 0 function 1 */
788 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
790 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
792 /* need to find out the number of channels */
793 pci_read_config_dword(pdev, E752X_DRC, &drc);
794 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
795 /* FIXME: should check >>12 or 0xf, true for all? */
796 /* Dual channel = 1, Single channel = 0 */
797 drc_chan = (((ddrcsr >> 12) & 3) == 3);
798 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
799 drc_ddim = (drc >> 20) & 0x3;
801 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1);
808 debugf3("%s(): init mci\n", __func__);
809 mci->mtype_cap = MEM_FLAG_RDDR;
810 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
812 /* FIXME - what if different memory types are in different csrows? */
813 mci->mod_name = EDAC_MOD_STR;
814 mci->mod_ver = "$Revision: 1.5.2.11 $";
817 debugf3("%s(): init pvt\n", __func__);
818 pvt = (struct e752x_pvt *) mci->pvt_info;
819 pvt->dev_info = &e752x_devs[dev_idx];
820 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
821 pvt->dev_info->err_dev,
824 if (pvt->bridge_ck == NULL)
825 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
828 if (pvt->bridge_ck == NULL) {
829 e752x_printk(KERN_ERR, "error reporting device not found:"
830 "vendor %x device 0x%x (broken BIOS?)\n",
831 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
835 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
836 debugf3("%s(): more mci init\n", __func__);
837 mci->ctl_name = pvt->dev_info->ctl_name;
838 mci->edac_check = e752x_check;
839 mci->ctl_page_to_phys = ctl_page_to_phys;
841 /* find out the device types */
842 pci_read_config_dword(pdev, E752X_DRA, &dra);
845 * The dram row boundary (DRB) reg values are boundary address for
846 * each DRAM row with a granularity of 64 or 128MB (single/dual
847 * channel operation). DRB regs are cumulative; therefore DRB7 will
848 * contain the total memory contained in all eight rows.
850 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
854 /* mem_dev 0=x8, 1=x4 */
855 int mem_dev = (dra >> (index * 4 + 2)) & 0x3;
856 struct csrow_info *csrow = &mci->csrows[index];
858 mem_dev = (mem_dev == 2);
859 pci_read_config_byte(mci->pdev, E752X_DRB + index, &value);
860 /* convert a 128 or 64 MiB DRB to a page size. */
861 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
862 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
865 if (cumul_size == last_cumul_size)
866 continue; /* not populated */
868 csrow->first_page = last_cumul_size;
869 csrow->last_page = cumul_size - 1;
870 csrow->nr_pages = cumul_size - last_cumul_size;
871 last_cumul_size = cumul_size;
872 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
873 csrow->mtype = MEM_RDDR; /* only one type supported */
874 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
877 * if single channel or x8 devices then SECDED
878 * if dual channel and x4 then S4ECD4ED
881 if (drc_chan && mem_dev) {
882 csrow->edac_mode = EDAC_S4ECD4ED;
883 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
885 csrow->edac_mode = EDAC_SECDED;
886 mci->edac_cap |= EDAC_FLAG_SECDED;
889 csrow->edac_mode = EDAC_NONE;
892 /* Fill in the memory map table */
898 for (index = 0; index < 8; index += 2) {
899 pci_read_config_byte(mci->pdev, E752X_DRB + index,
902 /* test if there is a dimm in this slot */
904 /* no dimm in the slot, so flag it as empty */
905 pvt->map[index] = 0xff;
906 pvt->map[index + 1] = 0xff;
907 } else { /* there is a dimm in the slot */
908 pvt->map[index] = row;
911 /* test the next value to see if the dimm is
913 pci_read_config_byte(mci->pdev,
914 E752X_DRB + index + 1,
916 pvt->map[index + 1] = (value == last) ?
917 0xff : /* the dimm is single sided,
920 row; /* this is a double sided dimm
921 * to save the next row #
929 /* set the map type. 1 = normal, 0 = reversed */
930 pci_read_config_byte(mci->pdev, E752X_DRM, &stat8);
931 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
933 mci->edac_cap |= EDAC_FLAG_NONE;
934 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
936 /* load the top of low memory, remap base, and remap limit vars */
937 pci_read_config_word(mci->pdev, E752X_TOLM, &pci_data);
938 pvt->tolm = ((u32) pci_data) << 4;
939 pci_read_config_word(mci->pdev, E752X_REMAPBASE, &pci_data);
940 pvt->remapbase = ((u32) pci_data) << 14;
941 pci_read_config_word(mci->pdev, E752X_REMAPLIMIT, &pci_data);
942 pvt->remaplimit = ((u32) pci_data) << 14;
943 e752x_printk(KERN_INFO,
944 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
945 pvt->remapbase, pvt->remaplimit);
947 if (edac_mc_add_mc(mci)) {
948 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
952 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
955 /* find the error reporting device and clear errors */
956 dev = pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
957 /* Turn off error disable & SMI in case the BIOS turned it on */
958 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
959 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
960 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
961 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
962 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
963 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
964 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
965 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
967 e752x_get_error_info(mci, &discard); /* clear other MCH errors */
969 /* get this far and it's successful */
970 debugf3("%s(): success\n", __func__);
976 pci_dev_put(pvt->dev_d0f0);
979 pci_dev_put(pvt->dev_d0f1);
982 pci_dev_put(pvt->bridge_ck);
990 /* returns count (>= 0), or negative on error */
991 static int __devinit e752x_init_one(struct pci_dev *pdev,
992 const struct pci_device_id *ent)
994 debugf0("%s()\n", __func__);
996 /* wake up and enable device */
997 if(pci_enable_device(pdev) < 0)
1000 return e752x_probe1(pdev, ent->driver_data);
1003 static void __devexit e752x_remove_one(struct pci_dev *pdev)
1005 struct mem_ctl_info *mci;
1006 struct e752x_pvt *pvt;
1008 debugf0("%s()\n", __func__);
1010 if ((mci = edac_mc_del_mc(pdev)) == NULL)
1013 pvt = (struct e752x_pvt *) mci->pvt_info;
1014 pci_dev_put(pvt->dev_d0f0);
1015 pci_dev_put(pvt->dev_d0f1);
1016 pci_dev_put(pvt->bridge_ck);
1020 static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
1022 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1026 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1030 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1035 } /* 0 terminated list. */
1038 MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1040 static struct pci_driver e752x_driver = {
1041 .name = EDAC_MOD_STR,
1042 .probe = e752x_init_one,
1043 .remove = __devexit_p(e752x_remove_one),
1044 .id_table = e752x_pci_tbl,
1047 static int __init e752x_init(void)
1051 debugf3("%s()\n", __func__);
1052 pci_rc = pci_register_driver(&e752x_driver);
1053 return (pci_rc < 0) ? pci_rc : 0;
1056 static void __exit e752x_exit(void)
1058 debugf3("%s()\n", __func__);
1059 pci_unregister_driver(&e752x_driver);
1062 module_init(e752x_init);
1063 module_exit(e752x_exit);
1065 MODULE_LICENSE("GPL");
1066 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1067 MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");