drivers/dma/ste_dma40.c

   1 /*
   2  * Copyright (C) Ericsson AB 2007-2008
   3  * Copyright (C) ST-Ericsson SA 2008-2010
   4  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
   5  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
   6  * License terms: GNU General Public License (GPL) version 2
   7  */
   8
   9 #include <linux/dma-mapping.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/export.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/pm.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/err.h>
  20 #include <linux/of.h>
  21 #include <linux/of_dma.h>
  22 #include <linux/amba/bus.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/platform_data/dma-ste-dma40.h>
  25
  26 #include "dmaengine.h"
  27 #include "ste_dma40_ll.h"
  28
  29 #define D40_NAME "dma40"
  30
  31 #define D40_PHY_CHAN -1
  32
  33 /* For masking out/in 2 bit channel positions */
  34 #define D40_CHAN_POS(chan)  (2 * (chan / 2))
  35 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
  36
  37 /* Maximum iterations taken before giving up suspending a channel */
  38 #define D40_SUSPEND_MAX_IT 500
  39
  40 /* Milliseconds */
  41 #define DMA40_AUTOSUSPEND_DELAY 100
  42
  43 /* Hardware requirement on LCLA alignment */
  44 #define LCLA_ALIGNMENT 0x40000
  45
  46 /* Max number of links per event group */
  47 #define D40_LCLA_LINK_PER_EVENT_GRP 128
  48 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
  49
  50 /* Max number of logical channels per physical channel */
  51 #define D40_MAX_LOG_CHAN_PER_PHY 32
  52
  53 /* Attempts before giving up to trying to get pages that are aligned */
  54 #define MAX_LCLA_ALLOC_ATTEMPTS 256
  55
  56 /* Bit markings for allocation map */
  57 #define D40_ALLOC_FREE          BIT(31)
  58 #define D40_ALLOC_PHY           BIT(30)
  59 #define D40_ALLOC_LOG_FREE      0
  60
  61 #define D40_MEMCPY_MAX_CHANS    8
  62
  63 /* Reserved event lines for memcpy only. */
  64 #define DB8500_DMA_MEMCPY_EV_0  51
  65 #define DB8500_DMA_MEMCPY_EV_1  56
  66 #define DB8500_DMA_MEMCPY_EV_2  57
  67 #define DB8500_DMA_MEMCPY_EV_3  58
  68 #define DB8500_DMA_MEMCPY_EV_4  59
  69 #define DB8500_DMA_MEMCPY_EV_5  60
  70
  71 static int dma40_memcpy_channels[] = {
  72         DB8500_DMA_MEMCPY_EV_0,
  73         DB8500_DMA_MEMCPY_EV_1,
  74         DB8500_DMA_MEMCPY_EV_2,
  75         DB8500_DMA_MEMCPY_EV_3,
  76         DB8500_DMA_MEMCPY_EV_4,
  77         DB8500_DMA_MEMCPY_EV_5,
  78 };
  79
  80 /* Default configuration for physcial memcpy */
  81 static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
  82         .mode = STEDMA40_MODE_PHYSICAL,
  83         .dir = DMA_MEM_TO_MEM,
  84
  85         .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  86         .src_info.psize = STEDMA40_PSIZE_PHY_1,
  87         .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  88
  89         .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  90         .dst_info.psize = STEDMA40_PSIZE_PHY_1,
  91         .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  92 };
  93
  94 /* Default configuration for logical memcpy */
  95 static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
  96         .mode = STEDMA40_MODE_LOGICAL,
  97         .dir = DMA_MEM_TO_MEM,
  98
  99         .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 100         .src_info.psize = STEDMA40_PSIZE_LOG_1,
 101         .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 102
 103         .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 104         .dst_info.psize = STEDMA40_PSIZE_LOG_1,
 105         .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 106 };
 107
 108 /**
 109  * enum 40_command - The different commands and/or statuses.
 110  *
 111  * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
 112  * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
 113  * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
 114  * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
 115  */
 116 enum d40_command {
 117         D40_DMA_STOP            = 0,
 118         D40_DMA_RUN             = 1,
 119         D40_DMA_SUSPEND_REQ     = 2,
 120         D40_DMA_SUSPENDED       = 3
 121 };
 122
 123 /*
 124  * enum d40_events - The different Event Enables for the event lines.
 125  *
 126  * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
 127  * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
 128  * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
 129  * @D40_ROUND_EVENTLINE: Status check for event line.
 130  */
 131
 132 enum d40_events {
 133         D40_DEACTIVATE_EVENTLINE        = 0,
 134         D40_ACTIVATE_EVENTLINE          = 1,
 135         D40_SUSPEND_REQ_EVENTLINE       = 2,
 136         D40_ROUND_EVENTLINE             = 3
 137 };
 138
 139 /*
 140  * These are the registers that has to be saved and later restored
 141  * when the DMA hw is powered off.
 142  * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
 143  */
 144 static u32 d40_backup_regs[] = {
 145         D40_DREG_LCPA,
 146         D40_DREG_LCLA,
 147         D40_DREG_PRMSE,
 148         D40_DREG_PRMSO,
 149         D40_DREG_PRMOE,
 150         D40_DREG_PRMOO,
 151 };
 152
 153 #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
 154
 155 /*
 156  * since 9540 and 8540 has the same HW revision
 157  * use v4a for 9540 or ealier
 158  * use v4b for 8540 or later
 159  * HW revision:
 160  * DB8500ed has revision 0
 161  * DB8500v1 has revision 2
 162  * DB8500v2 has revision 3
 163  * AP9540v1 has revision 4
 164  * DB8540v1 has revision 4
 165  * TODO: Check if all these registers have to be saved/restored on dma40 v4a
 166  */
 167 static u32 d40_backup_regs_v4a[] = {
 168         D40_DREG_PSEG1,
 169         D40_DREG_PSEG2,
 170         D40_DREG_PSEG3,
 171         D40_DREG_PSEG4,
 172         D40_DREG_PCEG1,
 173         D40_DREG_PCEG2,
 174         D40_DREG_PCEG3,
 175         D40_DREG_PCEG4,
 176         D40_DREG_RSEG1,
 177         D40_DREG_RSEG2,
 178         D40_DREG_RSEG3,
 179         D40_DREG_RSEG4,
 180         D40_DREG_RCEG1,
 181         D40_DREG_RCEG2,
 182         D40_DREG_RCEG3,
 183         D40_DREG_RCEG4,
 184 };
 185
 186 #define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
 187
 188 static u32 d40_backup_regs_v4b[] = {
 189         D40_DREG_CPSEG1,
 190         D40_DREG_CPSEG2,
 191         D40_DREG_CPSEG3,
 192         D40_DREG_CPSEG4,
 193         D40_DREG_CPSEG5,
 194         D40_DREG_CPCEG1,
 195         D40_DREG_CPCEG2,
 196         D40_DREG_CPCEG3,
 197         D40_DREG_CPCEG4,
 198         D40_DREG_CPCEG5,
 199         D40_DREG_CRSEG1,
 200         D40_DREG_CRSEG2,
 201         D40_DREG_CRSEG3,
 202         D40_DREG_CRSEG4,
 203         D40_DREG_CRSEG5,
 204         D40_DREG_CRCEG1,
 205         D40_DREG_CRCEG2,
 206         D40_DREG_CRCEG3,
 207         D40_DREG_CRCEG4,
 208         D40_DREG_CRCEG5,
 209 };
 210
 211 #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
 212
 213 static u32 d40_backup_regs_chan[] = {
 214         D40_CHAN_REG_SSCFG,
 215         D40_CHAN_REG_SSELT,
 216         D40_CHAN_REG_SSPTR,
 217         D40_CHAN_REG_SSLNK,
 218         D40_CHAN_REG_SDCFG,
 219         D40_CHAN_REG_SDELT,
 220         D40_CHAN_REG_SDPTR,
 221         D40_CHAN_REG_SDLNK,
 222 };
 223
 224 #define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
 225                              BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
 226
 227 /**
 228  * struct d40_interrupt_lookup - lookup table for interrupt handler
 229  *
 230  * @src: Interrupt mask register.
 231  * @clr: Interrupt clear register.
 232  * @is_error: true if this is an error interrupt.
 233  * @offset: start delta in the lookup_log_chans in d40_base. If equals to
 234  * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
 235  */
 236 struct d40_interrupt_lookup {
 237         u32 src;
 238         u32 clr;
 239         bool is_error;
 240         int offset;
 241 };
 242
 243
 244 static struct d40_interrupt_lookup il_v4a[] = {
 245         {D40_DREG_LCTIS0, D40_DREG_LCICR0, false,  0},
 246         {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
 247         {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
 248         {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
 249         {D40_DREG_LCEIS0, D40_DREG_LCICR0, true,   0},
 250         {D40_DREG_LCEIS1, D40_DREG_LCICR1, true,  32},
 251         {D40_DREG_LCEIS2, D40_DREG_LCICR2, true,  64},
 252         {D40_DREG_LCEIS3, D40_DREG_LCICR3, true,  96},
 253         {D40_DREG_PCTIS,  D40_DREG_PCICR,  false, D40_PHY_CHAN},
 254         {D40_DREG_PCEIS,  D40_DREG_PCICR,  true,  D40_PHY_CHAN},
 255 };
 256
 257 static struct d40_interrupt_lookup il_v4b[] = {
 258         {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false,  0},
 259         {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
 260         {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
 261         {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
 262         {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
 263         {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true,   0},
 264         {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true,  32},
 265         {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true,  64},
 266         {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true,  96},
 267         {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true,  128},
 268         {D40_DREG_CPCTIS,  D40_DREG_CPCICR,  false, D40_PHY_CHAN},
 269         {D40_DREG_CPCEIS,  D40_DREG_CPCICR,  true,  D40_PHY_CHAN},
 270 };
 271
 272 /**
 273  * struct d40_reg_val - simple lookup struct
 274  *
 275  * @reg: The register.
 276  * @val: The value that belongs to the register in reg.
 277  */
 278 struct d40_reg_val {
 279         unsigned int reg;
 280         unsigned int val;
 281 };
 282
 283 static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
 284         /* Clock every part of the DMA block from start */
 285         { .reg = D40_DREG_GCC,    .val = D40_DREG_GCC_ENABLE_ALL},
 286
 287         /* Interrupts on all logical channels */
 288         { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
 289         { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
 290         { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
 291         { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
 292         { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
 293         { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
 294         { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
 295         { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
 296         { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
 297         { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
 298         { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
 299         { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
 300 };
 301 static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
 302         /* Clock every part of the DMA block from start */
 303         { .reg = D40_DREG_GCC,    .val = D40_DREG_GCC_ENABLE_ALL},
 304
 305         /* Interrupts on all logical channels */
 306         { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
 307         { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
 308         { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
 309         { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
 310         { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
 311         { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
 312         { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
 313         { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
 314         { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
 315         { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
 316         { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
 317         { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
 318         { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
 319         { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
 320         { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
 321 };
 322
 323 /**
 324  * struct d40_lli_pool - Structure for keeping LLIs in memory
 325  *
 326  * @base: Pointer to memory area when the pre_alloc_lli's are not large
 327  * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
 328  * pre_alloc_lli is used.
 329  * @dma_addr: DMA address, if mapped
 330  * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
 331  * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
 332  * one buffer to one buffer.
 333  */
 334 struct d40_lli_pool {
 335         void    *base;
 336         int      size;
 337         dma_addr_t      dma_addr;
 338         /* Space for dst and src, plus an extra for padding */
 339         u8       pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
 340 };
 341
 342 /**
 343  * struct d40_desc - A descriptor is one DMA job.
 344  *
 345  * @lli_phy: LLI settings for physical channel. Both src and dst=
 346  * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
 347  * lli_len equals one.
 348  * @lli_log: Same as above but for logical channels.
 349  * @lli_pool: The pool with two entries pre-allocated.
 350  * @lli_len: Number of llis of current descriptor.
 351  * @lli_current: Number of transferred llis.
 352  * @lcla_alloc: Number of LCLA entries allocated.
 353  * @txd: DMA engine struct. Used for among other things for communication
 354  * during a transfer.
 355  * @node: List entry.
 356  * @is_in_client_list: true if the client owns this descriptor.
 357  * @cyclic: true if this is a cyclic job
 358  *
 359  * This descriptor is used for both logical and physical transfers.
 360  */
 361 struct d40_desc {
 362         /* LLI physical */
 363         struct d40_phy_lli_bidir         lli_phy;
 364         /* LLI logical */
 365         struct d40_log_lli_bidir         lli_log;
 366
 367         struct d40_lli_pool              lli_pool;
 368         int                              lli_len;
 369         int                              lli_current;
 370         int                              lcla_alloc;
 371
 372         struct dma_async_tx_descriptor   txd;
 373         struct list_head                 node;
 374
 375         bool                             is_in_client_list;
 376         bool                             cyclic;
 377 };
 378
 379 /**
 380  * struct d40_lcla_pool - LCLA pool settings and data.
 381  *
 382  * @base: The virtual address of LCLA. 18 bit aligned.
 383  * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
 384  * This pointer is only there for clean-up on error.
 385  * @pages: The number of pages needed for all physical channels.
 386  * Only used later for clean-up on error
 387  * @lock: Lock to protect the content in this struct.
 388  * @alloc_map: big map over which LCLA entry is own by which job.
 389  */
 390 struct d40_lcla_pool {
 391         void            *base;
 392         dma_addr_t      dma_addr;
 393         void            *base_unaligned;
 394         int              pages;
 395         spinlock_t       lock;
 396         struct d40_desc **alloc_map;
 397 };
 398
 399 /**
 400  * struct d40_phy_res - struct for handling eventlines mapped to physical
 401  * channels.
 402  *
 403  * @lock: A lock protection this entity.
 404  * @reserved: True if used by secure world or otherwise.
 405  * @num: The physical channel number of this entity.
 406  * @allocated_src: Bit mapped to show which src event line's are mapped to
 407  * this physical channel. Can also be free or physically allocated.
 408  * @allocated_dst: Same as for src but is dst.
 409  * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
 410  * event line number.
 411  * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
 412  */
 413 struct d40_phy_res {
 414         spinlock_t lock;
 415         bool       reserved;
 416         int        num;
 417         u32        allocated_src;
 418         u32        allocated_dst;
 419         bool       use_soft_lli;
 420 };
 421
 422 struct d40_base;
 423
 424 /**
 425  * struct d40_chan - Struct that describes a channel.
 426  *
 427  * @lock: A spinlock to protect this struct.
 428  * @log_num: The logical number, if any of this channel.
 429  * @pending_tx: The number of pending transfers. Used between interrupt handler
 430  * and tasklet.
 431  * @busy: Set to true when transfer is ongoing on this channel.
 432  * @phy_chan: Pointer to physical channel which this instance runs on. If this
 433  * point is NULL, then the channel is not allocated.
 434  * @chan: DMA engine handle.
 435  * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
 436  * transfer and call client callback.
 437  * @client: Cliented owned descriptor list.
 438  * @pending_queue: Submitted jobs, to be issued by issue_pending()
 439  * @active: Active descriptor.
 440  * @done: Completed jobs
 441  * @queue: Queued jobs.
 442  * @prepare_queue: Prepared jobs.
 443  * @dma_cfg: The client configuration of this dma channel.
 444  * @configured: whether the dma_cfg configuration is valid
 445  * @base: Pointer to the device instance struct.
 446  * @src_def_cfg: Default cfg register setting for src.
 447  * @dst_def_cfg: Default cfg register setting for dst.
 448  * @log_def: Default logical channel settings.
 449  * @lcpa: Pointer to dst and src lcpa settings.
 450  * @runtime_addr: runtime configured address.
 451  * @runtime_direction: runtime configured direction.
 452  *
 453  * This struct can either "be" a logical or a physical channel.
 454  */
 455 struct d40_chan {
 456         spinlock_t                       lock;
 457         int                              log_num;
 458         int                              pending_tx;
 459         bool                             busy;
 460         struct d40_phy_res              *phy_chan;
 461         struct dma_chan                  chan;
 462         struct tasklet_struct            tasklet;
 463         struct list_head                 client;
 464         struct list_head                 pending_queue;
 465         struct list_head                 active;
 466         struct list_head                 done;
 467         struct list_head                 queue;
 468         struct list_head                 prepare_queue;
 469         struct stedma40_chan_cfg         dma_cfg;
 470         bool                             configured;
 471         struct d40_base                 *base;
 472         /* Default register configurations */
 473         u32                              src_def_cfg;
 474         u32                              dst_def_cfg;
 475         struct d40_def_lcsp              log_def;
 476         struct d40_log_lli_full         *lcpa;
 477         /* Runtime reconfiguration */
 478         dma_addr_t                      runtime_addr;
 479         enum dma_transfer_direction     runtime_direction;
 480 };
 481
 482 /**
 483  * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
 484  * controller
 485  *
 486  * @backup: the pointer to the registers address array for backup
 487  * @backup_size: the size of the registers address array for backup
 488  * @realtime_en: the realtime enable register
 489  * @realtime_clear: the realtime clear register
 490  * @high_prio_en: the high priority enable register
 491  * @high_prio_clear: the high priority clear register
 492  * @interrupt_en: the interrupt enable register
 493  * @interrupt_clear: the interrupt clear register
 494  * @il: the pointer to struct d40_interrupt_lookup
 495  * @il_size: the size of d40_interrupt_lookup array
 496  * @init_reg: the pointer to the struct d40_reg_val
 497  * @init_reg_size: the size of d40_reg_val array
 498  */
 499 struct d40_gen_dmac {
 500         u32                             *backup;
 501         u32                              backup_size;
 502         u32                              realtime_en;
 503         u32                              realtime_clear;
 504         u32                              high_prio_en;
 505         u32                              high_prio_clear;
 506         u32                              interrupt_en;
 507         u32                              interrupt_clear;
 508         struct d40_interrupt_lookup     *il;
 509         u32                              il_size;
 510         struct d40_reg_val              *init_reg;
 511         u32                              init_reg_size;
 512 };
 513
 514 /**
 515  * struct d40_base - The big global struct, one for each probe'd instance.
 516  *
 517  * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
 518  * @execmd_lock: Lock for execute command usage since several channels share
 519  * the same physical register.
 520  * @dev: The device structure.
 521  * @virtbase: The virtual base address of the DMA's register.
 522  * @rev: silicon revision detected.
 523  * @clk: Pointer to the DMA clock structure.
 524  * @phy_start: Physical memory start of the DMA registers.
 525  * @phy_size: Size of the DMA register map.
 526  * @irq: The IRQ number.
 527  * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
 528  * transfers).
 529  * @num_phy_chans: The number of physical channels. Read from HW. This
 530  * is the number of available channels for this driver, not counting "Secure
 531  * mode" allocated physical channels.
 532  * @num_log_chans: The number of logical channels. Calculated from
 533  * num_phy_chans.
 534  * @dma_both: dma_device channels that can do both memcpy and slave transfers.
 535  * @dma_slave: dma_device channels that can do only do slave transfers.
 536  * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
 537  * @phy_chans: Room for all possible physical channels in system.
 538  * @log_chans: Room for all possible logical channels in system.
 539  * @lookup_log_chans: Used to map interrupt number to logical channel. Points
 540  * to log_chans entries.
 541  * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
 542  * to phy_chans entries.
 543  * @plat_data: Pointer to provided platform_data which is the driver
 544  * configuration.
 545  * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
 546  * @phy_res: Vector containing all physical channels.
 547  * @lcla_pool: lcla pool settings and data.
 548  * @lcpa_base: The virtual mapped address of LCPA.
 549  * @phy_lcpa: The physical address of the LCPA.
 550  * @lcpa_size: The size of the LCPA area.
 551  * @desc_slab: cache for descriptors.
 552  * @reg_val_backup: Here the values of some hardware registers are stored
 553  * before the DMA is powered off. They are restored when the power is back on.
 554  * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
 555  * later
 556  * @reg_val_backup_chan: Backup data for standard channel parameter registers.
 557  * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
 558  * @initialized: true if the dma has been initialized
 559  * @gen_dmac: the struct for generic registers values to represent u8500/8540
 560  * DMA controller
 561  */
 562 struct d40_base {
 563         spinlock_t                       interrupt_lock;
 564         spinlock_t                       execmd_lock;
 565         struct device                    *dev;
 566         void __iomem                     *virtbase;
 567         u8                                rev:4;
 568         struct clk                       *clk;
 569         phys_addr_t                       phy_start;
 570         resource_size_t                   phy_size;
 571         int                               irq;
 572         int                               num_memcpy_chans;
 573         int                               num_phy_chans;
 574         int                               num_log_chans;
 575         struct device_dma_parameters      dma_parms;
 576         struct dma_device                 dma_both;
 577         struct dma_device                 dma_slave;
 578         struct dma_device                 dma_memcpy;
 579         struct d40_chan                  *phy_chans;
 580         struct d40_chan                  *log_chans;
 581         struct d40_chan                 **lookup_log_chans;
 582         struct d40_chan                 **lookup_phy_chans;
 583         struct stedma40_platform_data    *plat_data;
 584         struct regulator                 *lcpa_regulator;
 585         /* Physical half channels */
 586         struct d40_phy_res               *phy_res;
 587         struct d40_lcla_pool              lcla_pool;
 588         void                             *lcpa_base;
 589         dma_addr_t                        phy_lcpa;
 590         resource_size_t                   lcpa_size;
 591         struct kmem_cache                *desc_slab;
 592         u32                               reg_val_backup[BACKUP_REGS_SZ];
 593         u32                               reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
 594         u32                              *reg_val_backup_chan;
 595         u16                               gcc_pwr_off_mask;
 596         bool                              initialized;
 597         struct d40_gen_dmac               gen_dmac;
 598 };
 599
 600 static struct device *chan2dev(struct d40_chan *d40c)
 601 {
 602         return &d40c->chan.dev->device;
 603 }
 604
 605 static bool chan_is_physical(struct d40_chan *chan)
 606 {
 607         return chan->log_num == D40_PHY_CHAN;
 608 }
 609
 610 static bool chan_is_logical(struct d40_chan *chan)
 611 {
 612         return !chan_is_physical(chan);
 613 }
 614
 615 static void __iomem *chan_base(struct d40_chan *chan)
 616 {
 617         return chan->base->virtbase + D40_DREG_PCBASE +
 618                chan->phy_chan->num * D40_DREG_PCDELTA;
 619 }
 620
 621 #define d40_err(dev, format, arg...)            \
 622         dev_err(dev, "[%s] " format, __func__, ## arg)
 623
 624 #define chan_err(d40c, format, arg...)          \
 625         d40_err(chan2dev(d40c), format, ## arg)
 626
 627 static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
 628                               int lli_len)
 629 {
 630         bool is_log = chan_is_logical(d40c);
 631         u32 align;
 632         void *base;
 633
 634         if (is_log)
 635                 align = sizeof(struct d40_log_lli);
 636         else
 637                 align = sizeof(struct d40_phy_lli);
 638
 639         if (lli_len == 1) {
 640                 base = d40d->lli_pool.pre_alloc_lli;
 641                 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
 642                 d40d->lli_pool.base = NULL;
 643         } else {
 644                 d40d->lli_pool.size = lli_len * 2 * align;
 645
 646                 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
 647                 d40d->lli_pool.base = base;
 648
 649                 if (d40d->lli_pool.base == NULL)
 650                         return -ENOMEM;
 651         }
 652
 653         if (is_log) {
 654                 d40d->lli_log.src = PTR_ALIGN(base, align);
 655                 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
 656
 657                 d40d->lli_pool.dma_addr = 0;
 658         } else {
 659                 d40d->lli_phy.src = PTR_ALIGN(base, align);
 660                 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
 661
 662                 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
 663                                                          d40d->lli_phy.src,
 664                                                          d40d->lli_pool.size,
 665                                                          DMA_TO_DEVICE);
 666
 667                 if (dma_mapping_error(d40c->base->dev,
 668                                       d40d->lli_pool.dma_addr)) {
 669                         kfree(d40d->lli_pool.base);
 670                         d40d->lli_pool.base = NULL;
 671                         d40d->lli_pool.dma_addr = 0;
 672                         return -ENOMEM;
 673                 }
 674         }
 675
 676         return 0;
 677 }
 678
 679 static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
 680 {
 681         if (d40d->lli_pool.dma_addr)
 682                 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
 683                                  d40d->lli_pool.size, DMA_TO_DEVICE);
 684
 685         kfree(d40d->lli_pool.base);
 686         d40d->lli_pool.base = NULL;
 687         d40d->lli_pool.size = 0;
 688         d40d->lli_log.src = NULL;
 689         d40d->lli_log.dst = NULL;
 690         d40d->lli_phy.src = NULL;
 691         d40d->lli_phy.dst = NULL;
 692 }
 693
 694 static int d40_lcla_alloc_one(struct d40_chan *d40c,
 695                               struct d40_desc *d40d)
 696 {
 697         unsigned long flags;
 698         int i;
 699         int ret = -EINVAL;
 700
 701         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
 702
 703         /*
 704          * Allocate both src and dst at the same time, therefore the half
 705          * start on 1 since 0 can't be used since zero is used as end marker.
 706          */
 707         for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
 708                 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
 709
 710                 if (!d40c->base->lcla_pool.alloc_map[idx]) {
 711                         d40c->base->lcla_pool.alloc_map[idx] = d40d;
 712                         d40d->lcla_alloc++;
 713                         ret = i;
 714                         break;
 715                 }
 716         }
 717
 718         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
 719
 720         return ret;
 721 }
 722
 723 static int d40_lcla_free_all(struct d40_chan *d40c,
 724                              struct d40_desc *d40d)
 725 {
 726         unsigned long flags;
 727         int i;
 728         int ret = -EINVAL;
 729
 730         if (chan_is_physical(d40c))
 731                 return 0;
 732
 733         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
 734
 735         for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
 736                 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
 737
 738                 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
 739                         d40c->base->lcla_pool.alloc_map[idx] = NULL;
 740                         d40d->lcla_alloc--;
 741                         if (d40d->lcla_alloc == 0) {
 742                                 ret = 0;
 743                                 break;
 744                         }
 745                 }
 746         }
 747
 748         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
 749
 750         return ret;
 751
 752 }
 753
 754 static void d40_desc_remove(struct d40_desc *d40d)
 755 {
 756         list_del(&d40d->node);
 757 }
 758
 759 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
 760 {
 761         struct d40_desc *desc = NULL;
 762
 763         if (!list_empty(&d40c->client)) {
 764                 struct d40_desc *d;
 765                 struct d40_desc *_d;
 766
 767                 list_for_each_entry_safe(d, _d, &d40c->client, node) {
 768                         if (async_tx_test_ack(&d->txd)) {
 769                                 d40_desc_remove(d);
 770                                 desc = d;
 771                                 memset(desc, 0, sizeof(*desc));
 772                                 break;
 773                         }
 774                 }
 775         }
 776
 777         if (!desc)
 778                 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
 779
 780         if (desc)
 781                 INIT_LIST_HEAD(&desc->node);
 782
 783         return desc;
 784 }
 785
 786 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
 787 {
 788
 789         d40_pool_lli_free(d40c, d40d);
 790         d40_lcla_free_all(d40c, d40d);
 791         kmem_cache_free(d40c->base->desc_slab, d40d);
 792 }
 793
 794 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
 795 {
 796         list_add_tail(&desc->node, &d40c->active);
 797 }
 798
 799 static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
 800 {
 801         struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
 802         struct d40_phy_lli *lli_src = desc->lli_phy.src;
 803         void __iomem *base = chan_base(chan);
 804
 805         writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
 806         writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
 807         writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
 808         writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
 809
 810         writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
 811         writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
 812         writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
 813         writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
 814 }
 815
 816 static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
 817 {
 818         list_add_tail(&desc->node, &d40c->done);
 819 }
 820
 821 static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
 822 {
 823         struct d40_lcla_pool *pool = &chan->base->lcla_pool;
 824         struct d40_log_lli_bidir *lli = &desc->lli_log;
 825         int lli_current = desc->lli_current;
 826         int lli_len = desc->lli_len;
 827         bool cyclic = desc->cyclic;
 828         int curr_lcla = -EINVAL;
 829         int first_lcla = 0;
 830         bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
 831         bool linkback;
 832
 833         /*
 834          * We may have partially running cyclic transfers, in case we did't get
 835          * enough LCLA entries.
 836          */
 837         linkback = cyclic && lli_current == 0;
 838
 839         /*
 840          * For linkback, we need one LCLA even with only one link, because we
 841          * can't link back to the one in LCPA space
 842          */
 843         if (linkback || (lli_len - lli_current > 1)) {
 844                 /*
 845                  * If the channel is expected to use only soft_lli don't
 846                  * allocate a lcla. This is to avoid a HW issue that exists
 847                  * in some controller during a peripheral to memory transfer
 848                  * that uses linked lists.
 849                  */
 850                 if (!(chan->phy_chan->use_soft_lli &&
 851                         chan->dma_cfg.dir == DMA_DEV_TO_MEM))
 852                         curr_lcla = d40_lcla_alloc_one(chan, desc);
 853
 854                 first_lcla = curr_lcla;
 855         }
 856
 857         /*
 858          * For linkback, we normally load the LCPA in the loop since we need to
 859          * link it to the second LCLA and not the first.  However, if we
 860          * couldn't even get a first LCLA, then we have to run in LCPA and
 861          * reload manually.
 862          */
 863         if (!linkback || curr_lcla == -EINVAL) {
 864                 unsigned int flags = 0;
 865
 866                 if (curr_lcla == -EINVAL)
 867                         flags |= LLI_TERM_INT;
 868
 869                 d40_log_lli_lcpa_write(chan->lcpa,
 870                                        &lli->dst[lli_current],
 871                                        &lli->src[lli_current],
 872                                        curr_lcla,
 873                                        flags);
 874                 lli_current++;
 875         }
 876
 877         if (curr_lcla < 0)
 878                 goto out;
 879
 880         for (; lli_current < lli_len; lli_current++) {
 881                 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
 882                                            8 * curr_lcla * 2;
 883                 struct d40_log_lli *lcla = pool->base + lcla_offset;
 884                 unsigned int flags = 0;
 885                 int next_lcla;
 886
 887                 if (lli_current + 1 < lli_len)
 888                         next_lcla = d40_lcla_alloc_one(chan, desc);
 889                 else
 890                         next_lcla = linkback ? first_lcla : -EINVAL;
 891
 892                 if (cyclic || next_lcla == -EINVAL)
 893                         flags |= LLI_TERM_INT;
 894
 895                 if (linkback && curr_lcla == first_lcla) {
 896                         /* First link goes in both LCPA and LCLA */
 897                         d40_log_lli_lcpa_write(chan->lcpa,
 898                                                &lli->dst[lli_current],
 899                                                &lli->src[lli_current],
 900                                                next_lcla, flags);
 901                 }
 902
 903                 /*
 904                  * One unused LCLA in the cyclic case if the very first
 905                  * next_lcla fails...
 906                  */
 907                 d40_log_lli_lcla_write(lcla,
 908                                        &lli->dst[lli_current],
 909                                        &lli->src[lli_current],
 910                                        next_lcla, flags);
 911
 912                 /*
 913                  * Cache maintenance is not needed if lcla is
 914                  * mapped in esram
 915                  */
 916                 if (!use_esram_lcla) {
 917                         dma_sync_single_range_for_device(chan->base->dev,
 918                                                 pool->dma_addr, lcla_offset,
 919                                                 2 * sizeof(struct d40_log_lli),
 920                                                 DMA_TO_DEVICE);
 921                 }
 922                 curr_lcla = next_lcla;
 923
 924                 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
 925                         lli_current++;
 926                         break;
 927                 }
 928         }
 929
 930 out:
 931         desc->lli_current = lli_current;
 932 }
 933
 934 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
 935 {
 936         if (chan_is_physical(d40c)) {
 937                 d40_phy_lli_load(d40c, d40d);
 938                 d40d->lli_current = d40d->lli_len;
 939         } else
 940                 d40_log_lli_to_lcxa(d40c, d40d);
 941 }
 942
 943 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
 944 {
 945         struct d40_desc *d;
 946
 947         if (list_empty(&d40c->active))
 948                 return NULL;
 949
 950         d = list_first_entry(&d40c->active,
 951                              struct d40_desc,
 952                              node);
 953         return d;
 954 }
 955
 956 /* remove desc from current queue and add it to the pending_queue */
 957 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
 958 {
 959         d40_desc_remove(desc);
 960         desc->is_in_client_list = false;
 961         list_add_tail(&desc->node, &d40c->pending_queue);
 962 }
 963
 964 static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
 965 {
 966         struct d40_desc *d;
 967
 968         if (list_empty(&d40c->pending_queue))
 969                 return NULL;
 970
 971         d = list_first_entry(&d40c->pending_queue,
 972                              struct d40_desc,
 973                              node);
 974         return d;
 975 }
 976
 977 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
 978 {
 979         struct d40_desc *d;
 980
 981         if (list_empty(&d40c->queue))
 982                 return NULL;
 983
 984         d = list_first_entry(&d40c->queue,
 985                              struct d40_desc,
 986                              node);
 987         return d;
 988 }
 989
 990 static struct d40_desc *d40_first_done(struct d40_chan *d40c)
 991 {
 992         if (list_empty(&d40c->done))
 993                 return NULL;
 994
 995         return list_first_entry(&d40c->done, struct d40_desc, node);
 996 }
 997
 998 static int d40_psize_2_burst_size(bool is_log, int psize)
 999 {
1000         if (is_log) {
1001                 if (psize == STEDMA40_PSIZE_LOG_1)
1002                         return 1;
1003         } else {
1004                 if (psize == STEDMA40_PSIZE_PHY_1)
1005                         return 1;
1006         }
1007
1008         return 2 << psize;
1009 }
1010
1011 /*
1012  * The dma only supports transmitting packages up to
1013  * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
1014  *
1015  * Calculate the total number of dma elements required to send the entire sg list.
1016  */
1017 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
1018 {
1019         int dmalen;
1020         u32 max_w = max(data_width1, data_width2);
1021         u32 min_w = min(data_width1, data_width2);
1022         u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
1023
1024         if (seg_max > STEDMA40_MAX_SEG_SIZE)
1025                 seg_max -= max_w;
1026
1027         if (!IS_ALIGNED(size, max_w))
1028                 return -EINVAL;
1029
1030         if (size <= seg_max)
1031                 dmalen = 1;
1032         else {
1033                 dmalen = size / seg_max;
1034                 if (dmalen * seg_max < size)
1035                         dmalen++;
1036         }
1037         return dmalen;
1038 }
1039
1040 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
1041                            u32 data_width1, u32 data_width2)
1042 {
1043         struct scatterlist *sg;
1044         int i;
1045         int len = 0;
1046         int ret;
1047
1048         for_each_sg(sgl, sg, sg_len, i) {
1049                 ret = d40_size_2_dmalen(sg_dma_len(sg),
1050                                         data_width1, data_width2);
1051                 if (ret < 0)
1052                         return ret;
1053                 len += ret;
1054         }
1055         return len;
1056 }
1057
1058
1059 #ifdef CONFIG_PM
1060 static void dma40_backup(void __iomem *baseaddr, u32 *backup,
1061                          u32 *regaddr, int num, bool save)
1062 {
1063         int i;
1064
1065         for (i = 0; i < num; i++) {
1066                 void __iomem *addr = baseaddr + regaddr[i];
1067
1068                 if (save)
1069                         backup[i] = readl_relaxed(addr);
1070                 else
1071                         writel_relaxed(backup[i], addr);
1072         }
1073 }
1074
1075 static void d40_save_restore_registers(struct d40_base *base, bool save)
1076 {
1077         int i;
1078
1079         /* Save/Restore channel specific registers */
1080         for (i = 0; i < base->num_phy_chans; i++) {
1081                 void __iomem *addr;
1082                 int idx;
1083
1084                 if (base->phy_res[i].reserved)
1085                         continue;
1086
1087                 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
1088                 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
1089
1090                 dma40_backup(addr, &base->reg_val_backup_chan[idx],
1091                              d40_backup_regs_chan,
1092                              ARRAY_SIZE(d40_backup_regs_chan),
1093                              save);
1094         }
1095
1096         /* Save/Restore global registers */
1097         dma40_backup(base->virtbase, base->reg_val_backup,
1098                      d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
1099                      save);
1100
1101         /* Save/Restore registers only existing on dma40 v3 and later */
1102         if (base->gen_dmac.backup)
1103                 dma40_backup(base->virtbase, base->reg_val_backup_v4,
1104                              base->gen_dmac.backup,
1105                         base->gen_dmac.backup_size,
1106                         save);
1107 }
1108 #else
1109 static void d40_save_restore_registers(struct d40_base *base, bool save)
1110 {
1111 }
1112 #endif
1113
1114 static int __d40_execute_command_phy(struct d40_chan *d40c,
1115                                      enum d40_command command)
1116 {
1117         u32 status;
1118         int i;
1119         void __iomem *active_reg;
1120         int ret = 0;
1121         unsigned long flags;
1122         u32 wmask;
1123
1124         if (command == D40_DMA_STOP) {
1125                 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
1126                 if (ret)
1127                         return ret;
1128         }
1129
1130         spin_lock_irqsave(&d40c->base->execmd_lock, flags);
1131
1132         if (d40c->phy_chan->num % 2 == 0)
1133                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1134         else
1135                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1136
1137         if (command == D40_DMA_SUSPEND_REQ) {
1138                 status = (readl(active_reg) &
1139                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1140                         D40_CHAN_POS(d40c->phy_chan->num);
1141
1142                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1143                         goto done;
1144         }
1145
1146         wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
1147         writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
1148                active_reg);
1149
1150         if (command == D40_DMA_SUSPEND_REQ) {
1151
1152                 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
1153                         status = (readl(active_reg) &
1154                                   D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1155                                 D40_CHAN_POS(d40c->phy_chan->num);
1156
1157                         cpu_relax();
1158                         /*
1159                          * Reduce the number of bus accesses while
1160                          * waiting for the DMA to suspend.
1161                          */
1162                         udelay(3);
1163
1164                         if (status == D40_DMA_STOP ||
1165                             status == D40_DMA_SUSPENDED)
1166                                 break;
1167                 }
1168
1169                 if (i == D40_SUSPEND_MAX_IT) {
1170                         chan_err(d40c,
1171                                 "unable to suspend the chl %d (log: %d) status %x\n",
1172                                 d40c->phy_chan->num, d40c->log_num,
1173                                 status);
1174                         dump_stack();
1175                         ret = -EBUSY;
1176                 }
1177
1178         }
1179 done:
1180         spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
1181         return ret;
1182 }
1183
1184 static void d40_term_all(struct d40_chan *d40c)
1185 {
1186         struct d40_desc *d40d;
1187         struct d40_desc *_d;
1188
1189         /* Release completed descriptors */
1190         while ((d40d = d40_first_done(d40c))) {
1191                 d40_desc_remove(d40d);
1192                 d40_desc_free(d40c, d40d);
1193         }
1194
1195         /* Release active descriptors */
1196         while ((d40d = d40_first_active_get(d40c))) {
1197                 d40_desc_remove(d40d);
1198                 d40_desc_free(d40c, d40d);
1199         }
1200
1201         /* Release queued descriptors waiting for transfer */
1202         while ((d40d = d40_first_queued(d40c))) {
1203                 d40_desc_remove(d40d);
1204                 d40_desc_free(d40c, d40d);
1205         }
1206
1207         /* Release pending descriptors */
1208         while ((d40d = d40_first_pending(d40c))) {
1209                 d40_desc_remove(d40d);
1210                 d40_desc_free(d40c, d40d);
1211         }
1212
1213         /* Release client owned descriptors */
1214         if (!list_empty(&d40c->client))
1215                 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
1216                         d40_desc_remove(d40d);
1217                         d40_desc_free(d40c, d40d);
1218                 }
1219
1220         /* Release descriptors in prepare queue */
1221         if (!list_empty(&d40c->prepare_queue))
1222                 list_for_each_entry_safe(d40d, _d,
1223                                          &d40c->prepare_queue, node) {
1224                         d40_desc_remove(d40d);
1225                         d40_desc_free(d40c, d40d);
1226                 }
1227
1228         d40c->pending_tx = 0;
1229 }
1230
1231 static void __d40_config_set_event(struct d40_chan *d40c,
1232                                    enum d40_events event_type, u32 event,
1233                                    int reg)
1234 {
1235         void __iomem *addr = chan_base(d40c) + reg;
1236         int tries;
1237         u32 status;
1238
1239         switch (event_type) {
1240
1241         case D40_DEACTIVATE_EVENTLINE:
1242
1243                 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1244                        | ~D40_EVENTLINE_MASK(event), addr);
1245                 break;
1246
1247         case D40_SUSPEND_REQ_EVENTLINE:
1248                 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1249                           D40_EVENTLINE_POS(event);
1250
1251                 if (status == D40_DEACTIVATE_EVENTLINE ||
1252                     status == D40_SUSPEND_REQ_EVENTLINE)
1253                         break;
1254
1255                 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1256                        | ~D40_EVENTLINE_MASK(event), addr);
1257
1258                 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1259
1260                         status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1261                                   D40_EVENTLINE_POS(event);
1262
1263                         cpu_relax();
1264                         /*
1265                          * Reduce the number of bus accesses while
1266                          * waiting for the DMA to suspend.
1267                          */
1268                         udelay(3);
1269
1270                         if (status == D40_DEACTIVATE_EVENTLINE)
1271                                 break;
1272                 }
1273
1274                 if (tries == D40_SUSPEND_MAX_IT) {
1275                         chan_err(d40c,
1276                                 "unable to stop the event_line chl %d (log: %d)"
1277                                 "status %x\n", d40c->phy_chan->num,
1278                                  d40c->log_num, status);
1279                 }
1280                 break;
1281
1282         case D40_ACTIVATE_EVENTLINE:
1283         /*
1284          * The hardware sometimes doesn't register the enable when src and dst
1285          * event lines are active on the same logical channel.  Retry to ensure
1286          * it does.  Usually only one retry is sufficient.
1287          */
1288                 tries = 100;
1289                 while (--tries) {
1290                         writel((D40_ACTIVATE_EVENTLINE <<
1291                                 D40_EVENTLINE_POS(event)) |
1292                                 ~D40_EVENTLINE_MASK(event), addr);
1293
1294                         if (readl(addr) & D40_EVENTLINE_MASK(event))
1295                                 break;
1296                 }
1297
1298                 if (tries != 99)
1299                         dev_dbg(chan2dev(d40c),
1300                                 "[%s] workaround enable S%cLNK (%d tries)\n",
1301                                 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1302                                 100 - tries);
1303
1304                 WARN_ON(!tries);
1305                 break;
1306
1307         case D40_ROUND_EVENTLINE:
1308                 BUG();
1309                 break;
1310
1311         }
1312 }
1313
1314 static void d40_config_set_event(struct d40_chan *d40c,
1315                                  enum d40_events event_type)
1316 {
1317         u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1318
1319         /* Enable event line connected to device (or memcpy) */
1320         if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
1321             (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
1322                 __d40_config_set_event(d40c, event_type, event,
1323                                        D40_CHAN_REG_SSLNK);
1324
1325         if (d40c->dma_cfg.dir !=  DMA_DEV_TO_MEM)
1326                 __d40_config_set_event(d40c, event_type, event,
1327                                        D40_CHAN_REG_SDLNK);
1328 }
1329
1330 static u32 d40_chan_has_events(struct d40_chan *d40c)
1331 {
1332         void __iomem *chanbase = chan_base(d40c);
1333         u32 val;
1334
1335         val = readl(chanbase + D40_CHAN_REG_SSLNK);
1336         val |= readl(chanbase + D40_CHAN_REG_SDLNK);
1337
1338         return val;
1339 }
1340
1341 static int
1342 __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1343 {
1344         unsigned long flags;
1345         int ret = 0;
1346         u32 active_status;
1347         void __iomem *active_reg;
1348
1349         if (d40c->phy_chan->num % 2 == 0)
1350                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1351         else
1352                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1353
1354
1355         spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1356
1357         switch (command) {
1358         case D40_DMA_STOP:
1359         case D40_DMA_SUSPEND_REQ:
1360
1361                 active_status = (readl(active_reg) &
1362                                  D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1363                                  D40_CHAN_POS(d40c->phy_chan->num);
1364
1365                 if (active_status == D40_DMA_RUN)
1366                         d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1367                 else
1368                         d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1369
1370                 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1371                         ret = __d40_execute_command_phy(d40c, command);
1372
1373                 break;
1374
1375         case D40_DMA_RUN:
1376
1377                 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1378                 ret = __d40_execute_command_phy(d40c, command);
1379                 break;
1380
1381         case D40_DMA_SUSPENDED:
1382                 BUG();
1383                 break;
1384         }
1385
1386         spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1387         return ret;
1388 }
1389
1390 static int d40_channel_execute_command(struct d40_chan *d40c,
1391                                        enum d40_command command)
1392 {
1393         if (chan_is_logical(d40c))
1394                 return __d40_execute_command_log(d40c, command);
1395         else
1396                 return __d40_execute_command_phy(d40c, command);
1397 }
1398
1399 static u32 d40_get_prmo(struct d40_chan *d40c)
1400 {
1401         static const unsigned int phy_map[] = {
1402                 [STEDMA40_PCHAN_BASIC_MODE]
1403                         = D40_DREG_PRMO_PCHAN_BASIC,
1404                 [STEDMA40_PCHAN_MODULO_MODE]
1405                         = D40_DREG_PRMO_PCHAN_MODULO,
1406                 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1407                         = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1408         };
1409         static const unsigned int log_map[] = {
1410                 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1411                         = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1412                 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1413                         = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1414                 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1415                         = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1416         };
1417
1418         if (chan_is_physical(d40c))
1419                 return phy_map[d40c->dma_cfg.mode_opt];
1420         else
1421                 return log_map[d40c->dma_cfg.mode_opt];
1422 }
1423
1424 static void d40_config_write(struct d40_chan *d40c)
1425 {
1426         u32 addr_base;
1427         u32 var;
1428
1429         /* Odd addresses are even addresses + 4 */
1430         addr_base = (d40c->phy_chan->num % 2) * 4;
1431         /* Setup channel mode to logical or physical */
1432         var = ((u32)(chan_is_logical(d40c)) + 1) <<
1433                 D40_CHAN_POS(d40c->phy_chan->num);
1434         writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1435
1436         /* Setup operational mode option register */
1437         var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
1438
1439         writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1440
1441         if (chan_is_logical(d40c)) {
1442                 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1443                            & D40_SREG_ELEM_LOG_LIDX_MASK;
1444                 void __iomem *chanbase = chan_base(d40c);
1445
1446                 /* Set default config for CFG reg */
1447                 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1448                 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
1449
1450                 /* Set LIDX for lcla */
1451                 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1452                 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
1453
1454                 /* Clear LNK which will be used by d40_chan_has_events() */
1455                 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1456                 writel(0, chanbase + D40_CHAN_REG_SDLNK);
1457         }
1458 }
1459
1460 static u32 d40_residue(struct d40_chan *d40c)
1461 {
1462         u32 num_elt;
1463
1464         if (chan_is_logical(d40c))
1465                 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1466                         >> D40_MEM_LCSP2_ECNT_POS;
1467         else {
1468                 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1469                 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1470                           >> D40_SREG_ELEM_PHY_ECNT_POS;
1471         }
1472
1473         return num_elt * d40c->dma_cfg.dst_info.data_width;
1474 }
1475
1476 static bool d40_tx_is_linked(struct d40_chan *d40c)
1477 {
1478         bool is_link;
1479
1480         if (chan_is_logical(d40c))
1481                 is_link = readl(&d40c->lcpa->lcsp3) &  D40_MEM_LCSP3_DLOS_MASK;
1482         else
1483                 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1484                           & D40_SREG_LNK_PHYS_LNK_MASK;
1485
1486         return is_link;
1487 }
1488
1489 static int d40_pause(struct d40_chan *d40c)
1490 {
1491         int res = 0;
1492         unsigned long flags;
1493
1494         if (!d40c->busy)
1495                 return 0;
1496
1497         pm_runtime_get_sync(d40c->base->dev);
1498         spin_lock_irqsave(&d40c->lock, flags);
1499
1500         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1501
1502         pm_runtime_mark_last_busy(d40c->base->dev);
1503         pm_runtime_put_autosuspend(d40c->base->dev);
1504         spin_unlock_irqrestore(&d40c->lock, flags);
1505         return res;
1506 }
1507
1508 static int d40_resume(struct d40_chan *d40c)
1509 {
1510         int res = 0;
1511         unsigned long flags;
1512
1513         if (!d40c->busy)
1514                 return 0;
1515
1516         spin_lock_irqsave(&d40c->lock, flags);
1517         pm_runtime_get_sync(d40c->base->dev);
1518
1519         /* If bytes left to transfer or linked tx resume job */
1520         if (d40_residue(d40c) || d40_tx_is_linked(d40c))
1521                 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1522
1523         pm_runtime_mark_last_busy(d40c->base->dev);
1524         pm_runtime_put_autosuspend(d40c->base->dev);
1525         spin_unlock_irqrestore(&d40c->lock, flags);
1526         return res;
1527 }
1528
1529 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1530 {
1531         struct d40_chan *d40c = container_of(tx->chan,
1532                                              struct d40_chan,
1533                                              chan);
1534         struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1535         unsigned long flags;
1536         dma_cookie_t cookie;
1537
1538         spin_lock_irqsave(&d40c->lock, flags);
1539         cookie = dma_cookie_assign(tx);
1540         d40_desc_queue(d40c, d40d);
1541         spin_unlock_irqrestore(&d40c->lock, flags);
1542
1543         return cookie;
1544 }
1545
1546 static int d40_start(struct d40_chan *d40c)
1547 {
1548         return d40_channel_execute_command(d40c, D40_DMA_RUN);
1549 }
1550
1551 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1552 {
1553         struct d40_desc *d40d;
1554         int err;
1555
1556         /* Start queued jobs, if any */
1557         d40d = d40_first_queued(d40c);
1558
1559         if (d40d != NULL) {
1560                 if (!d40c->busy) {
1561                         d40c->busy = true;
1562                         pm_runtime_get_sync(d40c->base->dev);
1563                 }
1564
1565                 /* Remove from queue */
1566                 d40_desc_remove(d40d);
1567
1568                 /* Add to active queue */
1569                 d40_desc_submit(d40c, d40d);
1570
1571                 /* Initiate DMA job */
1572                 d40_desc_load(d40c, d40d);
1573
1574                 /* Start dma job */
1575                 err = d40_start(d40c);
1576
1577                 if (err)
1578                         return NULL;
1579         }
1580
1581         return d40d;
1582 }
1583
1584 /* called from interrupt context */
1585 static void dma_tc_handle(struct d40_chan *d40c)
1586 {
1587         struct d40_desc *d40d;
1588
1589         /* Get first active entry from list */
1590         d40d = d40_first_active_get(d40c);
1591
1592         if (d40d == NULL)
1593                 return;
1594
1595         if (d40d->cyclic) {
1596                 /*
1597                  * If this was a paritially loaded list, we need to reloaded
1598                  * it, and only when the list is completed.  We need to check
1599                  * for done because the interrupt will hit for every link, and
1600                  * not just the last one.
1601                  */
1602                 if (d40d->lli_current < d40d->lli_len
1603                     && !d40_tx_is_linked(d40c)
1604                     && !d40_residue(d40c)) {
1605                         d40_lcla_free_all(d40c, d40d);
1606                         d40_desc_load(d40c, d40d);
1607                         (void) d40_start(d40c);
1608
1609                         if (d40d->lli_current == d40d->lli_len)
1610                                 d40d->lli_current = 0;
1611                 }
1612         } else {
1613                 d40_lcla_free_all(d40c, d40d);
1614
1615                 if (d40d->lli_current < d40d->lli_len) {
1616                         d40_desc_load(d40c, d40d);
1617                         /* Start dma job */
1618                         (void) d40_start(d40c);
1619                         return;
1620                 }
1621
1622                 if (d40_queue_start(d40c) == NULL) {
1623                         d40c->busy = false;
1624
1625                         pm_runtime_mark_last_busy(d40c->base->dev);
1626                         pm_runtime_put_autosuspend(d40c->base->dev);
1627                 }
1628
1629                 d40_desc_remove(d40d);
1630                 d40_desc_done(d40c, d40d);
1631         }
1632
1633         d40c->pending_tx++;
1634         tasklet_schedule(&d40c->tasklet);
1635
1636 }
1637
1638 static void dma_tasklet(unsigned long data)
1639 {
1640         struct d40_chan *d40c = (struct d40_chan *) data;
1641         struct d40_desc *d40d;
1642         unsigned long flags;
1643         dma_async_tx_callback callback;
1644         void *callback_param;
1645
1646         spin_lock_irqsave(&d40c->lock, flags);
1647
1648         /* Get first entry from the done list */
1649         d40d = d40_first_done(d40c);
1650         if (d40d == NULL) {
1651                 /* Check if we have reached here for cyclic job */
1652                 d40d = d40_first_active_get(d40c);
1653                 if (d40d == NULL || !d40d->cyclic)
1654                         goto err;
1655         }
1656
1657         if (!d40d->cyclic)
1658                 dma_cookie_complete(&d40d->txd);
1659
1660         /*
1661          * If terminating a channel pending_tx is set to zero.
1662          * This prevents any finished active jobs to return to the client.
1663          */
1664         if (d40c->pending_tx == 0) {
1665                 spin_unlock_irqrestore(&d40c->lock, flags);
1666                 return;
1667         }
1668
1669         /* Callback to client */
1670         callback = d40d->txd.callback;
1671         callback_param = d40d->txd.callback_param;
1672
1673         if (!d40d->cyclic) {
1674                 if (async_tx_test_ack(&d40d->txd)) {
1675                         d40_desc_remove(d40d);
1676                         d40_desc_free(d40c, d40d);
1677                 } else if (!d40d->is_in_client_list) {
1678                         d40_desc_remove(d40d);
1679                         d40_lcla_free_all(d40c, d40d);
1680                         list_add_tail(&d40d->node, &d40c->client);
1681                         d40d->is_in_client_list = true;
1682                 }
1683         }
1684
1685         d40c->pending_tx--;
1686
1687         if (d40c->pending_tx)
1688                 tasklet_schedule(&d40c->tasklet);
1689
1690         spin_unlock_irqrestore(&d40c->lock, flags);
1691
1692         if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
1693                 callback(callback_param);
1694
1695         return;
1696
1697 err:
1698         /* Rescue manouver if receiving double interrupts */
1699         if (d40c->pending_tx > 0)
1700                 d40c->pending_tx--;
1701         spin_unlock_irqrestore(&d40c->lock, flags);
1702 }
1703
1704 static irqreturn_t d40_handle_interrupt(int irq, void *data)
1705 {
1706         int i;
1707         u32 idx;
1708         u32 row;
1709         long chan = -1;
1710         struct d40_chan *d40c;
1711         unsigned long flags;
1712         struct d40_base *base = data;
1713         u32 regs[base->gen_dmac.il_size];
1714         struct d40_interrupt_lookup *il = base->gen_dmac.il;
1715         u32 il_size = base->gen_dmac.il_size;
1716
1717         spin_lock_irqsave(&base->interrupt_lock, flags);
1718
1719         /* Read interrupt status of both logical and physical channels */
1720         for (i = 0; i < il_size; i++)
1721                 regs[i] = readl(base->virtbase + il[i].src);
1722
1723         for (;;) {
1724
1725                 chan = find_next_bit((unsigned long *)regs,
1726                                      BITS_PER_LONG * il_size, chan + 1);
1727
1728                 /* No more set bits found? */
1729                 if (chan == BITS_PER_LONG * il_size)
1730                         break;
1731
1732                 row = chan / BITS_PER_LONG;
1733                 idx = chan & (BITS_PER_LONG - 1);
1734
1735                 if (il[row].offset == D40_PHY_CHAN)
1736                         d40c = base->lookup_phy_chans[idx];
1737                 else
1738                         d40c = base->lookup_log_chans[il[row].offset + idx];
1739
1740                 if (!d40c) {
1741                         /*
1742                          * No error because this can happen if something else
1743                          * in the system is using the channel.
1744                          */
1745                         continue;
1746                 }
1747
1748                 /* ACK interrupt */
1749                 writel(BIT(idx), base->virtbase + il[row].clr);
1750
1751                 spin_lock(&d40c->lock);
1752
1753                 if (!il[row].is_error)
1754                         dma_tc_handle(d40c);
1755                 else
1756                         d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1757                                 chan, il[row].offset, idx);
1758
1759                 spin_unlock(&d40c->lock);
1760         }
1761
1762         spin_unlock_irqrestore(&base->interrupt_lock, flags);
1763
1764         return IRQ_HANDLED;
1765 }
1766
1767 static int d40_validate_conf(struct d40_chan *d40c,
1768                              struct stedma40_chan_cfg *conf)
1769 {
1770         int res = 0;
1771         bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
1772
1773         if (!conf->dir) {
1774                 chan_err(d40c, "Invalid direction.\n");
1775                 res = -EINVAL;
1776         }
1777
1778         if ((is_log && conf->dev_type > d40c->base->num_log_chans)  ||
1779             (!is_log && conf->dev_type > d40c->base->num_phy_chans) ||
1780             (conf->dev_type < 0)) {
1781                 chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type);
1782                 res = -EINVAL;
1783         }
1784
1785         if (conf->dir == DMA_DEV_TO_DEV) {
1786                 /*
1787                  * DMAC HW supports it. Will be added to this driver,
1788                  * in case any dma client requires it.
1789                  */
1790                 chan_err(d40c, "periph to periph not supported\n");
1791                 res = -EINVAL;
1792         }
1793
1794         if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1795             conf->src_info.data_width !=
1796             d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1797             conf->dst_info.data_width) {
1798                 /*
1799                  * The DMAC hardware only supports
1800                  * src (burst x width) == dst (burst x width)
1801                  */
1802
1803                 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
1804                 res = -EINVAL;
1805         }
1806
1807         return res;
1808 }
1809
1810 static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1811                                bool is_src, int log_event_line, bool is_log,
1812                                bool *first_user)
1813 {
1814         unsigned long flags;
1815         spin_lock_irqsave(&phy->lock, flags);
1816
1817         *first_user = ((phy->allocated_src | phy->allocated_dst)
1818                         == D40_ALLOC_FREE);
1819
1820         if (!is_log) {
1821                 /* Physical interrupts are masked per physical full channel */
1822                 if (phy->allocated_src == D40_ALLOC_FREE &&
1823                     phy->allocated_dst == D40_ALLOC_FREE) {
1824                         phy->allocated_dst = D40_ALLOC_PHY;
1825                         phy->allocated_src = D40_ALLOC_PHY;
1826                         goto found;
1827                 } else
1828                         goto not_found;
1829         }
1830
1831         /* Logical channel */
1832         if (is_src) {
1833                 if (phy->allocated_src == D40_ALLOC_PHY)
1834                         goto not_found;
1835
1836                 if (phy->allocated_src == D40_ALLOC_FREE)
1837                         phy->allocated_src = D40_ALLOC_LOG_FREE;
1838
1839                 if (!(phy->allocated_src & BIT(log_event_line))) {
1840                         phy->allocated_src |= BIT(log_event_line);
1841                         goto found;
1842                 } else
1843                         goto not_found;
1844         } else {
1845                 if (phy->allocated_dst == D40_ALLOC_PHY)
1846                         goto not_found;
1847
1848                 if (phy->allocated_dst == D40_ALLOC_FREE)
1849                         phy->allocated_dst = D40_ALLOC_LOG_FREE;
1850
1851                 if (!(phy->allocated_dst & BIT(log_event_line))) {
1852                         phy->allocated_dst |= BIT(log_event_line);
1853                         goto found;
1854                 } else
1855                         goto not_found;
1856         }
1857
1858 not_found:
1859         spin_unlock_irqrestore(&phy->lock, flags);
1860         return false;
1861 found:
1862         spin_unlock_irqrestore(&phy->lock, flags);
1863         return true;
1864 }
1865
1866 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1867                                int log_event_line)
1868 {
1869         unsigned long flags;
1870         bool is_free = false;
1871
1872         spin_lock_irqsave(&phy->lock, flags);
1873         if (!log_event_line) {
1874                 phy->allocated_dst = D40_ALLOC_FREE;
1875                 phy->allocated_src = D40_ALLOC_FREE;
1876                 is_free = true;
1877                 goto out;
1878         }
1879
1880         /* Logical channel */
1881         if (is_src) {
1882                 phy->allocated_src &= ~BIT(log_event_line);
1883                 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1884                         phy->allocated_src = D40_ALLOC_FREE;
1885         } else {
1886                 phy->allocated_dst &= ~BIT(log_event_line);
1887                 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1888                         phy->allocated_dst = D40_ALLOC_FREE;
1889         }
1890
1891         is_free = ((phy->allocated_src | phy->allocated_dst) ==
1892                    D40_ALLOC_FREE);
1893
1894 out:
1895         spin_unlock_irqrestore(&phy->lock, flags);
1896
1897         return is_free;
1898 }
1899
1900 static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
1901 {
1902         int dev_type = d40c->dma_cfg.dev_type;
1903         int event_group;
1904         int event_line;
1905         struct d40_phy_res *phys;
1906         int i;
1907         int j;
1908         int log_num;
1909         int num_phy_chans;
1910         bool is_src;
1911         bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
1912
1913         phys = d40c->base->phy_res;
1914         num_phy_chans = d40c->base->num_phy_chans;
1915
1916         if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
1917                 log_num = 2 * dev_type;
1918                 is_src = true;
1919         } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
1920                    d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
1921                 /* dst event lines are used for logical memcpy */
1922                 log_num = 2 * dev_type + 1;
1923                 is_src = false;
1924         } else
1925                 return -EINVAL;
1926
1927         event_group = D40_TYPE_TO_GROUP(dev_type);
1928         event_line = D40_TYPE_TO_EVENT(dev_type);
1929
1930         if (!is_log) {
1931                 if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
1932                         /* Find physical half channel */
1933                         if (d40c->dma_cfg.use_fixed_channel) {
1934                                 i = d40c->dma_cfg.phy_channel;
1935                                 if (d40_alloc_mask_set(&phys[i], is_src,
1936                                                        0, is_log,
1937                                                        first_phy_user))
1938                                         goto found_phy;
1939                         } else {
1940                                 for (i = 0; i < num_phy_chans; i++) {
1941                                         if (d40_alloc_mask_set(&phys[i], is_src,
1942                                                        0, is_log,
1943                                                        first_phy_user))
1944                                                 goto found_phy;
1945                                 }
1946                         }
1947                 } else
1948                         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1949                                 int phy_num = j  + event_group * 2;
1950                                 for (i = phy_num; i < phy_num + 2; i++) {
1951                                         if (d40_alloc_mask_set(&phys[i],
1952                                                                is_src,
1953                                                                0,
1954                                                                is_log,
1955                                                                first_phy_user))
1956                                                 goto found_phy;
1957                                 }
1958                         }
1959                 return -EINVAL;
1960 found_phy:
1961                 d40c->phy_chan = &phys[i];
1962                 d40c->log_num = D40_PHY_CHAN;
1963                 goto out;
1964         }
1965         if (dev_type == -1)
1966                 return -EINVAL;
1967
1968         /* Find logical channel */
1969         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1970                 int phy_num = j + event_group * 2;
1971
1972                 if (d40c->dma_cfg.use_fixed_channel) {
1973                         i = d40c->dma_cfg.phy_channel;
1974
1975                         if ((i != phy_num) && (i != phy_num + 1)) {
1976                                 dev_err(chan2dev(d40c),
1977                                         "invalid fixed phy channel %d\n", i);
1978                                 return -EINVAL;
1979                         }
1980
1981                         if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1982                                                is_log, first_phy_user))
1983                                 goto found_log;
1984
1985                         dev_err(chan2dev(d40c),
1986                                 "could not allocate fixed phy channel %d\n", i);
1987                         return -EINVAL;
1988                 }
1989
1990                 /*
1991                  * Spread logical channels across all available physical rather
1992                  * than pack every logical channel at the first available phy
1993                  * channels.
1994                  */
1995                 if (is_src) {
1996                         for (i = phy_num; i < phy_num + 2; i++) {
1997                                 if (d40_alloc_mask_set(&phys[i], is_src,
1998                                                        event_line, is_log,
1999                                                        first_phy_user))
2000                                         goto found_log;
2001                         }
2002                 } else {
2003                         for (i = phy_num + 1; i >= phy_num; i--) {
2004                                 if (d40_alloc_mask_set(&phys[i], is_src,
2005                                                        event_line, is_log,
2006                                                        first_phy_user))
2007                                         goto found_log;
2008                         }
2009                 }
2010         }
2011         return -EINVAL;
2012
2013 found_log:
2014         d40c->phy_chan = &phys[i];
2015         d40c->log_num = log_num;
2016 out:
2017
2018         if (is_log)
2019                 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
2020         else
2021                 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
2022
2023         return 0;
2024
2025 }
2026
2027 static int d40_config_memcpy(struct d40_chan *d40c)
2028 {
2029         dma_cap_mask_t cap = d40c->chan.device->cap_mask;
2030
2031         if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
2032                 d40c->dma_cfg = dma40_memcpy_conf_log;
2033                 d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
2034
2035                 d40_log_cfg(&d40c->dma_cfg,
2036                             &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2037
2038         } else if (dma_has_cap(DMA_MEMCPY, cap) &&
2039                    dma_has_cap(DMA_SLAVE, cap)) {
2040                 d40c->dma_cfg = dma40_memcpy_conf_phy;
2041
2042                 /* Generate interrrupt at end of transfer or relink. */
2043                 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
2044
2045                 /* Generate interrupt on error. */
2046                 d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2047                 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2048
2049         } else {
2050                 chan_err(d40c, "No memcpy\n");
2051                 return -EINVAL;
2052         }
2053
2054         return 0;
2055 }
2056
2057 static int d40_free_dma(struct d40_chan *d40c)
2058 {
2059
2060         int res = 0;
2061         u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
2062         struct d40_phy_res *phy = d40c->phy_chan;
2063         bool is_src;
2064
2065         /* Terminate all queued and active transfers */
2066         d40_term_all(d40c);
2067
2068         if (phy == NULL) {
2069                 chan_err(d40c, "phy == null\n");
2070                 return -EINVAL;
2071         }
2072
2073         if (phy->allocated_src == D40_ALLOC_FREE &&
2074             phy->allocated_dst == D40_ALLOC_FREE) {
2075                 chan_err(d40c, "channel already free\n");
2076                 return -EINVAL;
2077         }
2078
2079         if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2080             d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
2081                 is_src = false;
2082         else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
2083                 is_src = true;
2084         else {
2085                 chan_err(d40c, "Unknown direction\n");
2086                 return -EINVAL;
2087         }
2088
2089         pm_runtime_get_sync(d40c->base->dev);
2090         res = d40_channel_execute_command(d40c, D40_DMA_STOP);
2091         if (res) {
2092                 chan_err(d40c, "stop failed\n");
2093                 goto out;
2094         }
2095
2096         d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
2097
2098         if (chan_is_logical(d40c))
2099                 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
2100         else
2101                 d40c->base->lookup_phy_chans[phy->num] = NULL;
2102
2103         if (d40c->busy) {
2104                 pm_runtime_mark_last_busy(d40c->base->dev);
2105                 pm_runtime_put_autosuspend(d40c->base->dev);
2106         }
2107
2108         d40c->busy = false;
2109         d40c->phy_chan = NULL;
2110         d40c->configured = false;
2111 out:
2112
2113         pm_runtime_mark_last_busy(d40c->base->dev);
2114         pm_runtime_put_autosuspend(d40c->base->dev);
2115         return res;
2116 }
2117
2118 static bool d40_is_paused(struct d40_chan *d40c)
2119 {
2120         void __iomem *chanbase = chan_base(d40c);
2121         bool is_paused = false;
2122         unsigned long flags;
2123         void __iomem *active_reg;
2124         u32 status;
2125         u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
2126
2127         spin_lock_irqsave(&d40c->lock, flags);
2128
2129         if (chan_is_physical(d40c)) {
2130                 if (d40c->phy_chan->num % 2 == 0)
2131                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2132                 else
2133                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2134
2135                 status = (readl(active_reg) &
2136                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
2137                         D40_CHAN_POS(d40c->phy_chan->num);
2138                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
2139                         is_paused = true;
2140
2141                 goto _exit;
2142         }
2143
2144         if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2145             d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
2146                 status = readl(chanbase + D40_CHAN_REG_SDLNK);
2147         } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
2148                 status = readl(chanbase + D40_CHAN_REG_SSLNK);
2149         } else {
2150                 chan_err(d40c, "Unknown direction\n");
2151                 goto _exit;
2152         }
2153
2154         status = (status & D40_EVENTLINE_MASK(event)) >>
2155                 D40_EVENTLINE_POS(event);
2156
2157         if (status != D40_DMA_RUN)
2158                 is_paused = true;
2159 _exit:
2160         spin_unlock_irqrestore(&d40c->lock, flags);
2161         return is_paused;
2162
2163 }
2164
2165 static u32 stedma40_residue(struct dma_chan *chan)
2166 {
2167         struct d40_chan *d40c =
2168                 container_of(chan, struct d40_chan, chan);
2169         u32 bytes_left;
2170         unsigned long flags;
2171
2172         spin_lock_irqsave(&d40c->lock, flags);
2173         bytes_left = d40_residue(d40c);
2174         spin_unlock_irqrestore(&d40c->lock, flags);
2175
2176         return bytes_left;
2177 }
2178
2179 static int
2180 d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
2181                 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2182                 unsigned int sg_len, dma_addr_t src_dev_addr,
2183                 dma_addr_t dst_dev_addr)
2184 {
2185         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2186         struct stedma40_half_channel_info *src_info = &cfg->src_info;
2187         struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2188         int ret;
2189
2190         ret = d40_log_sg_to_lli(sg_src, sg_len,
2191                                 src_dev_addr,
2192                                 desc->lli_log.src,
2193                                 chan->log_def.lcsp1,
2194                                 src_info->data_width,
2195                                 dst_info->data_width);
2196
2197         ret = d40_log_sg_to_lli(sg_dst, sg_len,
2198                                 dst_dev_addr,
2199                                 desc->lli_log.dst,
2200                                 chan->log_def.lcsp3,
2201                                 dst_info->data_width,
2202                                 src_info->data_width);
2203
2204         return ret < 0 ? ret : 0;
2205 }
2206
2207 static int
2208 d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
2209                 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2210                 unsigned int sg_len, dma_addr_t src_dev_addr,
2211                 dma_addr_t dst_dev_addr)
2212 {
2213         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2214         struct stedma40_half_channel_info *src_info = &cfg->src_info;
2215         struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2216         unsigned long flags = 0;
2217         int ret;
2218
2219         if (desc->cyclic)
2220                 flags |= LLI_CYCLIC | LLI_TERM_INT;
2221
2222         ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2223                                 desc->lli_phy.src,
2224                                 virt_to_phys(desc->lli_phy.src),
2225                                 chan->src_def_cfg,
2226                                 src_info, dst_info, flags);
2227
2228         ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2229                                 desc->lli_phy.dst,
2230                                 virt_to_phys(desc->lli_phy.dst),
2231                                 chan->dst_def_cfg,
2232                                 dst_info, src_info, flags);
2233
2234         dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
2235                                    desc->lli_pool.size, DMA_TO_DEVICE);
2236
2237         return ret < 0 ? ret : 0;
2238 }
2239
2240 static struct d40_desc *
2241 d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
2242               unsigned int sg_len, unsigned long dma_flags)
2243 {
2244         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2245         struct d40_desc *desc;
2246         int ret;
2247
2248         desc = d40_desc_get(chan);
2249         if (!desc)
2250                 return NULL;
2251
2252         desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2253                                         cfg->dst_info.data_width);
2254         if (desc->lli_len < 0) {
2255                 chan_err(chan, "Unaligned size\n");
2256                 goto err;
2257         }
2258
2259         ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2260         if (ret < 0) {
2261                 chan_err(chan, "Could not allocate lli\n");
2262                 goto err;
2263         }
2264
2265         desc->lli_current = 0;
2266         desc->txd.flags = dma_flags;
2267         desc->txd.tx_submit = d40_tx_submit;
2268
2269         dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2270
2271         return desc;
2272
2273 err:
2274         d40_desc_free(chan, desc);
2275         return NULL;
2276 }
2277
2278 static struct dma_async_tx_descriptor *
2279 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2280             struct scatterlist *sg_dst, unsigned int sg_len,
2281             enum dma_transfer_direction direction, unsigned long dma_flags)
2282 {
2283         struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
2284         dma_addr_t src_dev_addr = 0;
2285         dma_addr_t dst_dev_addr = 0;
2286         struct d40_desc *desc;
2287         unsigned long flags;
2288         int ret;
2289
2290         if (!chan->phy_chan) {
2291                 chan_err(chan, "Cannot prepare unallocated channel\n");
2292                 return NULL;
2293         }
2294
2295         spin_lock_irqsave(&chan->lock, flags);
2296
2297         desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2298         if (desc == NULL)
2299                 goto err;
2300
2301         if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2302                 desc->cyclic = true;
2303
2304         if (direction == DMA_DEV_TO_MEM)
2305                 src_dev_addr = chan->runtime_addr;
2306         else if (direction == DMA_MEM_TO_DEV)
2307                 dst_dev_addr = chan->runtime_addr;
2308
2309         if (chan_is_logical(chan))
2310                 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
2311                                       sg_len, src_dev_addr, dst_dev_addr);
2312         else
2313                 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
2314                                       sg_len, src_dev_addr, dst_dev_addr);
2315
2316         if (ret) {
2317                 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2318                          chan_is_logical(chan) ? "log" : "phy", ret);
2319                 goto err;
2320         }
2321
2322         /*
2323          * add descriptor to the prepare queue in order to be able
2324          * to free them later in terminate_all
2325          */
2326         list_add_tail(&desc->node, &chan->prepare_queue);
2327
2328         spin_unlock_irqrestore(&chan->lock, flags);
2329
2330         return &desc->txd;
2331
2332 err:
2333         if (desc)
2334                 d40_desc_free(chan, desc);
2335         spin_unlock_irqrestore(&chan->lock, flags);
2336         return NULL;
2337 }
2338
2339 bool stedma40_filter(struct dma_chan *chan, void *data)
2340 {
2341         struct stedma40_chan_cfg *info = data;
2342         struct d40_chan *d40c =
2343                 container_of(chan, struct d40_chan, chan);
2344         int err;
2345
2346         if (data) {
2347                 err = d40_validate_conf(d40c, info);
2348                 if (!err)
2349                         d40c->dma_cfg = *info;
2350         } else
2351                 err = d40_config_memcpy(d40c);
2352
2353         if (!err)
2354                 d40c->configured = true;
2355
2356         return err == 0;
2357 }
2358 EXPORT_SYMBOL(stedma40_filter);
2359
2360 static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2361 {
2362         bool realtime = d40c->dma_cfg.realtime;
2363         bool highprio = d40c->dma_cfg.high_priority;
2364         u32 rtreg;
2365         u32 event = D40_TYPE_TO_EVENT(dev_type);
2366         u32 group = D40_TYPE_TO_GROUP(dev_type);
2367         u32 bit = BIT(event);
2368         u32 prioreg;
2369         struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
2370
2371         rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear;
2372         /*
2373          * Due to a hardware bug, in some cases a logical channel triggered by
2374          * a high priority destination event line can generate extra packet
2375          * transactions.
2376          *
2377          * The workaround is to not set the high priority level for the
2378          * destination event lines that trigger logical channels.
2379          */
2380         if (!src && chan_is_logical(d40c))
2381                 highprio = false;
2382
2383         prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear;
2384
2385         /* Destination event lines are stored in the upper halfword */
2386         if (!src)
2387                 bit <<= 16;
2388
2389         writel(bit, d40c->base->virtbase + prioreg + group * 4);
2390         writel(bit, d40c->base->virtbase + rtreg + group * 4);
2391 }
2392
2393 static void d40_set_prio_realtime(struct d40_chan *d40c)
2394 {
2395         if (d40c->base->rev < 3)
2396                 return;
2397
2398         if ((d40c->dma_cfg.dir ==  DMA_DEV_TO_MEM) ||
2399             (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
2400                 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
2401
2402         if ((d40c->dma_cfg.dir ==  DMA_MEM_TO_DEV) ||
2403             (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
2404                 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
2405 }
2406
2407 #define D40_DT_FLAGS_MODE(flags)       ((flags >> 0) & 0x1)
2408 #define D40_DT_FLAGS_DIR(flags)        ((flags >> 1) & 0x1)
2409 #define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
2410 #define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
2411
2412 static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2413                                   struct of_dma *ofdma)
2414 {
2415         struct stedma40_chan_cfg cfg;
2416         dma_cap_mask_t cap;
2417         u32 flags;
2418
2419         memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
2420
2421         dma_cap_zero(cap);
2422         dma_cap_set(DMA_SLAVE, cap);
2423
2424         cfg.dev_type = dma_spec->args[0];
2425         flags = dma_spec->args[2];
2426
2427         switch (D40_DT_FLAGS_MODE(flags)) {
2428         case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
2429         case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
2430         }
2431
2432         switch (D40_DT_FLAGS_DIR(flags)) {
2433         case 0:
2434                 cfg.dir = DMA_MEM_TO_DEV;
2435                 cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2436                 break;
2437         case 1:
2438                 cfg.dir = DMA_DEV_TO_MEM;
2439                 cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2440                 break;
2441         }
2442
2443         if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
2444                 cfg.phy_channel = dma_spec->args[1];
2445                 cfg.use_fixed_channel = true;
2446         }
2447
2448         return dma_request_channel(cap, stedma40_filter, &cfg);
2449 }
2450
2451 /* DMA ENGINE functions */
2452 static int d40_alloc_chan_resources(struct dma_chan *chan)
2453 {
2454         int err;
2455         unsigned long flags;
2456         struct d40_chan *d40c =
2457                 container_of(chan, struct d40_chan, chan);
2458         bool is_free_phy;
2459         spin_lock_irqsave(&d40c->lock, flags);
2460
2461         dma_cookie_init(chan);
2462
2463         /* If no dma configuration is set use default configuration (memcpy) */
2464         if (!d40c->configured) {
2465                 err = d40_config_memcpy(d40c);
2466                 if (err) {
2467                         chan_err(d40c, "Failed to configure memcpy channel\n");
2468                         goto fail;
2469                 }
2470         }
2471
2472         err = d40_allocate_channel(d40c, &is_free_phy);
2473         if (err) {
2474                 chan_err(d40c, "Failed to allocate channel\n");
2475                 d40c->configured = false;
2476                 goto fail;
2477         }
2478
2479         pm_runtime_get_sync(d40c->base->dev);
2480
2481         d40_set_prio_realtime(d40c);
2482
2483         if (chan_is_logical(d40c)) {
2484                 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
2485                         d40c->lcpa = d40c->base->lcpa_base +
2486                                 d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
2487                 else
2488                         d40c->lcpa = d40c->base->lcpa_base +
2489                                 d40c->dma_cfg.dev_type *
2490                                 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2491
2492                 /* Unmask the Global Interrupt Mask. */
2493                 d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2494                 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2495         }
2496
2497         dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2498                  chan_is_logical(d40c) ? "logical" : "physical",
2499                  d40c->phy_chan->num,
2500                  d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2501
2502
2503         /*
2504          * Only write channel configuration to the DMA if the physical
2505          * resource is free. In case of multiple logical channels
2506          * on the same physical resource, only the first write is necessary.
2507          */
2508         if (is_free_phy)
2509                 d40_config_write(d40c);
2510 fail:
2511         pm_runtime_mark_last_busy(d40c->base->dev);
2512         pm_runtime_put_autosuspend(d40c->base->dev);
2513         spin_unlock_irqrestore(&d40c->lock, flags);
2514         return err;
2515 }
2516
2517 static void d40_free_chan_resources(struct dma_chan *chan)
2518 {
2519         struct d40_chan *d40c =
2520                 container_of(chan, struct d40_chan, chan);
2521         int err;
2522         unsigned long flags;
2523
2524         if (d40c->phy_chan == NULL) {
2525                 chan_err(d40c, "Cannot free unallocated channel\n");
2526                 return;
2527         }
2528
2529         spin_lock_irqsave(&d40c->lock, flags);
2530
2531         err = d40_free_dma(d40c);
2532
2533         if (err)
2534                 chan_err(d40c, "Failed to free channel\n");
2535         spin_unlock_irqrestore(&d40c->lock, flags);
2536 }
2537
2538 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2539                                                        dma_addr_t dst,
2540                                                        dma_addr_t src,
2541                                                        size_t size,
2542                                                        unsigned long dma_flags)
2543 {
2544         struct scatterlist dst_sg;
2545         struct scatterlist src_sg;
2546
2547         sg_init_table(&dst_sg, 1);
2548         sg_init_table(&src_sg, 1);
2549
2550         sg_dma_address(&dst_sg) = dst;
2551         sg_dma_address(&src_sg) = src;
2552
2553         sg_dma_len(&dst_sg) = size;
2554         sg_dma_len(&src_sg) = size;
2555
2556         return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
2557 }
2558
2559 static struct dma_async_tx_descriptor *
2560 d40_prep_memcpy_sg(struct dma_chan *chan,
2561                    struct scatterlist *dst_sg, unsigned int dst_nents,
2562                    struct scatterlist *src_sg, unsigned int src_nents,
2563                    unsigned long dma_flags)
2564 {
2565         if (dst_nents != src_nents)
2566                 return NULL;
2567
2568         return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
2569 }
2570
2571 static struct dma_async_tx_descriptor *
2572 d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2573                   unsigned int sg_len, enum dma_transfer_direction direction,
2574                   unsigned long dma_flags, void *context)
2575 {
2576         if (!is_slave_direction(direction))
2577                 return NULL;
2578
2579         return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
2580 }
2581
2582 static struct dma_async_tx_descriptor *
2583 dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2584                      size_t buf_len, size_t period_len,
2585                      enum dma_transfer_direction direction, unsigned long flags,
2586                      void *context)
2587 {
2588         unsigned int periods = buf_len / period_len;
2589         struct dma_async_tx_descriptor *txd;
2590         struct scatterlist *sg;
2591         int i;
2592
2593         sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
2594         if (!sg)
2595                 return NULL;
2596
2597         for (i = 0; i < periods; i++) {
2598                 sg_dma_address(&sg[i]) = dma_addr;
2599                 sg_dma_len(&sg[i]) = period_len;
2600                 dma_addr += period_len;
2601         }
2602
2603         sg[periods].offset = 0;
2604         sg_dma_len(&sg[periods]) = 0;
2605         sg[periods].page_link =
2606                 ((unsigned long)sg | 0x01) & ~0x02;
2607
2608         txd = d40_prep_sg(chan, sg, sg, periods, direction,
2609                           DMA_PREP_INTERRUPT);
2610
2611         kfree(sg);
2612
2613         return txd;
2614 }
2615
2616 static enum dma_status d40_tx_status(struct dma_chan *chan,
2617                                      dma_cookie_t cookie,
2618                                      struct dma_tx_state *txstate)
2619 {
2620         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2621         enum dma_status ret;
2622
2623         if (d40c->phy_chan == NULL) {
2624                 chan_err(d40c, "Cannot read status of unallocated channel\n");
2625                 return -EINVAL;
2626         }
2627
2628         ret = dma_cookie_status(chan, cookie, txstate);
2629         if (ret != DMA_SUCCESS)
2630                 dma_set_residue(txstate, stedma40_residue(chan));
2631
2632         if (d40_is_paused(d40c))
2633                 ret = DMA_PAUSED;
2634
2635         return ret;
2636 }
2637
2638 static void d40_issue_pending(struct dma_chan *chan)
2639 {
2640         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2641         unsigned long flags;
2642
2643         if (d40c->phy_chan == NULL) {
2644                 chan_err(d40c, "Channel is not allocated!\n");
2645                 return;
2646         }
2647
2648         spin_lock_irqsave(&d40c->lock, flags);
2649
2650         list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2651
2652         /* Busy means that queued jobs are already being processed */
2653         if (!d40c->busy)
2654                 (void) d40_queue_start(d40c);
2655
2656         spin_unlock_irqrestore(&d40c->lock, flags);
2657 }
2658
2659 static void d40_terminate_all(struct dma_chan *chan)
2660 {
2661         unsigned long flags;
2662         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2663         int ret;
2664
2665         spin_lock_irqsave(&d40c->lock, flags);
2666
2667         pm_runtime_get_sync(d40c->base->dev);
2668         ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2669         if (ret)
2670                 chan_err(d40c, "Failed to stop channel\n");
2671
2672         d40_term_all(d40c);
2673         pm_runtime_mark_last_busy(d40c->base->dev);
2674         pm_runtime_put_autosuspend(d40c->base->dev);
2675         if (d40c->busy) {
2676                 pm_runtime_mark_last_busy(d40c->base->dev);
2677                 pm_runtime_put_autosuspend(d40c->base->dev);
2678         }
2679         d40c->busy = false;
2680
2681         spin_unlock_irqrestore(&d40c->lock, flags);
2682 }
2683
2684 static int
2685 dma40_config_to_halfchannel(struct d40_chan *d40c,
2686                             struct stedma40_half_channel_info *info,
2687                             u32 maxburst)
2688 {
2689         int psize;
2690
2691         if (chan_is_logical(d40c)) {
2692                 if (maxburst >= 16)
2693                         psize = STEDMA40_PSIZE_LOG_16;
2694                 else if (maxburst >= 8)
2695                         psize = STEDMA40_PSIZE_LOG_8;
2696                 else if (maxburst >= 4)
2697                         psize = STEDMA40_PSIZE_LOG_4;
2698                 else
2699                         psize = STEDMA40_PSIZE_LOG_1;
2700         } else {
2701                 if (maxburst >= 16)
2702                         psize = STEDMA40_PSIZE_PHY_16;
2703                 else if (maxburst >= 8)
2704                         psize = STEDMA40_PSIZE_PHY_8;
2705                 else if (maxburst >= 4)
2706                         psize = STEDMA40_PSIZE_PHY_4;
2707                 else
2708                         psize = STEDMA40_PSIZE_PHY_1;
2709         }
2710
2711         info->psize = psize;
2712         info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2713
2714         return 0;
2715 }
2716
2717 /* Runtime reconfiguration extension */
2718 static int d40_set_runtime_config(struct dma_chan *chan,
2719                                   struct dma_slave_config *config)
2720 {
2721         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2722         struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2723         enum dma_slave_buswidth src_addr_width, dst_addr_width;
2724         dma_addr_t config_addr;
2725         u32 src_maxburst, dst_maxburst;
2726         int ret;
2727
2728         src_addr_width = config->src_addr_width;
2729         src_maxburst = config->src_maxburst;
2730         dst_addr_width = config->dst_addr_width;
2731         dst_maxburst = config->dst_maxburst;
2732
2733         if (config->direction == DMA_DEV_TO_MEM) {
2734                 config_addr = config->src_addr;
2735
2736                 if (cfg->dir != DMA_DEV_TO_MEM)
2737                         dev_dbg(d40c->base->dev,
2738                                 "channel was not configured for peripheral "
2739                                 "to memory transfer (%d) overriding\n",
2740                                 cfg->dir);
2741                 cfg->dir = DMA_DEV_TO_MEM;
2742
2743                 /* Configure the memory side */
2744                 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2745                         dst_addr_width = src_addr_width;
2746                 if (dst_maxburst == 0)
2747                         dst_maxburst = src_maxburst;
2748
2749         } else if (config->direction == DMA_MEM_TO_DEV) {
2750                 config_addr = config->dst_addr;
2751
2752                 if (cfg->dir != DMA_MEM_TO_DEV)
2753                         dev_dbg(d40c->base->dev,
2754                                 "channel was not configured for memory "
2755                                 "to peripheral transfer (%d) overriding\n",
2756                                 cfg->dir);
2757                 cfg->dir = DMA_MEM_TO_DEV;
2758
2759                 /* Configure the memory side */
2760                 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2761                         src_addr_width = dst_addr_width;
2762                 if (src_maxburst == 0)
2763                         src_maxburst = dst_maxburst;
2764         } else {
2765                 dev_err(d40c->base->dev,
2766                         "unrecognized channel direction %d\n",
2767                         config->direction);
2768                 return -EINVAL;
2769         }
2770
2771         if (config_addr <= 0) {
2772                 dev_err(d40c->base->dev, "no address supplied\n");
2773                 return -EINVAL;
2774         }
2775
2776         if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
2777                 dev_err(d40c->base->dev,
2778                         "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2779                         src_maxburst,
2780                         src_addr_width,
2781                         dst_maxburst,
2782                         dst_addr_width);
2783                 return -EINVAL;
2784         }
2785
2786         if (src_maxburst > 16) {
2787                 src_maxburst = 16;
2788                 dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
2789         } else if (dst_maxburst > 16) {
2790                 dst_maxburst = 16;
2791                 src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
2792         }
2793
2794         /* Only valid widths are; 1, 2, 4 and 8. */
2795         if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2796             src_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
2797             dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2798             dst_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
2799             ((src_addr_width > 1) && (src_addr_width & 1)) ||
2800             ((dst_addr_width > 1) && (dst_addr_width & 1)))
2801                 return -EINVAL;
2802
2803         cfg->src_info.data_width = src_addr_width;
2804         cfg->dst_info.data_width = dst_addr_width;
2805
2806         ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2807                                           src_maxburst);
2808         if (ret)
2809                 return ret;
2810
2811         ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2812                                           dst_maxburst);
2813         if (ret)
2814                 return ret;
2815
2816         /* Fill in register values */
2817         if (chan_is_logical(d40c))
2818                 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2819         else
2820                 d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
2821
2822         /* These settings will take precedence later */
2823         d40c->runtime_addr = config_addr;
2824         d40c->runtime_direction = config->direction;
2825         dev_dbg(d40c->base->dev,
2826                 "configured channel %s for %s, data width %d/%d, "
2827                 "maxburst %d/%d elements, LE, no flow control\n",
2828                 dma_chan_name(chan),
2829                 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
2830                 src_addr_width, dst_addr_width,
2831                 src_maxburst, dst_maxburst);
2832
2833         return 0;
2834 }
2835
2836 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2837                        unsigned long arg)
2838 {
2839         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2840
2841         if (d40c->phy_chan == NULL) {
2842                 chan_err(d40c, "Channel is not allocated!\n");
2843                 return -EINVAL;
2844         }
2845
2846         switch (cmd) {
2847         case DMA_TERMINATE_ALL:
2848                 d40_terminate_all(chan);
2849                 return 0;
2850         case DMA_PAUSE:
2851                 return d40_pause(d40c);
2852         case DMA_RESUME:
2853                 return d40_resume(d40c);
2854         case DMA_SLAVE_CONFIG:
2855                 return d40_set_runtime_config(chan,
2856                         (struct dma_slave_config *) arg);
2857         default:
2858                 break;
2859         }
2860
2861         /* Other commands are unimplemented */
2862         return -ENXIO;
2863 }
2864
2865 /* Initialization functions */
2866
2867 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2868                                  struct d40_chan *chans, int offset,
2869                                  int num_chans)
2870 {
2871         int i = 0;
2872         struct d40_chan *d40c;
2873
2874         INIT_LIST_HEAD(&dma->channels);
2875
2876         for (i = offset; i < offset + num_chans; i++) {
2877                 d40c = &chans[i];
2878                 d40c->base = base;
2879                 d40c->chan.device = dma;
2880
2881                 spin_lock_init(&d40c->lock);
2882
2883                 d40c->log_num = D40_PHY_CHAN;
2884
2885                 INIT_LIST_HEAD(&d40c->done);
2886                 INIT_LIST_HEAD(&d40c->active);
2887                 INIT_LIST_HEAD(&d40c->queue);
2888                 INIT_LIST_HEAD(&d40c->pending_queue);
2889                 INIT_LIST_HEAD(&d40c->client);
2890                 INIT_LIST_HEAD(&d40c->prepare_queue);
2891
2892                 tasklet_init(&d40c->tasklet, dma_tasklet,
2893                              (unsigned long) d40c);
2894
2895                 list_add_tail(&d40c->chan.device_node,
2896                               &dma->channels);
2897         }
2898 }
2899
2900 static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2901 {
2902         if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2903                 dev->device_prep_slave_sg = d40_prep_slave_sg;
2904
2905         if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2906                 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2907
2908                 /*
2909                  * This controller can only access address at even
2910                  * 32bit boundaries, i.e. 2^2
2911                  */
2912                 dev->copy_align = 2;
2913         }
2914
2915         if (dma_has_cap(DMA_SG, dev->cap_mask))
2916                 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2917
2918         if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2919                 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2920
2921         dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2922         dev->device_free_chan_resources = d40_free_chan_resources;
2923         dev->device_issue_pending = d40_issue_pending;
2924         dev->device_tx_status = d40_tx_status;
2925         dev->device_control = d40_control;
2926         dev->dev = base->dev;
2927 }
2928
2929 static int __init d40_dmaengine_init(struct d40_base *base,
2930                                      int num_reserved_chans)
2931 {
2932         int err ;
2933
2934         d40_chan_init(base, &base->dma_slave, base->log_chans,
2935                       0, base->num_log_chans);
2936
2937         dma_cap_zero(base->dma_slave.cap_mask);
2938         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2939         dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2940
2941         d40_ops_init(base, &base->dma_slave);
2942
2943         err = dma_async_device_register(&base->dma_slave);
2944
2945         if (err) {
2946                 d40_err(base->dev, "Failed to register slave channels\n");
2947                 goto failure1;
2948         }
2949
2950         d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2951                       base->num_log_chans, base->num_memcpy_chans);
2952
2953         dma_cap_zero(base->dma_memcpy.cap_mask);
2954         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2955         dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2956
2957         d40_ops_init(base, &base->dma_memcpy);
2958
2959         err = dma_async_device_register(&base->dma_memcpy);
2960
2961         if (err) {
2962                 d40_err(base->dev,
2963                         "Failed to regsiter memcpy only channels\n");
2964                 goto failure2;
2965         }
2966
2967         d40_chan_init(base, &base->dma_both, base->phy_chans,
2968                       0, num_reserved_chans);
2969
2970         dma_cap_zero(base->dma_both.cap_mask);
2971         dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2972         dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2973         dma_cap_set(DMA_SG, base->dma_both.cap_mask);
2974         dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2975
2976         d40_ops_init(base, &base->dma_both);
2977         err = dma_async_device_register(&base->dma_both);
2978
2979         if (err) {
2980                 d40_err(base->dev,
2981                         "Failed to register logical and physical capable channels\n");
2982                 goto failure3;
2983         }
2984         return 0;
2985 failure3:
2986         dma_async_device_unregister(&base->dma_memcpy);
2987 failure2:
2988         dma_async_device_unregister(&base->dma_slave);
2989 failure1:
2990         return err;
2991 }
2992
2993 /* Suspend resume functionality */
2994 #ifdef CONFIG_PM
2995 static int dma40_pm_suspend(struct device *dev)
2996 {
2997         struct platform_device *pdev = to_platform_device(dev);
2998         struct d40_base *base = platform_get_drvdata(pdev);
2999         int ret = 0;
3000
3001         if (base->lcpa_regulator)
3002                 ret = regulator_disable(base->lcpa_regulator);
3003         return ret;
3004 }
3005
3006 static int dma40_runtime_suspend(struct device *dev)
3007 {
3008         struct platform_device *pdev = to_platform_device(dev);
3009         struct d40_base *base = platform_get_drvdata(pdev);
3010
3011         d40_save_restore_registers(base, true);
3012
3013         /* Don't disable/enable clocks for v1 due to HW bugs */
3014         if (base->rev != 1)
3015                 writel_relaxed(base->gcc_pwr_off_mask,
3016                                base->virtbase + D40_DREG_GCC);
3017
3018         return 0;
3019 }
3020
3021 static int dma40_runtime_resume(struct device *dev)
3022 {
3023         struct platform_device *pdev = to_platform_device(dev);
3024         struct d40_base *base = platform_get_drvdata(pdev);
3025
3026         if (base->initialized)
3027                 d40_save_restore_registers(base, false);
3028
3029         writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
3030                        base->virtbase + D40_DREG_GCC);
3031         return 0;
3032 }
3033
3034 static int dma40_resume(struct device *dev)
3035 {
3036         struct platform_device *pdev = to_platform_device(dev);
3037         struct d40_base *base = platform_get_drvdata(pdev);
3038         int ret = 0;
3039
3040         if (base->lcpa_regulator)
3041                 ret = regulator_enable(base->lcpa_regulator);
3042
3043         return ret;
3044 }
3045
3046 static const struct dev_pm_ops dma40_pm_ops = {
3047         .suspend                = dma40_pm_suspend,
3048         .runtime_suspend        = dma40_runtime_suspend,
3049         .runtime_resume         = dma40_runtime_resume,
3050         .resume                 = dma40_resume,
3051 };
3052 #define DMA40_PM_OPS    (&dma40_pm_ops)
3053 #else
3054 #define DMA40_PM_OPS    NULL
3055 #endif
3056
3057 /* Initialization functions. */
3058
3059 static int __init d40_phy_res_init(struct d40_base *base)
3060 {
3061         int i;
3062         int num_phy_chans_avail = 0;
3063         u32 val[2];
3064         int odd_even_bit = -2;
3065         int gcc = D40_DREG_GCC_ENA;
3066
3067         val[0] = readl(base->virtbase + D40_DREG_PRSME);
3068         val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3069
3070         for (i = 0; i < base->num_phy_chans; i++) {
3071                 base->phy_res[i].num = i;
3072                 odd_even_bit += 2 * ((i % 2) == 0);
3073                 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
3074                         /* Mark security only channels as occupied */
3075                         base->phy_res[i].allocated_src = D40_ALLOC_PHY;
3076                         base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
3077                         base->phy_res[i].reserved = true;
3078                         gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3079                                                        D40_DREG_GCC_SRC);
3080                         gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3081                                                        D40_DREG_GCC_DST);
3082
3083
3084                 } else {
3085                         base->phy_res[i].allocated_src = D40_ALLOC_FREE;
3086                         base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
3087                         base->phy_res[i].reserved = false;
3088                         num_phy_chans_avail++;
3089                 }
3090                 spin_lock_init(&base->phy_res[i].lock);
3091         }
3092
3093         /* Mark disabled channels as occupied */
3094         for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
3095                 int chan = base->plat_data->disabled_channels[i];
3096
3097                 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
3098                 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
3099                 base->phy_res[chan].reserved = true;
3100                 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3101                                                D40_DREG_GCC_SRC);
3102                 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3103                                                D40_DREG_GCC_DST);
3104                 num_phy_chans_avail--;
3105         }
3106
3107         /* Mark soft_lli channels */
3108         for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) {
3109                 int chan = base->plat_data->soft_lli_chans[i];
3110
3111                 base->phy_res[chan].use_soft_lli = true;
3112         }
3113
3114         dev_info(base->dev, "%d of %d physical DMA channels available\n",
3115                  num_phy_chans_avail, base->num_phy_chans);
3116
3117         /* Verify settings extended vs standard */
3118         val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3119
3120         for (i = 0; i < base->num_phy_chans; i++) {
3121
3122                 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
3123                     (val[0] & 0x3) != 1)
3124                         dev_info(base->dev,
3125                                  "[%s] INFO: channel %d is misconfigured (%d)\n",
3126                                  __func__, i, val[0] & 0x3);
3127
3128                 val[0] = val[0] >> 2;
3129         }
3130
3131         /*
3132          * To keep things simple, Enable all clocks initially.
3133          * The clocks will get managed later post channel allocation.
3134          * The clocks for the event lines on which reserved channels exists
3135          * are not managed here.
3136          */
3137         writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3138         base->gcc_pwr_off_mask = gcc;
3139
3140         return num_phy_chans_avail;
3141 }
3142
3143 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3144 {
3145         struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
3146         struct clk *clk = NULL;
3147         void __iomem *virtbase = NULL;
3148         struct resource *res = NULL;
3149         struct d40_base *base = NULL;
3150         int num_log_chans = 0;
3151         int num_phy_chans;
3152         int num_memcpy_chans;
3153         int clk_ret = -EINVAL;
3154         int i;
3155         u32 pid;
3156         u32 cid;
3157         u8 rev;
3158
3159         clk = clk_get(&pdev->dev, NULL);
3160         if (IS_ERR(clk)) {
3161                 d40_err(&pdev->dev, "No matching clock found\n");
3162                 goto failure;
3163         }
3164
3165         clk_ret = clk_prepare_enable(clk);
3166         if (clk_ret) {
3167                 d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
3168                 goto failure;
3169         }
3170
3171         /* Get IO for DMAC base address */
3172         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
3173         if (!res)
3174                 goto failure;
3175
3176         if (request_mem_region(res->start, resource_size(res),
3177                                D40_NAME " I/O base") == NULL)
3178                 goto failure;
3179
3180         virtbase = ioremap(res->start, resource_size(res));
3181         if (!virtbase)
3182                 goto failure;
3183
3184         /* This is just a regular AMBA PrimeCell ID actually */
3185         for (pid = 0, i = 0; i < 4; i++)
3186                 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
3187                         & 255) << (i * 8);
3188         for (cid = 0, i = 0; i < 4; i++)
3189                 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
3190                         & 255) << (i * 8);
3191
3192         if (cid != AMBA_CID) {
3193                 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
3194                 goto failure;
3195         }
3196         if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
3197                 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
3198                         AMBA_MANF_BITS(pid),
3199                         AMBA_VENDOR_ST);
3200                 goto failure;
3201         }
3202         /*
3203          * HW revision:
3204          * DB8500ed has revision 0
3205          * ? has revision 1
3206          * DB8500v1 has revision 2
3207          * DB8500v2 has revision 3
3208          * AP9540v1 has revision 4
3209          * DB8540v1 has revision 4
3210          */
3211         rev = AMBA_REV_BITS(pid);
3212         if (rev < 2) {
3213                 d40_err(&pdev->dev, "hardware revision: %d is not supported", rev);
3214                 goto failure;
3215         }
3216
3217         /* The number of physical channels on this HW */
3218         if (plat_data->num_of_phy_chans)
3219                 num_phy_chans = plat_data->num_of_phy_chans;
3220         else
3221                 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
3222
3223         /* The number of channels used for memcpy */
3224         if (plat_data->num_of_memcpy_chans)
3225                 num_memcpy_chans = plat_data->num_of_memcpy_chans;
3226         else
3227                 num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
3228
3229         num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
3230
3231         dev_info(&pdev->dev,
3232                  "hardware rev: %d @ %pa with %d physical and %d logical channels\n",
3233                  rev, &res->start, num_phy_chans, num_log_chans);
3234
3235         base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
3236                        (num_phy_chans + num_log_chans + num_memcpy_chans) *
3237                        sizeof(struct d40_chan), GFP_KERNEL);
3238
3239         if (base == NULL) {
3240                 d40_err(&pdev->dev, "Out of memory\n");
3241                 goto failure;
3242         }
3243
3244         base->rev = rev;
3245         base->clk = clk;
3246         base->num_memcpy_chans = num_memcpy_chans;
3247         base->num_phy_chans = num_phy_chans;
3248         base->num_log_chans = num_log_chans;
3249         base->phy_start = res->start;
3250         base->phy_size = resource_size(res);
3251         base->virtbase = virtbase;
3252         base->plat_data = plat_data;
3253         base->dev = &pdev->dev;
3254         base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
3255         base->log_chans = &base->phy_chans[num_phy_chans];
3256
3257         if (base->plat_data->num_of_phy_chans == 14) {
3258                 base->gen_dmac.backup = d40_backup_regs_v4b;
3259                 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
3260                 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
3261                 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
3262                 base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
3263                 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
3264                 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
3265                 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
3266                 base->gen_dmac.il = il_v4b;
3267                 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
3268                 base->gen_dmac.init_reg = dma_init_reg_v4b;
3269                 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
3270         } else {
3271                 if (base->rev >= 3) {
3272                         base->gen_dmac.backup = d40_backup_regs_v4a;
3273                         base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
3274                 }
3275                 base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
3276                 base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
3277                 base->gen_dmac.realtime_en = D40_DREG_RSEG1;
3278                 base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
3279                 base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
3280                 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
3281                 base->gen_dmac.il = il_v4a;
3282                 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
3283                 base->gen_dmac.init_reg = dma_init_reg_v4a;
3284                 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
3285         }
3286
3287         base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
3288                                 GFP_KERNEL);
3289         if (!base->phy_res)
3290                 goto failure;
3291
3292         base->lookup_phy_chans = kzalloc(num_phy_chans *
3293                                          sizeof(struct d40_chan *),
3294                                          GFP_KERNEL);
3295         if (!base->lookup_phy_chans)
3296                 goto failure;
3297
3298         base->lookup_log_chans = kzalloc(num_log_chans *
3299                                          sizeof(struct d40_chan *),
3300                                          GFP_KERNEL);
3301         if (!base->lookup_log_chans)
3302                 goto failure;
3303
3304         base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
3305                                             sizeof(d40_backup_regs_chan),
3306                                             GFP_KERNEL);
3307         if (!base->reg_val_backup_chan)
3308                 goto failure;
3309
3310         base->lcla_pool.alloc_map =
3311                 kzalloc(num_phy_chans * sizeof(struct d40_desc *)
3312                         * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
3313         if (!base->lcla_pool.alloc_map)
3314                 goto failure;
3315
3316         base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
3317                                             0, SLAB_HWCACHE_ALIGN,
3318                                             NULL);
3319         if (base->desc_slab == NULL)
3320                 goto failure;
3321
3322         return base;
3323
3324 failure:
3325         if (!clk_ret)
3326                 clk_disable_unprepare(clk);
3327         if (!IS_ERR(clk))
3328                 clk_put(clk);
3329         if (virtbase)
3330                 iounmap(virtbase);
3331         if (res)
3332                 release_mem_region(res->start,
3333                                    resource_size(res));
3334         if (virtbase)
3335                 iounmap(virtbase);
3336
3337         if (base) {
3338                 kfree(base->lcla_pool.alloc_map);
3339                 kfree(base->reg_val_backup_chan);
3340                 kfree(base->lookup_log_chans);
3341                 kfree(base->lookup_phy_chans);
3342                 kfree(base->phy_res);
3343                 kfree(base);
3344         }
3345
3346         return NULL;
3347 }
3348
3349 static void __init d40_hw_init(struct d40_base *base)
3350 {
3351
3352         int i;
3353         u32 prmseo[2] = {0, 0};
3354         u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3355         u32 pcmis = 0;
3356         u32 pcicr = 0;
3357         struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
3358         u32 reg_size = base->gen_dmac.init_reg_size;
3359
3360         for (i = 0; i < reg_size; i++)
3361                 writel(dma_init_reg[i].val,
3362                        base->virtbase + dma_init_reg[i].reg);
3363
3364         /* Configure all our dma channels to default settings */
3365         for (i = 0; i < base->num_phy_chans; i++) {
3366
3367                 activeo[i % 2] = activeo[i % 2] << 2;
3368
3369                 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3370                     == D40_ALLOC_PHY) {
3371                         activeo[i % 2] |= 3;
3372                         continue;
3373                 }
3374
3375                 /* Enable interrupt # */
3376                 pcmis = (pcmis << 1) | 1;
3377
3378                 /* Clear interrupt # */
3379                 pcicr = (pcicr << 1) | 1;
3380
3381                 /* Set channel to physical mode */
3382                 prmseo[i % 2] = prmseo[i % 2] << 2;
3383                 prmseo[i % 2] |= 1;
3384
3385         }
3386
3387         writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3388         writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3389         writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3390         writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3391
3392         /* Write which interrupt to enable */
3393         writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
3394
3395         /* Write which interrupt to clear */
3396         writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
3397
3398         /* These are __initdata and cannot be accessed after init */
3399         base->gen_dmac.init_reg = NULL;
3400         base->gen_dmac.init_reg_size = 0;
3401 }
3402
3403 static int __init d40_lcla_allocate(struct d40_base *base)
3404 {
3405         struct d40_lcla_pool *pool = &base->lcla_pool;
3406         unsigned long *page_list;
3407         int i, j;
3408         int ret = 0;
3409
3410         /*
3411          * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3412          * To full fill this hardware requirement without wasting 256 kb
3413          * we allocate pages until we get an aligned one.
3414          */
3415         page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
3416                             GFP_KERNEL);
3417
3418         if (!page_list) {
3419                 ret = -ENOMEM;
3420                 goto failure;
3421         }
3422
3423         /* Calculating how many pages that are required */
3424         base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3425
3426         for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3427                 page_list[i] = __get_free_pages(GFP_KERNEL,
3428                                                 base->lcla_pool.pages);
3429                 if (!page_list[i]) {
3430
3431                         d40_err(base->dev, "Failed to allocate %d pages.\n",
3432                                 base->lcla_pool.pages);
3433
3434                         for (j = 0; j < i; j++)
3435                                 free_pages(page_list[j], base->lcla_pool.pages);
3436                         goto failure;
3437                 }
3438
3439                 if ((virt_to_phys((void *)page_list[i]) &
3440                      (LCLA_ALIGNMENT - 1)) == 0)
3441                         break;
3442         }
3443
3444         for (j = 0; j < i; j++)
3445                 free_pages(page_list[j], base->lcla_pool.pages);
3446
3447         if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3448                 base->lcla_pool.base = (void *)page_list[i];
3449         } else {
3450                 /*
3451                  * After many attempts and no succees with finding the correct
3452                  * alignment, try with allocating a big buffer.
3453                  */
3454                 dev_warn(base->dev,
3455                          "[%s] Failed to get %d pages @ 18 bit align.\n",
3456                          __func__, base->lcla_pool.pages);
3457                 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3458                                                          base->num_phy_chans +
3459                                                          LCLA_ALIGNMENT,
3460                                                          GFP_KERNEL);
3461                 if (!base->lcla_pool.base_unaligned) {
3462                         ret = -ENOMEM;
3463                         goto failure;
3464                 }
3465
3466                 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3467                                                  LCLA_ALIGNMENT);
3468         }
3469
3470         pool->dma_addr = dma_map_single(base->dev, pool->base,
3471                                         SZ_1K * base->num_phy_chans,
3472                                         DMA_TO_DEVICE);
3473         if (dma_mapping_error(base->dev, pool->dma_addr)) {
3474                 pool->dma_addr = 0;
3475                 ret = -ENOMEM;
3476                 goto failure;
3477         }
3478
3479         writel(virt_to_phys(base->lcla_pool.base),
3480                base->virtbase + D40_DREG_LCLA);
3481 failure:
3482         kfree(page_list);
3483         return ret;
3484 }
3485
3486 static int __init d40_of_probe(struct platform_device *pdev,
3487                                struct device_node *np)
3488 {
3489         struct stedma40_platform_data *pdata;
3490         int num_phy = 0, num_memcpy = 0, num_disabled = 0;
3491         const __be32 *list;
3492
3493         pdata = devm_kzalloc(&pdev->dev,
3494                              sizeof(struct stedma40_platform_data),
3495                              GFP_KERNEL);
3496         if (!pdata)
3497                 return -ENOMEM;
3498
3499         /* If absent this value will be obtained from h/w. */
3500         of_property_read_u32(np, "dma-channels", &num_phy);
3501         if (num_phy > 0)
3502                 pdata->num_of_phy_chans = num_phy;
3503
3504         list = of_get_property(np, "memcpy-channels", &num_memcpy);
3505         num_memcpy /= sizeof(*list);
3506
3507         if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
3508                 d40_err(&pdev->dev,
3509                         "Invalid number of memcpy channels specified (%d)\n",
3510                         num_memcpy);
3511                 return -EINVAL;
3512         }
3513         pdata->num_of_memcpy_chans = num_memcpy;
3514
3515         of_property_read_u32_array(np, "memcpy-channels",
3516                                    dma40_memcpy_channels,
3517                                    num_memcpy);
3518
3519         list = of_get_property(np, "disabled-channels", &num_disabled);
3520         num_disabled /= sizeof(*list);
3521
3522         if (num_disabled >= STEDMA40_MAX_PHYS || num_disabled < 0) {
3523                 d40_err(&pdev->dev,
3524                         "Invalid number of disabled channels specified (%d)\n",
3525                         num_disabled);
3526                 return -EINVAL;
3527         }
3528
3529         of_property_read_u32_array(np, "disabled-channels",
3530                                    pdata->disabled_channels,
3531                                    num_disabled);
3532         pdata->disabled_channels[num_disabled] = -1;
3533
3534         pdev->dev.platform_data = pdata;
3535
3536         return 0;
3537 }
3538
3539 static int __init d40_probe(struct platform_device *pdev)
3540 {
3541         struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
3542         struct device_node *np = pdev->dev.of_node;
3543         int ret = -ENOENT;
3544         struct d40_base *base = NULL;
3545         struct resource *res = NULL;
3546         int num_reserved_chans;
3547         u32 val;
3548
3549         if (!plat_data) {
3550                 if (np) {
3551                         if(d40_of_probe(pdev, np)) {
3552                                 ret = -ENOMEM;
3553                                 goto failure;
3554                         }
3555                 } else {
3556                         d40_err(&pdev->dev, "No pdata or Device Tree provided\n");
3557                         goto failure;
3558                 }
3559         }
3560
3561         base = d40_hw_detect_init(pdev);
3562         if (!base)
3563                 goto failure;
3564
3565         num_reserved_chans = d40_phy_res_init(base);
3566
3567         platform_set_drvdata(pdev, base);
3568
3569         spin_lock_init(&base->interrupt_lock);
3570         spin_lock_init(&base->execmd_lock);
3571
3572         /* Get IO for logical channel parameter address */
3573         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3574         if (!res) {
3575                 ret = -ENOENT;
3576                 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
3577                 goto failure;
3578         }
3579         base->lcpa_size = resource_size(res);
3580         base->phy_lcpa = res->start;
3581
3582         if (request_mem_region(res->start, resource_size(res),
3583                                D40_NAME " I/O lcpa") == NULL) {
3584                 ret = -EBUSY;
3585                 d40_err(&pdev->dev, "Failed to request LCPA region %pR\n", res);
3586                 goto failure;
3587         }
3588
3589         /* We make use of ESRAM memory for this. */
3590         val = readl(base->virtbase + D40_DREG_LCPA);
3591         if (res->start != val && val != 0) {
3592                 dev_warn(&pdev->dev,
3593                          "[%s] Mismatch LCPA dma 0x%x, def %pa\n",
3594                          __func__, val, &res->start);
3595         } else
3596                 writel(res->start, base->virtbase + D40_DREG_LCPA);
3597
3598         base->lcpa_base = ioremap(res->start, resource_size(res));
3599         if (!base->lcpa_base) {
3600                 ret = -ENOMEM;
3601                 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
3602                 goto failure;
3603         }
3604         /* If lcla has to be located in ESRAM we don't need to allocate */
3605         if (base->plat_data->use_esram_lcla) {
3606                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3607                                                         "lcla_esram");
3608                 if (!res) {
3609                         ret = -ENOENT;
3610                         d40_err(&pdev->dev,
3611                                 "No \"lcla_esram\" memory resource\n");
3612                         goto failure;
3613                 }
3614                 base->lcla_pool.base = ioremap(res->start,
3615                                                 resource_size(res));
3616                 if (!base->lcla_pool.base) {
3617                         ret = -ENOMEM;
3618                         d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3619                         goto failure;
3620                 }
3621                 writel(res->start, base->virtbase + D40_DREG_LCLA);
3622
3623         } else {
3624                 ret = d40_lcla_allocate(base);
3625                 if (ret) {
3626                         d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3627                         goto failure;
3628                 }
3629         }
3630
3631         spin_lock_init(&base->lcla_pool.lock);
3632
3633         base->irq = platform_get_irq(pdev, 0);
3634
3635         ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
3636         if (ret) {
3637                 d40_err(&pdev->dev, "No IRQ defined\n");
3638                 goto failure;
3639         }
3640
3641         pm_runtime_irq_safe(base->dev);
3642         pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3643         pm_runtime_use_autosuspend(base->dev);
3644         pm_runtime_enable(base->dev);
3645         pm_runtime_resume(base->dev);
3646
3647         if (base->plat_data->use_esram_lcla) {
3648
3649                 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3650                 if (IS_ERR(base->lcpa_regulator)) {
3651                         d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
3652                         ret = PTR_ERR(base->lcpa_regulator);
3653                         base->lcpa_regulator = NULL;
3654                         goto failure;
3655                 }
3656
3657                 ret = regulator_enable(base->lcpa_regulator);
3658                 if (ret) {
3659                         d40_err(&pdev->dev,
3660                                 "Failed to enable lcpa_regulator\n");
3661                         regulator_put(base->lcpa_regulator);
3662                         base->lcpa_regulator = NULL;
3663                         goto failure;
3664                 }
3665         }
3666
3667         base->initialized = true;
3668         ret = d40_dmaengine_init(base, num_reserved_chans);
3669         if (ret)
3670                 goto failure;
3671
3672         base->dev->dma_parms = &base->dma_parms;
3673         ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
3674         if (ret) {
3675                 d40_err(&pdev->dev, "Failed to set dma max seg size\n");
3676                 goto failure;
3677         }
3678
3679         d40_hw_init(base);
3680
3681         if (np) {
3682                 ret = of_dma_controller_register(np, d40_xlate, NULL);
3683                 if (ret)
3684                         dev_err(&pdev->dev,
3685                                 "could not register of_dma_controller\n");
3686         }
3687
3688         dev_info(base->dev, "initialized\n");
3689         return 0;
3690
3691 failure:
3692         if (base) {
3693                 if (base->desc_slab)
3694                         kmem_cache_destroy(base->desc_slab);
3695                 if (base->virtbase)
3696                         iounmap(base->virtbase);
3697
3698                 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3699                         iounmap(base->lcla_pool.base);
3700                         base->lcla_pool.base = NULL;
3701                 }
3702
3703                 if (base->lcla_pool.dma_addr)
3704                         dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3705                                          SZ_1K * base->num_phy_chans,
3706                                          DMA_TO_DEVICE);
3707
3708                 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3709                         free_pages((unsigned long)base->lcla_pool.base,
3710                                    base->lcla_pool.pages);
3711
3712                 kfree(base->lcla_pool.base_unaligned);
3713
3714                 if (base->phy_lcpa)
3715                         release_mem_region(base->phy_lcpa,
3716                                            base->lcpa_size);
3717                 if (base->phy_start)
3718                         release_mem_region(base->phy_start,
3719                                            base->phy_size);
3720                 if (base->clk) {
3721                         clk_disable_unprepare(base->clk);
3722                         clk_put(base->clk);
3723                 }
3724
3725                 if (base->lcpa_regulator) {
3726                         regulator_disable(base->lcpa_regulator);
3727                         regulator_put(base->lcpa_regulator);
3728                 }
3729
3730                 kfree(base->lcla_pool.alloc_map);
3731                 kfree(base->lookup_log_chans);
3732                 kfree(base->lookup_phy_chans);
3733                 kfree(base->phy_res);
3734                 kfree(base);
3735         }
3736
3737         d40_err(&pdev->dev, "probe failed\n");
3738         return ret;
3739 }
3740
3741 static const struct of_device_id d40_match[] = {
3742         { .compatible = "stericsson,dma40", },
3743         {}
3744 };
3745
3746 static struct platform_driver d40_driver = {
3747         .driver = {
3748                 .owner = THIS_MODULE,
3749                 .name  = D40_NAME,
3750                 .pm = DMA40_PM_OPS,
3751                 .of_match_table = d40_match,
3752         },
3753 };
3754
3755 static int __init stedma40_init(void)
3756 {
3757         return platform_driver_probe(&d40_driver, d40_probe);
3758 }
3759 subsys_initcall(stedma40_init);