drivers/dma/omap-dma.c

   1 /*
   2  * OMAP DMAengine support
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/delay.h>
   9 #include <linux/dmaengine.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/err.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/list.h>
  15 #include <linux/module.h>
  16 #include <linux/omap-dma.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/of_dma.h>
  21 #include <linux/of_device.h>
  22
  23 #include "virt-dma.h"
  24
  25 #define OMAP_SDMA_REQUESTS      127
  26 #define OMAP_SDMA_CHANNELS      32
  27
  28 struct omap_dmadev {
  29         struct dma_device ddev;
  30         spinlock_t lock;
  31         struct tasklet_struct task;
  32         struct list_head pending;
  33         void __iomem *base;
  34         const struct omap_dma_reg *reg_map;
  35         struct omap_system_dma_plat_info *plat;
  36         bool legacy;
  37         unsigned dma_requests;
  38         spinlock_t irq_lock;
  39         uint32_t irq_enable_mask;
  40         struct omap_chan *lch_map[OMAP_SDMA_CHANNELS];
  41 };
  42
  43 struct omap_chan {
  44         struct virt_dma_chan vc;
  45         struct list_head node;
  46         void __iomem *channel_base;
  47         const struct omap_dma_reg *reg_map;
  48         uint32_t ccr;
  49
  50         struct dma_slave_config cfg;
  51         unsigned dma_sig;
  52         bool cyclic;
  53         bool paused;
  54
  55         int dma_ch;
  56         struct omap_desc *desc;
  57         unsigned sgidx;
  58 };
  59
  60 struct omap_sg {
  61         dma_addr_t addr;
  62         uint32_t en;            /* number of elements (24-bit) */
  63         uint32_t fn;            /* number of frames (16-bit) */
  64 };
  65
  66 struct omap_desc {
  67         struct virt_dma_desc vd;
  68         enum dma_transfer_direction dir;
  69         dma_addr_t dev_addr;
  70
  71         int16_t fi;             /* for OMAP_DMA_SYNC_PACKET */
  72         uint8_t es;             /* CSDP_DATA_TYPE_xxx */
  73         uint32_t ccr;           /* CCR value */
  74         uint16_t clnk_ctrl;     /* CLNK_CTRL value */
  75         uint16_t cicr;          /* CICR value */
  76         uint32_t csdp;          /* CSDP value */
  77
  78         unsigned sglen;
  79         struct omap_sg sg[0];
  80 };
  81
  82 enum {
  83         CCR_FS                  = BIT(5),
  84         CCR_READ_PRIORITY       = BIT(6),
  85         CCR_ENABLE              = BIT(7),
  86         CCR_AUTO_INIT           = BIT(8),       /* OMAP1 only */
  87         CCR_REPEAT              = BIT(9),       /* OMAP1 only */
  88         CCR_OMAP31_DISABLE      = BIT(10),      /* OMAP1 only */
  89         CCR_SUSPEND_SENSITIVE   = BIT(8),       /* OMAP2+ only */
  90         CCR_RD_ACTIVE           = BIT(9),       /* OMAP2+ only */
  91         CCR_WR_ACTIVE           = BIT(10),      /* OMAP2+ only */
  92         CCR_SRC_AMODE_CONSTANT  = 0 << 12,
  93         CCR_SRC_AMODE_POSTINC   = 1 << 12,
  94         CCR_SRC_AMODE_SGLIDX    = 2 << 12,
  95         CCR_SRC_AMODE_DBLIDX    = 3 << 12,
  96         CCR_DST_AMODE_CONSTANT  = 0 << 14,
  97         CCR_DST_AMODE_POSTINC   = 1 << 14,
  98         CCR_DST_AMODE_SGLIDX    = 2 << 14,
  99         CCR_DST_AMODE_DBLIDX    = 3 << 14,
 100         CCR_CONSTANT_FILL       = BIT(16),
 101         CCR_TRANSPARENT_COPY    = BIT(17),
 102         CCR_BS                  = BIT(18),
 103         CCR_SUPERVISOR          = BIT(22),
 104         CCR_PREFETCH            = BIT(23),
 105         CCR_TRIGGER_SRC         = BIT(24),
 106         CCR_BUFFERING_DISABLE   = BIT(25),
 107         CCR_WRITE_PRIORITY      = BIT(26),
 108         CCR_SYNC_ELEMENT        = 0,
 109         CCR_SYNC_FRAME          = CCR_FS,
 110         CCR_SYNC_BLOCK          = CCR_BS,
 111         CCR_SYNC_PACKET         = CCR_BS | CCR_FS,
 112
 113         CSDP_DATA_TYPE_8        = 0,
 114         CSDP_DATA_TYPE_16       = 1,
 115         CSDP_DATA_TYPE_32       = 2,
 116         CSDP_SRC_PORT_EMIFF     = 0 << 2, /* OMAP1 only */
 117         CSDP_SRC_PORT_EMIFS     = 1 << 2, /* OMAP1 only */
 118         CSDP_SRC_PORT_OCP_T1    = 2 << 2, /* OMAP1 only */
 119         CSDP_SRC_PORT_TIPB      = 3 << 2, /* OMAP1 only */
 120         CSDP_SRC_PORT_OCP_T2    = 4 << 2, /* OMAP1 only */
 121         CSDP_SRC_PORT_MPUI      = 5 << 2, /* OMAP1 only */
 122         CSDP_SRC_PACKED         = BIT(6),
 123         CSDP_SRC_BURST_1        = 0 << 7,
 124         CSDP_SRC_BURST_16       = 1 << 7,
 125         CSDP_SRC_BURST_32       = 2 << 7,
 126         CSDP_SRC_BURST_64       = 3 << 7,
 127         CSDP_DST_PORT_EMIFF     = 0 << 9, /* OMAP1 only */
 128         CSDP_DST_PORT_EMIFS     = 1 << 9, /* OMAP1 only */
 129         CSDP_DST_PORT_OCP_T1    = 2 << 9, /* OMAP1 only */
 130         CSDP_DST_PORT_TIPB      = 3 << 9, /* OMAP1 only */
 131         CSDP_DST_PORT_OCP_T2    = 4 << 9, /* OMAP1 only */
 132         CSDP_DST_PORT_MPUI      = 5 << 9, /* OMAP1 only */
 133         CSDP_DST_PACKED         = BIT(13),
 134         CSDP_DST_BURST_1        = 0 << 14,
 135         CSDP_DST_BURST_16       = 1 << 14,
 136         CSDP_DST_BURST_32       = 2 << 14,
 137         CSDP_DST_BURST_64       = 3 << 14,
 138
 139         CICR_TOUT_IE            = BIT(0),       /* OMAP1 only */
 140         CICR_DROP_IE            = BIT(1),
 141         CICR_HALF_IE            = BIT(2),
 142         CICR_FRAME_IE           = BIT(3),
 143         CICR_LAST_IE            = BIT(4),
 144         CICR_BLOCK_IE           = BIT(5),
 145         CICR_PKT_IE             = BIT(7),       /* OMAP2+ only */
 146         CICR_TRANS_ERR_IE       = BIT(8),       /* OMAP2+ only */
 147         CICR_SUPERVISOR_ERR_IE  = BIT(10),      /* OMAP2+ only */
 148         CICR_MISALIGNED_ERR_IE  = BIT(11),      /* OMAP2+ only */
 149         CICR_DRAIN_IE           = BIT(12),      /* OMAP2+ only */
 150         CICR_SUPER_BLOCK_IE     = BIT(14),      /* OMAP2+ only */
 151
 152         CLNK_CTRL_ENABLE_LNK    = BIT(15),
 153 };
 154
 155 static const unsigned es_bytes[] = {
 156         [CSDP_DATA_TYPE_8] = 1,
 157         [CSDP_DATA_TYPE_16] = 2,
 158         [CSDP_DATA_TYPE_32] = 4,
 159 };
 160
 161 static struct of_dma_filter_info omap_dma_info = {
 162         .filter_fn = omap_dma_filter_fn,
 163 };
 164
 165 static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
 166 {
 167         return container_of(d, struct omap_dmadev, ddev);
 168 }
 169
 170 static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c)
 171 {
 172         return container_of(c, struct omap_chan, vc.chan);
 173 }
 174
 175 static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t)
 176 {
 177         return container_of(t, struct omap_desc, vd.tx);
 178 }
 179
 180 static void omap_dma_desc_free(struct virt_dma_desc *vd)
 181 {
 182         kfree(container_of(vd, struct omap_desc, vd));
 183 }
 184
 185 static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr)
 186 {
 187         switch (type) {
 188         case OMAP_DMA_REG_16BIT:
 189                 writew_relaxed(val, addr);
 190                 break;
 191         case OMAP_DMA_REG_2X16BIT:
 192                 writew_relaxed(val, addr);
 193                 writew_relaxed(val >> 16, addr + 2);
 194                 break;
 195         case OMAP_DMA_REG_32BIT:
 196                 writel_relaxed(val, addr);
 197                 break;
 198         default:
 199                 WARN_ON(1);
 200         }
 201 }
 202
 203 static unsigned omap_dma_read(unsigned type, void __iomem *addr)
 204 {
 205         unsigned val;
 206
 207         switch (type) {
 208         case OMAP_DMA_REG_16BIT:
 209                 val = readw_relaxed(addr);
 210                 break;
 211         case OMAP_DMA_REG_2X16BIT:
 212                 val = readw_relaxed(addr);
 213                 val |= readw_relaxed(addr + 2) << 16;
 214                 break;
 215         case OMAP_DMA_REG_32BIT:
 216                 val = readl_relaxed(addr);
 217                 break;
 218         default:
 219                 WARN_ON(1);
 220                 val = 0;
 221         }
 222
 223         return val;
 224 }
 225
 226 static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
 227 {
 228         const struct omap_dma_reg *r = od->reg_map + reg;
 229
 230         WARN_ON(r->stride);
 231
 232         omap_dma_write(val, r->type, od->base + r->offset);
 233 }
 234
 235 static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg)
 236 {
 237         const struct omap_dma_reg *r = od->reg_map + reg;
 238
 239         WARN_ON(r->stride);
 240
 241         return omap_dma_read(r->type, od->base + r->offset);
 242 }
 243
 244 static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val)
 245 {
 246         const struct omap_dma_reg *r = c->reg_map + reg;
 247
 248         omap_dma_write(val, r->type, c->channel_base + r->offset);
 249 }
 250
 251 static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg)
 252 {
 253         const struct omap_dma_reg *r = c->reg_map + reg;
 254
 255         return omap_dma_read(r->type, c->channel_base + r->offset);
 256 }
 257
 258 static void omap_dma_clear_csr(struct omap_chan *c)
 259 {
 260         if (dma_omap1())
 261                 omap_dma_chan_read(c, CSR);
 262         else
 263                 omap_dma_chan_write(c, CSR, ~0);
 264 }
 265
 266 static unsigned omap_dma_get_csr(struct omap_chan *c)
 267 {
 268         unsigned val = omap_dma_chan_read(c, CSR);
 269
 270         if (!dma_omap1())
 271                 omap_dma_chan_write(c, CSR, val);
 272
 273         return val;
 274 }
 275
 276 static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
 277         unsigned lch)
 278 {
 279         c->channel_base = od->base + od->plat->channel_stride * lch;
 280
 281         od->lch_map[lch] = c;
 282 }
 283
 284 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
 285 {
 286         struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
 287
 288         if (__dma_omap15xx(od->plat->dma_attr))
 289                 omap_dma_chan_write(c, CPC, 0);
 290         else
 291                 omap_dma_chan_write(c, CDAC, 0);
 292
 293         omap_dma_clear_csr(c);
 294
 295         /* Enable interrupts */
 296         omap_dma_chan_write(c, CICR, d->cicr);
 297
 298         /* Enable channel */
 299         omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE);
 300 }
 301
 302 static void omap_dma_stop(struct omap_chan *c)
 303 {
 304         struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
 305         uint32_t val;
 306
 307         /* disable irq */
 308         omap_dma_chan_write(c, CICR, 0);
 309
 310         omap_dma_clear_csr(c);
 311
 312         val = omap_dma_chan_read(c, CCR);
 313         if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
 314                 uint32_t sysconfig;
 315                 unsigned i;
 316
 317                 sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG);
 318                 val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK;
 319                 val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
 320                 omap_dma_glbl_write(od, OCP_SYSCONFIG, val);
 321
 322                 val = omap_dma_chan_read(c, CCR);
 323                 val &= ~CCR_ENABLE;
 324                 omap_dma_chan_write(c, CCR, val);
 325
 326                 /* Wait for sDMA FIFO to drain */
 327                 for (i = 0; ; i++) {
 328                         val = omap_dma_chan_read(c, CCR);
 329                         if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)))
 330                                 break;
 331
 332                         if (i > 100)
 333                                 break;
 334
 335                         udelay(5);
 336                 }
 337
 338                 if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))
 339                         dev_err(c->vc.chan.device->dev,
 340                                 "DMA drain did not complete on lch %d\n",
 341                                 c->dma_ch);
 342
 343                 omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig);
 344         } else {
 345                 val &= ~CCR_ENABLE;
 346                 omap_dma_chan_write(c, CCR, val);
 347         }
 348
 349         mb();
 350
 351         if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
 352                 val = omap_dma_chan_read(c, CLNK_CTRL);
 353
 354                 if (dma_omap1())
 355                         val |= 1 << 14; /* set the STOP_LNK bit */
 356                 else
 357                         val &= ~CLNK_CTRL_ENABLE_LNK;
 358
 359                 omap_dma_chan_write(c, CLNK_CTRL, val);
 360         }
 361 }
 362
 363 static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
 364         unsigned idx)
 365 {
 366         struct omap_sg *sg = d->sg + idx;
 367         unsigned cxsa, cxei, cxfi;
 368
 369         if (d->dir == DMA_DEV_TO_MEM) {
 370                 cxsa = CDSA;
 371                 cxei = CDEI;
 372                 cxfi = CDFI;
 373         } else {
 374                 cxsa = CSSA;
 375                 cxei = CSEI;
 376                 cxfi = CSFI;
 377         }
 378
 379         omap_dma_chan_write(c, cxsa, sg->addr);
 380         omap_dma_chan_write(c, cxei, 0);
 381         omap_dma_chan_write(c, cxfi, 0);
 382         omap_dma_chan_write(c, CEN, sg->en);
 383         omap_dma_chan_write(c, CFN, sg->fn);
 384
 385         omap_dma_start(c, d);
 386 }
 387
 388 static void omap_dma_start_desc(struct omap_chan *c)
 389 {
 390         struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
 391         struct omap_desc *d;
 392         unsigned cxsa, cxei, cxfi;
 393
 394         if (!vd) {
 395                 c->desc = NULL;
 396                 return;
 397         }
 398
 399         list_del(&vd->node);
 400
 401         c->desc = d = to_omap_dma_desc(&vd->tx);
 402         c->sgidx = 0;
 403
 404         /*
 405          * This provides the necessary barrier to ensure data held in
 406          * DMA coherent memory is visible to the DMA engine prior to
 407          * the transfer starting.
 408          */
 409         mb();
 410
 411         omap_dma_chan_write(c, CCR, d->ccr);
 412         if (dma_omap1())
 413                 omap_dma_chan_write(c, CCR2, d->ccr >> 16);
 414
 415         if (d->dir == DMA_DEV_TO_MEM) {
 416                 cxsa = CSSA;
 417                 cxei = CSEI;
 418                 cxfi = CSFI;
 419         } else {
 420                 cxsa = CDSA;
 421                 cxei = CDEI;
 422                 cxfi = CDFI;
 423         }
 424
 425         omap_dma_chan_write(c, cxsa, d->dev_addr);
 426         omap_dma_chan_write(c, cxei, 0);
 427         omap_dma_chan_write(c, cxfi, d->fi);
 428         omap_dma_chan_write(c, CSDP, d->csdp);
 429         omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl);
 430
 431         omap_dma_start_sg(c, d, 0);
 432 }
 433
 434 static void omap_dma_callback(int ch, u16 status, void *data)
 435 {
 436         struct omap_chan *c = data;
 437         struct omap_desc *d;
 438         unsigned long flags;
 439
 440         spin_lock_irqsave(&c->vc.lock, flags);
 441         d = c->desc;
 442         if (d) {
 443                 if (!c->cyclic) {
 444                         if (++c->sgidx < d->sglen) {
 445                                 omap_dma_start_sg(c, d, c->sgidx);
 446                         } else {
 447                                 omap_dma_start_desc(c);
 448                                 vchan_cookie_complete(&d->vd);
 449                         }
 450                 } else {
 451                         vchan_cyclic_callback(&d->vd);
 452                 }
 453         }
 454         spin_unlock_irqrestore(&c->vc.lock, flags);
 455 }
 456
 457 /*
 458  * This callback schedules all pending channels.  We could be more
 459  * clever here by postponing allocation of the real DMA channels to
 460  * this point, and freeing them when our virtual channel becomes idle.
 461  *
 462  * We would then need to deal with 'all channels in-use'
 463  */
 464 static void omap_dma_sched(unsigned long data)
 465 {
 466         struct omap_dmadev *d = (struct omap_dmadev *)data;
 467         LIST_HEAD(head);
 468
 469         spin_lock_irq(&d->lock);
 470         list_splice_tail_init(&d->pending, &head);
 471         spin_unlock_irq(&d->lock);
 472
 473         while (!list_empty(&head)) {
 474                 struct omap_chan *c = list_first_entry(&head,
 475                         struct omap_chan, node);
 476
 477                 spin_lock_irq(&c->vc.lock);
 478                 list_del_init(&c->node);
 479                 omap_dma_start_desc(c);
 480                 spin_unlock_irq(&c->vc.lock);
 481         }
 482 }
 483
 484 static irqreturn_t omap_dma_irq(int irq, void *devid)
 485 {
 486         struct omap_dmadev *od = devid;
 487         unsigned status, channel;
 488
 489         spin_lock(&od->irq_lock);
 490
 491         status = omap_dma_glbl_read(od, IRQSTATUS_L1);
 492         status &= od->irq_enable_mask;
 493         if (status == 0) {
 494                 spin_unlock(&od->irq_lock);
 495                 return IRQ_NONE;
 496         }
 497
 498         while ((channel = ffs(status)) != 0) {
 499                 unsigned mask, csr;
 500                 struct omap_chan *c;
 501
 502                 channel -= 1;
 503                 mask = BIT(channel);
 504                 status &= ~mask;
 505
 506                 c = od->lch_map[channel];
 507                 if (c == NULL) {
 508                         /* This should never happen */
 509                         dev_err(od->ddev.dev, "invalid channel %u\n", channel);
 510                         continue;
 511                 }
 512
 513                 csr = omap_dma_get_csr(c);
 514                 omap_dma_glbl_write(od, IRQSTATUS_L1, mask);
 515
 516                 omap_dma_callback(channel, csr, c);
 517         }
 518
 519         spin_unlock(&od->irq_lock);
 520
 521         return IRQ_HANDLED;
 522 }
 523
 524 static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
 525 {
 526         struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 527         struct omap_chan *c = to_omap_dma_chan(chan);
 528         int ret;
 529
 530         if (od->legacy) {
 531                 ret = omap_request_dma(c->dma_sig, "DMA engine",
 532                                        omap_dma_callback, c, &c->dma_ch);
 533         } else {
 534                 ret = omap_request_dma(c->dma_sig, "DMA engine", NULL, NULL,
 535                                        &c->dma_ch);
 536         }
 537
 538         dev_dbg(od->ddev.dev, "allocating channel %u for %u\n",
 539                 c->dma_ch, c->dma_sig);
 540
 541         if (ret >= 0) {
 542                 omap_dma_assign(od, c, c->dma_ch);
 543
 544                 if (!od->legacy) {
 545                         unsigned val;
 546
 547                         spin_lock_irq(&od->irq_lock);
 548                         val = BIT(c->dma_ch);
 549                         omap_dma_glbl_write(od, IRQSTATUS_L1, val);
 550                         od->irq_enable_mask |= val;
 551                         omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
 552
 553                         val = omap_dma_glbl_read(od, IRQENABLE_L0);
 554                         val &= ~BIT(c->dma_ch);
 555                         omap_dma_glbl_write(od, IRQENABLE_L0, val);
 556                         spin_unlock_irq(&od->irq_lock);
 557                 }
 558         }
 559
 560         if (dma_omap1()) {
 561                 if (__dma_omap16xx(od->plat->dma_attr)) {
 562                         c->ccr = CCR_OMAP31_DISABLE;
 563                         /* Duplicate what plat-omap/dma.c does */
 564                         c->ccr |= c->dma_ch + 1;
 565                 } else {
 566                         c->ccr = c->dma_sig & 0x1f;
 567                 }
 568         } else {
 569                 c->ccr = c->dma_sig & 0x1f;
 570                 c->ccr |= (c->dma_sig & ~0x1f) << 14;
 571         }
 572         if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
 573                 c->ccr |= CCR_BUFFERING_DISABLE;
 574
 575         return ret;
 576 }
 577
 578 static void omap_dma_free_chan_resources(struct dma_chan *chan)
 579 {
 580         struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 581         struct omap_chan *c = to_omap_dma_chan(chan);
 582
 583         if (!od->legacy) {
 584                 spin_lock_irq(&od->irq_lock);
 585                 od->irq_enable_mask &= ~BIT(c->dma_ch);
 586                 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
 587                 spin_unlock_irq(&od->irq_lock);
 588         }
 589
 590         c->channel_base = NULL;
 591         od->lch_map[c->dma_ch] = NULL;
 592         vchan_free_chan_resources(&c->vc);
 593         omap_free_dma(c->dma_ch);
 594
 595         dev_dbg(od->ddev.dev, "freeing channel for %u\n", c->dma_sig);
 596 }
 597
 598 static size_t omap_dma_sg_size(struct omap_sg *sg)
 599 {
 600         return sg->en * sg->fn;
 601 }
 602
 603 static size_t omap_dma_desc_size(struct omap_desc *d)
 604 {
 605         unsigned i;
 606         size_t size;
 607
 608         for (size = i = 0; i < d->sglen; i++)
 609                 size += omap_dma_sg_size(&d->sg[i]);
 610
 611         return size * es_bytes[d->es];
 612 }
 613
 614 static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr)
 615 {
 616         unsigned i;
 617         size_t size, es_size = es_bytes[d->es];
 618
 619         for (size = i = 0; i < d->sglen; i++) {
 620                 size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size;
 621
 622                 if (size)
 623                         size += this_size;
 624                 else if (addr >= d->sg[i].addr &&
 625                          addr < d->sg[i].addr + this_size)
 626                         size += d->sg[i].addr + this_size - addr;
 627         }
 628         return size;
 629 }
 630
 631 /*
 632  * OMAP 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 633  * read before the DMA controller finished disabling the channel.
 634  */
 635 static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg)
 636 {
 637         struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
 638         uint32_t val;
 639
 640         val = omap_dma_chan_read(c, reg);
 641         if (val == 0 && od->plat->errata & DMA_ERRATA_3_3)
 642                 val = omap_dma_chan_read(c, reg);
 643
 644         return val;
 645 }
 646
 647 static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
 648 {
 649         struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
 650         dma_addr_t addr, cdac;
 651
 652         if (__dma_omap15xx(od->plat->dma_attr)) {
 653                 addr = omap_dma_chan_read(c, CPC);
 654         } else {
 655                 addr = omap_dma_chan_read_3_3(c, CSAC);
 656                 cdac = omap_dma_chan_read_3_3(c, CDAC);
 657
 658                 /*
 659                  * CDAC == 0 indicates that the DMA transfer on the channel has
 660                  * not been started (no data has been transferred so far).
 661                  * Return the programmed source start address in this case.
 662                  */
 663                 if (cdac == 0)
 664                         addr = omap_dma_chan_read(c, CSSA);
 665         }
 666
 667         if (dma_omap1())
 668                 addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000;
 669
 670         return addr;
 671 }
 672
 673 static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c)
 674 {
 675         struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
 676         dma_addr_t addr;
 677
 678         if (__dma_omap15xx(od->plat->dma_attr)) {
 679                 addr = omap_dma_chan_read(c, CPC);
 680         } else {
 681                 addr = omap_dma_chan_read_3_3(c, CDAC);
 682
 683                 /*
 684                  * CDAC == 0 indicates that the DMA transfer on the channel
 685                  * has not been started (no data has been transferred so
 686                  * far).  Return the programmed destination start address in
 687                  * this case.
 688                  */
 689                 if (addr == 0)
 690                         addr = omap_dma_chan_read(c, CDSA);
 691         }
 692
 693         if (dma_omap1())
 694                 addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000;
 695
 696         return addr;
 697 }
 698
 699 static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
 700         dma_cookie_t cookie, struct dma_tx_state *txstate)
 701 {
 702         struct omap_chan *c = to_omap_dma_chan(chan);
 703         struct virt_dma_desc *vd;
 704         enum dma_status ret;
 705         unsigned long flags;
 706
 707         ret = dma_cookie_status(chan, cookie, txstate);
 708         if (ret == DMA_COMPLETE || !txstate)
 709                 return ret;
 710
 711         spin_lock_irqsave(&c->vc.lock, flags);
 712         vd = vchan_find_desc(&c->vc, cookie);
 713         if (vd) {
 714                 txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx));
 715         } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
 716                 struct omap_desc *d = c->desc;
 717                 dma_addr_t pos;
 718
 719                 if (d->dir == DMA_MEM_TO_DEV)
 720                         pos = omap_dma_get_src_pos(c);
 721                 else if (d->dir == DMA_DEV_TO_MEM)
 722                         pos = omap_dma_get_dst_pos(c);
 723                 else
 724                         pos = 0;
 725
 726                 txstate->residue = omap_dma_desc_size_pos(d, pos);
 727         } else {
 728                 txstate->residue = 0;
 729         }
 730         spin_unlock_irqrestore(&c->vc.lock, flags);
 731
 732         return ret;
 733 }
 734
 735 static void omap_dma_issue_pending(struct dma_chan *chan)
 736 {
 737         struct omap_chan *c = to_omap_dma_chan(chan);
 738         unsigned long flags;
 739
 740         spin_lock_irqsave(&c->vc.lock, flags);
 741         if (vchan_issue_pending(&c->vc) && !c->desc) {
 742                 /*
 743                  * c->cyclic is used only by audio and in this case the DMA need
 744                  * to be started without delay.
 745                  */
 746                 if (!c->cyclic) {
 747                         struct omap_dmadev *d = to_omap_dma_dev(chan->device);
 748                         spin_lock(&d->lock);
 749                         if (list_empty(&c->node))
 750                                 list_add_tail(&c->node, &d->pending);
 751                         spin_unlock(&d->lock);
 752                         tasklet_schedule(&d->task);
 753                 } else {
 754                         omap_dma_start_desc(c);
 755                 }
 756         }
 757         spin_unlock_irqrestore(&c->vc.lock, flags);
 758 }
 759
 760 static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 761         struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen,
 762         enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
 763 {
 764         struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 765         struct omap_chan *c = to_omap_dma_chan(chan);
 766         enum dma_slave_buswidth dev_width;
 767         struct scatterlist *sgent;
 768         struct omap_desc *d;
 769         dma_addr_t dev_addr;
 770         unsigned i, j = 0, es, en, frame_bytes;
 771         u32 burst;
 772
 773         if (dir == DMA_DEV_TO_MEM) {
 774                 dev_addr = c->cfg.src_addr;
 775                 dev_width = c->cfg.src_addr_width;
 776                 burst = c->cfg.src_maxburst;
 777         } else if (dir == DMA_MEM_TO_DEV) {
 778                 dev_addr = c->cfg.dst_addr;
 779                 dev_width = c->cfg.dst_addr_width;
 780                 burst = c->cfg.dst_maxburst;
 781         } else {
 782                 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 783                 return NULL;
 784         }
 785
 786         /* Bus width translates to the element size (ES) */
 787         switch (dev_width) {
 788         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 789                 es = CSDP_DATA_TYPE_8;
 790                 break;
 791         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 792                 es = CSDP_DATA_TYPE_16;
 793                 break;
 794         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 795                 es = CSDP_DATA_TYPE_32;
 796                 break;
 797         default: /* not reached */
 798                 return NULL;
 799         }
 800
 801         /* Now allocate and setup the descriptor. */
 802         d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC);
 803         if (!d)
 804                 return NULL;
 805
 806         d->dir = dir;
 807         d->dev_addr = dev_addr;
 808         d->es = es;
 809
 810         d->ccr = c->ccr | CCR_SYNC_FRAME;
 811         if (dir == DMA_DEV_TO_MEM)
 812                 d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
 813         else
 814                 d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
 815
 816         d->cicr = CICR_DROP_IE | CICR_BLOCK_IE;
 817         d->csdp = es;
 818
 819         if (dma_omap1()) {
 820                 d->cicr |= CICR_TOUT_IE;
 821
 822                 if (dir == DMA_DEV_TO_MEM)
 823                         d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB;
 824                 else
 825                         d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF;
 826         } else {
 827                 if (dir == DMA_DEV_TO_MEM)
 828                         d->ccr |= CCR_TRIGGER_SRC;
 829
 830                 d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
 831         }
 832         if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
 833                 d->clnk_ctrl = c->dma_ch;
 834
 835         /*
 836          * Build our scatterlist entries: each contains the address,
 837          * the number of elements (EN) in each frame, and the number of
 838          * frames (FN).  Number of bytes for this entry = ES * EN * FN.
 839          *
 840          * Burst size translates to number of elements with frame sync.
 841          * Note: DMA engine defines burst to be the number of dev-width
 842          * transfers.
 843          */
 844         en = burst;
 845         frame_bytes = es_bytes[es] * en;
 846         for_each_sg(sgl, sgent, sglen, i) {
 847                 d->sg[j].addr = sg_dma_address(sgent);
 848                 d->sg[j].en = en;
 849                 d->sg[j].fn = sg_dma_len(sgent) / frame_bytes;
 850                 j++;
 851         }
 852
 853         d->sglen = j;
 854
 855         return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
 856 }
 857
 858 static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 859         struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 860         size_t period_len, enum dma_transfer_direction dir, unsigned long flags)
 861 {
 862         struct omap_dmadev *od = to_omap_dma_dev(chan->device);
 863         struct omap_chan *c = to_omap_dma_chan(chan);
 864         enum dma_slave_buswidth dev_width;
 865         struct omap_desc *d;
 866         dma_addr_t dev_addr;
 867         unsigned es;
 868         u32 burst;
 869
 870         if (dir == DMA_DEV_TO_MEM) {
 871                 dev_addr = c->cfg.src_addr;
 872                 dev_width = c->cfg.src_addr_width;
 873                 burst = c->cfg.src_maxburst;
 874         } else if (dir == DMA_MEM_TO_DEV) {
 875                 dev_addr = c->cfg.dst_addr;
 876                 dev_width = c->cfg.dst_addr_width;
 877                 burst = c->cfg.dst_maxburst;
 878         } else {
 879                 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 880                 return NULL;
 881         }
 882
 883         /* Bus width translates to the element size (ES) */
 884         switch (dev_width) {
 885         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 886                 es = CSDP_DATA_TYPE_8;
 887                 break;
 888         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 889                 es = CSDP_DATA_TYPE_16;
 890                 break;
 891         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 892                 es = CSDP_DATA_TYPE_32;
 893                 break;
 894         default: /* not reached */
 895                 return NULL;
 896         }
 897
 898         /* Now allocate and setup the descriptor. */
 899         d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC);
 900         if (!d)
 901                 return NULL;
 902
 903         d->dir = dir;
 904         d->dev_addr = dev_addr;
 905         d->fi = burst;
 906         d->es = es;
 907         d->sg[0].addr = buf_addr;
 908         d->sg[0].en = period_len / es_bytes[es];
 909         d->sg[0].fn = buf_len / period_len;
 910         d->sglen = 1;
 911
 912         d->ccr = c->ccr;
 913         if (dir == DMA_DEV_TO_MEM)
 914                 d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
 915         else
 916                 d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
 917
 918         d->cicr = CICR_DROP_IE;
 919         if (flags & DMA_PREP_INTERRUPT)
 920                 d->cicr |= CICR_FRAME_IE;
 921
 922         d->csdp = es;
 923
 924         if (dma_omap1()) {
 925                 d->cicr |= CICR_TOUT_IE;
 926
 927                 if (dir == DMA_DEV_TO_MEM)
 928                         d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI;
 929                 else
 930                         d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF;
 931         } else {
 932                 if (burst)
 933                         d->ccr |= CCR_SYNC_PACKET;
 934                 else
 935                         d->ccr |= CCR_SYNC_ELEMENT;
 936
 937                 if (dir == DMA_DEV_TO_MEM)
 938                         d->ccr |= CCR_TRIGGER_SRC;
 939
 940                 d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
 941
 942                 d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
 943         }
 944
 945         if (__dma_omap15xx(od->plat->dma_attr))
 946                 d->ccr |= CCR_AUTO_INIT | CCR_REPEAT;
 947         else
 948                 d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK;
 949
 950         c->cyclic = true;
 951
 952         return vchan_tx_prep(&c->vc, &d->vd, flags);
 953 }
 954
 955 static int omap_dma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)
 956 {
 957         struct omap_chan *c = to_omap_dma_chan(chan);
 958
 959         if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
 960             cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
 961                 return -EINVAL;
 962
 963         memcpy(&c->cfg, cfg, sizeof(c->cfg));
 964
 965         return 0;
 966 }
 967
 968 static int omap_dma_terminate_all(struct dma_chan *chan)
 969 {
 970         struct omap_chan *c = to_omap_dma_chan(chan);
 971         struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device);
 972         unsigned long flags;
 973         LIST_HEAD(head);
 974
 975         spin_lock_irqsave(&c->vc.lock, flags);
 976
 977         /* Prevent this channel being scheduled */
 978         spin_lock(&d->lock);
 979         list_del_init(&c->node);
 980         spin_unlock(&d->lock);
 981
 982         /*
 983          * Stop DMA activity: we assume the callback will not be called
 984          * after omap_dma_stop() returns (even if it does, it will see
 985          * c->desc is NULL and exit.)
 986          */
 987         if (c->desc) {
 988                 omap_dma_desc_free(&c->desc->vd);
 989                 c->desc = NULL;
 990                 /* Avoid stopping the dma twice */
 991                 if (!c->paused)
 992                         omap_dma_stop(c);
 993         }
 994
 995         if (c->cyclic) {
 996                 c->cyclic = false;
 997                 c->paused = false;
 998         }
 999
1000         vchan_get_all_descriptors(&c->vc, &head);
1001         spin_unlock_irqrestore(&c->vc.lock, flags);
1002         vchan_dma_desc_free_list(&c->vc, &head);
1003
1004         return 0;
1005 }
1006
1007 static int omap_dma_pause(struct dma_chan *chan)
1008 {
1009         struct omap_chan *c = to_omap_dma_chan(chan);
1010
1011         /* Pause/Resume only allowed with cyclic mode */
1012         if (!c->cyclic)
1013                 return -EINVAL;
1014
1015         if (!c->paused) {
1016                 omap_dma_stop(c);
1017                 c->paused = true;
1018         }
1019
1020         return 0;
1021 }
1022
1023 static int omap_dma_resume(struct dma_chan *chan)
1024 {
1025         struct omap_chan *c = to_omap_dma_chan(chan);
1026
1027         /* Pause/Resume only allowed with cyclic mode */
1028         if (!c->cyclic)
1029                 return -EINVAL;
1030
1031         if (c->paused) {
1032                 mb();
1033
1034                 /* Restore channel link register */
1035                 omap_dma_chan_write(c, CLNK_CTRL, c->desc->clnk_ctrl);
1036
1037                 omap_dma_start(c, c->desc);
1038                 c->paused = false;
1039         }
1040
1041         return 0;
1042 }
1043
1044 static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
1045 {
1046         struct omap_chan *c;
1047
1048         c = kzalloc(sizeof(*c), GFP_KERNEL);
1049         if (!c)
1050                 return -ENOMEM;
1051
1052         c->reg_map = od->reg_map;
1053         c->dma_sig = dma_sig;
1054         c->vc.desc_free = omap_dma_desc_free;
1055         vchan_init(&c->vc, &od->ddev);
1056         INIT_LIST_HEAD(&c->node);
1057
1058         return 0;
1059 }
1060
1061 static void omap_dma_free(struct omap_dmadev *od)
1062 {
1063         tasklet_kill(&od->task);
1064         while (!list_empty(&od->ddev.channels)) {
1065                 struct omap_chan *c = list_first_entry(&od->ddev.channels,
1066                         struct omap_chan, vc.chan.device_node);
1067
1068                 list_del(&c->vc.chan.device_node);
1069                 tasklet_kill(&c->vc.task);
1070                 kfree(c);
1071         }
1072 }
1073
1074 #define OMAP_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1075                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1076                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1077
1078 static int omap_dma_probe(struct platform_device *pdev)
1079 {
1080         struct omap_dmadev *od;
1081         struct resource *res;
1082         int rc, i, irq;
1083
1084         od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
1085         if (!od)
1086                 return -ENOMEM;
1087
1088         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1089         od->base = devm_ioremap_resource(&pdev->dev, res);
1090         if (IS_ERR(od->base))
1091                 return PTR_ERR(od->base);
1092
1093         od->plat = omap_get_plat_info();
1094         if (!od->plat)
1095                 return -EPROBE_DEFER;
1096
1097         od->reg_map = od->plat->reg_map;
1098
1099         dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
1100         dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
1101         od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
1102         od->ddev.device_free_chan_resources = omap_dma_free_chan_resources;
1103         od->ddev.device_tx_status = omap_dma_tx_status;
1104         od->ddev.device_issue_pending = omap_dma_issue_pending;
1105         od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg;
1106         od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic;
1107         od->ddev.device_config = omap_dma_slave_config;
1108         od->ddev.device_pause = omap_dma_pause;
1109         od->ddev.device_resume = omap_dma_resume;
1110         od->ddev.device_terminate_all = omap_dma_terminate_all;
1111         od->ddev.src_addr_widths = OMAP_DMA_BUSWIDTHS;
1112         od->ddev.dst_addr_widths = OMAP_DMA_BUSWIDTHS;
1113         od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1114         od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1115         od->ddev.dev = &pdev->dev;
1116         INIT_LIST_HEAD(&od->ddev.channels);
1117         INIT_LIST_HEAD(&od->pending);
1118         spin_lock_init(&od->lock);
1119         spin_lock_init(&od->irq_lock);
1120
1121         tasklet_init(&od->task, omap_dma_sched, (unsigned long)od);
1122
1123         od->dma_requests = OMAP_SDMA_REQUESTS;
1124         if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node,
1125                                                       "dma-requests",
1126                                                       &od->dma_requests)) {
1127                 dev_info(&pdev->dev,
1128                          "Missing dma-requests property, using %u.\n",
1129                          OMAP_SDMA_REQUESTS);
1130         }
1131
1132         for (i = 0; i < od->dma_requests; i++) {
1133                 rc = omap_dma_chan_init(od, i);
1134                 if (rc) {
1135                         omap_dma_free(od);
1136                         return rc;
1137                 }
1138         }
1139
1140         irq = platform_get_irq(pdev, 1);
1141         if (irq <= 0) {
1142                 dev_info(&pdev->dev, "failed to get L1 IRQ: %d\n", irq);
1143                 od->legacy = true;
1144         } else {
1145                 /* Disable all interrupts */
1146                 od->irq_enable_mask = 0;
1147                 omap_dma_glbl_write(od, IRQENABLE_L1, 0);
1148
1149                 rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq,
1150                                       IRQF_SHARED, "omap-dma-engine", od);
1151                 if (rc)
1152                         return rc;
1153         }
1154
1155         rc = dma_async_device_register(&od->ddev);
1156         if (rc) {
1157                 pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
1158                         rc);
1159                 omap_dma_free(od);
1160                 return rc;
1161         }
1162
1163         platform_set_drvdata(pdev, od);
1164
1165         if (pdev->dev.of_node) {
1166                 omap_dma_info.dma_cap = od->ddev.cap_mask;
1167
1168                 /* Device-tree DMA controller registration */
1169                 rc = of_dma_controller_register(pdev->dev.of_node,
1170                                 of_dma_simple_xlate, &omap_dma_info);
1171                 if (rc) {
1172                         pr_warn("OMAP-DMA: failed to register DMA controller\n");
1173                         dma_async_device_unregister(&od->ddev);
1174                         omap_dma_free(od);
1175                 }
1176         }
1177
1178         dev_info(&pdev->dev, "OMAP DMA engine driver\n");
1179
1180         return rc;
1181 }
1182
1183 static int omap_dma_remove(struct platform_device *pdev)
1184 {
1185         struct omap_dmadev *od = platform_get_drvdata(pdev);
1186
1187         if (pdev->dev.of_node)
1188                 of_dma_controller_free(pdev->dev.of_node);
1189
1190         dma_async_device_unregister(&od->ddev);
1191
1192         if (!od->legacy) {
1193                 /* Disable all interrupts */
1194                 omap_dma_glbl_write(od, IRQENABLE_L0, 0);
1195         }
1196
1197         omap_dma_free(od);
1198
1199         return 0;
1200 }
1201
1202 static const struct of_device_id omap_dma_match[] = {
1203         { .compatible = "ti,omap2420-sdma", },
1204         { .compatible = "ti,omap2430-sdma", },
1205         { .compatible = "ti,omap3430-sdma", },
1206         { .compatible = "ti,omap3630-sdma", },
1207         { .compatible = "ti,omap4430-sdma", },
1208         {},
1209 };
1210 MODULE_DEVICE_TABLE(of, omap_dma_match);
1211
1212 static struct platform_driver omap_dma_driver = {
1213         .probe  = omap_dma_probe,
1214         .remove = omap_dma_remove,
1215         .driver = {
1216                 .name = "omap-dma-engine",
1217                 .of_match_table = of_match_ptr(omap_dma_match),
1218         },
1219 };
1220
1221 bool omap_dma_filter_fn(struct dma_chan *chan, void *param)
1222 {
1223         if (chan->device->dev->driver == &omap_dma_driver.driver) {
1224                 struct omap_chan *c = to_omap_dma_chan(chan);
1225                 unsigned req = *(unsigned *)param;
1226
1227                 return req == c->dma_sig;
1228         }
1229         return false;
1230 }
1231 EXPORT_SYMBOL_GPL(omap_dma_filter_fn);
1232
1233 static int omap_dma_init(void)
1234 {
1235         return platform_driver_register(&omap_dma_driver);
1236 }
1237 subsys_initcall(omap_dma_init);
1238
1239 static void __exit omap_dma_exit(void)
1240 {
1241         platform_driver_unregister(&omap_dma_driver);
1242 }
1243 module_exit(omap_dma_exit);
1244
1245 MODULE_AUTHOR("Russell King");
1246 MODULE_LICENSE("GPL");