drivers/clk/h8300/clk-h8s2678.c

   1 /*
   2  * H8S2678 clock driver
   3  *
   4  * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/clkdev.h>
   9 #include <linux/clk-provider.h>
  10 #include <linux/err.h>
  11 #include <linux/device.h>
  12 #include <linux/of_address.h>
  13
  14 static DEFINE_SPINLOCK(clklock);
  15
  16 #define MAX_FREQ 33333333
  17 #define MIN_FREQ  8000000
  18
  19 struct pll_clock {
  20         struct clk_hw hw;
  21         void __iomem *sckcr;
  22         void __iomem *pllcr;
  23 };
  24
  25 #define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
  26
  27 static unsigned long pll_recalc_rate(struct clk_hw *hw,
  28                 unsigned long parent_rate)
  29 {
  30         struct pll_clock *pll_clock = to_pll_clock(hw);
  31         int mul = 1 << (ctrl_inb((unsigned long)pll_clock->pllcr) & 3);
  32
  33         return parent_rate * mul;
  34 }
  35
  36 static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
  37                                 unsigned long *prate)
  38 {
  39         int i, m = -1;
  40         long offset[3];
  41
  42         if (rate > MAX_FREQ)
  43                 rate = MAX_FREQ;
  44         if (rate < MIN_FREQ)
  45                 rate = MIN_FREQ;
  46
  47         for (i = 0; i < 3; i++)
  48                 offset[i] = abs(rate - (*prate * (1 << i)));
  49         for (i = 0; i < 3; i++)
  50                 if (m < 0)
  51                         m = i;
  52                 else
  53                         m = (offset[i] < offset[m])?i:m;
  54
  55         return *prate * (1 << m);
  56 }
  57
  58 static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
  59                         unsigned long parent_rate)
  60 {
  61         int pll;
  62         unsigned char val;
  63         unsigned long flags;
  64         struct pll_clock *pll_clock = to_pll_clock(hw);
  65
  66         pll = ((rate / parent_rate) / 2) & 0x03;
  67         spin_lock_irqsave(&clklock, flags);
  68         val = ctrl_inb((unsigned long)pll_clock->sckcr);
  69         val |= 0x08;
  70         ctrl_outb(val, (unsigned long)pll_clock->sckcr);
  71         val = ctrl_inb((unsigned long)pll_clock->pllcr);
  72         val &= ~0x03;
  73         val |= pll;
  74         ctrl_outb(val, (unsigned long)pll_clock->pllcr);
  75         spin_unlock_irqrestore(&clklock, flags);
  76         return 0;
  77 }
  78
  79 static const struct clk_ops pll_ops = {
  80         .recalc_rate = pll_recalc_rate,
  81         .round_rate = pll_round_rate,
  82         .set_rate = pll_set_rate,
  83 };
  84
  85 static void __init h8s2678_pll_clk_setup(struct device_node *node)
  86 {
  87         unsigned int num_parents;
  88         struct clk *clk;
  89         const char *clk_name = node->name;
  90         const char *parent_name;
  91         struct pll_clock *pll_clock;
  92         struct clk_init_data init;
  93
  94         num_parents = of_clk_get_parent_count(node);
  95         if (num_parents < 1) {
  96                 pr_err("%s: no parent found", clk_name);
  97                 return;
  98         }
  99
 100
 101         pll_clock = kzalloc(sizeof(struct pll_clock), GFP_KERNEL);
 102         if (!pll_clock) {
 103                 pr_err("%s: failed to alloc memory", clk_name);
 104                 return;
 105         }
 106
 107         pll_clock->sckcr = of_iomap(node, 0);
 108         if (pll_clock->sckcr == NULL) {
 109                 pr_err("%s: failed to map divide register", clk_name);
 110                 goto free_clock;
 111         }
 112
 113         pll_clock->pllcr = of_iomap(node, 1);
 114         if (pll_clock->pllcr == NULL) {
 115                 pr_err("%s: failed to map multiply register", clk_name);
 116                 goto unmap_sckcr;
 117         }
 118
 119         parent_name = of_clk_get_parent_name(node, 0);
 120         init.name = clk_name;
 121         init.ops = &pll_ops;
 122         init.flags = CLK_IS_BASIC;
 123         init.parent_names = &parent_name;
 124         init.num_parents = 1;
 125         pll_clock->hw.init = &init;
 126
 127         clk = clk_register(NULL, &pll_clock->hw);
 128         if (IS_ERR(clk)) {
 129                 pr_err("%s: failed to register %s div clock (%ld)\n",
 130                        __func__, clk_name, PTR_ERR(clk));
 131                 goto unmap_pllcr;
 132         }
 133
 134         of_clk_add_provider(node, of_clk_src_simple_get, clk);
 135         return;
 136
 137 unmap_pllcr:
 138         iounmap(pll_clock->pllcr);
 139 unmap_sckcr:
 140         iounmap(pll_clock->sckcr);
 141 free_clock:
 142         kfree(pll_clock);
 143 }
 144
 145 CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock",
 146                h8s2678_pll_clk_setup);