2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #include <linux/msi.h>
34 #include <linux/htirq.h>
36 #include <acpi/acpi_bus.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
50 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
52 #define __apicdebuginit __init
54 int sis_apic_bug; /* not actually supported, dummy for compile */
56 static int no_timer_check;
58 static int disable_timer_pin_1 __initdata;
60 int timer_over_8254 __initdata = 1;
62 /* Where if anywhere is the i8259 connect in external int mode */
63 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
65 static DEFINE_SPINLOCK(ioapic_lock);
66 DEFINE_SPINLOCK(vector_lock);
69 * # of IRQ routing registers
71 int nr_ioapic_registers[MAX_IO_APICS];
74 * Rough estimation of how many shared IRQs there are, can
77 #define MAX_PLUS_SHARED_IRQS NR_IRQS
78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
81 * This is performance-critical, we want to do it O(1)
83 * the indexing order of this array favors 1:1 mappings
84 * between pins and IRQs.
87 static struct irq_pin_list {
88 short apic, pin, next;
89 } irq_2_pin[PIN_MAP_SIZE];
93 unsigned int unused[3];
97 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
99 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
100 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
103 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
105 struct io_apic __iomem *io_apic = io_apic_base(apic);
106 writel(reg, &io_apic->index);
107 return readl(&io_apic->data);
110 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
112 struct io_apic __iomem *io_apic = io_apic_base(apic);
113 writel(reg, &io_apic->index);
114 writel(value, &io_apic->data);
118 * Re-write a value: to be used for read-modify-write
119 * cycles where the read already set up the index register.
121 static inline void io_apic_modify(unsigned int apic, unsigned int value)
123 struct io_apic __iomem *io_apic = io_apic_base(apic);
124 writel(value, &io_apic->data);
128 * Synchronize the IO-APIC and the CPU by doing
129 * a dummy read from the IO-APIC
131 static inline void io_apic_sync(unsigned int apic)
133 struct io_apic __iomem *io_apic = io_apic_base(apic);
134 readl(&io_apic->data);
137 #define __DO_ACTION(R, ACTION, FINAL) \
141 struct irq_pin_list *entry = irq_2_pin + irq; \
143 BUG_ON(irq >= NR_IRQS); \
149 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
151 io_apic_modify(entry->apic, reg); \
155 entry = irq_2_pin + entry->next; \
160 struct { u32 w1, w2; };
161 struct IO_APIC_route_entry entry;
164 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
166 union entry_union eu;
168 spin_lock_irqsave(&ioapic_lock, flags);
169 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
170 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
171 spin_unlock_irqrestore(&ioapic_lock, flags);
176 * When we write a new IO APIC routing entry, we need to write the high
177 * word first! If the mask bit in the low word is clear, we will enable
178 * the interrupt, and we need to make sure the entry is fully populated
179 * before that happens.
182 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
184 union entry_union eu;
186 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
187 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
190 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
193 spin_lock_irqsave(&ioapic_lock, flags);
194 __ioapic_write_entry(apic, pin, e);
195 spin_unlock_irqrestore(&ioapic_lock, flags);
199 * When we mask an IO APIC routing entry, we need to write the low
200 * word first, in order to set the mask bit before we change the
203 static void ioapic_mask_entry(int apic, int pin)
206 union entry_union eu = { .entry.mask = 1 };
208 spin_lock_irqsave(&ioapic_lock, flags);
209 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
210 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
211 spin_unlock_irqrestore(&ioapic_lock, flags);
215 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
218 struct irq_pin_list *entry = irq_2_pin + irq;
220 BUG_ON(irq >= NR_IRQS);
227 io_apic_write(apic, 0x11 + pin*2, dest);
228 reg = io_apic_read(apic, 0x10 + pin*2);
231 io_apic_modify(apic, reg);
234 entry = irq_2_pin + entry->next;
238 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
245 cpus_and(tmp, mask, cpu_online_map);
249 vector = assign_irq_vector(irq, mask, &tmp);
253 dest = cpu_mask_to_apicid(tmp);
256 * Only the high 8 bits are valid.
258 dest = SET_APIC_LOGICAL_ID(dest);
260 spin_lock_irqsave(&ioapic_lock, flags);
261 __target_IO_APIC_irq(irq, dest, vector);
262 irq_desc[irq].affinity = mask;
263 spin_unlock_irqrestore(&ioapic_lock, flags);
268 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
269 * shared ISA-space IRQs, so we have to support them. We are super
270 * fast in the common case, and fast for shared ISA-space IRQs.
272 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
274 static int first_free_entry = NR_IRQS;
275 struct irq_pin_list *entry = irq_2_pin + irq;
277 BUG_ON(irq >= NR_IRQS);
279 entry = irq_2_pin + entry->next;
281 if (entry->pin != -1) {
282 entry->next = first_free_entry;
283 entry = irq_2_pin + entry->next;
284 if (++first_free_entry >= PIN_MAP_SIZE)
285 panic("io_apic.c: ran out of irq_2_pin entries!");
292 #define DO_ACTION(name,R,ACTION, FINAL) \
294 static void name##_IO_APIC_irq (unsigned int irq) \
295 __DO_ACTION(R, ACTION, FINAL)
297 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
299 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
302 static void mask_IO_APIC_irq (unsigned int irq)
306 spin_lock_irqsave(&ioapic_lock, flags);
307 __mask_IO_APIC_irq(irq);
308 spin_unlock_irqrestore(&ioapic_lock, flags);
311 static void unmask_IO_APIC_irq (unsigned int irq)
315 spin_lock_irqsave(&ioapic_lock, flags);
316 __unmask_IO_APIC_irq(irq);
317 spin_unlock_irqrestore(&ioapic_lock, flags);
320 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
322 struct IO_APIC_route_entry entry;
324 /* Check delivery_mode to be sure we're not clearing an SMI pin */
325 entry = ioapic_read_entry(apic, pin);
326 if (entry.delivery_mode == dest_SMI)
329 * Disable it in the IO-APIC irq-routing table:
331 ioapic_mask_entry(apic, pin);
334 static void clear_IO_APIC (void)
338 for (apic = 0; apic < nr_ioapics; apic++)
339 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
340 clear_IO_APIC_pin(apic, pin);
343 int skip_ioapic_setup;
346 /* dummy parsing: see setup.c */
348 static int __init disable_ioapic_setup(char *str)
350 skip_ioapic_setup = 1;
353 early_param("noapic", disable_ioapic_setup);
355 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
356 static int __init disable_timer_pin_setup(char *arg)
358 disable_timer_pin_1 = 1;
361 __setup("disable_timer_pin_1", disable_timer_pin_setup);
363 static int __init setup_disable_8254_timer(char *s)
365 timer_over_8254 = -1;
368 static int __init setup_enable_8254_timer(char *s)
374 __setup("disable_8254_timer", setup_disable_8254_timer);
375 __setup("enable_8254_timer", setup_enable_8254_timer);
379 * Find the IRQ entry number of a certain pin.
381 static int find_irq_entry(int apic, int pin, int type)
385 for (i = 0; i < mp_irq_entries; i++)
386 if (mp_irqs[i].mpc_irqtype == type &&
387 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
388 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
389 mp_irqs[i].mpc_dstirq == pin)
396 * Find the pin to which IRQ[irq] (ISA) is connected
398 static int __init find_isa_irq_pin(int irq, int type)
402 for (i = 0; i < mp_irq_entries; i++) {
403 int lbus = mp_irqs[i].mpc_srcbus;
405 if (test_bit(lbus, mp_bus_not_pci) &&
406 (mp_irqs[i].mpc_irqtype == type) &&
407 (mp_irqs[i].mpc_srcbusirq == irq))
409 return mp_irqs[i].mpc_dstirq;
414 static int __init find_isa_irq_apic(int irq, int type)
418 for (i = 0; i < mp_irq_entries; i++) {
419 int lbus = mp_irqs[i].mpc_srcbus;
421 if (test_bit(lbus, mp_bus_not_pci) &&
422 (mp_irqs[i].mpc_irqtype == type) &&
423 (mp_irqs[i].mpc_srcbusirq == irq))
426 if (i < mp_irq_entries) {
428 for(apic = 0; apic < nr_ioapics; apic++) {
429 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
438 * Find a specific PCI IRQ entry.
439 * Not an __init, possibly needed by modules
441 static int pin_2_irq(int idx, int apic, int pin);
443 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
445 int apic, i, best_guess = -1;
447 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
449 if (mp_bus_id_to_pci_bus[bus] == -1) {
450 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
453 for (i = 0; i < mp_irq_entries; i++) {
454 int lbus = mp_irqs[i].mpc_srcbus;
456 for (apic = 0; apic < nr_ioapics; apic++)
457 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
458 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
461 if (!test_bit(lbus, mp_bus_not_pci) &&
462 !mp_irqs[i].mpc_irqtype &&
464 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
465 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
467 if (!(apic || IO_APIC_IRQ(irq)))
470 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
473 * Use the first all-but-pin matching entry as a
474 * best-guess fuzzy result for broken mptables.
480 BUG_ON(best_guess >= NR_IRQS);
484 /* ISA interrupts are always polarity zero edge triggered,
485 * when listed as conforming in the MP table. */
487 #define default_ISA_trigger(idx) (0)
488 #define default_ISA_polarity(idx) (0)
490 /* PCI interrupts are always polarity one level triggered,
491 * when listed as conforming in the MP table. */
493 #define default_PCI_trigger(idx) (1)
494 #define default_PCI_polarity(idx) (1)
496 static int __init MPBIOS_polarity(int idx)
498 int bus = mp_irqs[idx].mpc_srcbus;
502 * Determine IRQ line polarity (high active or low active):
504 switch (mp_irqs[idx].mpc_irqflag & 3)
506 case 0: /* conforms, ie. bus-type dependent polarity */
507 if (test_bit(bus, mp_bus_not_pci))
508 polarity = default_ISA_polarity(idx);
510 polarity = default_PCI_polarity(idx);
512 case 1: /* high active */
517 case 2: /* reserved */
519 printk(KERN_WARNING "broken BIOS!!\n");
523 case 3: /* low active */
528 default: /* invalid */
530 printk(KERN_WARNING "broken BIOS!!\n");
538 static int MPBIOS_trigger(int idx)
540 int bus = mp_irqs[idx].mpc_srcbus;
544 * Determine IRQ trigger mode (edge or level sensitive):
546 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
548 case 0: /* conforms, ie. bus-type dependent */
549 if (test_bit(bus, mp_bus_not_pci))
550 trigger = default_ISA_trigger(idx);
552 trigger = default_PCI_trigger(idx);
559 case 2: /* reserved */
561 printk(KERN_WARNING "broken BIOS!!\n");
570 default: /* invalid */
572 printk(KERN_WARNING "broken BIOS!!\n");
580 static inline int irq_polarity(int idx)
582 return MPBIOS_polarity(idx);
585 static inline int irq_trigger(int idx)
587 return MPBIOS_trigger(idx);
590 static int pin_2_irq(int idx, int apic, int pin)
593 int bus = mp_irqs[idx].mpc_srcbus;
596 * Debugging check, we are in big trouble if this message pops up!
598 if (mp_irqs[idx].mpc_dstirq != pin)
599 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
601 if (test_bit(bus, mp_bus_not_pci)) {
602 irq = mp_irqs[idx].mpc_srcbusirq;
605 * PCI IRQs are mapped in order
609 irq += nr_ioapic_registers[i++];
612 BUG_ON(irq >= NR_IRQS);
617 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
618 static u8 irq_vector[NR_IRQS] __read_mostly = {
619 [0] = FIRST_EXTERNAL_VECTOR + 0,
620 [1] = FIRST_EXTERNAL_VECTOR + 1,
621 [2] = FIRST_EXTERNAL_VECTOR + 2,
622 [3] = FIRST_EXTERNAL_VECTOR + 3,
623 [4] = FIRST_EXTERNAL_VECTOR + 4,
624 [5] = FIRST_EXTERNAL_VECTOR + 5,
625 [6] = FIRST_EXTERNAL_VECTOR + 6,
626 [7] = FIRST_EXTERNAL_VECTOR + 7,
627 [8] = FIRST_EXTERNAL_VECTOR + 8,
628 [9] = FIRST_EXTERNAL_VECTOR + 9,
629 [10] = FIRST_EXTERNAL_VECTOR + 10,
630 [11] = FIRST_EXTERNAL_VECTOR + 11,
631 [12] = FIRST_EXTERNAL_VECTOR + 12,
632 [13] = FIRST_EXTERNAL_VECTOR + 13,
633 [14] = FIRST_EXTERNAL_VECTOR + 14,
634 [15] = FIRST_EXTERNAL_VECTOR + 15,
637 static cpumask_t irq_domain[NR_IRQS] __read_mostly = {
656 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
659 * NOTE! The local APIC isn't very good at handling
660 * multiple interrupts at the same interrupt level.
661 * As the interrupt level is determined by taking the
662 * vector number and shifting that right by 4, we
663 * want to spread these out a bit so that they don't
664 * all fall in the same interrupt level.
666 * Also, we've got to be careful not to trash gate
667 * 0x80, because int 0x80 is hm, kind of importantish. ;)
669 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
670 cpumask_t old_mask = CPU_MASK_NONE;
674 BUG_ON((unsigned)irq >= NR_IRQS);
676 /* Only try and allocate irqs on cpus that are present */
677 cpus_and(mask, mask, cpu_online_map);
679 if (irq_vector[irq] > 0)
680 old_vector = irq_vector[irq];
681 if (old_vector > 0) {
682 cpus_and(*result, irq_domain[irq], mask);
683 if (!cpus_empty(*result))
685 cpus_and(old_mask, irq_domain[irq], cpu_online_map);
688 for_each_cpu_mask(cpu, mask) {
689 cpumask_t domain, new_mask;
690 int new_cpu, old_cpu;
693 domain = vector_allocation_domain(cpu);
694 cpus_and(new_mask, domain, cpu_online_map);
696 vector = current_vector;
697 offset = current_offset;
700 if (vector >= FIRST_SYSTEM_VECTOR) {
701 /* If we run out of vectors on large boxen, must share them. */
702 offset = (offset + 1) % 8;
703 vector = FIRST_DEVICE_VECTOR + offset;
705 if (unlikely(current_vector == vector))
707 if (vector == IA32_SYSCALL_VECTOR)
709 for_each_cpu_mask(new_cpu, new_mask)
710 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
713 current_vector = vector;
714 current_offset = offset;
715 for_each_cpu_mask(old_cpu, old_mask)
716 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
717 for_each_cpu_mask(new_cpu, new_mask)
718 per_cpu(vector_irq, new_cpu)[vector] = irq;
719 irq_vector[irq] = vector;
720 irq_domain[irq] = domain;
721 cpus_and(*result, domain, mask);
727 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
732 spin_lock_irqsave(&vector_lock, flags);
733 vector = __assign_irq_vector(irq, mask, result);
734 spin_unlock_irqrestore(&vector_lock, flags);
738 static void __clear_irq_vector(int irq)
743 BUG_ON(!irq_vector[irq]);
745 vector = irq_vector[irq];
746 cpus_and(mask, irq_domain[irq], cpu_online_map);
747 for_each_cpu_mask(cpu, mask)
748 per_cpu(vector_irq, cpu)[vector] = -1;
751 irq_domain[irq] = CPU_MASK_NONE;
754 void __setup_vector_irq(int cpu)
756 /* Initialize vector_irq on a new cpu */
757 /* This function must be called with vector_lock held */
760 /* Mark the inuse vectors */
761 for (irq = 0; irq < NR_IRQS; ++irq) {
762 if (!cpu_isset(cpu, irq_domain[irq]))
764 vector = irq_vector[irq];
765 per_cpu(vector_irq, cpu)[vector] = irq;
767 /* Mark the free vectors */
768 for (vector = 0; vector < NR_VECTORS; ++vector) {
769 irq = per_cpu(vector_irq, cpu)[vector];
772 if (!cpu_isset(cpu, irq_domain[irq]))
773 per_cpu(vector_irq, cpu)[vector] = -1;
778 static struct irq_chip ioapic_chip;
780 static void ioapic_register_intr(int irq, unsigned long trigger)
783 set_irq_chip_and_handler_name(irq, &ioapic_chip,
784 handle_fasteoi_irq, "fasteoi");
786 set_irq_chip_and_handler_name(irq, &ioapic_chip,
787 handle_edge_irq, "edge");
790 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
791 int trigger, int polarity)
793 struct IO_APIC_route_entry entry;
798 if (!IO_APIC_IRQ(irq))
801 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
805 apic_printk(APIC_VERBOSE,KERN_DEBUG
806 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
807 "IRQ %d Mode:%i Active:%i)\n",
808 apic, mp_ioapics[apic].mpc_apicid, pin, vector,
809 irq, trigger, polarity);
812 * add it to the IO-APIC irq-routing table:
814 memset(&entry,0,sizeof(entry));
816 entry.delivery_mode = INT_DELIVERY_MODE;
817 entry.dest_mode = INT_DEST_MODE;
818 entry.dest = cpu_mask_to_apicid(mask);
819 entry.mask = 0; /* enable IRQ */
820 entry.trigger = trigger;
821 entry.polarity = polarity;
822 entry.vector = vector;
824 /* Mask level triggered irqs.
825 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
830 ioapic_register_intr(irq, trigger);
832 disable_8259A_irq(irq);
834 ioapic_write_entry(apic, pin, entry);
836 spin_lock_irqsave(&ioapic_lock, flags);
837 irq_desc[irq].affinity = TARGET_CPUS;
838 spin_unlock_irqrestore(&ioapic_lock, flags);
841 static void __init setup_IO_APIC_irqs(void)
843 int apic, pin, idx, irq, first_notcon = 1;
845 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
847 for (apic = 0; apic < nr_ioapics; apic++) {
848 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
850 idx = find_irq_entry(apic,pin,mp_INT);
853 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
856 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
860 irq = pin_2_irq(idx, apic, pin);
861 add_pin_to_irq(irq, apic, pin);
863 setup_IO_APIC_irq(apic, pin, irq,
864 irq_trigger(idx), irq_polarity(idx));
869 apic_printk(APIC_VERBOSE," not connected.\n");
873 * Set up the 8259A-master output pin as broadcast to all
876 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
878 struct IO_APIC_route_entry entry;
881 memset(&entry,0,sizeof(entry));
883 disable_8259A_irq(0);
886 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
889 * We use logical delivery to get the timer IRQ
892 entry.dest_mode = INT_DEST_MODE;
893 entry.mask = 0; /* unmask IRQ now */
894 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
895 entry.delivery_mode = INT_DELIVERY_MODE;
898 entry.vector = vector;
901 * The timer IRQ doesn't have to know that behind the
902 * scene we have a 8259A-master in AEOI mode ...
904 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
907 * Add it to the IO-APIC irq-routing table:
909 spin_lock_irqsave(&ioapic_lock, flags);
910 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
911 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
912 spin_unlock_irqrestore(&ioapic_lock, flags);
917 void __init UNEXPECTED_IO_APIC(void)
921 void __apicdebuginit print_IO_APIC(void)
924 union IO_APIC_reg_00 reg_00;
925 union IO_APIC_reg_01 reg_01;
926 union IO_APIC_reg_02 reg_02;
929 if (apic_verbosity == APIC_QUIET)
932 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
933 for (i = 0; i < nr_ioapics; i++)
934 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
935 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
938 * We are a bit conservative about what we expect. We have to
939 * know about every hardware change ASAP.
941 printk(KERN_INFO "testing the IO APIC.......................\n");
943 for (apic = 0; apic < nr_ioapics; apic++) {
945 spin_lock_irqsave(&ioapic_lock, flags);
946 reg_00.raw = io_apic_read(apic, 0);
947 reg_01.raw = io_apic_read(apic, 1);
948 if (reg_01.bits.version >= 0x10)
949 reg_02.raw = io_apic_read(apic, 2);
950 spin_unlock_irqrestore(&ioapic_lock, flags);
953 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
954 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
955 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
956 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
957 UNEXPECTED_IO_APIC();
959 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
960 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
961 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
962 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
963 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
964 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
965 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
966 (reg_01.bits.entries != 0x2E) &&
967 (reg_01.bits.entries != 0x3F) &&
968 (reg_01.bits.entries != 0x03)
970 UNEXPECTED_IO_APIC();
972 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
973 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
974 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
975 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
976 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
977 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
978 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
979 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
981 UNEXPECTED_IO_APIC();
982 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
983 UNEXPECTED_IO_APIC();
985 if (reg_01.bits.version >= 0x10) {
986 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
987 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
988 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
989 UNEXPECTED_IO_APIC();
992 printk(KERN_DEBUG ".... IRQ redirection table:\n");
994 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
995 " Stat Dmod Deli Vect: \n");
997 for (i = 0; i <= reg_01.bits.entries; i++) {
998 struct IO_APIC_route_entry entry;
1000 entry = ioapic_read_entry(apic, i);
1002 printk(KERN_DEBUG " %02x %03X ",
1007 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1012 entry.delivery_status,
1014 entry.delivery_mode,
1019 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1020 for (i = 0; i < NR_IRQS; i++) {
1021 struct irq_pin_list *entry = irq_2_pin + i;
1024 printk(KERN_DEBUG "IRQ%d ", i);
1026 printk("-> %d:%d", entry->apic, entry->pin);
1029 entry = irq_2_pin + entry->next;
1034 printk(KERN_INFO ".................................... done.\n");
1041 static __apicdebuginit void print_APIC_bitfield (int base)
1046 if (apic_verbosity == APIC_QUIET)
1049 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1050 for (i = 0; i < 8; i++) {
1051 v = apic_read(base + i*0x10);
1052 for (j = 0; j < 32; j++) {
1062 void __apicdebuginit print_local_APIC(void * dummy)
1064 unsigned int v, ver, maxlvt;
1066 if (apic_verbosity == APIC_QUIET)
1069 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1070 smp_processor_id(), hard_smp_processor_id());
1071 v = apic_read(APIC_ID);
1072 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1073 v = apic_read(APIC_LVR);
1074 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1075 ver = GET_APIC_VERSION(v);
1076 maxlvt = get_maxlvt();
1078 v = apic_read(APIC_TASKPRI);
1079 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1081 v = apic_read(APIC_ARBPRI);
1082 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1083 v & APIC_ARBPRI_MASK);
1084 v = apic_read(APIC_PROCPRI);
1085 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1087 v = apic_read(APIC_EOI);
1088 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1089 v = apic_read(APIC_RRR);
1090 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1091 v = apic_read(APIC_LDR);
1092 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1093 v = apic_read(APIC_DFR);
1094 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1095 v = apic_read(APIC_SPIV);
1096 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1098 printk(KERN_DEBUG "... APIC ISR field:\n");
1099 print_APIC_bitfield(APIC_ISR);
1100 printk(KERN_DEBUG "... APIC TMR field:\n");
1101 print_APIC_bitfield(APIC_TMR);
1102 printk(KERN_DEBUG "... APIC IRR field:\n");
1103 print_APIC_bitfield(APIC_IRR);
1105 v = apic_read(APIC_ESR);
1106 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1108 v = apic_read(APIC_ICR);
1109 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1110 v = apic_read(APIC_ICR2);
1111 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1113 v = apic_read(APIC_LVTT);
1114 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1116 if (maxlvt > 3) { /* PC is LVT#4. */
1117 v = apic_read(APIC_LVTPC);
1118 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1120 v = apic_read(APIC_LVT0);
1121 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1122 v = apic_read(APIC_LVT1);
1123 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1125 if (maxlvt > 2) { /* ERR is LVT#3. */
1126 v = apic_read(APIC_LVTERR);
1127 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1130 v = apic_read(APIC_TMICT);
1131 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1132 v = apic_read(APIC_TMCCT);
1133 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1134 v = apic_read(APIC_TDCR);
1135 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1139 void print_all_local_APICs (void)
1141 on_each_cpu(print_local_APIC, NULL, 1, 1);
1144 void __apicdebuginit print_PIC(void)
1147 unsigned long flags;
1149 if (apic_verbosity == APIC_QUIET)
1152 printk(KERN_DEBUG "\nprinting PIC contents\n");
1154 spin_lock_irqsave(&i8259A_lock, flags);
1156 v = inb(0xa1) << 8 | inb(0x21);
1157 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1159 v = inb(0xa0) << 8 | inb(0x20);
1160 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1164 v = inb(0xa0) << 8 | inb(0x20);
1168 spin_unlock_irqrestore(&i8259A_lock, flags);
1170 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1172 v = inb(0x4d1) << 8 | inb(0x4d0);
1173 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1178 static void __init enable_IO_APIC(void)
1180 union IO_APIC_reg_01 reg_01;
1181 int i8259_apic, i8259_pin;
1183 unsigned long flags;
1185 for (i = 0; i < PIN_MAP_SIZE; i++) {
1186 irq_2_pin[i].pin = -1;
1187 irq_2_pin[i].next = 0;
1191 * The number of IO-APIC IRQ registers (== #pins):
1193 for (apic = 0; apic < nr_ioapics; apic++) {
1194 spin_lock_irqsave(&ioapic_lock, flags);
1195 reg_01.raw = io_apic_read(apic, 1);
1196 spin_unlock_irqrestore(&ioapic_lock, flags);
1197 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1199 for(apic = 0; apic < nr_ioapics; apic++) {
1201 /* See if any of the pins is in ExtINT mode */
1202 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1203 struct IO_APIC_route_entry entry;
1204 entry = ioapic_read_entry(apic, pin);
1206 /* If the interrupt line is enabled and in ExtInt mode
1207 * I have found the pin where the i8259 is connected.
1209 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1210 ioapic_i8259.apic = apic;
1211 ioapic_i8259.pin = pin;
1217 /* Look to see what if the MP table has reported the ExtINT */
1218 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1219 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1220 /* Trust the MP table if nothing is setup in the hardware */
1221 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1222 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1223 ioapic_i8259.pin = i8259_pin;
1224 ioapic_i8259.apic = i8259_apic;
1226 /* Complain if the MP table and the hardware disagree */
1227 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1228 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1230 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1234 * Do not trust the IO-APIC being empty at bootup
1240 * Not an __init, needed by the reboot code
1242 void disable_IO_APIC(void)
1245 * Clear the IO-APIC before rebooting:
1250 * If the i8259 is routed through an IOAPIC
1251 * Put that IOAPIC in virtual wire mode
1252 * so legacy interrupts can be delivered.
1254 if (ioapic_i8259.pin != -1) {
1255 struct IO_APIC_route_entry entry;
1257 memset(&entry, 0, sizeof(entry));
1258 entry.mask = 0; /* Enabled */
1259 entry.trigger = 0; /* Edge */
1261 entry.polarity = 0; /* High */
1262 entry.delivery_status = 0;
1263 entry.dest_mode = 0; /* Physical */
1264 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1266 entry.dest = GET_APIC_ID(apic_read(APIC_ID));
1269 * Add it to the IO-APIC irq-routing table:
1271 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1274 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1278 * There is a nasty bug in some older SMP boards, their mptable lies
1279 * about the timer IRQ. We do the following to work around the situation:
1281 * - timer IRQ defaults to IO-APIC IRQ
1282 * - if this function detects that timer IRQs are defunct, then we fall
1283 * back to ISA timer IRQs
1285 static int __init timer_irq_works(void)
1287 unsigned long t1 = jiffies;
1290 /* Let ten ticks pass... */
1291 mdelay((10 * 1000) / HZ);
1294 * Expect a few ticks at least, to be sure some possible
1295 * glue logic does not lock up after one or two first
1296 * ticks in a non-ExtINT mode. Also the local APIC
1297 * might have cached one ExtINT interrupt. Finally, at
1298 * least one tick may be lost due to delays.
1302 if (jiffies - t1 > 4)
1308 * In the SMP+IOAPIC case it might happen that there are an unspecified
1309 * number of pending IRQ events unhandled. These cases are very rare,
1310 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1311 * better to do it this way as thus we do not have to be aware of
1312 * 'pending' interrupts in the IRQ path, except at this point.
1315 * Edge triggered needs to resend any interrupt
1316 * that was delayed but this is now handled in the device
1321 * Starting up a edge-triggered IO-APIC interrupt is
1322 * nasty - we need to make sure that we get the edge.
1323 * If it is already asserted for some reason, we need
1324 * return 1 to indicate that is was pending.
1326 * This is not complete - we should be able to fake
1327 * an edge even if it isn't on the 8259A...
1330 static unsigned int startup_ioapic_irq(unsigned int irq)
1332 int was_pending = 0;
1333 unsigned long flags;
1335 spin_lock_irqsave(&ioapic_lock, flags);
1337 disable_8259A_irq(irq);
1338 if (i8259A_irq_pending(irq))
1341 __unmask_IO_APIC_irq(irq);
1342 spin_unlock_irqrestore(&ioapic_lock, flags);
1347 static int ioapic_retrigger_irq(unsigned int irq)
1351 unsigned long flags;
1353 spin_lock_irqsave(&vector_lock, flags);
1354 vector = irq_vector[irq];
1356 cpu_set(first_cpu(irq_domain[irq]), mask);
1358 send_IPI_mask(mask, vector);
1359 spin_unlock_irqrestore(&vector_lock, flags);
1365 * Level and edge triggered IO-APIC interrupts need different handling,
1366 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1367 * handled with the level-triggered descriptor, but that one has slightly
1368 * more overhead. Level-triggered interrupts cannot be handled with the
1369 * edge-triggered handler, without risking IRQ storms and other ugly
1373 static void ack_apic_edge(unsigned int irq)
1375 move_native_irq(irq);
1379 static void ack_apic_level(unsigned int irq)
1381 int do_unmask_irq = 0;
1383 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1384 /* If we are moving the irq we need to mask it */
1385 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1387 mask_IO_APIC_irq(irq);
1392 * We must acknowledge the irq before we move it or the acknowledge will
1393 * not propogate properly.
1397 /* Now we can move and renable the irq */
1398 move_masked_irq(irq);
1399 if (unlikely(do_unmask_irq))
1400 unmask_IO_APIC_irq(irq);
1403 static struct irq_chip ioapic_chip __read_mostly = {
1405 .startup = startup_ioapic_irq,
1406 .mask = mask_IO_APIC_irq,
1407 .unmask = unmask_IO_APIC_irq,
1408 .ack = ack_apic_edge,
1409 .eoi = ack_apic_level,
1411 .set_affinity = set_ioapic_affinity_irq,
1413 .retrigger = ioapic_retrigger_irq,
1416 static inline void init_IO_APIC_traps(void)
1421 * NOTE! The local APIC isn't very good at handling
1422 * multiple interrupts at the same interrupt level.
1423 * As the interrupt level is determined by taking the
1424 * vector number and shifting that right by 4, we
1425 * want to spread these out a bit so that they don't
1426 * all fall in the same interrupt level.
1428 * Also, we've got to be careful not to trash gate
1429 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1431 for (irq = 0; irq < NR_IRQS ; irq++) {
1433 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1435 * Hmm.. We don't have an entry for this,
1436 * so default to an old-fashioned 8259
1437 * interrupt if we can..
1440 make_8259A_irq(irq);
1442 /* Strange. Oh, well.. */
1443 irq_desc[irq].chip = &no_irq_chip;
1448 static void enable_lapic_irq (unsigned int irq)
1452 v = apic_read(APIC_LVT0);
1453 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1456 static void disable_lapic_irq (unsigned int irq)
1460 v = apic_read(APIC_LVT0);
1461 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1464 static void ack_lapic_irq (unsigned int irq)
1469 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1471 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1472 .typename = "local-APIC-edge",
1473 .startup = NULL, /* startup_irq() not used for IRQ0 */
1474 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1475 .enable = enable_lapic_irq,
1476 .disable = disable_lapic_irq,
1477 .ack = ack_lapic_irq,
1478 .end = end_lapic_irq,
1481 static void setup_nmi (void)
1484 * Dirty trick to enable the NMI watchdog ...
1485 * We put the 8259A master into AEOI mode and
1486 * unmask on all local APICs LVT0 as NMI.
1488 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1489 * is from Maciej W. Rozycki - so we do not have to EOI from
1490 * the NMI handler or the timer interrupt.
1492 printk(KERN_INFO "activating NMI Watchdog ...");
1494 enable_NMI_through_LVT0(NULL);
1500 * This looks a bit hackish but it's about the only one way of sending
1501 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1502 * not support the ExtINT mode, unfortunately. We need to send these
1503 * cycles as some i82489DX-based boards have glue logic that keeps the
1504 * 8259A interrupt line asserted until INTA. --macro
1506 static inline void unlock_ExtINT_logic(void)
1509 struct IO_APIC_route_entry entry0, entry1;
1510 unsigned char save_control, save_freq_select;
1511 unsigned long flags;
1513 pin = find_isa_irq_pin(8, mp_INT);
1514 apic = find_isa_irq_apic(8, mp_INT);
1518 spin_lock_irqsave(&ioapic_lock, flags);
1519 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1520 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1521 spin_unlock_irqrestore(&ioapic_lock, flags);
1522 clear_IO_APIC_pin(apic, pin);
1524 memset(&entry1, 0, sizeof(entry1));
1526 entry1.dest_mode = 0; /* physical delivery */
1527 entry1.mask = 0; /* unmask IRQ now */
1528 entry1.dest = hard_smp_processor_id();
1529 entry1.delivery_mode = dest_ExtINT;
1530 entry1.polarity = entry0.polarity;
1534 spin_lock_irqsave(&ioapic_lock, flags);
1535 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1536 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1537 spin_unlock_irqrestore(&ioapic_lock, flags);
1539 save_control = CMOS_READ(RTC_CONTROL);
1540 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1541 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1543 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1548 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1552 CMOS_WRITE(save_control, RTC_CONTROL);
1553 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1554 clear_IO_APIC_pin(apic, pin);
1556 spin_lock_irqsave(&ioapic_lock, flags);
1557 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1558 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1559 spin_unlock_irqrestore(&ioapic_lock, flags);
1563 * This code may look a bit paranoid, but it's supposed to cooperate with
1564 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1565 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1566 * fanatically on his truly buggy board.
1568 * FIXME: really need to revamp this for modern platforms only.
1570 static inline void check_timer(void)
1572 int apic1, pin1, apic2, pin2;
1577 * get/set the timer IRQ vector:
1579 disable_8259A_irq(0);
1580 vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1583 * Subtle, code in do_timer_interrupt() expects an AEOI
1584 * mode for the 8259A whenever interrupts are routed
1585 * through I/O APICs. Also IRQ0 has to be enabled in
1586 * the 8259A which implies the virtual wire has to be
1587 * disabled in the local APIC.
1589 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1591 if (timer_over_8254 > 0)
1592 enable_8259A_irq(0);
1594 pin1 = find_isa_irq_pin(0, mp_INT);
1595 apic1 = find_isa_irq_apic(0, mp_INT);
1596 pin2 = ioapic_i8259.pin;
1597 apic2 = ioapic_i8259.apic;
1599 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1600 vector, apic1, pin1, apic2, pin2);
1604 * Ok, does IRQ0 through the IOAPIC work?
1606 unmask_IO_APIC_irq(0);
1607 if (!no_timer_check && timer_irq_works()) {
1608 nmi_watchdog_default();
1609 if (nmi_watchdog == NMI_IO_APIC) {
1610 disable_8259A_irq(0);
1612 enable_8259A_irq(0);
1614 if (disable_timer_pin_1 > 0)
1615 clear_IO_APIC_pin(0, pin1);
1618 clear_IO_APIC_pin(apic1, pin1);
1619 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1620 "connected to IO-APIC\n");
1623 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1624 "through the 8259A ... ");
1626 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1629 * legacy devices should be connected to IO APIC #0
1631 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1632 if (timer_irq_works()) {
1633 apic_printk(APIC_VERBOSE," works.\n");
1634 nmi_watchdog_default();
1635 if (nmi_watchdog == NMI_IO_APIC) {
1641 * Cleanup, just in case ...
1643 clear_IO_APIC_pin(apic2, pin2);
1645 apic_printk(APIC_VERBOSE," failed.\n");
1647 if (nmi_watchdog == NMI_IO_APIC) {
1648 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1652 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1654 disable_8259A_irq(0);
1655 irq_desc[0].chip = &lapic_irq_type;
1656 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1657 enable_8259A_irq(0);
1659 if (timer_irq_works()) {
1660 apic_printk(APIC_VERBOSE," works.\n");
1663 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1664 apic_printk(APIC_VERBOSE," failed.\n");
1666 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1670 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1672 unlock_ExtINT_logic();
1674 if (timer_irq_works()) {
1675 apic_printk(APIC_VERBOSE," works.\n");
1678 apic_printk(APIC_VERBOSE," failed :(.\n");
1679 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1682 static int __init notimercheck(char *s)
1687 __setup("no_timer_check", notimercheck);
1691 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1692 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1693 * Linux doesn't really care, as it's not actually used
1694 * for any interrupt handling anyway.
1696 #define PIC_IRQS (1<<2)
1698 void __init setup_IO_APIC(void)
1703 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1705 io_apic_irqs = ~PIC_IRQS;
1707 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1710 setup_IO_APIC_irqs();
1711 init_IO_APIC_traps();
1717 struct sysfs_ioapic_data {
1718 struct sys_device dev;
1719 struct IO_APIC_route_entry entry[0];
1721 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1723 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1725 struct IO_APIC_route_entry *entry;
1726 struct sysfs_ioapic_data *data;
1729 data = container_of(dev, struct sysfs_ioapic_data, dev);
1730 entry = data->entry;
1731 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1732 *entry = ioapic_read_entry(dev->id, i);
1737 static int ioapic_resume(struct sys_device *dev)
1739 struct IO_APIC_route_entry *entry;
1740 struct sysfs_ioapic_data *data;
1741 unsigned long flags;
1742 union IO_APIC_reg_00 reg_00;
1745 data = container_of(dev, struct sysfs_ioapic_data, dev);
1746 entry = data->entry;
1748 spin_lock_irqsave(&ioapic_lock, flags);
1749 reg_00.raw = io_apic_read(dev->id, 0);
1750 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1751 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1752 io_apic_write(dev->id, 0, reg_00.raw);
1754 spin_unlock_irqrestore(&ioapic_lock, flags);
1755 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1756 ioapic_write_entry(dev->id, i, entry[i]);
1761 static struct sysdev_class ioapic_sysdev_class = {
1762 set_kset_name("ioapic"),
1763 .suspend = ioapic_suspend,
1764 .resume = ioapic_resume,
1767 static int __init ioapic_init_sysfs(void)
1769 struct sys_device * dev;
1770 int i, size, error = 0;
1772 error = sysdev_class_register(&ioapic_sysdev_class);
1776 for (i = 0; i < nr_ioapics; i++ ) {
1777 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1778 * sizeof(struct IO_APIC_route_entry);
1779 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1780 if (!mp_ioapic_data[i]) {
1781 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1784 memset(mp_ioapic_data[i], 0, size);
1785 dev = &mp_ioapic_data[i]->dev;
1787 dev->cls = &ioapic_sysdev_class;
1788 error = sysdev_register(dev);
1790 kfree(mp_ioapic_data[i]);
1791 mp_ioapic_data[i] = NULL;
1792 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1800 device_initcall(ioapic_init_sysfs);
1803 * Dynamic irq allocate and deallocation
1805 int create_irq(void)
1807 /* Allocate an unused irq */
1811 unsigned long flags;
1815 spin_lock_irqsave(&vector_lock, flags);
1816 for (new = (NR_IRQS - 1); new >= 0; new--) {
1817 if (platform_legacy_irq(new))
1819 if (irq_vector[new] != 0)
1821 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1822 if (likely(vector > 0))
1826 spin_unlock_irqrestore(&vector_lock, flags);
1829 dynamic_irq_init(irq);
1834 void destroy_irq(unsigned int irq)
1836 unsigned long flags;
1838 dynamic_irq_cleanup(irq);
1840 spin_lock_irqsave(&vector_lock, flags);
1841 __clear_irq_vector(irq);
1842 spin_unlock_irqrestore(&vector_lock, flags);
1846 * MSI mesage composition
1848 #ifdef CONFIG_PCI_MSI
1849 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1855 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1857 dest = cpu_mask_to_apicid(tmp);
1859 msg->address_hi = MSI_ADDR_BASE_HI;
1862 ((INT_DEST_MODE == 0) ?
1863 MSI_ADDR_DEST_MODE_PHYSICAL:
1864 MSI_ADDR_DEST_MODE_LOGICAL) |
1865 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1866 MSI_ADDR_REDIRECTION_CPU:
1867 MSI_ADDR_REDIRECTION_LOWPRI) |
1868 MSI_ADDR_DEST_ID(dest);
1871 MSI_DATA_TRIGGER_EDGE |
1872 MSI_DATA_LEVEL_ASSERT |
1873 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1874 MSI_DATA_DELIVERY_FIXED:
1875 MSI_DATA_DELIVERY_LOWPRI) |
1876 MSI_DATA_VECTOR(vector);
1882 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1889 cpus_and(tmp, mask, cpu_online_map);
1890 if (cpus_empty(tmp))
1893 vector = assign_irq_vector(irq, mask, &tmp);
1897 dest = cpu_mask_to_apicid(tmp);
1899 read_msi_msg(irq, &msg);
1901 msg.data &= ~MSI_DATA_VECTOR_MASK;
1902 msg.data |= MSI_DATA_VECTOR(vector);
1903 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1904 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1906 write_msi_msg(irq, &msg);
1907 irq_desc[irq].affinity = mask;
1909 #endif /* CONFIG_SMP */
1912 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1913 * which implement the MSI or MSI-X Capability Structure.
1915 static struct irq_chip msi_chip = {
1917 .unmask = unmask_msi_irq,
1918 .mask = mask_msi_irq,
1919 .ack = ack_apic_edge,
1921 .set_affinity = set_msi_irq_affinity,
1923 .retrigger = ioapic_retrigger_irq,
1926 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
1934 set_irq_msi(irq, desc);
1935 ret = msi_compose_msg(dev, irq, &msg);
1941 write_msi_msg(irq, &msg);
1943 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1948 void arch_teardown_msi_irq(unsigned int irq)
1953 #endif /* CONFIG_PCI_MSI */
1956 * Hypertransport interrupt support
1958 #ifdef CONFIG_HT_IRQ
1962 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1964 struct ht_irq_msg msg;
1965 fetch_ht_irq_msg(irq, &msg);
1967 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1968 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1970 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1971 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
1973 write_ht_irq_msg(irq, &msg);
1976 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1982 cpus_and(tmp, mask, cpu_online_map);
1983 if (cpus_empty(tmp))
1986 vector = assign_irq_vector(irq, mask, &tmp);
1990 dest = cpu_mask_to_apicid(tmp);
1992 target_ht_irq(irq, dest, vector);
1993 irq_desc[irq].affinity = mask;
1997 static struct irq_chip ht_irq_chip = {
1999 .mask = mask_ht_irq,
2000 .unmask = unmask_ht_irq,
2001 .ack = ack_apic_edge,
2003 .set_affinity = set_ht_irq_affinity,
2005 .retrigger = ioapic_retrigger_irq,
2008 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2013 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
2015 struct ht_irq_msg msg;
2018 dest = cpu_mask_to_apicid(tmp);
2020 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2024 HT_IRQ_LOW_DEST_ID(dest) |
2025 HT_IRQ_LOW_VECTOR(vector) |
2026 ((INT_DEST_MODE == 0) ?
2027 HT_IRQ_LOW_DM_PHYSICAL :
2028 HT_IRQ_LOW_DM_LOGICAL) |
2029 HT_IRQ_LOW_RQEOI_EDGE |
2030 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2031 HT_IRQ_LOW_MT_FIXED :
2032 HT_IRQ_LOW_MT_ARBITRATED) |
2033 HT_IRQ_LOW_IRQ_MASKED;
2035 write_ht_irq_msg(irq, &msg);
2037 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2038 handle_edge_irq, "edge");
2042 #endif /* CONFIG_HT_IRQ */
2044 /* --------------------------------------------------------------------------
2045 ACPI-based IOAPIC Configuration
2046 -------------------------------------------------------------------------- */
2050 #define IO_APIC_MAX_ID 0xFE
2052 int __init io_apic_get_redir_entries (int ioapic)
2054 union IO_APIC_reg_01 reg_01;
2055 unsigned long flags;
2057 spin_lock_irqsave(&ioapic_lock, flags);
2058 reg_01.raw = io_apic_read(ioapic, 1);
2059 spin_unlock_irqrestore(&ioapic_lock, flags);
2061 return reg_01.bits.entries;
2065 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2067 if (!IO_APIC_IRQ(irq)) {
2068 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2074 * IRQs < 16 are already in the irq_2_pin[] map
2077 add_pin_to_irq(irq, ioapic, pin);
2079 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2084 #endif /* CONFIG_ACPI */
2088 * This function currently is only a helper for the i386 smp boot process where
2089 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2090 * so mask in all cases should simply be TARGET_CPUS
2093 void __init setup_ioapic_dest(void)
2095 int pin, ioapic, irq, irq_entry;
2097 if (skip_ioapic_setup == 1)
2100 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2101 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2102 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2103 if (irq_entry == -1)
2105 irq = pin_2_irq(irq_entry, ioapic, pin);
2107 /* setup_IO_APIC_irqs could fail to get vector for some device
2108 * when you have too many devices, because at that time only boot
2111 if(!irq_vector[irq])
2112 setup_IO_APIC_irq(ioapic, pin, irq,
2113 irq_trigger(irq_entry),
2114 irq_polarity(irq_entry));
2116 set_ioapic_affinity_irq(irq, TARGET_CPUS);