arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/pci.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/msi.h>
  34 #include <linux/htirq.h>
  35 #ifdef CONFIG_ACPI
  36 #include <acpi/acpi_bus.h>
  37 #endif
  38
  39 #include <asm/idle.h>
  40 #include <asm/io.h>
  41 #include <asm/smp.h>
  42 #include <asm/desc.h>
  43 #include <asm/proto.h>
  44 #include <asm/mach_apic.h>
  45 #include <asm/acpi.h>
  46 #include <asm/dma.h>
  47 #include <asm/nmi.h>
  48 #include <asm/msidef.h>
  49 #include <asm/hypertransport.h>
  50
  51 struct irq_cfg {
  52         cpumask_t domain;
  53         cpumask_t old_domain;
  54         unsigned move_cleanup_count;
  55         u8 vector;
  56         u8 move_in_progress : 1;
  57 };
  58
  59 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
  60 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
  61         [0]  = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR,  },
  62         [1]  = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR,  },
  63         [2]  = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR,  },
  64         [3]  = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR,  },
  65         [4]  = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR,  },
  66         [5]  = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR,  },
  67         [6]  = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR,  },
  68         [7]  = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR,  },
  69         [8]  = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR,  },
  70         [9]  = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR,  },
  71         [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
  72         [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
  73         [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
  74         [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
  75         [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
  76         [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
  77 };
  78
  79 static int assign_irq_vector(int irq, cpumask_t mask);
  80
  81 #define __apicdebuginit  __init
  82
  83 int sis_apic_bug; /* not actually supported, dummy for compile */
  84
  85 static int no_timer_check;
  86
  87 static int disable_timer_pin_1 __initdata;
  88
  89 int timer_over_8254 __initdata = 1;
  90
  91 /* Where if anywhere is the i8259 connect in external int mode */
  92 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  93
  94 static DEFINE_SPINLOCK(ioapic_lock);
  95 DEFINE_SPINLOCK(vector_lock);
  96
  97 /*
  98  * # of IRQ routing registers
  99  */
 100 int nr_ioapic_registers[MAX_IO_APICS];
 101
 102 /*
 103  * Rough estimation of how many shared IRQs there are, can
 104  * be changed anytime.
 105  */
 106 #define MAX_PLUS_SHARED_IRQS NR_IRQS
 107 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
 108
 109 /*
 110  * This is performance-critical, we want to do it O(1)
 111  *
 112  * the indexing order of this array favors 1:1 mappings
 113  * between pins and IRQs.
 114  */
 115
 116 static struct irq_pin_list {
 117         short apic, pin, next;
 118 } irq_2_pin[PIN_MAP_SIZE];
 119
 120 struct io_apic {
 121         unsigned int index;
 122         unsigned int unused[3];
 123         unsigned int data;
 124 };
 125
 126 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 127 {
 128         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 129                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 130 }
 131
 132 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 133 {
 134         struct io_apic __iomem *io_apic = io_apic_base(apic);
 135         writel(reg, &io_apic->index);
 136         return readl(&io_apic->data);
 137 }
 138
 139 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 140 {
 141         struct io_apic __iomem *io_apic = io_apic_base(apic);
 142         writel(reg, &io_apic->index);
 143         writel(value, &io_apic->data);
 144 }
 145
 146 /*
 147  * Re-write a value: to be used for read-modify-write
 148  * cycles where the read already set up the index register.
 149  */
 150 static inline void io_apic_modify(unsigned int apic, unsigned int value)
 151 {
 152         struct io_apic __iomem *io_apic = io_apic_base(apic);
 153         writel(value, &io_apic->data);
 154 }
 155
 156 /*
 157  * Synchronize the IO-APIC and the CPU by doing
 158  * a dummy read from the IO-APIC
 159  */
 160 static inline void io_apic_sync(unsigned int apic)
 161 {
 162         struct io_apic __iomem *io_apic = io_apic_base(apic);
 163         readl(&io_apic->data);
 164 }
 165
 166 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 167                                                                         \
 168 {                                                                       \
 169         int pin;                                                        \
 170         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 171                                                                         \
 172         BUG_ON(irq >= NR_IRQS);                                         \
 173         for (;;) {                                                      \
 174                 unsigned int reg;                                       \
 175                 pin = entry->pin;                                       \
 176                 if (pin == -1)                                          \
 177                         break;                                          \
 178                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 179                 reg ACTION;                                             \
 180                 io_apic_modify(entry->apic, reg);                       \
 181                 FINAL;                                                  \
 182                 if (!entry->next)                                       \
 183                         break;                                          \
 184                 entry = irq_2_pin + entry->next;                        \
 185         }                                                               \
 186 }
 187
 188 union entry_union {
 189         struct { u32 w1, w2; };
 190         struct IO_APIC_route_entry entry;
 191 };
 192
 193 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 194 {
 195         union entry_union eu;
 196         unsigned long flags;
 197         spin_lock_irqsave(&ioapic_lock, flags);
 198         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 199         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 200         spin_unlock_irqrestore(&ioapic_lock, flags);
 201         return eu.entry;
 202 }
 203
 204 /*
 205  * When we write a new IO APIC routing entry, we need to write the high
 206  * word first! If the mask bit in the low word is clear, we will enable
 207  * the interrupt, and we need to make sure the entry is fully populated
 208  * before that happens.
 209  */
 210 static void
 211 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 212 {
 213         union entry_union eu;
 214         eu.entry = e;
 215         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 216         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 217 }
 218
 219 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 220 {
 221         unsigned long flags;
 222         spin_lock_irqsave(&ioapic_lock, flags);
 223         __ioapic_write_entry(apic, pin, e);
 224         spin_unlock_irqrestore(&ioapic_lock, flags);
 225 }
 226
 227 /*
 228  * When we mask an IO APIC routing entry, we need to write the low
 229  * word first, in order to set the mask bit before we change the
 230  * high bits!
 231  */
 232 static void ioapic_mask_entry(int apic, int pin)
 233 {
 234         unsigned long flags;
 235         union entry_union eu = { .entry.mask = 1 };
 236
 237         spin_lock_irqsave(&ioapic_lock, flags);
 238         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 239         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 240         spin_unlock_irqrestore(&ioapic_lock, flags);
 241 }
 242
 243 #ifdef CONFIG_SMP
 244 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
 245 {
 246         int apic, pin;
 247         struct irq_pin_list *entry = irq_2_pin + irq;
 248
 249         BUG_ON(irq >= NR_IRQS);
 250         for (;;) {
 251                 unsigned int reg;
 252                 apic = entry->apic;
 253                 pin = entry->pin;
 254                 if (pin == -1)
 255                         break;
 256                 io_apic_write(apic, 0x11 + pin*2, dest);
 257                 reg = io_apic_read(apic, 0x10 + pin*2);
 258                 reg &= ~0x000000ff;
 259                 reg |= vector;
 260                 io_apic_modify(apic, reg);
 261                 if (!entry->next)
 262                         break;
 263                 entry = irq_2_pin + entry->next;
 264         }
 265 }
 266
 267 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 268 {
 269         struct irq_cfg *cfg = irq_cfg + irq;
 270         unsigned long flags;
 271         unsigned int dest;
 272         cpumask_t tmp;
 273
 274         cpus_and(tmp, mask, cpu_online_map);
 275         if (cpus_empty(tmp))
 276                 return;
 277
 278         if (assign_irq_vector(irq, mask))
 279                 return;
 280
 281         cpus_and(tmp, cfg->domain, mask);
 282         dest = cpu_mask_to_apicid(tmp);
 283
 284         /*
 285          * Only the high 8 bits are valid.
 286          */
 287         dest = SET_APIC_LOGICAL_ID(dest);
 288
 289         spin_lock_irqsave(&ioapic_lock, flags);
 290         __target_IO_APIC_irq(irq, dest, cfg->vector);
 291         irq_desc[irq].affinity = mask;
 292         spin_unlock_irqrestore(&ioapic_lock, flags);
 293 }
 294 #endif
 295
 296 /*
 297  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 298  * shared ISA-space IRQs, so we have to support them. We are super
 299  * fast in the common case, and fast for shared ISA-space IRQs.
 300  */
 301 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 302 {
 303         static int first_free_entry = NR_IRQS;
 304         struct irq_pin_list *entry = irq_2_pin + irq;
 305
 306         BUG_ON(irq >= NR_IRQS);
 307         while (entry->next)
 308                 entry = irq_2_pin + entry->next;
 309
 310         if (entry->pin != -1) {
 311                 entry->next = first_free_entry;
 312                 entry = irq_2_pin + entry->next;
 313                 if (++first_free_entry >= PIN_MAP_SIZE)
 314                         panic("io_apic.c: ran out of irq_2_pin entries!");
 315         }
 316         entry->apic = apic;
 317         entry->pin = pin;
 318 }
 319
 320
 321 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 322                                                                         \
 323         static void name##_IO_APIC_irq (unsigned int irq)               \
 324         __DO_ACTION(R, ACTION, FINAL)
 325
 326 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 327                                                 /* mask = 1 */
 328 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 329                                                 /* mask = 0 */
 330
 331 static void mask_IO_APIC_irq (unsigned int irq)
 332 {
 333         unsigned long flags;
 334
 335         spin_lock_irqsave(&ioapic_lock, flags);
 336         __mask_IO_APIC_irq(irq);
 337         spin_unlock_irqrestore(&ioapic_lock, flags);
 338 }
 339
 340 static void unmask_IO_APIC_irq (unsigned int irq)
 341 {
 342         unsigned long flags;
 343
 344         spin_lock_irqsave(&ioapic_lock, flags);
 345         __unmask_IO_APIC_irq(irq);
 346         spin_unlock_irqrestore(&ioapic_lock, flags);
 347 }
 348
 349 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 350 {
 351         struct IO_APIC_route_entry entry;
 352
 353         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 354         entry = ioapic_read_entry(apic, pin);
 355         if (entry.delivery_mode == dest_SMI)
 356                 return;
 357         /*
 358          * Disable it in the IO-APIC irq-routing table:
 359          */
 360         ioapic_mask_entry(apic, pin);
 361 }
 362
 363 static void clear_IO_APIC (void)
 364 {
 365         int apic, pin;
 366
 367         for (apic = 0; apic < nr_ioapics; apic++)
 368                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 369                         clear_IO_APIC_pin(apic, pin);
 370 }
 371
 372 int skip_ioapic_setup;
 373 int ioapic_force;
 374
 375 /* dummy parsing: see setup.c */
 376
 377 static int __init disable_ioapic_setup(char *str)
 378 {
 379         skip_ioapic_setup = 1;
 380         return 0;
 381 }
 382 early_param("noapic", disable_ioapic_setup);
 383
 384 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
 385 static int __init disable_timer_pin_setup(char *arg)
 386 {
 387         disable_timer_pin_1 = 1;
 388         return 1;
 389 }
 390 __setup("disable_timer_pin_1", disable_timer_pin_setup);
 391
 392 static int __init setup_disable_8254_timer(char *s)
 393 {
 394         timer_over_8254 = -1;
 395         return 1;
 396 }
 397 static int __init setup_enable_8254_timer(char *s)
 398 {
 399         timer_over_8254 = 2;
 400         return 1;
 401 }
 402
 403 __setup("disable_8254_timer", setup_disable_8254_timer);
 404 __setup("enable_8254_timer", setup_enable_8254_timer);
 405
 406
 407 /*
 408  * Find the IRQ entry number of a certain pin.
 409  */
 410 static int find_irq_entry(int apic, int pin, int type)
 411 {
 412         int i;
 413
 414         for (i = 0; i < mp_irq_entries; i++)
 415                 if (mp_irqs[i].mpc_irqtype == type &&
 416                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 417                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 418                     mp_irqs[i].mpc_dstirq == pin)
 419                         return i;
 420
 421         return -1;
 422 }
 423
 424 /*
 425  * Find the pin to which IRQ[irq] (ISA) is connected
 426  */
 427 static int __init find_isa_irq_pin(int irq, int type)
 428 {
 429         int i;
 430
 431         for (i = 0; i < mp_irq_entries; i++) {
 432                 int lbus = mp_irqs[i].mpc_srcbus;
 433
 434                 if (test_bit(lbus, mp_bus_not_pci) &&
 435                     (mp_irqs[i].mpc_irqtype == type) &&
 436                     (mp_irqs[i].mpc_srcbusirq == irq))
 437
 438                         return mp_irqs[i].mpc_dstirq;
 439         }
 440         return -1;
 441 }
 442
 443 static int __init find_isa_irq_apic(int irq, int type)
 444 {
 445         int i;
 446
 447         for (i = 0; i < mp_irq_entries; i++) {
 448                 int lbus = mp_irqs[i].mpc_srcbus;
 449
 450                 if (test_bit(lbus, mp_bus_not_pci) &&
 451                     (mp_irqs[i].mpc_irqtype == type) &&
 452                     (mp_irqs[i].mpc_srcbusirq == irq))
 453                         break;
 454         }
 455         if (i < mp_irq_entries) {
 456                 int apic;
 457                 for(apic = 0; apic < nr_ioapics; apic++) {
 458                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 459                                 return apic;
 460                 }
 461         }
 462
 463         return -1;
 464 }
 465
 466 /*
 467  * Find a specific PCI IRQ entry.
 468  * Not an __init, possibly needed by modules
 469  */
 470 static int pin_2_irq(int idx, int apic, int pin);
 471
 472 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 473 {
 474         int apic, i, best_guess = -1;
 475
 476         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 477                 bus, slot, pin);
 478         if (mp_bus_id_to_pci_bus[bus] == -1) {
 479                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 480                 return -1;
 481         }
 482         for (i = 0; i < mp_irq_entries; i++) {
 483                 int lbus = mp_irqs[i].mpc_srcbus;
 484
 485                 for (apic = 0; apic < nr_ioapics; apic++)
 486                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 487                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 488                                 break;
 489
 490                 if (!test_bit(lbus, mp_bus_not_pci) &&
 491                     !mp_irqs[i].mpc_irqtype &&
 492                     (bus == lbus) &&
 493                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 494                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 495
 496                         if (!(apic || IO_APIC_IRQ(irq)))
 497                                 continue;
 498
 499                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 500                                 return irq;
 501                         /*
 502                          * Use the first all-but-pin matching entry as a
 503                          * best-guess fuzzy result for broken mptables.
 504                          */
 505                         if (best_guess < 0)
 506                                 best_guess = irq;
 507                 }
 508         }
 509         BUG_ON(best_guess >= NR_IRQS);
 510         return best_guess;
 511 }
 512
 513 /* ISA interrupts are always polarity zero edge triggered,
 514  * when listed as conforming in the MP table. */
 515
 516 #define default_ISA_trigger(idx)        (0)
 517 #define default_ISA_polarity(idx)       (0)
 518
 519 /* PCI interrupts are always polarity one level triggered,
 520  * when listed as conforming in the MP table. */
 521
 522 #define default_PCI_trigger(idx)        (1)
 523 #define default_PCI_polarity(idx)       (1)
 524
 525 static int __init MPBIOS_polarity(int idx)
 526 {
 527         int bus = mp_irqs[idx].mpc_srcbus;
 528         int polarity;
 529
 530         /*
 531          * Determine IRQ line polarity (high active or low active):
 532          */
 533         switch (mp_irqs[idx].mpc_irqflag & 3)
 534         {
 535                 case 0: /* conforms, ie. bus-type dependent polarity */
 536                         if (test_bit(bus, mp_bus_not_pci))
 537                                 polarity = default_ISA_polarity(idx);
 538                         else
 539                                 polarity = default_PCI_polarity(idx);
 540                         break;
 541                 case 1: /* high active */
 542                 {
 543                         polarity = 0;
 544                         break;
 545                 }
 546                 case 2: /* reserved */
 547                 {
 548                         printk(KERN_WARNING "broken BIOS!!\n");
 549                         polarity = 1;
 550                         break;
 551                 }
 552                 case 3: /* low active */
 553                 {
 554                         polarity = 1;
 555                         break;
 556                 }
 557                 default: /* invalid */
 558                 {
 559                         printk(KERN_WARNING "broken BIOS!!\n");
 560                         polarity = 1;
 561                         break;
 562                 }
 563         }
 564         return polarity;
 565 }
 566
 567 static int MPBIOS_trigger(int idx)
 568 {
 569         int bus = mp_irqs[idx].mpc_srcbus;
 570         int trigger;
 571
 572         /*
 573          * Determine IRQ trigger mode (edge or level sensitive):
 574          */
 575         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 576         {
 577                 case 0: /* conforms, ie. bus-type dependent */
 578                         if (test_bit(bus, mp_bus_not_pci))
 579                                 trigger = default_ISA_trigger(idx);
 580                         else
 581                                 trigger = default_PCI_trigger(idx);
 582                         break;
 583                 case 1: /* edge */
 584                 {
 585                         trigger = 0;
 586                         break;
 587                 }
 588                 case 2: /* reserved */
 589                 {
 590                         printk(KERN_WARNING "broken BIOS!!\n");
 591                         trigger = 1;
 592                         break;
 593                 }
 594                 case 3: /* level */
 595                 {
 596                         trigger = 1;
 597                         break;
 598                 }
 599                 default: /* invalid */
 600                 {
 601                         printk(KERN_WARNING "broken BIOS!!\n");
 602                         trigger = 0;
 603                         break;
 604                 }
 605         }
 606         return trigger;
 607 }
 608
 609 static inline int irq_polarity(int idx)
 610 {
 611         return MPBIOS_polarity(idx);
 612 }
 613
 614 static inline int irq_trigger(int idx)
 615 {
 616         return MPBIOS_trigger(idx);
 617 }
 618
 619 static int pin_2_irq(int idx, int apic, int pin)
 620 {
 621         int irq, i;
 622         int bus = mp_irqs[idx].mpc_srcbus;
 623
 624         /*
 625          * Debugging check, we are in big trouble if this message pops up!
 626          */
 627         if (mp_irqs[idx].mpc_dstirq != pin)
 628                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 629
 630         if (test_bit(bus, mp_bus_not_pci)) {
 631                 irq = mp_irqs[idx].mpc_srcbusirq;
 632         } else {
 633                 /*
 634                  * PCI IRQs are mapped in order
 635                  */
 636                 i = irq = 0;
 637                 while (i < apic)
 638                         irq += nr_ioapic_registers[i++];
 639                 irq += pin;
 640         }
 641         BUG_ON(irq >= NR_IRQS);
 642         return irq;
 643 }
 644
 645 static int __assign_irq_vector(int irq, cpumask_t mask)
 646 {
 647         /*
 648          * NOTE! The local APIC isn't very good at handling
 649          * multiple interrupts at the same interrupt level.
 650          * As the interrupt level is determined by taking the
 651          * vector number and shifting that right by 4, we
 652          * want to spread these out a bit so that they don't
 653          * all fall in the same interrupt level.
 654          *
 655          * Also, we've got to be careful not to trash gate
 656          * 0x80, because int 0x80 is hm, kind of importantish. ;)
 657          */
 658         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
 659         unsigned int old_vector;
 660         int cpu;
 661         struct irq_cfg *cfg;
 662
 663         BUG_ON((unsigned)irq >= NR_IRQS);
 664         cfg = &irq_cfg[irq];
 665
 666         /* Only try and allocate irqs on cpus that are present */
 667         cpus_and(mask, mask, cpu_online_map);
 668
 669         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
 670                 return -EBUSY;
 671
 672         old_vector = cfg->vector;
 673         if (old_vector) {
 674                 cpumask_t tmp;
 675                 cpus_and(tmp, cfg->domain, mask);
 676                 if (!cpus_empty(tmp))
 677                         return 0;
 678         }
 679
 680         for_each_cpu_mask(cpu, mask) {
 681                 cpumask_t domain, new_mask;
 682                 int new_cpu;
 683                 int vector, offset;
 684
 685                 domain = vector_allocation_domain(cpu);
 686                 cpus_and(new_mask, domain, cpu_online_map);
 687
 688                 vector = current_vector;
 689                 offset = current_offset;
 690 next:
 691                 vector += 8;
 692                 if (vector >= FIRST_SYSTEM_VECTOR) {
 693                         /* If we run out of vectors on large boxen, must share them. */
 694                         offset = (offset + 1) % 8;
 695                         vector = FIRST_DEVICE_VECTOR + offset;
 696                 }
 697                 if (unlikely(current_vector == vector))
 698                         continue;
 699                 if (vector == IA32_SYSCALL_VECTOR)
 700                         goto next;
 701                 for_each_cpu_mask(new_cpu, new_mask)
 702                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
 703                                 goto next;
 704                 /* Found one! */
 705                 current_vector = vector;
 706                 current_offset = offset;
 707                 if (old_vector) {
 708                         cfg->move_in_progress = 1;
 709                         cfg->old_domain = cfg->domain;
 710                 }
 711                 for_each_cpu_mask(new_cpu, new_mask)
 712                         per_cpu(vector_irq, new_cpu)[vector] = irq;
 713                 cfg->vector = vector;
 714                 cfg->domain = domain;
 715                 return 0;
 716         }
 717         return -ENOSPC;
 718 }
 719
 720 static int assign_irq_vector(int irq, cpumask_t mask)
 721 {
 722         int err;
 723         unsigned long flags;
 724
 725         spin_lock_irqsave(&vector_lock, flags);
 726         err = __assign_irq_vector(irq, mask);
 727         spin_unlock_irqrestore(&vector_lock, flags);
 728         return err;
 729 }
 730
 731 static void __clear_irq_vector(int irq)
 732 {
 733         struct irq_cfg *cfg;
 734         cpumask_t mask;
 735         int cpu, vector;
 736
 737         BUG_ON((unsigned)irq >= NR_IRQS);
 738         cfg = &irq_cfg[irq];
 739         BUG_ON(!cfg->vector);
 740
 741         vector = cfg->vector;
 742         cpus_and(mask, cfg->domain, cpu_online_map);
 743         for_each_cpu_mask(cpu, mask)
 744                 per_cpu(vector_irq, cpu)[vector] = -1;
 745
 746         cfg->vector = 0;
 747         cfg->domain = CPU_MASK_NONE;
 748 }
 749
 750 void __setup_vector_irq(int cpu)
 751 {
 752         /* Initialize vector_irq on a new cpu */
 753         /* This function must be called with vector_lock held */
 754         int irq, vector;
 755
 756         /* Mark the inuse vectors */
 757         for (irq = 0; irq < NR_IRQS; ++irq) {
 758                 if (!cpu_isset(cpu, irq_cfg[irq].domain))
 759                         continue;
 760                 vector = irq_cfg[irq].vector;
 761                 per_cpu(vector_irq, cpu)[vector] = irq;
 762         }
 763         /* Mark the free vectors */
 764         for (vector = 0; vector < NR_VECTORS; ++vector) {
 765                 irq = per_cpu(vector_irq, cpu)[vector];
 766                 if (irq < 0)
 767                         continue;
 768                 if (!cpu_isset(cpu, irq_cfg[irq].domain))
 769                         per_cpu(vector_irq, cpu)[vector] = -1;
 770         }
 771 }
 772
 773
 774 static struct irq_chip ioapic_chip;
 775
 776 static void ioapic_register_intr(int irq, unsigned long trigger)
 777 {
 778         if (trigger)
 779                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 780                                               handle_fasteoi_irq, "fasteoi");
 781         else
 782                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 783                                               handle_edge_irq, "edge");
 784 }
 785
 786 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
 787                               int trigger, int polarity)
 788 {
 789         struct irq_cfg *cfg = irq_cfg + irq;
 790         struct IO_APIC_route_entry entry;
 791         cpumask_t mask;
 792         unsigned long flags;
 793
 794         if (!IO_APIC_IRQ(irq))
 795                 return;
 796
 797         mask = TARGET_CPUS;
 798         if (assign_irq_vector(irq, mask))
 799                 return;
 800
 801         cpus_and(mask, cfg->domain, mask);
 802
 803         apic_printk(APIC_VERBOSE,KERN_DEBUG
 804                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
 805                     "IRQ %d Mode:%i Active:%i)\n",
 806                     apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
 807                     irq, trigger, polarity);
 808
 809         /*
 810          * add it to the IO-APIC irq-routing table:
 811          */
 812         memset(&entry,0,sizeof(entry));
 813
 814         entry.delivery_mode = INT_DELIVERY_MODE;
 815         entry.dest_mode = INT_DEST_MODE;
 816         entry.dest = cpu_mask_to_apicid(mask);
 817         entry.mask = 0;                         /* enable IRQ */
 818         entry.trigger = trigger;
 819         entry.polarity = polarity;
 820         entry.vector = cfg->vector;
 821
 822         /* Mask level triggered irqs.
 823          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
 824          */
 825         if (trigger)
 826                 entry.mask = 1;
 827
 828         ioapic_register_intr(irq, trigger);
 829         if (irq < 16)
 830                 disable_8259A_irq(irq);
 831
 832         ioapic_write_entry(apic, pin, entry);
 833 }
 834
 835 static void __init setup_IO_APIC_irqs(void)
 836 {
 837         int apic, pin, idx, irq, first_notcon = 1;
 838
 839         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 840
 841         for (apic = 0; apic < nr_ioapics; apic++) {
 842         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 843
 844                 idx = find_irq_entry(apic,pin,mp_INT);
 845                 if (idx == -1) {
 846                         if (first_notcon) {
 847                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 848                                 first_notcon = 0;
 849                         } else
 850                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 851                         continue;
 852                 }
 853
 854                 irq = pin_2_irq(idx, apic, pin);
 855                 add_pin_to_irq(irq, apic, pin);
 856
 857                 setup_IO_APIC_irq(apic, pin, irq,
 858                                   irq_trigger(idx), irq_polarity(idx));
 859         }
 860         }
 861
 862         if (!first_notcon)
 863                 apic_printk(APIC_VERBOSE," not connected.\n");
 864 }
 865
 866 /*
 867  * Set up the 8259A-master output pin as broadcast to all
 868  * CPUs.
 869  */
 870 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 871 {
 872         struct IO_APIC_route_entry entry;
 873         unsigned long flags;
 874
 875         memset(&entry,0,sizeof(entry));
 876
 877         disable_8259A_irq(0);
 878
 879         /* mask LVT0 */
 880         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 881
 882         /*
 883          * We use logical delivery to get the timer IRQ
 884          * to the first CPU.
 885          */
 886         entry.dest_mode = INT_DEST_MODE;
 887         entry.mask = 0;                                 /* unmask IRQ now */
 888         entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
 889         entry.delivery_mode = INT_DELIVERY_MODE;
 890         entry.polarity = 0;
 891         entry.trigger = 0;
 892         entry.vector = vector;
 893
 894         /*
 895          * The timer IRQ doesn't have to know that behind the
 896          * scene we have a 8259A-master in AEOI mode ...
 897          */
 898         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
 899
 900         /*
 901          * Add it to the IO-APIC irq-routing table:
 902          */
 903         spin_lock_irqsave(&ioapic_lock, flags);
 904         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 905         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 906         spin_unlock_irqrestore(&ioapic_lock, flags);
 907
 908         enable_8259A_irq(0);
 909 }
 910
 911 void __init UNEXPECTED_IO_APIC(void)
 912 {
 913 }
 914
 915 void __apicdebuginit print_IO_APIC(void)
 916 {
 917         int apic, i;
 918         union IO_APIC_reg_00 reg_00;
 919         union IO_APIC_reg_01 reg_01;
 920         union IO_APIC_reg_02 reg_02;
 921         unsigned long flags;
 922
 923         if (apic_verbosity == APIC_QUIET)
 924                 return;
 925
 926         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 927         for (i = 0; i < nr_ioapics; i++)
 928                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 929                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 930
 931         /*
 932          * We are a bit conservative about what we expect.  We have to
 933          * know about every hardware change ASAP.
 934          */
 935         printk(KERN_INFO "testing the IO APIC.......................\n");
 936
 937         for (apic = 0; apic < nr_ioapics; apic++) {
 938
 939         spin_lock_irqsave(&ioapic_lock, flags);
 940         reg_00.raw = io_apic_read(apic, 0);
 941         reg_01.raw = io_apic_read(apic, 1);
 942         if (reg_01.bits.version >= 0x10)
 943                 reg_02.raw = io_apic_read(apic, 2);
 944         spin_unlock_irqrestore(&ioapic_lock, flags);
 945
 946         printk("\n");
 947         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 948         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 949         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 950         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 951                 UNEXPECTED_IO_APIC();
 952
 953         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 954         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 955         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 956                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 957                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 958                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 959                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 960                 (reg_01.bits.entries != 0x2E) &&
 961                 (reg_01.bits.entries != 0x3F) &&
 962                 (reg_01.bits.entries != 0x03)
 963         )
 964                 UNEXPECTED_IO_APIC();
 965
 966         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 967         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 968         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 969                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 970                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 971                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 972                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 973                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 974         )
 975                 UNEXPECTED_IO_APIC();
 976         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 977                 UNEXPECTED_IO_APIC();
 978
 979         if (reg_01.bits.version >= 0x10) {
 980                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 981                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 982                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 983                         UNEXPECTED_IO_APIC();
 984         }
 985
 986         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 987
 988         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
 989                           " Stat Dmod Deli Vect:   \n");
 990
 991         for (i = 0; i <= reg_01.bits.entries; i++) {
 992                 struct IO_APIC_route_entry entry;
 993
 994                 entry = ioapic_read_entry(apic, i);
 995
 996                 printk(KERN_DEBUG " %02x %03X ",
 997                         i,
 998                         entry.dest
 999                 );
1000
1001                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1002                         entry.mask,
1003                         entry.trigger,
1004                         entry.irr,
1005                         entry.polarity,
1006                         entry.delivery_status,
1007                         entry.dest_mode,
1008                         entry.delivery_mode,
1009                         entry.vector
1010                 );
1011         }
1012         }
1013         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1014         for (i = 0; i < NR_IRQS; i++) {
1015                 struct irq_pin_list *entry = irq_2_pin + i;
1016                 if (entry->pin < 0)
1017                         continue;
1018                 printk(KERN_DEBUG "IRQ%d ", i);
1019                 for (;;) {
1020                         printk("-> %d:%d", entry->apic, entry->pin);
1021                         if (!entry->next)
1022                                 break;
1023                         entry = irq_2_pin + entry->next;
1024                 }
1025                 printk("\n");
1026         }
1027
1028         printk(KERN_INFO ".................................... done.\n");
1029
1030         return;
1031 }
1032
1033 #if 0
1034
1035 static __apicdebuginit void print_APIC_bitfield (int base)
1036 {
1037         unsigned int v;
1038         int i, j;
1039
1040         if (apic_verbosity == APIC_QUIET)
1041                 return;
1042
1043         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1044         for (i = 0; i < 8; i++) {
1045                 v = apic_read(base + i*0x10);
1046                 for (j = 0; j < 32; j++) {
1047                         if (v & (1<<j))
1048                                 printk("1");
1049                         else
1050                                 printk("0");
1051                 }
1052                 printk("\n");
1053         }
1054 }
1055
1056 void __apicdebuginit print_local_APIC(void * dummy)
1057 {
1058         unsigned int v, ver, maxlvt;
1059
1060         if (apic_verbosity == APIC_QUIET)
1061                 return;
1062
1063         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1064                 smp_processor_id(), hard_smp_processor_id());
1065         v = apic_read(APIC_ID);
1066         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1067         v = apic_read(APIC_LVR);
1068         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1069         ver = GET_APIC_VERSION(v);
1070         maxlvt = get_maxlvt();
1071
1072         v = apic_read(APIC_TASKPRI);
1073         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1074
1075         v = apic_read(APIC_ARBPRI);
1076         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1077                 v & APIC_ARBPRI_MASK);
1078         v = apic_read(APIC_PROCPRI);
1079         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1080
1081         v = apic_read(APIC_EOI);
1082         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1083         v = apic_read(APIC_RRR);
1084         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1085         v = apic_read(APIC_LDR);
1086         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1087         v = apic_read(APIC_DFR);
1088         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1089         v = apic_read(APIC_SPIV);
1090         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1091
1092         printk(KERN_DEBUG "... APIC ISR field:\n");
1093         print_APIC_bitfield(APIC_ISR);
1094         printk(KERN_DEBUG "... APIC TMR field:\n");
1095         print_APIC_bitfield(APIC_TMR);
1096         printk(KERN_DEBUG "... APIC IRR field:\n");
1097         print_APIC_bitfield(APIC_IRR);
1098
1099         v = apic_read(APIC_ESR);
1100         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1101
1102         v = apic_read(APIC_ICR);
1103         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1104         v = apic_read(APIC_ICR2);
1105         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1106
1107         v = apic_read(APIC_LVTT);
1108         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1109
1110         if (maxlvt > 3) {                       /* PC is LVT#4. */
1111                 v = apic_read(APIC_LVTPC);
1112                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1113         }
1114         v = apic_read(APIC_LVT0);
1115         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1116         v = apic_read(APIC_LVT1);
1117         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1118
1119         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1120                 v = apic_read(APIC_LVTERR);
1121                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1122         }
1123
1124         v = apic_read(APIC_TMICT);
1125         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1126         v = apic_read(APIC_TMCCT);
1127         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1128         v = apic_read(APIC_TDCR);
1129         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1130         printk("\n");
1131 }
1132
1133 void print_all_local_APICs (void)
1134 {
1135         on_each_cpu(print_local_APIC, NULL, 1, 1);
1136 }
1137
1138 void __apicdebuginit print_PIC(void)
1139 {
1140         unsigned int v;
1141         unsigned long flags;
1142
1143         if (apic_verbosity == APIC_QUIET)
1144                 return;
1145
1146         printk(KERN_DEBUG "\nprinting PIC contents\n");
1147
1148         spin_lock_irqsave(&i8259A_lock, flags);
1149
1150         v = inb(0xa1) << 8 | inb(0x21);
1151         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1152
1153         v = inb(0xa0) << 8 | inb(0x20);
1154         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1155
1156         outb(0x0b,0xa0);
1157         outb(0x0b,0x20);
1158         v = inb(0xa0) << 8 | inb(0x20);
1159         outb(0x0a,0xa0);
1160         outb(0x0a,0x20);
1161
1162         spin_unlock_irqrestore(&i8259A_lock, flags);
1163
1164         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1165
1166         v = inb(0x4d1) << 8 | inb(0x4d0);
1167         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1168 }
1169
1170 #endif  /*  0  */
1171
1172 static void __init enable_IO_APIC(void)
1173 {
1174         union IO_APIC_reg_01 reg_01;
1175         int i8259_apic, i8259_pin;
1176         int i, apic;
1177         unsigned long flags;
1178
1179         for (i = 0; i < PIN_MAP_SIZE; i++) {
1180                 irq_2_pin[i].pin = -1;
1181                 irq_2_pin[i].next = 0;
1182         }
1183
1184         /*
1185          * The number of IO-APIC IRQ registers (== #pins):
1186          */
1187         for (apic = 0; apic < nr_ioapics; apic++) {
1188                 spin_lock_irqsave(&ioapic_lock, flags);
1189                 reg_01.raw = io_apic_read(apic, 1);
1190                 spin_unlock_irqrestore(&ioapic_lock, flags);
1191                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1192         }
1193         for(apic = 0; apic < nr_ioapics; apic++) {
1194                 int pin;
1195                 /* See if any of the pins is in ExtINT mode */
1196                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1197                         struct IO_APIC_route_entry entry;
1198                         entry = ioapic_read_entry(apic, pin);
1199
1200                         /* If the interrupt line is enabled and in ExtInt mode
1201                          * I have found the pin where the i8259 is connected.
1202                          */
1203                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1204                                 ioapic_i8259.apic = apic;
1205                                 ioapic_i8259.pin  = pin;
1206                                 goto found_i8259;
1207                         }
1208                 }
1209         }
1210  found_i8259:
1211         /* Look to see what if the MP table has reported the ExtINT */
1212         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1213         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1214         /* Trust the MP table if nothing is setup in the hardware */
1215         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1216                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1217                 ioapic_i8259.pin  = i8259_pin;
1218                 ioapic_i8259.apic = i8259_apic;
1219         }
1220         /* Complain if the MP table and the hardware disagree */
1221         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1222                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1223         {
1224                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1225         }
1226
1227         /*
1228          * Do not trust the IO-APIC being empty at bootup
1229          */
1230         clear_IO_APIC();
1231 }
1232
1233 /*
1234  * Not an __init, needed by the reboot code
1235  */
1236 void disable_IO_APIC(void)
1237 {
1238         /*
1239          * Clear the IO-APIC before rebooting:
1240          */
1241         clear_IO_APIC();
1242
1243         /*
1244          * If the i8259 is routed through an IOAPIC
1245          * Put that IOAPIC in virtual wire mode
1246          * so legacy interrupts can be delivered.
1247          */
1248         if (ioapic_i8259.pin != -1) {
1249                 struct IO_APIC_route_entry entry;
1250
1251                 memset(&entry, 0, sizeof(entry));
1252                 entry.mask            = 0; /* Enabled */
1253                 entry.trigger         = 0; /* Edge */
1254                 entry.irr             = 0;
1255                 entry.polarity        = 0; /* High */
1256                 entry.delivery_status = 0;
1257                 entry.dest_mode       = 0; /* Physical */
1258                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1259                 entry.vector          = 0;
1260                 entry.dest          = GET_APIC_ID(apic_read(APIC_ID));
1261
1262                 /*
1263                  * Add it to the IO-APIC irq-routing table:
1264                  */
1265                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1266         }
1267
1268         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1269 }
1270
1271 /*
1272  * There is a nasty bug in some older SMP boards, their mptable lies
1273  * about the timer IRQ. We do the following to work around the situation:
1274  *
1275  *      - timer IRQ defaults to IO-APIC IRQ
1276  *      - if this function detects that timer IRQs are defunct, then we fall
1277  *        back to ISA timer IRQs
1278  */
1279 static int __init timer_irq_works(void)
1280 {
1281         unsigned long t1 = jiffies;
1282
1283         local_irq_enable();
1284         /* Let ten ticks pass... */
1285         mdelay((10 * 1000) / HZ);
1286
1287         /*
1288          * Expect a few ticks at least, to be sure some possible
1289          * glue logic does not lock up after one or two first
1290          * ticks in a non-ExtINT mode.  Also the local APIC
1291          * might have cached one ExtINT interrupt.  Finally, at
1292          * least one tick may be lost due to delays.
1293          */
1294
1295         /* jiffies wrap? */
1296         if (jiffies - t1 > 4)
1297                 return 1;
1298         return 0;
1299 }
1300
1301 /*
1302  * In the SMP+IOAPIC case it might happen that there are an unspecified
1303  * number of pending IRQ events unhandled. These cases are very rare,
1304  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1305  * better to do it this way as thus we do not have to be aware of
1306  * 'pending' interrupts in the IRQ path, except at this point.
1307  */
1308 /*
1309  * Edge triggered needs to resend any interrupt
1310  * that was delayed but this is now handled in the device
1311  * independent code.
1312  */
1313
1314 /*
1315  * Starting up a edge-triggered IO-APIC interrupt is
1316  * nasty - we need to make sure that we get the edge.
1317  * If it is already asserted for some reason, we need
1318  * return 1 to indicate that is was pending.
1319  *
1320  * This is not complete - we should be able to fake
1321  * an edge even if it isn't on the 8259A...
1322  */
1323
1324 static unsigned int startup_ioapic_irq(unsigned int irq)
1325 {
1326         int was_pending = 0;
1327         unsigned long flags;
1328
1329         spin_lock_irqsave(&ioapic_lock, flags);
1330         if (irq < 16) {
1331                 disable_8259A_irq(irq);
1332                 if (i8259A_irq_pending(irq))
1333                         was_pending = 1;
1334         }
1335         __unmask_IO_APIC_irq(irq);
1336         spin_unlock_irqrestore(&ioapic_lock, flags);
1337
1338         return was_pending;
1339 }
1340
1341 static int ioapic_retrigger_irq(unsigned int irq)
1342 {
1343         struct irq_cfg *cfg = &irq_cfg[irq];
1344         cpumask_t mask;
1345         unsigned long flags;
1346
1347         spin_lock_irqsave(&vector_lock, flags);
1348         cpus_clear(mask);
1349         cpu_set(first_cpu(cfg->domain), mask);
1350
1351         send_IPI_mask(mask, cfg->vector);
1352         spin_unlock_irqrestore(&vector_lock, flags);
1353
1354         return 1;
1355 }
1356
1357 /*
1358  * Level and edge triggered IO-APIC interrupts need different handling,
1359  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1360  * handled with the level-triggered descriptor, but that one has slightly
1361  * more overhead. Level-triggered interrupts cannot be handled with the
1362  * edge-triggered handler, without risking IRQ storms and other ugly
1363  * races.
1364  */
1365
1366 #ifdef CONFIG_SMP
1367 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1368 {
1369         unsigned vector, me;
1370         ack_APIC_irq();
1371         exit_idle();
1372         irq_enter();
1373
1374         me = smp_processor_id();
1375         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1376                 unsigned int irq;
1377                 struct irq_desc *desc;
1378                 struct irq_cfg *cfg;
1379                 irq = __get_cpu_var(vector_irq)[vector];
1380                 if (irq >= NR_IRQS)
1381                         continue;
1382
1383                 desc = irq_desc + irq;
1384                 cfg = irq_cfg + irq;
1385                 spin_lock(&desc->lock);
1386                 if (!cfg->move_cleanup_count)
1387                         goto unlock;
1388
1389                 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1390                         goto unlock;
1391
1392                 __get_cpu_var(vector_irq)[vector] = -1;
1393                 cfg->move_cleanup_count--;
1394 unlock:
1395                 spin_unlock(&desc->lock);
1396         }
1397
1398         irq_exit();
1399 }
1400
1401 static void irq_complete_move(unsigned int irq)
1402 {
1403         struct irq_cfg *cfg = irq_cfg + irq;
1404         unsigned vector, me;
1405
1406         if (likely(!cfg->move_in_progress))
1407                 return;
1408
1409         vector = ~get_irq_regs()->orig_rax;
1410         me = smp_processor_id();
1411         if ((vector == cfg->vector) &&
1412             cpu_isset(smp_processor_id(), cfg->domain)) {
1413                 cpumask_t cleanup_mask;
1414
1415                 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1416                 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1417                 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1418                 cfg->move_in_progress = 0;
1419         }
1420 }
1421 #else
1422 static inline void irq_complete_move(unsigned int irq) {}
1423 #endif
1424
1425 static void ack_apic_edge(unsigned int irq)
1426 {
1427         irq_complete_move(irq);
1428         move_native_irq(irq);
1429         ack_APIC_irq();
1430 }
1431
1432 static void ack_apic_level(unsigned int irq)
1433 {
1434         int do_unmask_irq = 0;
1435
1436         irq_complete_move(irq);
1437 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1438         /* If we are moving the irq we need to mask it */
1439         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1440                 do_unmask_irq = 1;
1441                 mask_IO_APIC_irq(irq);
1442         }
1443 #endif
1444
1445         /*
1446          * We must acknowledge the irq before we move it or the acknowledge will
1447          * not propogate properly.
1448          */
1449         ack_APIC_irq();
1450
1451         /* Now we can move and renable the irq */
1452         move_masked_irq(irq);
1453         if (unlikely(do_unmask_irq))
1454                 unmask_IO_APIC_irq(irq);
1455 }
1456
1457 static struct irq_chip ioapic_chip __read_mostly = {
1458         .name           = "IO-APIC",
1459         .startup        = startup_ioapic_irq,
1460         .mask           = mask_IO_APIC_irq,
1461         .unmask         = unmask_IO_APIC_irq,
1462         .ack            = ack_apic_edge,
1463         .eoi            = ack_apic_level,
1464 #ifdef CONFIG_SMP
1465         .set_affinity   = set_ioapic_affinity_irq,
1466 #endif
1467         .retrigger      = ioapic_retrigger_irq,
1468 };
1469
1470 static inline void init_IO_APIC_traps(void)
1471 {
1472         int irq;
1473
1474         /*
1475          * NOTE! The local APIC isn't very good at handling
1476          * multiple interrupts at the same interrupt level.
1477          * As the interrupt level is determined by taking the
1478          * vector number and shifting that right by 4, we
1479          * want to spread these out a bit so that they don't
1480          * all fall in the same interrupt level.
1481          *
1482          * Also, we've got to be careful not to trash gate
1483          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1484          */
1485         for (irq = 0; irq < NR_IRQS ; irq++) {
1486                 int tmp = irq;
1487                 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1488                         /*
1489                          * Hmm.. We don't have an entry for this,
1490                          * so default to an old-fashioned 8259
1491                          * interrupt if we can..
1492                          */
1493                         if (irq < 16)
1494                                 make_8259A_irq(irq);
1495                         else
1496                                 /* Strange. Oh, well.. */
1497                                 irq_desc[irq].chip = &no_irq_chip;
1498                 }
1499         }
1500 }
1501
1502 static void enable_lapic_irq (unsigned int irq)
1503 {
1504         unsigned long v;
1505
1506         v = apic_read(APIC_LVT0);
1507         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1508 }
1509
1510 static void disable_lapic_irq (unsigned int irq)
1511 {
1512         unsigned long v;
1513
1514         v = apic_read(APIC_LVT0);
1515         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1516 }
1517
1518 static void ack_lapic_irq (unsigned int irq)
1519 {
1520         ack_APIC_irq();
1521 }
1522
1523 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1524
1525 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1526         .typename = "local-APIC-edge",
1527         .startup = NULL, /* startup_irq() not used for IRQ0 */
1528         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1529         .enable = enable_lapic_irq,
1530         .disable = disable_lapic_irq,
1531         .ack = ack_lapic_irq,
1532         .end = end_lapic_irq,
1533 };
1534
1535 static void setup_nmi (void)
1536 {
1537         /*
1538          * Dirty trick to enable the NMI watchdog ...
1539          * We put the 8259A master into AEOI mode and
1540          * unmask on all local APICs LVT0 as NMI.
1541          *
1542          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1543          * is from Maciej W. Rozycki - so we do not have to EOI from
1544          * the NMI handler or the timer interrupt.
1545          */
1546         printk(KERN_INFO "activating NMI Watchdog ...");
1547
1548         enable_NMI_through_LVT0(NULL);
1549
1550         printk(" done.\n");
1551 }
1552
1553 /*
1554  * This looks a bit hackish but it's about the only one way of sending
1555  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1556  * not support the ExtINT mode, unfortunately.  We need to send these
1557  * cycles as some i82489DX-based boards have glue logic that keeps the
1558  * 8259A interrupt line asserted until INTA.  --macro
1559  */
1560 static inline void unlock_ExtINT_logic(void)
1561 {
1562         int apic, pin, i;
1563         struct IO_APIC_route_entry entry0, entry1;
1564         unsigned char save_control, save_freq_select;
1565         unsigned long flags;
1566
1567         pin  = find_isa_irq_pin(8, mp_INT);
1568         apic = find_isa_irq_apic(8, mp_INT);
1569         if (pin == -1)
1570                 return;
1571
1572         spin_lock_irqsave(&ioapic_lock, flags);
1573         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1574         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1575         spin_unlock_irqrestore(&ioapic_lock, flags);
1576         clear_IO_APIC_pin(apic, pin);
1577
1578         memset(&entry1, 0, sizeof(entry1));
1579
1580         entry1.dest_mode = 0;                   /* physical delivery */
1581         entry1.mask = 0;                        /* unmask IRQ now */
1582         entry1.dest = hard_smp_processor_id();
1583         entry1.delivery_mode = dest_ExtINT;
1584         entry1.polarity = entry0.polarity;
1585         entry1.trigger = 0;
1586         entry1.vector = 0;
1587
1588         spin_lock_irqsave(&ioapic_lock, flags);
1589         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1590         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1591         spin_unlock_irqrestore(&ioapic_lock, flags);
1592
1593         save_control = CMOS_READ(RTC_CONTROL);
1594         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1595         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1596                    RTC_FREQ_SELECT);
1597         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1598
1599         i = 100;
1600         while (i-- > 0) {
1601                 mdelay(10);
1602                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1603                         i -= 10;
1604         }
1605
1606         CMOS_WRITE(save_control, RTC_CONTROL);
1607         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1608         clear_IO_APIC_pin(apic, pin);
1609
1610         spin_lock_irqsave(&ioapic_lock, flags);
1611         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1612         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1613         spin_unlock_irqrestore(&ioapic_lock, flags);
1614 }
1615
1616 /*
1617  * This code may look a bit paranoid, but it's supposed to cooperate with
1618  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1619  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1620  * fanatically on his truly buggy board.
1621  *
1622  * FIXME: really need to revamp this for modern platforms only.
1623  */
1624 static inline void check_timer(void)
1625 {
1626         struct irq_cfg *cfg = irq_cfg + 0;
1627         int apic1, pin1, apic2, pin2;
1628
1629         /*
1630          * get/set the timer IRQ vector:
1631          */
1632         disable_8259A_irq(0);
1633         assign_irq_vector(0, TARGET_CPUS);
1634
1635         /*
1636          * Subtle, code in do_timer_interrupt() expects an AEOI
1637          * mode for the 8259A whenever interrupts are routed
1638          * through I/O APICs.  Also IRQ0 has to be enabled in
1639          * the 8259A which implies the virtual wire has to be
1640          * disabled in the local APIC.
1641          */
1642         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1643         init_8259A(1);
1644         if (timer_over_8254 > 0)
1645                 enable_8259A_irq(0);
1646
1647         pin1  = find_isa_irq_pin(0, mp_INT);
1648         apic1 = find_isa_irq_apic(0, mp_INT);
1649         pin2  = ioapic_i8259.pin;
1650         apic2 = ioapic_i8259.apic;
1651
1652         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1653                 cfg->vector, apic1, pin1, apic2, pin2);
1654
1655         if (pin1 != -1) {
1656                 /*
1657                  * Ok, does IRQ0 through the IOAPIC work?
1658                  */
1659                 unmask_IO_APIC_irq(0);
1660                 if (!no_timer_check && timer_irq_works()) {
1661                         nmi_watchdog_default();
1662                         if (nmi_watchdog == NMI_IO_APIC) {
1663                                 disable_8259A_irq(0);
1664                                 setup_nmi();
1665                                 enable_8259A_irq(0);
1666                         }
1667                         if (disable_timer_pin_1 > 0)
1668                                 clear_IO_APIC_pin(0, pin1);
1669                         return;
1670                 }
1671                 clear_IO_APIC_pin(apic1, pin1);
1672                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1673                                 "connected to IO-APIC\n");
1674         }
1675
1676         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1677                                 "through the 8259A ... ");
1678         if (pin2 != -1) {
1679                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1680                         apic2, pin2);
1681                 /*
1682                  * legacy devices should be connected to IO APIC #0
1683                  */
1684                 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1685                 if (timer_irq_works()) {
1686                         apic_printk(APIC_VERBOSE," works.\n");
1687                         nmi_watchdog_default();
1688                         if (nmi_watchdog == NMI_IO_APIC) {
1689                                 setup_nmi();
1690                         }
1691                         return;
1692                 }
1693                 /*
1694                  * Cleanup, just in case ...
1695                  */
1696                 clear_IO_APIC_pin(apic2, pin2);
1697         }
1698         apic_printk(APIC_VERBOSE," failed.\n");
1699
1700         if (nmi_watchdog == NMI_IO_APIC) {
1701                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1702                 nmi_watchdog = 0;
1703         }
1704
1705         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1706
1707         disable_8259A_irq(0);
1708         irq_desc[0].chip = &lapic_irq_type;
1709         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
1710         enable_8259A_irq(0);
1711
1712         if (timer_irq_works()) {
1713                 apic_printk(APIC_VERBOSE," works.\n");
1714                 return;
1715         }
1716         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1717         apic_printk(APIC_VERBOSE," failed.\n");
1718
1719         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1720
1721         init_8259A(0);
1722         make_8259A_irq(0);
1723         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1724
1725         unlock_ExtINT_logic();
1726
1727         if (timer_irq_works()) {
1728                 apic_printk(APIC_VERBOSE," works.\n");
1729                 return;
1730         }
1731         apic_printk(APIC_VERBOSE," failed :(.\n");
1732         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1733 }
1734
1735 static int __init notimercheck(char *s)
1736 {
1737         no_timer_check = 1;
1738         return 1;
1739 }
1740 __setup("no_timer_check", notimercheck);
1741
1742 /*
1743  *
1744  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1745  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1746  *   Linux doesn't really care, as it's not actually used
1747  *   for any interrupt handling anyway.
1748  */
1749 #define PIC_IRQS        (1<<2)
1750
1751 void __init setup_IO_APIC(void)
1752 {
1753         enable_IO_APIC();
1754
1755         if (acpi_ioapic)
1756                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1757         else
1758                 io_apic_irqs = ~PIC_IRQS;
1759
1760         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1761
1762         sync_Arb_IDs();
1763         setup_IO_APIC_irqs();
1764         init_IO_APIC_traps();
1765         check_timer();
1766         if (!acpi_ioapic)
1767                 print_IO_APIC();
1768 }
1769
1770 struct sysfs_ioapic_data {
1771         struct sys_device dev;
1772         struct IO_APIC_route_entry entry[0];
1773 };
1774 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1775
1776 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1777 {
1778         struct IO_APIC_route_entry *entry;
1779         struct sysfs_ioapic_data *data;
1780         int i;
1781
1782         data = container_of(dev, struct sysfs_ioapic_data, dev);
1783         entry = data->entry;
1784         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1785                 *entry = ioapic_read_entry(dev->id, i);
1786
1787         return 0;
1788 }
1789
1790 static int ioapic_resume(struct sys_device *dev)
1791 {
1792         struct IO_APIC_route_entry *entry;
1793         struct sysfs_ioapic_data *data;
1794         unsigned long flags;
1795         union IO_APIC_reg_00 reg_00;
1796         int i;
1797
1798         data = container_of(dev, struct sysfs_ioapic_data, dev);
1799         entry = data->entry;
1800
1801         spin_lock_irqsave(&ioapic_lock, flags);
1802         reg_00.raw = io_apic_read(dev->id, 0);
1803         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1804                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1805                 io_apic_write(dev->id, 0, reg_00.raw);
1806         }
1807         spin_unlock_irqrestore(&ioapic_lock, flags);
1808         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1809                 ioapic_write_entry(dev->id, i, entry[i]);
1810
1811         return 0;
1812 }
1813
1814 static struct sysdev_class ioapic_sysdev_class = {
1815         set_kset_name("ioapic"),
1816         .suspend = ioapic_suspend,
1817         .resume = ioapic_resume,
1818 };
1819
1820 static int __init ioapic_init_sysfs(void)
1821 {
1822         struct sys_device * dev;
1823         int i, size, error = 0;
1824
1825         error = sysdev_class_register(&ioapic_sysdev_class);
1826         if (error)
1827                 return error;
1828
1829         for (i = 0; i < nr_ioapics; i++ ) {
1830                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1831                         * sizeof(struct IO_APIC_route_entry);
1832                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1833                 if (!mp_ioapic_data[i]) {
1834                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1835                         continue;
1836                 }
1837                 memset(mp_ioapic_data[i], 0, size);
1838                 dev = &mp_ioapic_data[i]->dev;
1839                 dev->id = i;
1840                 dev->cls = &ioapic_sysdev_class;
1841                 error = sysdev_register(dev);
1842                 if (error) {
1843                         kfree(mp_ioapic_data[i]);
1844                         mp_ioapic_data[i] = NULL;
1845                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1846                         continue;
1847                 }
1848         }
1849
1850         return 0;
1851 }
1852
1853 device_initcall(ioapic_init_sysfs);
1854
1855 /*
1856  * Dynamic irq allocate and deallocation
1857  */
1858 int create_irq(void)
1859 {
1860         /* Allocate an unused irq */
1861         int irq;
1862         int new;
1863         unsigned long flags;
1864
1865         irq = -ENOSPC;
1866         spin_lock_irqsave(&vector_lock, flags);
1867         for (new = (NR_IRQS - 1); new >= 0; new--) {
1868                 if (platform_legacy_irq(new))
1869                         continue;
1870                 if (irq_cfg[new].vector != 0)
1871                         continue;
1872                 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1873                         irq = new;
1874                 break;
1875         }
1876         spin_unlock_irqrestore(&vector_lock, flags);
1877
1878         if (irq >= 0) {
1879                 dynamic_irq_init(irq);
1880         }
1881         return irq;
1882 }
1883
1884 void destroy_irq(unsigned int irq)
1885 {
1886         unsigned long flags;
1887
1888         dynamic_irq_cleanup(irq);
1889
1890         spin_lock_irqsave(&vector_lock, flags);
1891         __clear_irq_vector(irq);
1892         spin_unlock_irqrestore(&vector_lock, flags);
1893 }
1894
1895 /*
1896  * MSI mesage composition
1897  */
1898 #ifdef CONFIG_PCI_MSI
1899 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1900 {
1901         struct irq_cfg *cfg = irq_cfg + irq;
1902         int err;
1903         unsigned dest;
1904         cpumask_t tmp;
1905
1906         tmp = TARGET_CPUS;
1907         err = assign_irq_vector(irq, tmp);
1908         if (!err) {
1909                 cpus_and(tmp, cfg->domain, tmp);
1910                 dest = cpu_mask_to_apicid(tmp);
1911
1912                 msg->address_hi = MSI_ADDR_BASE_HI;
1913                 msg->address_lo =
1914                         MSI_ADDR_BASE_LO |
1915                         ((INT_DEST_MODE == 0) ?
1916                                 MSI_ADDR_DEST_MODE_PHYSICAL:
1917                                 MSI_ADDR_DEST_MODE_LOGICAL) |
1918                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1919                                 MSI_ADDR_REDIRECTION_CPU:
1920                                 MSI_ADDR_REDIRECTION_LOWPRI) |
1921                         MSI_ADDR_DEST_ID(dest);
1922
1923                 msg->data =
1924                         MSI_DATA_TRIGGER_EDGE |
1925                         MSI_DATA_LEVEL_ASSERT |
1926                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1927                                 MSI_DATA_DELIVERY_FIXED:
1928                                 MSI_DATA_DELIVERY_LOWPRI) |
1929                         MSI_DATA_VECTOR(cfg->vector);
1930         }
1931         return err;
1932 }
1933
1934 #ifdef CONFIG_SMP
1935 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1936 {
1937         struct irq_cfg *cfg = irq_cfg + irq;
1938         struct msi_msg msg;
1939         unsigned int dest;
1940         cpumask_t tmp;
1941
1942         cpus_and(tmp, mask, cpu_online_map);
1943         if (cpus_empty(tmp))
1944                 return;
1945
1946         if (assign_irq_vector(irq, mask))
1947                 return;
1948
1949         cpus_and(tmp, cfg->domain, mask);
1950         dest = cpu_mask_to_apicid(tmp);
1951
1952         read_msi_msg(irq, &msg);
1953
1954         msg.data &= ~MSI_DATA_VECTOR_MASK;
1955         msg.data |= MSI_DATA_VECTOR(cfg->vector);
1956         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1957         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1958
1959         write_msi_msg(irq, &msg);
1960         irq_desc[irq].affinity = mask;
1961 }
1962 #endif /* CONFIG_SMP */
1963
1964 /*
1965  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1966  * which implement the MSI or MSI-X Capability Structure.
1967  */
1968 static struct irq_chip msi_chip = {
1969         .name           = "PCI-MSI",
1970         .unmask         = unmask_msi_irq,
1971         .mask           = mask_msi_irq,
1972         .ack            = ack_apic_edge,
1973 #ifdef CONFIG_SMP
1974         .set_affinity   = set_msi_irq_affinity,
1975 #endif
1976         .retrigger      = ioapic_retrigger_irq,
1977 };
1978
1979 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
1980 {
1981         struct msi_msg msg;
1982         int irq, ret;
1983         irq = create_irq();
1984         if (irq < 0)
1985                 return irq;
1986
1987         set_irq_msi(irq, desc);
1988         ret = msi_compose_msg(dev, irq, &msg);
1989         if (ret < 0) {
1990                 destroy_irq(irq);
1991                 return ret;
1992         }
1993
1994         write_msi_msg(irq, &msg);
1995
1996         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1997
1998         return irq;
1999 }
2000
2001 void arch_teardown_msi_irq(unsigned int irq)
2002 {
2003         destroy_irq(irq);
2004 }
2005
2006 #endif /* CONFIG_PCI_MSI */
2007
2008 /*
2009  * Hypertransport interrupt support
2010  */
2011 #ifdef CONFIG_HT_IRQ
2012
2013 #ifdef CONFIG_SMP
2014
2015 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2016 {
2017         struct ht_irq_msg msg;
2018         fetch_ht_irq_msg(irq, &msg);
2019
2020         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2021         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2022
2023         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2024         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2025
2026         write_ht_irq_msg(irq, &msg);
2027 }
2028
2029 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2030 {
2031         struct irq_cfg *cfg = irq_cfg + irq;
2032         unsigned int dest;
2033         cpumask_t tmp;
2034
2035         cpus_and(tmp, mask, cpu_online_map);
2036         if (cpus_empty(tmp))
2037                 return;
2038
2039         if (assign_irq_vector(irq, mask))
2040                 return;
2041
2042         cpus_and(tmp, cfg->domain, mask);
2043         dest = cpu_mask_to_apicid(tmp);
2044
2045         target_ht_irq(irq, dest, cfg->vector);
2046         irq_desc[irq].affinity = mask;
2047 }
2048 #endif
2049
2050 static struct irq_chip ht_irq_chip = {
2051         .name           = "PCI-HT",
2052         .mask           = mask_ht_irq,
2053         .unmask         = unmask_ht_irq,
2054         .ack            = ack_apic_edge,
2055 #ifdef CONFIG_SMP
2056         .set_affinity   = set_ht_irq_affinity,
2057 #endif
2058         .retrigger      = ioapic_retrigger_irq,
2059 };
2060
2061 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2062 {
2063         struct irq_cfg *cfg = irq_cfg + irq;
2064         int err;
2065         cpumask_t tmp;
2066
2067         tmp = TARGET_CPUS;
2068         err = assign_irq_vector(irq, tmp);
2069         if (!err) {
2070                 struct ht_irq_msg msg;
2071                 unsigned dest;
2072
2073                 cpus_and(tmp, cfg->domain, tmp);
2074                 dest = cpu_mask_to_apicid(tmp);
2075
2076                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2077
2078                 msg.address_lo =
2079                         HT_IRQ_LOW_BASE |
2080                         HT_IRQ_LOW_DEST_ID(dest) |
2081                         HT_IRQ_LOW_VECTOR(cfg->vector) |
2082                         ((INT_DEST_MODE == 0) ?
2083                                 HT_IRQ_LOW_DM_PHYSICAL :
2084                                 HT_IRQ_LOW_DM_LOGICAL) |
2085                         HT_IRQ_LOW_RQEOI_EDGE |
2086                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2087                                 HT_IRQ_LOW_MT_FIXED :
2088                                 HT_IRQ_LOW_MT_ARBITRATED) |
2089                         HT_IRQ_LOW_IRQ_MASKED;
2090
2091                 write_ht_irq_msg(irq, &msg);
2092
2093                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2094                                               handle_edge_irq, "edge");
2095         }
2096         return err;
2097 }
2098 #endif /* CONFIG_HT_IRQ */
2099
2100 /* --------------------------------------------------------------------------
2101                           ACPI-based IOAPIC Configuration
2102    -------------------------------------------------------------------------- */
2103
2104 #ifdef CONFIG_ACPI
2105
2106 #define IO_APIC_MAX_ID          0xFE
2107
2108 int __init io_apic_get_redir_entries (int ioapic)
2109 {
2110         union IO_APIC_reg_01    reg_01;
2111         unsigned long flags;
2112
2113         spin_lock_irqsave(&ioapic_lock, flags);
2114         reg_01.raw = io_apic_read(ioapic, 1);
2115         spin_unlock_irqrestore(&ioapic_lock, flags);
2116
2117         return reg_01.bits.entries;
2118 }
2119
2120
2121 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2122 {
2123         if (!IO_APIC_IRQ(irq)) {
2124                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2125                         ioapic);
2126                 return -EINVAL;
2127         }
2128
2129         /*
2130          * IRQs < 16 are already in the irq_2_pin[] map
2131          */
2132         if (irq >= 16)
2133                 add_pin_to_irq(irq, ioapic, pin);
2134
2135         setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2136
2137         return 0;
2138 }
2139
2140 #endif /* CONFIG_ACPI */
2141
2142
2143 /*
2144  * This function currently is only a helper for the i386 smp boot process where
2145  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2146  * so mask in all cases should simply be TARGET_CPUS
2147  */
2148 #ifdef CONFIG_SMP
2149 void __init setup_ioapic_dest(void)
2150 {
2151         int pin, ioapic, irq, irq_entry;
2152
2153         if (skip_ioapic_setup == 1)
2154                 return;
2155
2156         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2157                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2158                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2159                         if (irq_entry == -1)
2160                                 continue;
2161                         irq = pin_2_irq(irq_entry, ioapic, pin);
2162
2163                         /* setup_IO_APIC_irqs could fail to get vector for some device
2164                          * when you have too many devices, because at that time only boot
2165                          * cpu is online.
2166                          */
2167                         if (!irq_cfg[irq].vector)
2168                                 setup_IO_APIC_irq(ioapic, pin, irq,
2169                                                   irq_trigger(irq_entry),
2170                                                   irq_polarity(irq_entry));
2171                         else
2172                                 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2173                 }
2174
2175         }
2176 }
2177 #endif