arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/pci.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/msi.h>
  34 #include <linux/htirq.h>
  35 #ifdef CONFIG_ACPI
  36 #include <acpi/acpi_bus.h>
  37 #endif
  38
  39 #include <asm/io.h>
  40 #include <asm/smp.h>
  41 #include <asm/desc.h>
  42 #include <asm/proto.h>
  43 #include <asm/mach_apic.h>
  44 #include <asm/acpi.h>
  45 #include <asm/dma.h>
  46 #include <asm/nmi.h>
  47 #include <asm/msidef.h>
  48 #include <asm/hypertransport.h>
  49
  50 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
  51
  52 #define __apicdebuginit  __init
  53
  54 int sis_apic_bug; /* not actually supported, dummy for compile */
  55
  56 static int no_timer_check;
  57
  58 static int disable_timer_pin_1 __initdata;
  59
  60 int timer_over_8254 __initdata = 1;
  61
  62 /* Where if anywhere is the i8259 connect in external int mode */
  63 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  64
  65 static DEFINE_SPINLOCK(ioapic_lock);
  66 DEFINE_SPINLOCK(vector_lock);
  67
  68 /*
  69  * # of IRQ routing registers
  70  */
  71 int nr_ioapic_registers[MAX_IO_APICS];
  72
  73 /*
  74  * Rough estimation of how many shared IRQs there are, can
  75  * be changed anytime.
  76  */
  77 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  79
  80 /*
  81  * This is performance-critical, we want to do it O(1)
  82  *
  83  * the indexing order of this array favors 1:1 mappings
  84  * between pins and IRQs.
  85  */
  86
  87 static struct irq_pin_list {
  88         short apic, pin, next;
  89 } irq_2_pin[PIN_MAP_SIZE];
  90
  91 struct io_apic {
  92         unsigned int index;
  93         unsigned int unused[3];
  94         unsigned int data;
  95 };
  96
  97 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
  98 {
  99         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 100                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 101 }
 102
 103 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 104 {
 105         struct io_apic __iomem *io_apic = io_apic_base(apic);
 106         writel(reg, &io_apic->index);
 107         return readl(&io_apic->data);
 108 }
 109
 110 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 111 {
 112         struct io_apic __iomem *io_apic = io_apic_base(apic);
 113         writel(reg, &io_apic->index);
 114         writel(value, &io_apic->data);
 115 }
 116
 117 /*
 118  * Re-write a value: to be used for read-modify-write
 119  * cycles where the read already set up the index register.
 120  */
 121 static inline void io_apic_modify(unsigned int apic, unsigned int value)
 122 {
 123         struct io_apic __iomem *io_apic = io_apic_base(apic);
 124         writel(value, &io_apic->data);
 125 }
 126
 127 /*
 128  * Synchronize the IO-APIC and the CPU by doing
 129  * a dummy read from the IO-APIC
 130  */
 131 static inline void io_apic_sync(unsigned int apic)
 132 {
 133         struct io_apic __iomem *io_apic = io_apic_base(apic);
 134         readl(&io_apic->data);
 135 }
 136
 137 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 138                                                                         \
 139 {                                                                       \
 140         int pin;                                                        \
 141         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 142                                                                         \
 143         BUG_ON(irq >= NR_IRQS);                                         \
 144         for (;;) {                                                      \
 145                 unsigned int reg;                                       \
 146                 pin = entry->pin;                                       \
 147                 if (pin == -1)                                          \
 148                         break;                                          \
 149                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 150                 reg ACTION;                                             \
 151                 io_apic_modify(entry->apic, reg);                       \
 152                 if (!entry->next)                                       \
 153                         break;                                          \
 154                 entry = irq_2_pin + entry->next;                        \
 155         }                                                               \
 156         FINAL;                                                          \
 157 }
 158
 159 union entry_union {
 160         struct { u32 w1, w2; };
 161         struct IO_APIC_route_entry entry;
 162 };
 163
 164 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 165 {
 166         union entry_union eu;
 167         unsigned long flags;
 168         spin_lock_irqsave(&ioapic_lock, flags);
 169         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 170         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 171         spin_unlock_irqrestore(&ioapic_lock, flags);
 172         return eu.entry;
 173 }
 174
 175 /*
 176  * When we write a new IO APIC routing entry, we need to write the high
 177  * word first! If the mask bit in the low word is clear, we will enable
 178  * the interrupt, and we need to make sure the entry is fully populated
 179  * before that happens.
 180  */
 181 static void
 182 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 183 {
 184         union entry_union eu;
 185         eu.entry = e;
 186         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 187         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 188 }
 189
 190 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 191 {
 192         unsigned long flags;
 193         spin_lock_irqsave(&ioapic_lock, flags);
 194         __ioapic_write_entry(apic, pin, e);
 195         spin_unlock_irqrestore(&ioapic_lock, flags);
 196 }
 197
 198 /*
 199  * When we mask an IO APIC routing entry, we need to write the low
 200  * word first, in order to set the mask bit before we change the
 201  * high bits!
 202  */
 203 static void ioapic_mask_entry(int apic, int pin)
 204 {
 205         unsigned long flags;
 206         union entry_union eu = { .entry.mask = 1 };
 207
 208         spin_lock_irqsave(&ioapic_lock, flags);
 209         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 210         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 211         spin_unlock_irqrestore(&ioapic_lock, flags);
 212 }
 213
 214 #ifdef CONFIG_SMP
 215 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
 216 {
 217         int apic, pin;
 218         struct irq_pin_list *entry = irq_2_pin + irq;
 219
 220         BUG_ON(irq >= NR_IRQS);
 221         for (;;) {
 222                 unsigned int reg;
 223                 apic = entry->apic;
 224                 pin = entry->pin;
 225                 if (pin == -1)
 226                         break;
 227                 io_apic_write(apic, 0x11 + pin*2, dest);
 228                 reg = io_apic_read(apic, 0x10 + pin*2);
 229                 reg &= ~0x000000ff;
 230                 reg |= vector;
 231                 io_apic_modify(apic, reg);
 232                 if (!entry->next)
 233                         break;
 234                 entry = irq_2_pin + entry->next;
 235         }
 236 }
 237
 238 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 239 {
 240         unsigned long flags;
 241         unsigned int dest;
 242         cpumask_t tmp;
 243         int vector;
 244
 245         cpus_and(tmp, mask, cpu_online_map);
 246         if (cpus_empty(tmp))
 247                 return;
 248
 249         vector = assign_irq_vector(irq, mask, &tmp);
 250         if (vector < 0)
 251                 return;
 252
 253         dest = cpu_mask_to_apicid(tmp);
 254
 255         /*
 256          * Only the high 8 bits are valid.
 257          */
 258         dest = SET_APIC_LOGICAL_ID(dest);
 259
 260         spin_lock_irqsave(&ioapic_lock, flags);
 261         __target_IO_APIC_irq(irq, dest, vector);
 262         irq_desc[irq].affinity = mask;
 263         spin_unlock_irqrestore(&ioapic_lock, flags);
 264 }
 265 #endif
 266
 267 /*
 268  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 269  * shared ISA-space IRQs, so we have to support them. We are super
 270  * fast in the common case, and fast for shared ISA-space IRQs.
 271  */
 272 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 273 {
 274         static int first_free_entry = NR_IRQS;
 275         struct irq_pin_list *entry = irq_2_pin + irq;
 276
 277         BUG_ON(irq >= NR_IRQS);
 278         while (entry->next)
 279                 entry = irq_2_pin + entry->next;
 280
 281         if (entry->pin != -1) {
 282                 entry->next = first_free_entry;
 283                 entry = irq_2_pin + entry->next;
 284                 if (++first_free_entry >= PIN_MAP_SIZE)
 285                         panic("io_apic.c: ran out of irq_2_pin entries!");
 286         }
 287         entry->apic = apic;
 288         entry->pin = pin;
 289 }
 290
 291
 292 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 293                                                                         \
 294         static void name##_IO_APIC_irq (unsigned int irq)               \
 295         __DO_ACTION(R, ACTION, FINAL)
 296
 297 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 298                                                 /* mask = 1 */
 299 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 300                                                 /* mask = 0 */
 301
 302 static void mask_IO_APIC_irq (unsigned int irq)
 303 {
 304         unsigned long flags;
 305
 306         spin_lock_irqsave(&ioapic_lock, flags);
 307         __mask_IO_APIC_irq(irq);
 308         spin_unlock_irqrestore(&ioapic_lock, flags);
 309 }
 310
 311 static void unmask_IO_APIC_irq (unsigned int irq)
 312 {
 313         unsigned long flags;
 314
 315         spin_lock_irqsave(&ioapic_lock, flags);
 316         __unmask_IO_APIC_irq(irq);
 317         spin_unlock_irqrestore(&ioapic_lock, flags);
 318 }
 319
 320 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 321 {
 322         struct IO_APIC_route_entry entry;
 323
 324         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 325         entry = ioapic_read_entry(apic, pin);
 326         if (entry.delivery_mode == dest_SMI)
 327                 return;
 328         /*
 329          * Disable it in the IO-APIC irq-routing table:
 330          */
 331         ioapic_mask_entry(apic, pin);
 332 }
 333
 334 static void clear_IO_APIC (void)
 335 {
 336         int apic, pin;
 337
 338         for (apic = 0; apic < nr_ioapics; apic++)
 339                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 340                         clear_IO_APIC_pin(apic, pin);
 341 }
 342
 343 int skip_ioapic_setup;
 344 int ioapic_force;
 345
 346 /* dummy parsing: see setup.c */
 347
 348 static int __init disable_ioapic_setup(char *str)
 349 {
 350         skip_ioapic_setup = 1;
 351         return 0;
 352 }
 353 early_param("noapic", disable_ioapic_setup);
 354
 355 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
 356 static int __init disable_timer_pin_setup(char *arg)
 357 {
 358         disable_timer_pin_1 = 1;
 359         return 1;
 360 }
 361 __setup("disable_timer_pin_1", disable_timer_pin_setup);
 362
 363 static int __init setup_disable_8254_timer(char *s)
 364 {
 365         timer_over_8254 = -1;
 366         return 1;
 367 }
 368 static int __init setup_enable_8254_timer(char *s)
 369 {
 370         timer_over_8254 = 2;
 371         return 1;
 372 }
 373
 374 __setup("disable_8254_timer", setup_disable_8254_timer);
 375 __setup("enable_8254_timer", setup_enable_8254_timer);
 376
 377
 378 /*
 379  * Find the IRQ entry number of a certain pin.
 380  */
 381 static int find_irq_entry(int apic, int pin, int type)
 382 {
 383         int i;
 384
 385         for (i = 0; i < mp_irq_entries; i++)
 386                 if (mp_irqs[i].mpc_irqtype == type &&
 387                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 388                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 389                     mp_irqs[i].mpc_dstirq == pin)
 390                         return i;
 391
 392         return -1;
 393 }
 394
 395 /*
 396  * Find the pin to which IRQ[irq] (ISA) is connected
 397  */
 398 static int __init find_isa_irq_pin(int irq, int type)
 399 {
 400         int i;
 401
 402         for (i = 0; i < mp_irq_entries; i++) {
 403                 int lbus = mp_irqs[i].mpc_srcbus;
 404
 405                 if (test_bit(lbus, mp_bus_not_pci) &&
 406                     (mp_irqs[i].mpc_irqtype == type) &&
 407                     (mp_irqs[i].mpc_srcbusirq == irq))
 408
 409                         return mp_irqs[i].mpc_dstirq;
 410         }
 411         return -1;
 412 }
 413
 414 static int __init find_isa_irq_apic(int irq, int type)
 415 {
 416         int i;
 417
 418         for (i = 0; i < mp_irq_entries; i++) {
 419                 int lbus = mp_irqs[i].mpc_srcbus;
 420
 421                 if (test_bit(lbus, mp_bus_not_pci) &&
 422                     (mp_irqs[i].mpc_irqtype == type) &&
 423                     (mp_irqs[i].mpc_srcbusirq == irq))
 424                         break;
 425         }
 426         if (i < mp_irq_entries) {
 427                 int apic;
 428                 for(apic = 0; apic < nr_ioapics; apic++) {
 429                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 430                                 return apic;
 431                 }
 432         }
 433
 434         return -1;
 435 }
 436
 437 /*
 438  * Find a specific PCI IRQ entry.
 439  * Not an __init, possibly needed by modules
 440  */
 441 static int pin_2_irq(int idx, int apic, int pin);
 442
 443 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 444 {
 445         int apic, i, best_guess = -1;
 446
 447         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 448                 bus, slot, pin);
 449         if (mp_bus_id_to_pci_bus[bus] == -1) {
 450                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 451                 return -1;
 452         }
 453         for (i = 0; i < mp_irq_entries; i++) {
 454                 int lbus = mp_irqs[i].mpc_srcbus;
 455
 456                 for (apic = 0; apic < nr_ioapics; apic++)
 457                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 458                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 459                                 break;
 460
 461                 if (!test_bit(lbus, mp_bus_not_pci) &&
 462                     !mp_irqs[i].mpc_irqtype &&
 463                     (bus == lbus) &&
 464                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 465                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 466
 467                         if (!(apic || IO_APIC_IRQ(irq)))
 468                                 continue;
 469
 470                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 471                                 return irq;
 472                         /*
 473                          * Use the first all-but-pin matching entry as a
 474                          * best-guess fuzzy result for broken mptables.
 475                          */
 476                         if (best_guess < 0)
 477                                 best_guess = irq;
 478                 }
 479         }
 480         BUG_ON(best_guess >= NR_IRQS);
 481         return best_guess;
 482 }
 483
 484 /* ISA interrupts are always polarity zero edge triggered,
 485  * when listed as conforming in the MP table. */
 486
 487 #define default_ISA_trigger(idx)        (0)
 488 #define default_ISA_polarity(idx)       (0)
 489
 490 /* PCI interrupts are always polarity one level triggered,
 491  * when listed as conforming in the MP table. */
 492
 493 #define default_PCI_trigger(idx)        (1)
 494 #define default_PCI_polarity(idx)       (1)
 495
 496 static int __init MPBIOS_polarity(int idx)
 497 {
 498         int bus = mp_irqs[idx].mpc_srcbus;
 499         int polarity;
 500
 501         /*
 502          * Determine IRQ line polarity (high active or low active):
 503          */
 504         switch (mp_irqs[idx].mpc_irqflag & 3)
 505         {
 506                 case 0: /* conforms, ie. bus-type dependent polarity */
 507                         if (test_bit(bus, mp_bus_not_pci))
 508                                 polarity = default_ISA_polarity(idx);
 509                         else
 510                                 polarity = default_PCI_polarity(idx);
 511                         break;
 512                 case 1: /* high active */
 513                 {
 514                         polarity = 0;
 515                         break;
 516                 }
 517                 case 2: /* reserved */
 518                 {
 519                         printk(KERN_WARNING "broken BIOS!!\n");
 520                         polarity = 1;
 521                         break;
 522                 }
 523                 case 3: /* low active */
 524                 {
 525                         polarity = 1;
 526                         break;
 527                 }
 528                 default: /* invalid */
 529                 {
 530                         printk(KERN_WARNING "broken BIOS!!\n");
 531                         polarity = 1;
 532                         break;
 533                 }
 534         }
 535         return polarity;
 536 }
 537
 538 static int MPBIOS_trigger(int idx)
 539 {
 540         int bus = mp_irqs[idx].mpc_srcbus;
 541         int trigger;
 542
 543         /*
 544          * Determine IRQ trigger mode (edge or level sensitive):
 545          */
 546         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 547         {
 548                 case 0: /* conforms, ie. bus-type dependent */
 549                         if (test_bit(bus, mp_bus_not_pci))
 550                                 trigger = default_ISA_trigger(idx);
 551                         else
 552                                 trigger = default_PCI_trigger(idx);
 553                         break;
 554                 case 1: /* edge */
 555                 {
 556                         trigger = 0;
 557                         break;
 558                 }
 559                 case 2: /* reserved */
 560                 {
 561                         printk(KERN_WARNING "broken BIOS!!\n");
 562                         trigger = 1;
 563                         break;
 564                 }
 565                 case 3: /* level */
 566                 {
 567                         trigger = 1;
 568                         break;
 569                 }
 570                 default: /* invalid */
 571                 {
 572                         printk(KERN_WARNING "broken BIOS!!\n");
 573                         trigger = 0;
 574                         break;
 575                 }
 576         }
 577         return trigger;
 578 }
 579
 580 static inline int irq_polarity(int idx)
 581 {
 582         return MPBIOS_polarity(idx);
 583 }
 584
 585 static inline int irq_trigger(int idx)
 586 {
 587         return MPBIOS_trigger(idx);
 588 }
 589
 590 static int pin_2_irq(int idx, int apic, int pin)
 591 {
 592         int irq, i;
 593         int bus = mp_irqs[idx].mpc_srcbus;
 594
 595         /*
 596          * Debugging check, we are in big trouble if this message pops up!
 597          */
 598         if (mp_irqs[idx].mpc_dstirq != pin)
 599                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 600
 601         if (test_bit(bus, mp_bus_not_pci)) {
 602                 irq = mp_irqs[idx].mpc_srcbusirq;
 603         } else {
 604                 /*
 605                  * PCI IRQs are mapped in order
 606                  */
 607                 i = irq = 0;
 608                 while (i < apic)
 609                         irq += nr_ioapic_registers[i++];
 610                 irq += pin;
 611         }
 612         BUG_ON(irq >= NR_IRQS);
 613         return irq;
 614 }
 615
 616
 617 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 618 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
 619         [0] = FIRST_EXTERNAL_VECTOR + 0,
 620         [1] = FIRST_EXTERNAL_VECTOR + 1,
 621         [2] = FIRST_EXTERNAL_VECTOR + 2,
 622         [3] = FIRST_EXTERNAL_VECTOR + 3,
 623         [4] = FIRST_EXTERNAL_VECTOR + 4,
 624         [5] = FIRST_EXTERNAL_VECTOR + 5,
 625         [6] = FIRST_EXTERNAL_VECTOR + 6,
 626         [7] = FIRST_EXTERNAL_VECTOR + 7,
 627         [8] = FIRST_EXTERNAL_VECTOR + 8,
 628         [9] = FIRST_EXTERNAL_VECTOR + 9,
 629         [10] = FIRST_EXTERNAL_VECTOR + 10,
 630         [11] = FIRST_EXTERNAL_VECTOR + 11,
 631         [12] = FIRST_EXTERNAL_VECTOR + 12,
 632         [13] = FIRST_EXTERNAL_VECTOR + 13,
 633         [14] = FIRST_EXTERNAL_VECTOR + 14,
 634         [15] = FIRST_EXTERNAL_VECTOR + 15,
 635 };
 636
 637 static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
 638         [0] = CPU_MASK_ALL,
 639         [1] = CPU_MASK_ALL,
 640         [2] = CPU_MASK_ALL,
 641         [3] = CPU_MASK_ALL,
 642         [4] = CPU_MASK_ALL,
 643         [5] = CPU_MASK_ALL,
 644         [6] = CPU_MASK_ALL,
 645         [7] = CPU_MASK_ALL,
 646         [8] = CPU_MASK_ALL,
 647         [9] = CPU_MASK_ALL,
 648         [10] = CPU_MASK_ALL,
 649         [11] = CPU_MASK_ALL,
 650         [12] = CPU_MASK_ALL,
 651         [13] = CPU_MASK_ALL,
 652         [14] = CPU_MASK_ALL,
 653         [15] = CPU_MASK_ALL,
 654 };
 655
 656 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
 657 {
 658         /*
 659          * NOTE! The local APIC isn't very good at handling
 660          * multiple interrupts at the same interrupt level.
 661          * As the interrupt level is determined by taking the
 662          * vector number and shifting that right by 4, we
 663          * want to spread these out a bit so that they don't
 664          * all fall in the same interrupt level.
 665          *
 666          * Also, we've got to be careful not to trash gate
 667          * 0x80, because int 0x80 is hm, kind of importantish. ;)
 668          */
 669         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
 670         cpumask_t old_mask = CPU_MASK_NONE;
 671         int old_vector = -1;
 672         int cpu;
 673
 674         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
 675
 676         /* Only try and allocate irqs on cpus that are present */
 677         cpus_and(mask, mask, cpu_online_map);
 678
 679         if (irq_vector[irq] > 0)
 680                 old_vector = irq_vector[irq];
 681         if (old_vector > 0) {
 682                 cpus_and(*result, irq_domain[irq], mask);
 683                 if (!cpus_empty(*result))
 684                         return old_vector;
 685                 cpus_and(old_mask, irq_domain[irq], cpu_online_map);
 686         }
 687
 688         for_each_cpu_mask(cpu, mask) {
 689                 cpumask_t domain, new_mask;
 690                 int new_cpu, old_cpu;
 691                 int vector, offset;
 692
 693                 domain = vector_allocation_domain(cpu);
 694                 cpus_and(new_mask, domain, cpu_online_map);
 695
 696                 vector = current_vector;
 697                 offset = current_offset;
 698 next:
 699                 vector += 8;
 700                 if (vector >= FIRST_SYSTEM_VECTOR) {
 701                         /* If we run out of vectors on large boxen, must share them. */
 702                         offset = (offset + 1) % 8;
 703                         vector = FIRST_DEVICE_VECTOR + offset;
 704                 }
 705                 if (unlikely(current_vector == vector))
 706                         continue;
 707                 if (vector == IA32_SYSCALL_VECTOR)
 708                         goto next;
 709                 for_each_cpu_mask(new_cpu, new_mask)
 710                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
 711                                 goto next;
 712                 /* Found one! */
 713                 current_vector = vector;
 714                 current_offset = offset;
 715                 for_each_cpu_mask(old_cpu, old_mask)
 716                         per_cpu(vector_irq, old_cpu)[old_vector] = -1;
 717                 for_each_cpu_mask(new_cpu, new_mask)
 718                         per_cpu(vector_irq, new_cpu)[vector] = irq;
 719                 irq_vector[irq] = vector;
 720                 irq_domain[irq] = domain;
 721                 cpus_and(*result, domain, mask);
 722                 return vector;
 723         }
 724         return -ENOSPC;
 725 }
 726
 727 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
 728 {
 729         int vector;
 730         unsigned long flags;
 731
 732         spin_lock_irqsave(&vector_lock, flags);
 733         vector = __assign_irq_vector(irq, mask, result);
 734         spin_unlock_irqrestore(&vector_lock, flags);
 735         return vector;
 736 }
 737
 738 static void __clear_irq_vector(int irq)
 739 {
 740         cpumask_t mask;
 741         int cpu, vector;
 742
 743         BUG_ON(!irq_vector[irq]);
 744
 745         vector = irq_vector[irq];
 746         cpus_and(mask, irq_domain[irq], cpu_online_map);
 747         for_each_cpu_mask(cpu, mask)
 748                 per_cpu(vector_irq, cpu)[vector] = -1;
 749
 750         irq_vector[irq] = 0;
 751         irq_domain[irq] = CPU_MASK_NONE;
 752 }
 753
 754 void __setup_vector_irq(int cpu)
 755 {
 756         /* Initialize vector_irq on a new cpu */
 757         /* This function must be called with vector_lock held */
 758         int irq, vector;
 759
 760         /* Mark the inuse vectors */
 761         for (irq = 0; irq < NR_IRQ_VECTORS; ++irq) {
 762                 if (!cpu_isset(cpu, irq_domain[irq]))
 763                         continue;
 764                 vector = irq_vector[irq];
 765                 per_cpu(vector_irq, cpu)[vector] = irq;
 766         }
 767         /* Mark the free vectors */
 768         for (vector = 0; vector < NR_VECTORS; ++vector) {
 769                 irq = per_cpu(vector_irq, cpu)[vector];
 770                 if (irq < 0)
 771                         continue;
 772                 if (!cpu_isset(cpu, irq_domain[irq]))
 773                         per_cpu(vector_irq, cpu)[vector] = -1;
 774         }
 775 }
 776
 777
 778 static struct irq_chip ioapic_chip;
 779
 780 static void ioapic_register_intr(int irq, unsigned long trigger)
 781 {
 782         if (trigger)
 783                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 784                                               handle_fasteoi_irq, "fasteoi");
 785         else
 786                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 787                                               handle_edge_irq, "edge");
 788 }
 789
 790 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
 791                               int trigger, int polarity)
 792 {
 793         struct IO_APIC_route_entry entry;
 794         cpumask_t mask;
 795         int vector;
 796         unsigned long flags;
 797
 798         if (!IO_APIC_IRQ(irq))
 799                 return;
 800
 801         vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
 802         if (vector < 0)
 803                 return;
 804
 805         apic_printk(APIC_VERBOSE,KERN_DEBUG
 806                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
 807                     "IRQ %d Mode:%i Active:%i)\n",
 808                     apic, mp_ioapics[apic].mpc_apicid, pin, vector,
 809                     irq, trigger, polarity);
 810
 811         /*
 812          * add it to the IO-APIC irq-routing table:
 813          */
 814         memset(&entry,0,sizeof(entry));
 815
 816         entry.delivery_mode = INT_DELIVERY_MODE;
 817         entry.dest_mode = INT_DEST_MODE;
 818         entry.dest = cpu_mask_to_apicid(mask);
 819         entry.mask = 0;                         /* enable IRQ */
 820         entry.trigger = trigger;
 821         entry.polarity = polarity;
 822         entry.vector = vector;
 823
 824         /* Mask level triggered irqs.
 825          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
 826          */
 827         if (trigger)
 828                 entry.mask = 1;
 829
 830         ioapic_register_intr(irq, trigger);
 831         if (irq < 16)
 832                 disable_8259A_irq(irq);
 833
 834         ioapic_write_entry(apic, pin, entry);
 835
 836         spin_lock_irqsave(&ioapic_lock, flags);
 837         irq_desc[irq].affinity = TARGET_CPUS;
 838         spin_unlock_irqrestore(&ioapic_lock, flags);
 839 }
 840
 841 static void __init setup_IO_APIC_irqs(void)
 842 {
 843         int apic, pin, idx, irq, first_notcon = 1;
 844
 845         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 846
 847         for (apic = 0; apic < nr_ioapics; apic++) {
 848         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 849
 850                 idx = find_irq_entry(apic,pin,mp_INT);
 851                 if (idx == -1) {
 852                         if (first_notcon) {
 853                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 854                                 first_notcon = 0;
 855                         } else
 856                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 857                         continue;
 858                 }
 859
 860                 irq = pin_2_irq(idx, apic, pin);
 861                 add_pin_to_irq(irq, apic, pin);
 862
 863                 setup_IO_APIC_irq(apic, pin, irq,
 864                                   irq_trigger(idx), irq_polarity(idx));
 865         }
 866         }
 867
 868         if (!first_notcon)
 869                 apic_printk(APIC_VERBOSE," not connected.\n");
 870 }
 871
 872 /*
 873  * Set up the 8259A-master output pin as broadcast to all
 874  * CPUs.
 875  */
 876 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 877 {
 878         struct IO_APIC_route_entry entry;
 879         unsigned long flags;
 880
 881         memset(&entry,0,sizeof(entry));
 882
 883         disable_8259A_irq(0);
 884
 885         /* mask LVT0 */
 886         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 887
 888         /*
 889          * We use logical delivery to get the timer IRQ
 890          * to the first CPU.
 891          */
 892         entry.dest_mode = INT_DEST_MODE;
 893         entry.mask = 0;                                 /* unmask IRQ now */
 894         entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
 895         entry.delivery_mode = INT_DELIVERY_MODE;
 896         entry.polarity = 0;
 897         entry.trigger = 0;
 898         entry.vector = vector;
 899
 900         /*
 901          * The timer IRQ doesn't have to know that behind the
 902          * scene we have a 8259A-master in AEOI mode ...
 903          */
 904         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
 905
 906         /*
 907          * Add it to the IO-APIC irq-routing table:
 908          */
 909         spin_lock_irqsave(&ioapic_lock, flags);
 910         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 911         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 912         spin_unlock_irqrestore(&ioapic_lock, flags);
 913
 914         enable_8259A_irq(0);
 915 }
 916
 917 void __init UNEXPECTED_IO_APIC(void)
 918 {
 919 }
 920
 921 void __apicdebuginit print_IO_APIC(void)
 922 {
 923         int apic, i;
 924         union IO_APIC_reg_00 reg_00;
 925         union IO_APIC_reg_01 reg_01;
 926         union IO_APIC_reg_02 reg_02;
 927         unsigned long flags;
 928
 929         if (apic_verbosity == APIC_QUIET)
 930                 return;
 931
 932         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 933         for (i = 0; i < nr_ioapics; i++)
 934                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 935                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 936
 937         /*
 938          * We are a bit conservative about what we expect.  We have to
 939          * know about every hardware change ASAP.
 940          */
 941         printk(KERN_INFO "testing the IO APIC.......................\n");
 942
 943         for (apic = 0; apic < nr_ioapics; apic++) {
 944
 945         spin_lock_irqsave(&ioapic_lock, flags);
 946         reg_00.raw = io_apic_read(apic, 0);
 947         reg_01.raw = io_apic_read(apic, 1);
 948         if (reg_01.bits.version >= 0x10)
 949                 reg_02.raw = io_apic_read(apic, 2);
 950         spin_unlock_irqrestore(&ioapic_lock, flags);
 951
 952         printk("\n");
 953         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 954         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 955         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 956         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 957                 UNEXPECTED_IO_APIC();
 958
 959         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 960         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 961         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 962                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 963                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 964                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 965                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 966                 (reg_01.bits.entries != 0x2E) &&
 967                 (reg_01.bits.entries != 0x3F) &&
 968                 (reg_01.bits.entries != 0x03)
 969         )
 970                 UNEXPECTED_IO_APIC();
 971
 972         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 973         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 974         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 975                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 976                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 977                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 978                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 979                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 980         )
 981                 UNEXPECTED_IO_APIC();
 982         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 983                 UNEXPECTED_IO_APIC();
 984
 985         if (reg_01.bits.version >= 0x10) {
 986                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 987                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 988                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 989                         UNEXPECTED_IO_APIC();
 990         }
 991
 992         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 993
 994         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
 995                           " Stat Dmod Deli Vect:   \n");
 996
 997         for (i = 0; i <= reg_01.bits.entries; i++) {
 998                 struct IO_APIC_route_entry entry;
 999
1000                 entry = ioapic_read_entry(apic, i);
1001
1002                 printk(KERN_DEBUG " %02x %03X ",
1003                         i,
1004                         entry.dest
1005                 );
1006
1007                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1008                         entry.mask,
1009                         entry.trigger,
1010                         entry.irr,
1011                         entry.polarity,
1012                         entry.delivery_status,
1013                         entry.dest_mode,
1014                         entry.delivery_mode,
1015                         entry.vector
1016                 );
1017         }
1018         }
1019         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1020         for (i = 0; i < NR_IRQS; i++) {
1021                 struct irq_pin_list *entry = irq_2_pin + i;
1022                 if (entry->pin < 0)
1023                         continue;
1024                 printk(KERN_DEBUG "IRQ%d ", i);
1025                 for (;;) {
1026                         printk("-> %d:%d", entry->apic, entry->pin);
1027                         if (!entry->next)
1028                                 break;
1029                         entry = irq_2_pin + entry->next;
1030                 }
1031                 printk("\n");
1032         }
1033
1034         printk(KERN_INFO ".................................... done.\n");
1035
1036         return;
1037 }
1038
1039 #if 0
1040
1041 static __apicdebuginit void print_APIC_bitfield (int base)
1042 {
1043         unsigned int v;
1044         int i, j;
1045
1046         if (apic_verbosity == APIC_QUIET)
1047                 return;
1048
1049         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1050         for (i = 0; i < 8; i++) {
1051                 v = apic_read(base + i*0x10);
1052                 for (j = 0; j < 32; j++) {
1053                         if (v & (1<<j))
1054                                 printk("1");
1055                         else
1056                                 printk("0");
1057                 }
1058                 printk("\n");
1059         }
1060 }
1061
1062 void __apicdebuginit print_local_APIC(void * dummy)
1063 {
1064         unsigned int v, ver, maxlvt;
1065
1066         if (apic_verbosity == APIC_QUIET)
1067                 return;
1068
1069         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1070                 smp_processor_id(), hard_smp_processor_id());
1071         v = apic_read(APIC_ID);
1072         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1073         v = apic_read(APIC_LVR);
1074         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1075         ver = GET_APIC_VERSION(v);
1076         maxlvt = get_maxlvt();
1077
1078         v = apic_read(APIC_TASKPRI);
1079         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1080
1081         v = apic_read(APIC_ARBPRI);
1082         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1083                 v & APIC_ARBPRI_MASK);
1084         v = apic_read(APIC_PROCPRI);
1085         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1086
1087         v = apic_read(APIC_EOI);
1088         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1089         v = apic_read(APIC_RRR);
1090         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1091         v = apic_read(APIC_LDR);
1092         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1093         v = apic_read(APIC_DFR);
1094         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1095         v = apic_read(APIC_SPIV);
1096         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1097
1098         printk(KERN_DEBUG "... APIC ISR field:\n");
1099         print_APIC_bitfield(APIC_ISR);
1100         printk(KERN_DEBUG "... APIC TMR field:\n");
1101         print_APIC_bitfield(APIC_TMR);
1102         printk(KERN_DEBUG "... APIC IRR field:\n");
1103         print_APIC_bitfield(APIC_IRR);
1104
1105         v = apic_read(APIC_ESR);
1106         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1107
1108         v = apic_read(APIC_ICR);
1109         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1110         v = apic_read(APIC_ICR2);
1111         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1112
1113         v = apic_read(APIC_LVTT);
1114         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1115
1116         if (maxlvt > 3) {                       /* PC is LVT#4. */
1117                 v = apic_read(APIC_LVTPC);
1118                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1119         }
1120         v = apic_read(APIC_LVT0);
1121         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1122         v = apic_read(APIC_LVT1);
1123         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1124
1125         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1126                 v = apic_read(APIC_LVTERR);
1127                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1128         }
1129
1130         v = apic_read(APIC_TMICT);
1131         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1132         v = apic_read(APIC_TMCCT);
1133         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1134         v = apic_read(APIC_TDCR);
1135         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1136         printk("\n");
1137 }
1138
1139 void print_all_local_APICs (void)
1140 {
1141         on_each_cpu(print_local_APIC, NULL, 1, 1);
1142 }
1143
1144 void __apicdebuginit print_PIC(void)
1145 {
1146         unsigned int v;
1147         unsigned long flags;
1148
1149         if (apic_verbosity == APIC_QUIET)
1150                 return;
1151
1152         printk(KERN_DEBUG "\nprinting PIC contents\n");
1153
1154         spin_lock_irqsave(&i8259A_lock, flags);
1155
1156         v = inb(0xa1) << 8 | inb(0x21);
1157         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1158
1159         v = inb(0xa0) << 8 | inb(0x20);
1160         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1161
1162         outb(0x0b,0xa0);
1163         outb(0x0b,0x20);
1164         v = inb(0xa0) << 8 | inb(0x20);
1165         outb(0x0a,0xa0);
1166         outb(0x0a,0x20);
1167
1168         spin_unlock_irqrestore(&i8259A_lock, flags);
1169
1170         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1171
1172         v = inb(0x4d1) << 8 | inb(0x4d0);
1173         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1174 }
1175
1176 #endif  /*  0  */
1177
1178 static void __init enable_IO_APIC(void)
1179 {
1180         union IO_APIC_reg_01 reg_01;
1181         int i8259_apic, i8259_pin;
1182         int i, apic;
1183         unsigned long flags;
1184
1185         for (i = 0; i < PIN_MAP_SIZE; i++) {
1186                 irq_2_pin[i].pin = -1;
1187                 irq_2_pin[i].next = 0;
1188         }
1189
1190         /*
1191          * The number of IO-APIC IRQ registers (== #pins):
1192          */
1193         for (apic = 0; apic < nr_ioapics; apic++) {
1194                 spin_lock_irqsave(&ioapic_lock, flags);
1195                 reg_01.raw = io_apic_read(apic, 1);
1196                 spin_unlock_irqrestore(&ioapic_lock, flags);
1197                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1198         }
1199         for(apic = 0; apic < nr_ioapics; apic++) {
1200                 int pin;
1201                 /* See if any of the pins is in ExtINT mode */
1202                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1203                         struct IO_APIC_route_entry entry;
1204                         entry = ioapic_read_entry(apic, pin);
1205
1206                         /* If the interrupt line is enabled and in ExtInt mode
1207                          * I have found the pin where the i8259 is connected.
1208                          */
1209                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1210                                 ioapic_i8259.apic = apic;
1211                                 ioapic_i8259.pin  = pin;
1212                                 goto found_i8259;
1213                         }
1214                 }
1215         }
1216  found_i8259:
1217         /* Look to see what if the MP table has reported the ExtINT */
1218         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1219         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1220         /* Trust the MP table if nothing is setup in the hardware */
1221         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1222                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1223                 ioapic_i8259.pin  = i8259_pin;
1224                 ioapic_i8259.apic = i8259_apic;
1225         }
1226         /* Complain if the MP table and the hardware disagree */
1227         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1228                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1229         {
1230                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1231         }
1232
1233         /*
1234          * Do not trust the IO-APIC being empty at bootup
1235          */
1236         clear_IO_APIC();
1237 }
1238
1239 /*
1240  * Not an __init, needed by the reboot code
1241  */
1242 void disable_IO_APIC(void)
1243 {
1244         /*
1245          * Clear the IO-APIC before rebooting:
1246          */
1247         clear_IO_APIC();
1248
1249         /*
1250          * If the i8259 is routed through an IOAPIC
1251          * Put that IOAPIC in virtual wire mode
1252          * so legacy interrupts can be delivered.
1253          */
1254         if (ioapic_i8259.pin != -1) {
1255                 struct IO_APIC_route_entry entry;
1256
1257                 memset(&entry, 0, sizeof(entry));
1258                 entry.mask            = 0; /* Enabled */
1259                 entry.trigger         = 0; /* Edge */
1260                 entry.irr             = 0;
1261                 entry.polarity        = 0; /* High */
1262                 entry.delivery_status = 0;
1263                 entry.dest_mode       = 0; /* Physical */
1264                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1265                 entry.vector          = 0;
1266                 entry.dest          = GET_APIC_ID(apic_read(APIC_ID));
1267
1268                 /*
1269                  * Add it to the IO-APIC irq-routing table:
1270                  */
1271                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1272         }
1273
1274         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1275 }
1276
1277 /*
1278  * There is a nasty bug in some older SMP boards, their mptable lies
1279  * about the timer IRQ. We do the following to work around the situation:
1280  *
1281  *      - timer IRQ defaults to IO-APIC IRQ
1282  *      - if this function detects that timer IRQs are defunct, then we fall
1283  *        back to ISA timer IRQs
1284  */
1285 static int __init timer_irq_works(void)
1286 {
1287         unsigned long t1 = jiffies;
1288
1289         local_irq_enable();
1290         /* Let ten ticks pass... */
1291         mdelay((10 * 1000) / HZ);
1292
1293         /*
1294          * Expect a few ticks at least, to be sure some possible
1295          * glue logic does not lock up after one or two first
1296          * ticks in a non-ExtINT mode.  Also the local APIC
1297          * might have cached one ExtINT interrupt.  Finally, at
1298          * least one tick may be lost due to delays.
1299          */
1300
1301         /* jiffies wrap? */
1302         if (jiffies - t1 > 4)
1303                 return 1;
1304         return 0;
1305 }
1306
1307 /*
1308  * In the SMP+IOAPIC case it might happen that there are an unspecified
1309  * number of pending IRQ events unhandled. These cases are very rare,
1310  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1311  * better to do it this way as thus we do not have to be aware of
1312  * 'pending' interrupts in the IRQ path, except at this point.
1313  */
1314 /*
1315  * Edge triggered needs to resend any interrupt
1316  * that was delayed but this is now handled in the device
1317  * independent code.
1318  */
1319
1320 /*
1321  * Starting up a edge-triggered IO-APIC interrupt is
1322  * nasty - we need to make sure that we get the edge.
1323  * If it is already asserted for some reason, we need
1324  * return 1 to indicate that is was pending.
1325  *
1326  * This is not complete - we should be able to fake
1327  * an edge even if it isn't on the 8259A...
1328  */
1329
1330 static unsigned int startup_ioapic_irq(unsigned int irq)
1331 {
1332         int was_pending = 0;
1333         unsigned long flags;
1334
1335         spin_lock_irqsave(&ioapic_lock, flags);
1336         if (irq < 16) {
1337                 disable_8259A_irq(irq);
1338                 if (i8259A_irq_pending(irq))
1339                         was_pending = 1;
1340         }
1341         __unmask_IO_APIC_irq(irq);
1342         spin_unlock_irqrestore(&ioapic_lock, flags);
1343
1344         return was_pending;
1345 }
1346
1347 static int ioapic_retrigger_irq(unsigned int irq)
1348 {
1349         cpumask_t mask;
1350         unsigned vector;
1351         unsigned long flags;
1352
1353         spin_lock_irqsave(&vector_lock, flags);
1354         vector = irq_vector[irq];
1355         cpus_clear(mask);
1356         cpu_set(first_cpu(irq_domain[irq]), mask);
1357
1358         send_IPI_mask(mask, vector);
1359         spin_unlock_irqrestore(&vector_lock, flags);
1360
1361         return 1;
1362 }
1363
1364 /*
1365  * Level and edge triggered IO-APIC interrupts need different handling,
1366  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1367  * handled with the level-triggered descriptor, but that one has slightly
1368  * more overhead. Level-triggered interrupts cannot be handled with the
1369  * edge-triggered handler, without risking IRQ storms and other ugly
1370  * races.
1371  */
1372
1373 static void ack_apic_edge(unsigned int irq)
1374 {
1375         move_native_irq(irq);
1376         ack_APIC_irq();
1377 }
1378
1379 static void ack_apic_level(unsigned int irq)
1380 {
1381         int do_unmask_irq = 0;
1382
1383 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1384         /* If we are moving the irq we need to mask it */
1385         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1386                 do_unmask_irq = 1;
1387                 mask_IO_APIC_irq(irq);
1388         }
1389 #endif
1390
1391         /*
1392          * We must acknowledge the irq before we move it or the acknowledge will
1393          * not propogate properly.
1394          */
1395         ack_APIC_irq();
1396
1397         /* Now we can move and renable the irq */
1398         move_masked_irq(irq);
1399         if (unlikely(do_unmask_irq))
1400                 unmask_IO_APIC_irq(irq);
1401 }
1402
1403 static struct irq_chip ioapic_chip __read_mostly = {
1404         .name           = "IO-APIC",
1405         .startup        = startup_ioapic_irq,
1406         .mask           = mask_IO_APIC_irq,
1407         .unmask         = unmask_IO_APIC_irq,
1408         .ack            = ack_apic_edge,
1409         .eoi            = ack_apic_level,
1410 #ifdef CONFIG_SMP
1411         .set_affinity   = set_ioapic_affinity_irq,
1412 #endif
1413         .retrigger      = ioapic_retrigger_irq,
1414 };
1415
1416 static inline void init_IO_APIC_traps(void)
1417 {
1418         int irq;
1419
1420         /*
1421          * NOTE! The local APIC isn't very good at handling
1422          * multiple interrupts at the same interrupt level.
1423          * As the interrupt level is determined by taking the
1424          * vector number and shifting that right by 4, we
1425          * want to spread these out a bit so that they don't
1426          * all fall in the same interrupt level.
1427          *
1428          * Also, we've got to be careful not to trash gate
1429          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1430          */
1431         for (irq = 0; irq < NR_IRQS ; irq++) {
1432                 int tmp = irq;
1433                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1434                         /*
1435                          * Hmm.. We don't have an entry for this,
1436                          * so default to an old-fashioned 8259
1437                          * interrupt if we can..
1438                          */
1439                         if (irq < 16)
1440                                 make_8259A_irq(irq);
1441                         else
1442                                 /* Strange. Oh, well.. */
1443                                 irq_desc[irq].chip = &no_irq_chip;
1444                 }
1445         }
1446 }
1447
1448 static void enable_lapic_irq (unsigned int irq)
1449 {
1450         unsigned long v;
1451
1452         v = apic_read(APIC_LVT0);
1453         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1454 }
1455
1456 static void disable_lapic_irq (unsigned int irq)
1457 {
1458         unsigned long v;
1459
1460         v = apic_read(APIC_LVT0);
1461         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1462 }
1463
1464 static void ack_lapic_irq (unsigned int irq)
1465 {
1466         ack_APIC_irq();
1467 }
1468
1469 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1470
1471 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1472         .typename = "local-APIC-edge",
1473         .startup = NULL, /* startup_irq() not used for IRQ0 */
1474         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1475         .enable = enable_lapic_irq,
1476         .disable = disable_lapic_irq,
1477         .ack = ack_lapic_irq,
1478         .end = end_lapic_irq,
1479 };
1480
1481 static void setup_nmi (void)
1482 {
1483         /*
1484          * Dirty trick to enable the NMI watchdog ...
1485          * We put the 8259A master into AEOI mode and
1486          * unmask on all local APICs LVT0 as NMI.
1487          *
1488          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1489          * is from Maciej W. Rozycki - so we do not have to EOI from
1490          * the NMI handler or the timer interrupt.
1491          */
1492         printk(KERN_INFO "activating NMI Watchdog ...");
1493
1494         enable_NMI_through_LVT0(NULL);
1495
1496         printk(" done.\n");
1497 }
1498
1499 /*
1500  * This looks a bit hackish but it's about the only one way of sending
1501  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1502  * not support the ExtINT mode, unfortunately.  We need to send these
1503  * cycles as some i82489DX-based boards have glue logic that keeps the
1504  * 8259A interrupt line asserted until INTA.  --macro
1505  */
1506 static inline void unlock_ExtINT_logic(void)
1507 {
1508         int apic, pin, i;
1509         struct IO_APIC_route_entry entry0, entry1;
1510         unsigned char save_control, save_freq_select;
1511         unsigned long flags;
1512
1513         pin  = find_isa_irq_pin(8, mp_INT);
1514         apic = find_isa_irq_apic(8, mp_INT);
1515         if (pin == -1)
1516                 return;
1517
1518         spin_lock_irqsave(&ioapic_lock, flags);
1519         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1520         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1521         spin_unlock_irqrestore(&ioapic_lock, flags);
1522         clear_IO_APIC_pin(apic, pin);
1523
1524         memset(&entry1, 0, sizeof(entry1));
1525
1526         entry1.dest_mode = 0;                   /* physical delivery */
1527         entry1.mask = 0;                        /* unmask IRQ now */
1528         entry1.dest = hard_smp_processor_id();
1529         entry1.delivery_mode = dest_ExtINT;
1530         entry1.polarity = entry0.polarity;
1531         entry1.trigger = 0;
1532         entry1.vector = 0;
1533
1534         spin_lock_irqsave(&ioapic_lock, flags);
1535         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1536         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1537         spin_unlock_irqrestore(&ioapic_lock, flags);
1538
1539         save_control = CMOS_READ(RTC_CONTROL);
1540         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1541         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1542                    RTC_FREQ_SELECT);
1543         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1544
1545         i = 100;
1546         while (i-- > 0) {
1547                 mdelay(10);
1548                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1549                         i -= 10;
1550         }
1551
1552         CMOS_WRITE(save_control, RTC_CONTROL);
1553         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1554         clear_IO_APIC_pin(apic, pin);
1555
1556         spin_lock_irqsave(&ioapic_lock, flags);
1557         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1558         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1559         spin_unlock_irqrestore(&ioapic_lock, flags);
1560 }
1561
1562 /*
1563  * This code may look a bit paranoid, but it's supposed to cooperate with
1564  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1565  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1566  * fanatically on his truly buggy board.
1567  *
1568  * FIXME: really need to revamp this for modern platforms only.
1569  */
1570 static inline void check_timer(void)
1571 {
1572         int apic1, pin1, apic2, pin2;
1573         int vector;
1574         cpumask_t mask;
1575
1576         /*
1577          * get/set the timer IRQ vector:
1578          */
1579         disable_8259A_irq(0);
1580         vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1581
1582         /*
1583          * Subtle, code in do_timer_interrupt() expects an AEOI
1584          * mode for the 8259A whenever interrupts are routed
1585          * through I/O APICs.  Also IRQ0 has to be enabled in
1586          * the 8259A which implies the virtual wire has to be
1587          * disabled in the local APIC.
1588          */
1589         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1590         init_8259A(1);
1591         if (timer_over_8254 > 0)
1592                 enable_8259A_irq(0);
1593
1594         pin1  = find_isa_irq_pin(0, mp_INT);
1595         apic1 = find_isa_irq_apic(0, mp_INT);
1596         pin2  = ioapic_i8259.pin;
1597         apic2 = ioapic_i8259.apic;
1598
1599         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1600                 vector, apic1, pin1, apic2, pin2);
1601
1602         if (pin1 != -1) {
1603                 /*
1604                  * Ok, does IRQ0 through the IOAPIC work?
1605                  */
1606                 unmask_IO_APIC_irq(0);
1607                 if (!no_timer_check && timer_irq_works()) {
1608                         nmi_watchdog_default();
1609                         if (nmi_watchdog == NMI_IO_APIC) {
1610                                 disable_8259A_irq(0);
1611                                 setup_nmi();
1612                                 enable_8259A_irq(0);
1613                         }
1614                         if (disable_timer_pin_1 > 0)
1615                                 clear_IO_APIC_pin(0, pin1);
1616                         return;
1617                 }
1618                 clear_IO_APIC_pin(apic1, pin1);
1619                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1620                                 "connected to IO-APIC\n");
1621         }
1622
1623         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1624                                 "through the 8259A ... ");
1625         if (pin2 != -1) {
1626                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1627                         apic2, pin2);
1628                 /*
1629                  * legacy devices should be connected to IO APIC #0
1630                  */
1631                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1632                 if (timer_irq_works()) {
1633                         apic_printk(APIC_VERBOSE," works.\n");
1634                         nmi_watchdog_default();
1635                         if (nmi_watchdog == NMI_IO_APIC) {
1636                                 setup_nmi();
1637                         }
1638                         return;
1639                 }
1640                 /*
1641                  * Cleanup, just in case ...
1642                  */
1643                 clear_IO_APIC_pin(apic2, pin2);
1644         }
1645         apic_printk(APIC_VERBOSE," failed.\n");
1646
1647         if (nmi_watchdog == NMI_IO_APIC) {
1648                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1649                 nmi_watchdog = 0;
1650         }
1651
1652         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1653
1654         disable_8259A_irq(0);
1655         irq_desc[0].chip = &lapic_irq_type;
1656         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1657         enable_8259A_irq(0);
1658
1659         if (timer_irq_works()) {
1660                 apic_printk(APIC_VERBOSE," works.\n");
1661                 return;
1662         }
1663         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1664         apic_printk(APIC_VERBOSE," failed.\n");
1665
1666         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1667
1668         init_8259A(0);
1669         make_8259A_irq(0);
1670         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1671
1672         unlock_ExtINT_logic();
1673
1674         if (timer_irq_works()) {
1675                 apic_printk(APIC_VERBOSE," works.\n");
1676                 return;
1677         }
1678         apic_printk(APIC_VERBOSE," failed :(.\n");
1679         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1680 }
1681
1682 static int __init notimercheck(char *s)
1683 {
1684         no_timer_check = 1;
1685         return 1;
1686 }
1687 __setup("no_timer_check", notimercheck);
1688
1689 /*
1690  *
1691  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1692  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1693  *   Linux doesn't really care, as it's not actually used
1694  *   for any interrupt handling anyway.
1695  */
1696 #define PIC_IRQS        (1<<2)
1697
1698 void __init setup_IO_APIC(void)
1699 {
1700         enable_IO_APIC();
1701
1702         if (acpi_ioapic)
1703                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1704         else
1705                 io_apic_irqs = ~PIC_IRQS;
1706
1707         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1708
1709         sync_Arb_IDs();
1710         setup_IO_APIC_irqs();
1711         init_IO_APIC_traps();
1712         check_timer();
1713         if (!acpi_ioapic)
1714                 print_IO_APIC();
1715 }
1716
1717 struct sysfs_ioapic_data {
1718         struct sys_device dev;
1719         struct IO_APIC_route_entry entry[0];
1720 };
1721 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1722
1723 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1724 {
1725         struct IO_APIC_route_entry *entry;
1726         struct sysfs_ioapic_data *data;
1727         int i;
1728
1729         data = container_of(dev, struct sysfs_ioapic_data, dev);
1730         entry = data->entry;
1731         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1732                 *entry = ioapic_read_entry(dev->id, i);
1733
1734         return 0;
1735 }
1736
1737 static int ioapic_resume(struct sys_device *dev)
1738 {
1739         struct IO_APIC_route_entry *entry;
1740         struct sysfs_ioapic_data *data;
1741         unsigned long flags;
1742         union IO_APIC_reg_00 reg_00;
1743         int i;
1744
1745         data = container_of(dev, struct sysfs_ioapic_data, dev);
1746         entry = data->entry;
1747
1748         spin_lock_irqsave(&ioapic_lock, flags);
1749         reg_00.raw = io_apic_read(dev->id, 0);
1750         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1751                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1752                 io_apic_write(dev->id, 0, reg_00.raw);
1753         }
1754         spin_unlock_irqrestore(&ioapic_lock, flags);
1755         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1756                 ioapic_write_entry(dev->id, i, entry[i]);
1757
1758         return 0;
1759 }
1760
1761 static struct sysdev_class ioapic_sysdev_class = {
1762         set_kset_name("ioapic"),
1763         .suspend = ioapic_suspend,
1764         .resume = ioapic_resume,
1765 };
1766
1767 static int __init ioapic_init_sysfs(void)
1768 {
1769         struct sys_device * dev;
1770         int i, size, error = 0;
1771
1772         error = sysdev_class_register(&ioapic_sysdev_class);
1773         if (error)
1774                 return error;
1775
1776         for (i = 0; i < nr_ioapics; i++ ) {
1777                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1778                         * sizeof(struct IO_APIC_route_entry);
1779                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1780                 if (!mp_ioapic_data[i]) {
1781                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1782                         continue;
1783                 }
1784                 memset(mp_ioapic_data[i], 0, size);
1785                 dev = &mp_ioapic_data[i]->dev;
1786                 dev->id = i;
1787                 dev->cls = &ioapic_sysdev_class;
1788                 error = sysdev_register(dev);
1789                 if (error) {
1790                         kfree(mp_ioapic_data[i]);
1791                         mp_ioapic_data[i] = NULL;
1792                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1793                         continue;
1794                 }
1795         }
1796
1797         return 0;
1798 }
1799
1800 device_initcall(ioapic_init_sysfs);
1801
1802 /*
1803  * Dynamic irq allocate and deallocation
1804  */
1805 int create_irq(void)
1806 {
1807         /* Allocate an unused irq */
1808         int irq;
1809         int new;
1810         int vector = 0;
1811         unsigned long flags;
1812         cpumask_t mask;
1813
1814         irq = -ENOSPC;
1815         spin_lock_irqsave(&vector_lock, flags);
1816         for (new = (NR_IRQS - 1); new >= 0; new--) {
1817                 if (platform_legacy_irq(new))
1818                         continue;
1819                 if (irq_vector[new] != 0)
1820                         continue;
1821                 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1822                 if (likely(vector > 0))
1823                         irq = new;
1824                 break;
1825         }
1826         spin_unlock_irqrestore(&vector_lock, flags);
1827
1828         if (irq >= 0) {
1829                 dynamic_irq_init(irq);
1830         }
1831         return irq;
1832 }
1833
1834 void destroy_irq(unsigned int irq)
1835 {
1836         unsigned long flags;
1837
1838         dynamic_irq_cleanup(irq);
1839
1840         spin_lock_irqsave(&vector_lock, flags);
1841         __clear_irq_vector(irq);
1842         spin_unlock_irqrestore(&vector_lock, flags);
1843 }
1844
1845 /*
1846  * MSI mesage composition
1847  */
1848 #ifdef CONFIG_PCI_MSI
1849 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1850 {
1851         int vector;
1852         unsigned dest;
1853         cpumask_t tmp;
1854
1855         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1856         if (vector >= 0) {
1857                 dest = cpu_mask_to_apicid(tmp);
1858
1859                 msg->address_hi = MSI_ADDR_BASE_HI;
1860                 msg->address_lo =
1861                         MSI_ADDR_BASE_LO |
1862                         ((INT_DEST_MODE == 0) ?
1863                                 MSI_ADDR_DEST_MODE_PHYSICAL:
1864                                 MSI_ADDR_DEST_MODE_LOGICAL) |
1865                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1866                                 MSI_ADDR_REDIRECTION_CPU:
1867                                 MSI_ADDR_REDIRECTION_LOWPRI) |
1868                         MSI_ADDR_DEST_ID(dest);
1869
1870                 msg->data =
1871                         MSI_DATA_TRIGGER_EDGE |
1872                         MSI_DATA_LEVEL_ASSERT |
1873                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1874                                 MSI_DATA_DELIVERY_FIXED:
1875                                 MSI_DATA_DELIVERY_LOWPRI) |
1876                         MSI_DATA_VECTOR(vector);
1877         }
1878         return vector;
1879 }
1880
1881 #ifdef CONFIG_SMP
1882 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1883 {
1884         struct msi_msg msg;
1885         unsigned int dest;
1886         cpumask_t tmp;
1887         int vector;
1888
1889         cpus_and(tmp, mask, cpu_online_map);
1890         if (cpus_empty(tmp))
1891                 return;
1892
1893         vector = assign_irq_vector(irq, mask, &tmp);
1894         if (vector < 0)
1895                 return;
1896
1897         dest = cpu_mask_to_apicid(tmp);
1898
1899         read_msi_msg(irq, &msg);
1900
1901         msg.data &= ~MSI_DATA_VECTOR_MASK;
1902         msg.data |= MSI_DATA_VECTOR(vector);
1903         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1904         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1905
1906         write_msi_msg(irq, &msg);
1907         irq_desc[irq].affinity = mask;
1908 }
1909 #endif /* CONFIG_SMP */
1910
1911 /*
1912  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1913  * which implement the MSI or MSI-X Capability Structure.
1914  */
1915 static struct irq_chip msi_chip = {
1916         .name           = "PCI-MSI",
1917         .unmask         = unmask_msi_irq,
1918         .mask           = mask_msi_irq,
1919         .ack            = ack_apic_edge,
1920 #ifdef CONFIG_SMP
1921         .set_affinity   = set_msi_irq_affinity,
1922 #endif
1923         .retrigger      = ioapic_retrigger_irq,
1924 };
1925
1926 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
1927 {
1928         struct msi_msg msg;
1929         int irq, ret;
1930         irq = create_irq();
1931         if (irq < 0)
1932                 return irq;
1933
1934         set_irq_msi(irq, desc);
1935         ret = msi_compose_msg(dev, irq, &msg);
1936         if (ret < 0) {
1937                 destroy_irq(irq);
1938                 return ret;
1939         }
1940
1941         write_msi_msg(irq, &msg);
1942
1943         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1944
1945         return irq;
1946 }
1947
1948 void arch_teardown_msi_irq(unsigned int irq)
1949 {
1950         destroy_irq(irq);
1951 }
1952
1953 #endif /* CONFIG_PCI_MSI */
1954
1955 /*
1956  * Hypertransport interrupt support
1957  */
1958 #ifdef CONFIG_HT_IRQ
1959
1960 #ifdef CONFIG_SMP
1961
1962 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1963 {
1964         struct ht_irq_msg msg;
1965         fetch_ht_irq_msg(irq, &msg);
1966
1967         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1968         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1969
1970         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1971         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
1972
1973         write_ht_irq_msg(irq, &msg);
1974 }
1975
1976 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1977 {
1978         unsigned int dest;
1979         cpumask_t tmp;
1980         int vector;
1981
1982         cpus_and(tmp, mask, cpu_online_map);
1983         if (cpus_empty(tmp))
1984                 return;
1985
1986         vector = assign_irq_vector(irq, mask, &tmp);
1987         if (vector < 0)
1988                 return;
1989
1990         dest = cpu_mask_to_apicid(tmp);
1991
1992         target_ht_irq(irq, dest, vector);
1993         irq_desc[irq].affinity = mask;
1994 }
1995 #endif
1996
1997 static struct irq_chip ht_irq_chip = {
1998         .name           = "PCI-HT",
1999         .mask           = mask_ht_irq,
2000         .unmask         = unmask_ht_irq,
2001         .ack            = ack_apic_edge,
2002 #ifdef CONFIG_SMP
2003         .set_affinity   = set_ht_irq_affinity,
2004 #endif
2005         .retrigger      = ioapic_retrigger_irq,
2006 };
2007
2008 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2009 {
2010         int vector;
2011         cpumask_t tmp;
2012
2013         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
2014         if (vector >= 0) {
2015                 struct ht_irq_msg msg;
2016                 unsigned dest;
2017
2018                 dest = cpu_mask_to_apicid(tmp);
2019
2020                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2021
2022                 msg.address_lo =
2023                         HT_IRQ_LOW_BASE |
2024                         HT_IRQ_LOW_DEST_ID(dest) |
2025                         HT_IRQ_LOW_VECTOR(vector) |
2026                         ((INT_DEST_MODE == 0) ?
2027                                 HT_IRQ_LOW_DM_PHYSICAL :
2028                                 HT_IRQ_LOW_DM_LOGICAL) |
2029                         HT_IRQ_LOW_RQEOI_EDGE |
2030                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2031                                 HT_IRQ_LOW_MT_FIXED :
2032                                 HT_IRQ_LOW_MT_ARBITRATED) |
2033                         HT_IRQ_LOW_IRQ_MASKED;
2034
2035                 write_ht_irq_msg(irq, &msg);
2036
2037                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2038                                               handle_edge_irq, "edge");
2039         }
2040         return vector;
2041 }
2042 #endif /* CONFIG_HT_IRQ */
2043
2044 /* --------------------------------------------------------------------------
2045                           ACPI-based IOAPIC Configuration
2046    -------------------------------------------------------------------------- */
2047
2048 #ifdef CONFIG_ACPI
2049
2050 #define IO_APIC_MAX_ID          0xFE
2051
2052 int __init io_apic_get_redir_entries (int ioapic)
2053 {
2054         union IO_APIC_reg_01    reg_01;
2055         unsigned long flags;
2056
2057         spin_lock_irqsave(&ioapic_lock, flags);
2058         reg_01.raw = io_apic_read(ioapic, 1);
2059         spin_unlock_irqrestore(&ioapic_lock, flags);
2060
2061         return reg_01.bits.entries;
2062 }
2063
2064
2065 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2066 {
2067         if (!IO_APIC_IRQ(irq)) {
2068                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2069                         ioapic);
2070                 return -EINVAL;
2071         }
2072
2073         /*
2074          * IRQs < 16 are already in the irq_2_pin[] map
2075          */
2076         if (irq >= 16)
2077                 add_pin_to_irq(irq, ioapic, pin);
2078
2079         setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2080
2081         return 0;
2082 }
2083
2084 #endif /* CONFIG_ACPI */
2085
2086
2087 /*
2088  * This function currently is only a helper for the i386 smp boot process where
2089  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2090  * so mask in all cases should simply be TARGET_CPUS
2091  */
2092 #ifdef CONFIG_SMP
2093 void __init setup_ioapic_dest(void)
2094 {
2095         int pin, ioapic, irq, irq_entry;
2096
2097         if (skip_ioapic_setup == 1)
2098                 return;
2099
2100         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2101                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2102                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2103                         if (irq_entry == -1)
2104                                 continue;
2105                         irq = pin_2_irq(irq_entry, ioapic, pin);
2106
2107                         /* setup_IO_APIC_irqs could fail to get vector for some device
2108                          * when you have too many devices, because at that time only boot
2109                          * cpu is online.
2110                          */
2111                         if(!irq_vector[irq])
2112                                 setup_IO_APIC_irq(ioapic, pin, irq,
2113                                                   irq_trigger(irq_entry),
2114                                                   irq_polarity(irq_entry));
2115                         else
2116                                 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2117                 }
2118
2119         }
2120 }
2121 #endif