arch/x86/kvm/x86.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * derived from drivers/kvm/kvm_main.c
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright (C) 2008 Qumranet, Inc.
   8  * Copyright IBM Corporation, 2008
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  *   Amit Shah    <amit.shah@qumranet.com>
  15  *   Ben-Ami Yassour <benami@il.ibm.com>
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  *
  20  */
  21
  22 #include <linux/kvm_host.h>
  23 #include "irq.h"
  24 #include "mmu.h"
  25 #include "i8254.h"
  26 #include "tss.h"
  27 #include "kvm_cache_regs.h"
  28 #include "x86.h"
  29 #include "cpuid.h"
  30
  31 #include <linux/clocksource.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/kvm.h>
  34 #include <linux/fs.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/module.h>
  37 #include <linux/mman.h>
  38 #include <linux/highmem.h>
  39 #include <linux/iommu.h>
  40 #include <linux/intel-iommu.h>
  41 #include <linux/cpufreq.h>
  42 #include <linux/user-return-notifier.h>
  43 #include <linux/srcu.h>
  44 #include <linux/slab.h>
  45 #include <linux/perf_event.h>
  46 #include <linux/uaccess.h>
  47 #include <linux/hash.h>
  48 #include <linux/pci.h>
  49 #include <linux/timekeeper_internal.h>
  50 #include <linux/pvclock_gtod.h>
  51 #include <trace/events/kvm.h>
  52
  53 #define CREATE_TRACE_POINTS
  54 #include "trace.h"
  55
  56 #include <asm/debugreg.h>
  57 #include <asm/msr.h>
  58 #include <asm/desc.h>
  59 #include <asm/mtrr.h>
  60 #include <asm/mce.h>
  61 #include <asm/i387.h>
  62 #include <asm/fpu-internal.h> /* Ugh! */
  63 #include <asm/xcr.h>
  64 #include <asm/pvclock.h>
  65 #include <asm/div64.h>
  66
  67 #define MAX_IO_MSRS 256
  68 #define KVM_MAX_MCE_BANKS 32
  69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
  70
  71 #define emul_to_vcpu(ctxt) \
  72         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
  73
  74 /* EFER defaults:
  75  * - enable syscall per default because its emulated by KVM
  76  * - enable LME and LMA per default on 64 bit KVM
  77  */
  78 #ifdef CONFIG_X86_64
  79 static
  80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  81 #else
  82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  83 #endif
  84
  85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
  86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
  87
  88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
  89 static void process_nmi(struct kvm_vcpu *vcpu);
  90
  91 struct kvm_x86_ops *kvm_x86_ops;
  92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
  93
  94 static bool ignore_msrs = 0;
  95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
  96
  97 unsigned int min_timer_period_us = 500;
  98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
  99
 100 bool kvm_has_tsc_control;
 101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 102 u32  kvm_max_guest_tsc_khz;
 103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 104
 105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 106 static u32 tsc_tolerance_ppm = 250;
 107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 108
 109 #define KVM_NR_SHARED_MSRS 16
 110
 111 struct kvm_shared_msrs_global {
 112         int nr;
 113         u32 msrs[KVM_NR_SHARED_MSRS];
 114 };
 115
 116 struct kvm_shared_msrs {
 117         struct user_return_notifier urn;
 118         bool registered;
 119         struct kvm_shared_msr_values {
 120                 u64 host;
 121                 u64 curr;
 122         } values[KVM_NR_SHARED_MSRS];
 123 };
 124
 125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 126 static struct kvm_shared_msrs __percpu *shared_msrs;
 127
 128 struct kvm_stats_debugfs_item debugfs_entries[] = {
 129         { "pf_fixed", VCPU_STAT(pf_fixed) },
 130         { "pf_guest", VCPU_STAT(pf_guest) },
 131         { "tlb_flush", VCPU_STAT(tlb_flush) },
 132         { "invlpg", VCPU_STAT(invlpg) },
 133         { "exits", VCPU_STAT(exits) },
 134         { "io_exits", VCPU_STAT(io_exits) },
 135         { "mmio_exits", VCPU_STAT(mmio_exits) },
 136         { "signal_exits", VCPU_STAT(signal_exits) },
 137         { "irq_window", VCPU_STAT(irq_window_exits) },
 138         { "nmi_window", VCPU_STAT(nmi_window_exits) },
 139         { "halt_exits", VCPU_STAT(halt_exits) },
 140         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
 141         { "hypercalls", VCPU_STAT(hypercalls) },
 142         { "request_irq", VCPU_STAT(request_irq_exits) },
 143         { "irq_exits", VCPU_STAT(irq_exits) },
 144         { "host_state_reload", VCPU_STAT(host_state_reload) },
 145         { "efer_reload", VCPU_STAT(efer_reload) },
 146         { "fpu_reload", VCPU_STAT(fpu_reload) },
 147         { "insn_emulation", VCPU_STAT(insn_emulation) },
 148         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
 149         { "irq_injections", VCPU_STAT(irq_injections) },
 150         { "nmi_injections", VCPU_STAT(nmi_injections) },
 151         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
 152         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
 153         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
 154         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
 155         { "mmu_flooded", VM_STAT(mmu_flooded) },
 156         { "mmu_recycled", VM_STAT(mmu_recycled) },
 157         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
 158         { "mmu_unsync", VM_STAT(mmu_unsync) },
 159         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
 160         { "largepages", VM_STAT(lpages) },
 161         { NULL }
 162 };
 163
 164 u64 __read_mostly host_xcr0;
 165
 166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 167
 168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 169 {
 170         int i;
 171         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
 172                 vcpu->arch.apf.gfns[i] = ~0;
 173 }
 174
 175 static void kvm_on_user_return(struct user_return_notifier *urn)
 176 {
 177         unsigned slot;
 178         struct kvm_shared_msrs *locals
 179                 = container_of(urn, struct kvm_shared_msrs, urn);
 180         struct kvm_shared_msr_values *values;
 181
 182         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 183                 values = &locals->values[slot];
 184                 if (values->host != values->curr) {
 185                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 186                         values->curr = values->host;
 187                 }
 188         }
 189         locals->registered = false;
 190         user_return_notifier_unregister(urn);
 191 }
 192
 193 static void shared_msr_update(unsigned slot, u32 msr)
 194 {
 195         u64 value;
 196         unsigned int cpu = smp_processor_id();
 197         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 198
 199         /* only read, and nobody should modify it at this time,
 200          * so don't need lock */
 201         if (slot >= shared_msrs_global.nr) {
 202                 printk(KERN_ERR "kvm: invalid MSR slot!");
 203                 return;
 204         }
 205         rdmsrl_safe(msr, &value);
 206         smsr->values[slot].host = value;
 207         smsr->values[slot].curr = value;
 208 }
 209
 210 void kvm_define_shared_msr(unsigned slot, u32 msr)
 211 {
 212         if (slot >= shared_msrs_global.nr)
 213                 shared_msrs_global.nr = slot + 1;
 214         shared_msrs_global.msrs[slot] = msr;
 215         /* we need ensured the shared_msr_global have been updated */
 216         smp_wmb();
 217 }
 218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 219
 220 static void kvm_shared_msr_cpu_online(void)
 221 {
 222         unsigned i;
 223
 224         for (i = 0; i < shared_msrs_global.nr; ++i)
 225                 shared_msr_update(i, shared_msrs_global.msrs[i]);
 226 }
 227
 228 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 229 {
 230         unsigned int cpu = smp_processor_id();
 231         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 232
 233         if (((value ^ smsr->values[slot].curr) & mask) == 0)
 234                 return;
 235         smsr->values[slot].curr = value;
 236         wrmsrl(shared_msrs_global.msrs[slot], value);
 237         if (!smsr->registered) {
 238                 smsr->urn.on_user_return = kvm_on_user_return;
 239                 user_return_notifier_register(&smsr->urn);
 240                 smsr->registered = true;
 241         }
 242 }
 243 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 244
 245 static void drop_user_return_notifiers(void *ignore)
 246 {
 247         unsigned int cpu = smp_processor_id();
 248         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 249
 250         if (smsr->registered)
 251                 kvm_on_user_return(&smsr->urn);
 252 }
 253
 254 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 255 {
 256         return vcpu->arch.apic_base;
 257 }
 258 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 259
 260 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 261 {
 262         u64 old_state = vcpu->arch.apic_base &
 263                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
 264         u64 new_state = msr_info->data &
 265                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
 266         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
 267                 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
 268
 269         if (!msr_info->host_initiated &&
 270             ((msr_info->data & reserved_bits) != 0 ||
 271              new_state == X2APIC_ENABLE ||
 272              (new_state == MSR_IA32_APICBASE_ENABLE &&
 273               old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
 274              (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
 275               old_state == 0)))
 276                 return 1;
 277
 278         kvm_lapic_set_base(vcpu, msr_info->data);
 279         return 0;
 280 }
 281 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 282
 283 asmlinkage void kvm_spurious_fault(void)
 284 {
 285         /* Fault while not rebooting.  We want the trace. */
 286         BUG();
 287 }
 288 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 289
 290 #define EXCPT_BENIGN            0
 291 #define EXCPT_CONTRIBUTORY      1
 292 #define EXCPT_PF                2
 293
 294 static int exception_class(int vector)
 295 {
 296         switch (vector) {
 297         case PF_VECTOR:
 298                 return EXCPT_PF;
 299         case DE_VECTOR:
 300         case TS_VECTOR:
 301         case NP_VECTOR:
 302         case SS_VECTOR:
 303         case GP_VECTOR:
 304                 return EXCPT_CONTRIBUTORY;
 305         default:
 306                 break;
 307         }
 308         return EXCPT_BENIGN;
 309 }
 310
 311 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 312                 unsigned nr, bool has_error, u32 error_code,
 313                 bool reinject)
 314 {
 315         u32 prev_nr;
 316         int class1, class2;
 317
 318         kvm_make_request(KVM_REQ_EVENT, vcpu);
 319
 320         if (!vcpu->arch.exception.pending) {
 321         queue:
 322                 vcpu->arch.exception.pending = true;
 323                 vcpu->arch.exception.has_error_code = has_error;
 324                 vcpu->arch.exception.nr = nr;
 325                 vcpu->arch.exception.error_code = error_code;
 326                 vcpu->arch.exception.reinject = reinject;
 327                 return;
 328         }
 329
 330         /* to check exception */
 331         prev_nr = vcpu->arch.exception.nr;
 332         if (prev_nr == DF_VECTOR) {
 333                 /* triple fault -> shutdown */
 334                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 335                 return;
 336         }
 337         class1 = exception_class(prev_nr);
 338         class2 = exception_class(nr);
 339         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 340                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 341                 /* generate double fault per SDM Table 5-5 */
 342                 vcpu->arch.exception.pending = true;
 343                 vcpu->arch.exception.has_error_code = true;
 344                 vcpu->arch.exception.nr = DF_VECTOR;
 345                 vcpu->arch.exception.error_code = 0;
 346         } else
 347                 /* replace previous exception with a new one in a hope
 348                    that instruction re-execution will regenerate lost
 349                    exception */
 350                 goto queue;
 351 }
 352
 353 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 354 {
 355         kvm_multiple_exception(vcpu, nr, false, 0, false);
 356 }
 357 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 358
 359 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 360 {
 361         kvm_multiple_exception(vcpu, nr, false, 0, true);
 362 }
 363 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 364
 365 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 366 {
 367         if (err)
 368                 kvm_inject_gp(vcpu, 0);
 369         else
 370                 kvm_x86_ops->skip_emulated_instruction(vcpu);
 371 }
 372 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 373
 374 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 375 {
 376         ++vcpu->stat.pf_guest;
 377         vcpu->arch.cr2 = fault->address;
 378         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 379 }
 380 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 381
 382 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 383 {
 384         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
 385                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
 386         else
 387                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
 388 }
 389
 390 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 391 {
 392         atomic_inc(&vcpu->arch.nmi_queued);
 393         kvm_make_request(KVM_REQ_NMI, vcpu);
 394 }
 395 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 396
 397 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 398 {
 399         kvm_multiple_exception(vcpu, nr, true, error_code, false);
 400 }
 401 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 402
 403 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 404 {
 405         kvm_multiple_exception(vcpu, nr, true, error_code, true);
 406 }
 407 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 408
 409 /*
 410  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 411  * a #GP and return false.
 412  */
 413 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 414 {
 415         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
 416                 return true;
 417         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 418         return false;
 419 }
 420 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 421
 422 /*
 423  * This function will be used to read from the physical memory of the currently
 424  * running guest. The difference to kvm_read_guest_page is that this function
 425  * can read from guest physical or from the guest's guest physical memory.
 426  */
 427 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 428                             gfn_t ngfn, void *data, int offset, int len,
 429                             u32 access)
 430 {
 431         gfn_t real_gfn;
 432         gpa_t ngpa;
 433
 434         ngpa     = gfn_to_gpa(ngfn);
 435         real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
 436         if (real_gfn == UNMAPPED_GVA)
 437                 return -EFAULT;
 438
 439         real_gfn = gpa_to_gfn(real_gfn);
 440
 441         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
 442 }
 443 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 444
 445 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 446                                void *data, int offset, int len, u32 access)
 447 {
 448         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 449                                        data, offset, len, access);
 450 }
 451
 452 /*
 453  * Load the pae pdptrs.  Return true is they are all valid.
 454  */
 455 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 456 {
 457         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 458         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 459         int i;
 460         int ret;
 461         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 462
 463         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 464                                       offset * sizeof(u64), sizeof(pdpte),
 465                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 466         if (ret < 0) {
 467                 ret = 0;
 468                 goto out;
 469         }
 470         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 471                 if (is_present_gpte(pdpte[i]) &&
 472                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
 473                         ret = 0;
 474                         goto out;
 475                 }
 476         }
 477         ret = 1;
 478
 479         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 480         __set_bit(VCPU_EXREG_PDPTR,
 481                   (unsigned long *)&vcpu->arch.regs_avail);
 482         __set_bit(VCPU_EXREG_PDPTR,
 483                   (unsigned long *)&vcpu->arch.regs_dirty);
 484 out:
 485
 486         return ret;
 487 }
 488 EXPORT_SYMBOL_GPL(load_pdptrs);
 489
 490 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
 491 {
 492         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 493         bool changed = true;
 494         int offset;
 495         gfn_t gfn;
 496         int r;
 497
 498         if (is_long_mode(vcpu) || !is_pae(vcpu))
 499                 return false;
 500
 501         if (!test_bit(VCPU_EXREG_PDPTR,
 502                       (unsigned long *)&vcpu->arch.regs_avail))
 503                 return true;
 504
 505         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
 506         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
 507         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 508                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 509         if (r < 0)
 510                 goto out;
 511         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 512 out:
 513
 514         return changed;
 515 }
 516
 517 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 518 {
 519         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 520         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
 521                                     X86_CR0_CD | X86_CR0_NW;
 522
 523         cr0 |= X86_CR0_ET;
 524
 525 #ifdef CONFIG_X86_64
 526         if (cr0 & 0xffffffff00000000UL)
 527                 return 1;
 528 #endif
 529
 530         cr0 &= ~CR0_RESERVED_BITS;
 531
 532         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 533                 return 1;
 534
 535         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 536                 return 1;
 537
 538         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 539 #ifdef CONFIG_X86_64
 540                 if ((vcpu->arch.efer & EFER_LME)) {
 541                         int cs_db, cs_l;
 542
 543                         if (!is_pae(vcpu))
 544                                 return 1;
 545                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 546                         if (cs_l)
 547                                 return 1;
 548                 } else
 549 #endif
 550                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 551                                                  kvm_read_cr3(vcpu)))
 552                         return 1;
 553         }
 554
 555         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 556                 return 1;
 557
 558         kvm_x86_ops->set_cr0(vcpu, cr0);
 559
 560         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 561                 kvm_clear_async_pf_completion_queue(vcpu);
 562                 kvm_async_pf_hash_reset(vcpu);
 563         }
 564
 565         if ((cr0 ^ old_cr0) & update_bits)
 566                 kvm_mmu_reset_context(vcpu);
 567         return 0;
 568 }
 569 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 570
 571 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 572 {
 573         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 574 }
 575 EXPORT_SYMBOL_GPL(kvm_lmsw);
 576
 577 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
 578 {
 579         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
 580                         !vcpu->guest_xcr0_loaded) {
 581                 /* kvm_set_xcr() also depends on this */
 582                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 583                 vcpu->guest_xcr0_loaded = 1;
 584         }
 585 }
 586
 587 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
 588 {
 589         if (vcpu->guest_xcr0_loaded) {
 590                 if (vcpu->arch.xcr0 != host_xcr0)
 591                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 592                 vcpu->guest_xcr0_loaded = 0;
 593         }
 594 }
 595
 596 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 597 {
 598         u64 xcr0 = xcr;
 599         u64 old_xcr0 = vcpu->arch.xcr0;
 600         u64 valid_bits;
 601
 602         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 603         if (index != XCR_XFEATURE_ENABLED_MASK)
 604                 return 1;
 605         if (!(xcr0 & XSTATE_FP))
 606                 return 1;
 607         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
 608                 return 1;
 609
 610         /*
 611          * Do not allow the guest to set bits that we do not support
 612          * saving.  However, xcr0 bit 0 is always set, even if the
 613          * emulated CPU does not support XSAVE (see fx_init).
 614          */
 615         valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
 616         if (xcr0 & ~valid_bits)
 617                 return 1;
 618
 619         if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
 620                 return 1;
 621
 622         kvm_put_guest_xcr0(vcpu);
 623         vcpu->arch.xcr0 = xcr0;
 624
 625         if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
 626                 kvm_update_cpuid(vcpu);
 627         return 0;
 628 }
 629
 630 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 631 {
 632         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
 633             __kvm_set_xcr(vcpu, index, xcr)) {
 634                 kvm_inject_gp(vcpu, 0);
 635                 return 1;
 636         }
 637         return 0;
 638 }
 639 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 640
 641 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 642 {
 643         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 644         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
 645                                    X86_CR4_PAE | X86_CR4_SMEP;
 646         if (cr4 & CR4_RESERVED_BITS)
 647                 return 1;
 648
 649         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
 650                 return 1;
 651
 652         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
 653                 return 1;
 654
 655         if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
 656                 return 1;
 657
 658         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
 659                 return 1;
 660
 661         if (is_long_mode(vcpu)) {
 662                 if (!(cr4 & X86_CR4_PAE))
 663                         return 1;
 664         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 665                    && ((cr4 ^ old_cr4) & pdptr_bits)
 666                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 667                                    kvm_read_cr3(vcpu)))
 668                 return 1;
 669
 670         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
 671                 if (!guest_cpuid_has_pcid(vcpu))
 672                         return 1;
 673
 674                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
 675                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
 676                         return 1;
 677         }
 678
 679         if (kvm_x86_ops->set_cr4(vcpu, cr4))
 680                 return 1;
 681
 682         if (((cr4 ^ old_cr4) & pdptr_bits) ||
 683             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
 684                 kvm_mmu_reset_context(vcpu);
 685
 686         if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
 687                 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
 688
 689         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
 690                 kvm_update_cpuid(vcpu);
 691
 692         return 0;
 693 }
 694 EXPORT_SYMBOL_GPL(kvm_set_cr4);
 695
 696 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 697 {
 698         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
 699                 kvm_mmu_sync_roots(vcpu);
 700                 kvm_mmu_flush_tlb(vcpu);
 701                 return 0;
 702         }
 703
 704         if (is_long_mode(vcpu)) {
 705                 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
 706                         if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
 707                                 return 1;
 708                 } else
 709                         if (cr3 & CR3_L_MODE_RESERVED_BITS)
 710                                 return 1;
 711         } else {
 712                 if (is_pae(vcpu)) {
 713                         if (cr3 & CR3_PAE_RESERVED_BITS)
 714                                 return 1;
 715                         if (is_paging(vcpu) &&
 716                             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
 717                                 return 1;
 718                 }
 719                 /*
 720                  * We don't check reserved bits in nonpae mode, because
 721                  * this isn't enforced, and VMware depends on this.
 722                  */
 723         }
 724
 725         vcpu->arch.cr3 = cr3;
 726         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
 727         kvm_mmu_new_cr3(vcpu);
 728         return 0;
 729 }
 730 EXPORT_SYMBOL_GPL(kvm_set_cr3);
 731
 732 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
 733 {
 734         if (cr8 & CR8_RESERVED_BITS)
 735                 return 1;
 736         if (irqchip_in_kernel(vcpu->kvm))
 737                 kvm_lapic_set_tpr(vcpu, cr8);
 738         else
 739                 vcpu->arch.cr8 = cr8;
 740         return 0;
 741 }
 742 EXPORT_SYMBOL_GPL(kvm_set_cr8);
 743
 744 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
 745 {
 746         if (irqchip_in_kernel(vcpu->kvm))
 747                 return kvm_lapic_get_cr8(vcpu);
 748         else
 749                 return vcpu->arch.cr8;
 750 }
 751 EXPORT_SYMBOL_GPL(kvm_get_cr8);
 752
 753 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
 754 {
 755         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
 756                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
 757 }
 758
 759 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
 760 {
 761         unsigned long dr7;
 762
 763         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 764                 dr7 = vcpu->arch.guest_debug_dr7;
 765         else
 766                 dr7 = vcpu->arch.dr7;
 767         kvm_x86_ops->set_dr7(vcpu, dr7);
 768         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
 769         if (dr7 & DR7_BP_EN_MASK)
 770                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
 771 }
 772
 773 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
 774 {
 775         switch (dr) {
 776         case 0 ... 3:
 777                 vcpu->arch.db[dr] = val;
 778                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
 779                         vcpu->arch.eff_db[dr] = val;
 780                 break;
 781         case 4:
 782                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 783                         return 1; /* #UD */
 784                 /* fall through */
 785         case 6:
 786                 if (val & 0xffffffff00000000ULL)
 787                         return -1; /* #GP */
 788                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
 789                 kvm_update_dr6(vcpu);
 790                 break;
 791         case 5:
 792                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 793                         return 1; /* #UD */
 794                 /* fall through */
 795         default: /* 7 */
 796                 if (val & 0xffffffff00000000ULL)
 797                         return -1; /* #GP */
 798                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
 799                 kvm_update_dr7(vcpu);
 800                 break;
 801         }
 802
 803         return 0;
 804 }
 805
 806 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
 807 {
 808         int res;
 809
 810         res = __kvm_set_dr(vcpu, dr, val);
 811         if (res > 0)
 812                 kvm_queue_exception(vcpu, UD_VECTOR);
 813         else if (res < 0)
 814                 kvm_inject_gp(vcpu, 0);
 815
 816         return res;
 817 }
 818 EXPORT_SYMBOL_GPL(kvm_set_dr);
 819
 820 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 821 {
 822         switch (dr) {
 823         case 0 ... 3:
 824                 *val = vcpu->arch.db[dr];
 825                 break;
 826         case 4:
 827                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 828                         return 1;
 829                 /* fall through */
 830         case 6:
 831                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 832                         *val = vcpu->arch.dr6;
 833                 else
 834                         *val = kvm_x86_ops->get_dr6(vcpu);
 835                 break;
 836         case 5:
 837                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 838                         return 1;
 839                 /* fall through */
 840         default: /* 7 */
 841                 *val = vcpu->arch.dr7;
 842                 break;
 843         }
 844
 845         return 0;
 846 }
 847
 848 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 849 {
 850         if (_kvm_get_dr(vcpu, dr, val)) {
 851                 kvm_queue_exception(vcpu, UD_VECTOR);
 852                 return 1;
 853         }
 854         return 0;
 855 }
 856 EXPORT_SYMBOL_GPL(kvm_get_dr);
 857
 858 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
 859 {
 860         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
 861         u64 data;
 862         int err;
 863
 864         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
 865         if (err)
 866                 return err;
 867         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
 868         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
 869         return err;
 870 }
 871 EXPORT_SYMBOL_GPL(kvm_rdpmc);
 872
 873 /*
 874  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
 875  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
 876  *
 877  * This list is modified at module load time to reflect the
 878  * capabilities of the host cpu. This capabilities test skips MSRs that are
 879  * kvm-specific. Those are put in the beginning of the list.
 880  */
 881
 882 #define KVM_SAVE_MSRS_BEGIN     12
 883 static u32 msrs_to_save[] = {
 884         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
 885         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
 886         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
 887         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
 888         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
 889         MSR_KVM_PV_EOI_EN,
 890         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 891         MSR_STAR,
 892 #ifdef CONFIG_X86_64
 893         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
 894 #endif
 895         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
 896         MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
 897 };
 898
 899 static unsigned num_msrs_to_save;
 900
 901 static const u32 emulated_msrs[] = {
 902         MSR_IA32_TSC_ADJUST,
 903         MSR_IA32_TSCDEADLINE,
 904         MSR_IA32_MISC_ENABLE,
 905         MSR_IA32_MCG_STATUS,
 906         MSR_IA32_MCG_CTL,
 907 };
 908
 909 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
 910 {
 911         if (efer & efer_reserved_bits)
 912                 return false;
 913
 914         if (efer & EFER_FFXSR) {
 915                 struct kvm_cpuid_entry2 *feat;
 916
 917                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
 918                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
 919                         return false;
 920         }
 921
 922         if (efer & EFER_SVME) {
 923                 struct kvm_cpuid_entry2 *feat;
 924
 925                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
 926                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
 927                         return false;
 928         }
 929
 930         return true;
 931 }
 932 EXPORT_SYMBOL_GPL(kvm_valid_efer);
 933
 934 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
 935 {
 936         u64 old_efer = vcpu->arch.efer;
 937
 938         if (!kvm_valid_efer(vcpu, efer))
 939                 return 1;
 940
 941         if (is_paging(vcpu)
 942             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
 943                 return 1;
 944
 945         efer &= ~EFER_LMA;
 946         efer |= vcpu->arch.efer & EFER_LMA;
 947
 948         kvm_x86_ops->set_efer(vcpu, efer);
 949
 950         /* Update reserved bits */
 951         if ((efer ^ old_efer) & EFER_NX)
 952                 kvm_mmu_reset_context(vcpu);
 953
 954         return 0;
 955 }
 956
 957 void kvm_enable_efer_bits(u64 mask)
 958 {
 959        efer_reserved_bits &= ~mask;
 960 }
 961 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
 962
 963
 964 /*
 965  * Writes msr value into into the appropriate "register".
 966  * Returns 0 on success, non-0 otherwise.
 967  * Assumes vcpu_load() was already called.
 968  */
 969 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
 970 {
 971         return kvm_x86_ops->set_msr(vcpu, msr);
 972 }
 973
 974 /*
 975  * Adapt set_msr() to msr_io()'s calling convention
 976  */
 977 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
 978 {
 979         struct msr_data msr;
 980
 981         msr.data = *data;
 982         msr.index = index;
 983         msr.host_initiated = true;
 984         return kvm_set_msr(vcpu, &msr);
 985 }
 986
 987 #ifdef CONFIG_X86_64
 988 struct pvclock_gtod_data {
 989         seqcount_t      seq;
 990
 991         struct { /* extract of a clocksource struct */
 992                 int vclock_mode;
 993                 cycle_t cycle_last;
 994                 cycle_t mask;
 995                 u32     mult;
 996                 u32     shift;
 997         } clock;
 998
 999         /* open coded 'struct timespec' */
1000         u64             monotonic_time_snsec;
1001         time_t          monotonic_time_sec;
1002 };
1003
1004 static struct pvclock_gtod_data pvclock_gtod_data;
1005
1006 static void update_pvclock_gtod(struct timekeeper *tk)
1007 {
1008         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1009
1010         write_seqcount_begin(&vdata->seq);
1011
1012         /* copy pvclock gtod data */
1013         vdata->clock.vclock_mode        = tk->clock->archdata.vclock_mode;
1014         vdata->clock.cycle_last         = tk->clock->cycle_last;
1015         vdata->clock.mask               = tk->clock->mask;
1016         vdata->clock.mult               = tk->mult;
1017         vdata->clock.shift              = tk->shift;
1018
1019         vdata->monotonic_time_sec       = tk->xtime_sec
1020                                         + tk->wall_to_monotonic.tv_sec;
1021         vdata->monotonic_time_snsec     = tk->xtime_nsec
1022                                         + (tk->wall_to_monotonic.tv_nsec
1023                                                 << tk->shift);
1024         while (vdata->monotonic_time_snsec >=
1025                                         (((u64)NSEC_PER_SEC) << tk->shift)) {
1026                 vdata->monotonic_time_snsec -=
1027                                         ((u64)NSEC_PER_SEC) << tk->shift;
1028                 vdata->monotonic_time_sec++;
1029         }
1030
1031         write_seqcount_end(&vdata->seq);
1032 }
1033 #endif
1034
1035
1036 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1037 {
1038         int version;
1039         int r;
1040         struct pvclock_wall_clock wc;
1041         struct timespec boot;
1042
1043         if (!wall_clock)
1044                 return;
1045
1046         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1047         if (r)
1048                 return;
1049
1050         if (version & 1)
1051                 ++version;  /* first time write, random junk */
1052
1053         ++version;
1054
1055         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1056
1057         /*
1058          * The guest calculates current wall clock time by adding
1059          * system time (updated by kvm_guest_time_update below) to the
1060          * wall clock specified here.  guest system time equals host
1061          * system time for us, thus we must fill in host boot time here.
1062          */
1063         getboottime(&boot);
1064
1065         if (kvm->arch.kvmclock_offset) {
1066                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1067                 boot = timespec_sub(boot, ts);
1068         }
1069         wc.sec = boot.tv_sec;
1070         wc.nsec = boot.tv_nsec;
1071         wc.version = version;
1072
1073         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1074
1075         version++;
1076         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1077 }
1078
1079 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1080 {
1081         uint32_t quotient, remainder;
1082
1083         /* Don't try to replace with do_div(), this one calculates
1084          * "(dividend << 32) / divisor" */
1085         __asm__ ( "divl %4"
1086                   : "=a" (quotient), "=d" (remainder)
1087                   : "0" (0), "1" (dividend), "r" (divisor) );
1088         return quotient;
1089 }
1090
1091 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1092                                s8 *pshift, u32 *pmultiplier)
1093 {
1094         uint64_t scaled64;
1095         int32_t  shift = 0;
1096         uint64_t tps64;
1097         uint32_t tps32;
1098
1099         tps64 = base_khz * 1000LL;
1100         scaled64 = scaled_khz * 1000LL;
1101         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1102                 tps64 >>= 1;
1103                 shift--;
1104         }
1105
1106         tps32 = (uint32_t)tps64;
1107         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1108                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1109                         scaled64 >>= 1;
1110                 else
1111                         tps32 <<= 1;
1112                 shift++;
1113         }
1114
1115         *pshift = shift;
1116         *pmultiplier = div_frac(scaled64, tps32);
1117
1118         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1119                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
1120 }
1121
1122 static inline u64 get_kernel_ns(void)
1123 {
1124         struct timespec ts;
1125
1126         ktime_get_ts(&ts);
1127         monotonic_to_bootbased(&ts);
1128         return timespec_to_ns(&ts);
1129 }
1130
1131 #ifdef CONFIG_X86_64
1132 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1133 #endif
1134
1135 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1136 unsigned long max_tsc_khz;
1137
1138 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1139 {
1140         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1141                                    vcpu->arch.virtual_tsc_shift);
1142 }
1143
1144 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1145 {
1146         u64 v = (u64)khz * (1000000 + ppm);
1147         do_div(v, 1000000);
1148         return v;
1149 }
1150
1151 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1152 {
1153         u32 thresh_lo, thresh_hi;
1154         int use_scaling = 0;
1155
1156         /* tsc_khz can be zero if TSC calibration fails */
1157         if (this_tsc_khz == 0)
1158                 return;
1159
1160         /* Compute a scale to convert nanoseconds in TSC cycles */
1161         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1162                            &vcpu->arch.virtual_tsc_shift,
1163                            &vcpu->arch.virtual_tsc_mult);
1164         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1165
1166         /*
1167          * Compute the variation in TSC rate which is acceptable
1168          * within the range of tolerance and decide if the
1169          * rate being applied is within that bounds of the hardware
1170          * rate.  If so, no scaling or compensation need be done.
1171          */
1172         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1173         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1174         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1175                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1176                 use_scaling = 1;
1177         }
1178         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1179 }
1180
1181 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1182 {
1183         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1184                                       vcpu->arch.virtual_tsc_mult,
1185                                       vcpu->arch.virtual_tsc_shift);
1186         tsc += vcpu->arch.this_tsc_write;
1187         return tsc;
1188 }
1189
1190 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1191 {
1192 #ifdef CONFIG_X86_64
1193         bool vcpus_matched;
1194         bool do_request = false;
1195         struct kvm_arch *ka = &vcpu->kvm->arch;
1196         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1197
1198         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1199                          atomic_read(&vcpu->kvm->online_vcpus));
1200
1201         if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1202                 if (!ka->use_master_clock)
1203                         do_request = 1;
1204
1205         if (!vcpus_matched && ka->use_master_clock)
1206                         do_request = 1;
1207
1208         if (do_request)
1209                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1210
1211         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1212                             atomic_read(&vcpu->kvm->online_vcpus),
1213                             ka->use_master_clock, gtod->clock.vclock_mode);
1214 #endif
1215 }
1216
1217 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1218 {
1219         u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1220         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1221 }
1222
1223 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1224 {
1225         struct kvm *kvm = vcpu->kvm;
1226         u64 offset, ns, elapsed;
1227         unsigned long flags;
1228         s64 usdiff;
1229         bool matched;
1230         u64 data = msr->data;
1231
1232         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1233         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1234         ns = get_kernel_ns();
1235         elapsed = ns - kvm->arch.last_tsc_nsec;
1236
1237         if (vcpu->arch.virtual_tsc_khz) {
1238                 int faulted = 0;
1239
1240                 /* n.b - signed multiplication and division required */
1241                 usdiff = data - kvm->arch.last_tsc_write;
1242 #ifdef CONFIG_X86_64
1243                 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1244 #else
1245                 /* do_div() only does unsigned */
1246                 asm("1: idivl %[divisor]\n"
1247                     "2: xor %%edx, %%edx\n"
1248                     "   movl $0, %[faulted]\n"
1249                     "3:\n"
1250                     ".section .fixup,\"ax\"\n"
1251                     "4: movl $1, %[faulted]\n"
1252                     "   jmp  3b\n"
1253                     ".previous\n"
1254
1255                 _ASM_EXTABLE(1b, 4b)
1256
1257                 : "=A"(usdiff), [faulted] "=r" (faulted)
1258                 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1259
1260 #endif
1261                 do_div(elapsed, 1000);
1262                 usdiff -= elapsed;
1263                 if (usdiff < 0)
1264                         usdiff = -usdiff;
1265
1266                 /* idivl overflow => difference is larger than USEC_PER_SEC */
1267                 if (faulted)
1268                         usdiff = USEC_PER_SEC;
1269         } else
1270                 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1271
1272         /*
1273          * Special case: TSC write with a small delta (1 second) of virtual
1274          * cycle time against real time is interpreted as an attempt to
1275          * synchronize the CPU.
1276          *
1277          * For a reliable TSC, we can match TSC offsets, and for an unstable
1278          * TSC, we add elapsed time in this computation.  We could let the
1279          * compensation code attempt to catch up if we fall behind, but
1280          * it's better to try to match offsets from the beginning.
1281          */
1282         if (usdiff < USEC_PER_SEC &&
1283             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1284                 if (!check_tsc_unstable()) {
1285                         offset = kvm->arch.cur_tsc_offset;
1286                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1287                 } else {
1288                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1289                         data += delta;
1290                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1291                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1292                 }
1293                 matched = true;
1294         } else {
1295                 /*
1296                  * We split periods of matched TSC writes into generations.
1297                  * For each generation, we track the original measured
1298                  * nanosecond time, offset, and write, so if TSCs are in
1299                  * sync, we can match exact offset, and if not, we can match
1300                  * exact software computation in compute_guest_tsc()
1301                  *
1302                  * These values are tracked in kvm->arch.cur_xxx variables.
1303                  */
1304                 kvm->arch.cur_tsc_generation++;
1305                 kvm->arch.cur_tsc_nsec = ns;
1306                 kvm->arch.cur_tsc_write = data;
1307                 kvm->arch.cur_tsc_offset = offset;
1308                 matched = false;
1309                 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1310                          kvm->arch.cur_tsc_generation, data);
1311         }
1312
1313         /*
1314          * We also track th most recent recorded KHZ, write and time to
1315          * allow the matching interval to be extended at each write.
1316          */
1317         kvm->arch.last_tsc_nsec = ns;
1318         kvm->arch.last_tsc_write = data;
1319         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1320
1321         vcpu->arch.last_guest_tsc = data;
1322
1323         /* Keep track of which generation this VCPU has synchronized to */
1324         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1325         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1326         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1327
1328         if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1329                 update_ia32_tsc_adjust_msr(vcpu, offset);
1330         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1331         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1332
1333         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1334         if (matched)
1335                 kvm->arch.nr_vcpus_matched_tsc++;
1336         else
1337                 kvm->arch.nr_vcpus_matched_tsc = 0;
1338
1339         kvm_track_tsc_matching(vcpu);
1340         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1341 }
1342
1343 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1344
1345 #ifdef CONFIG_X86_64
1346
1347 static cycle_t read_tsc(void)
1348 {
1349         cycle_t ret;
1350         u64 last;
1351
1352         /*
1353          * Empirically, a fence (of type that depends on the CPU)
1354          * before rdtsc is enough to ensure that rdtsc is ordered
1355          * with respect to loads.  The various CPU manuals are unclear
1356          * as to whether rdtsc can be reordered with later loads,
1357          * but no one has ever seen it happen.
1358          */
1359         rdtsc_barrier();
1360         ret = (cycle_t)vget_cycles();
1361
1362         last = pvclock_gtod_data.clock.cycle_last;
1363
1364         if (likely(ret >= last))
1365                 return ret;
1366
1367         /*
1368          * GCC likes to generate cmov here, but this branch is extremely
1369          * predictable (it's just a funciton of time and the likely is
1370          * very likely) and there's a data dependence, so force GCC
1371          * to generate a branch instead.  I don't barrier() because
1372          * we don't actually need a barrier, and if this function
1373          * ever gets inlined it will generate worse code.
1374          */
1375         asm volatile ("");
1376         return last;
1377 }
1378
1379 static inline u64 vgettsc(cycle_t *cycle_now)
1380 {
1381         long v;
1382         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1383
1384         *cycle_now = read_tsc();
1385
1386         v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1387         return v * gtod->clock.mult;
1388 }
1389
1390 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1391 {
1392         unsigned long seq;
1393         u64 ns;
1394         int mode;
1395         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1396
1397         ts->tv_nsec = 0;
1398         do {
1399                 seq = read_seqcount_begin(&gtod->seq);
1400                 mode = gtod->clock.vclock_mode;
1401                 ts->tv_sec = gtod->monotonic_time_sec;
1402                 ns = gtod->monotonic_time_snsec;
1403                 ns += vgettsc(cycle_now);
1404                 ns >>= gtod->clock.shift;
1405         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1406         timespec_add_ns(ts, ns);
1407
1408         return mode;
1409 }
1410
1411 /* returns true if host is using tsc clocksource */
1412 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1413 {
1414         struct timespec ts;
1415
1416         /* checked again under seqlock below */
1417         if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1418                 return false;
1419
1420         if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1421                 return false;
1422
1423         monotonic_to_bootbased(&ts);
1424         *kernel_ns = timespec_to_ns(&ts);
1425
1426         return true;
1427 }
1428 #endif
1429
1430 /*
1431  *
1432  * Assuming a stable TSC across physical CPUS, and a stable TSC
1433  * across virtual CPUs, the following condition is possible.
1434  * Each numbered line represents an event visible to both
1435  * CPUs at the next numbered event.
1436  *
1437  * "timespecX" represents host monotonic time. "tscX" represents
1438  * RDTSC value.
1439  *
1440  *              VCPU0 on CPU0           |       VCPU1 on CPU1
1441  *
1442  * 1.  read timespec0,tsc0
1443  * 2.                                   | timespec1 = timespec0 + N
1444  *                                      | tsc1 = tsc0 + M
1445  * 3. transition to guest               | transition to guest
1446  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1447  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
1448  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1449  *
1450  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1451  *
1452  *      - ret0 < ret1
1453  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1454  *              ...
1455  *      - 0 < N - M => M < N
1456  *
1457  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1458  * always the case (the difference between two distinct xtime instances
1459  * might be smaller then the difference between corresponding TSC reads,
1460  * when updating guest vcpus pvclock areas).
1461  *
1462  * To avoid that problem, do not allow visibility of distinct
1463  * system_timestamp/tsc_timestamp values simultaneously: use a master
1464  * copy of host monotonic time values. Update that master copy
1465  * in lockstep.
1466  *
1467  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1468  *
1469  */
1470
1471 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1472 {
1473 #ifdef CONFIG_X86_64
1474         struct kvm_arch *ka = &kvm->arch;
1475         int vclock_mode;
1476         bool host_tsc_clocksource, vcpus_matched;
1477
1478         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1479                         atomic_read(&kvm->online_vcpus));
1480
1481         /*
1482          * If the host uses TSC clock, then passthrough TSC as stable
1483          * to the guest.
1484          */
1485         host_tsc_clocksource = kvm_get_time_and_clockread(
1486                                         &ka->master_kernel_ns,
1487                                         &ka->master_cycle_now);
1488
1489         ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1490
1491         if (ka->use_master_clock)
1492                 atomic_set(&kvm_guest_has_master_clock, 1);
1493
1494         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1495         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1496                                         vcpus_matched);
1497 #endif
1498 }
1499
1500 static void kvm_gen_update_masterclock(struct kvm *kvm)
1501 {
1502 #ifdef CONFIG_X86_64
1503         int i;
1504         struct kvm_vcpu *vcpu;
1505         struct kvm_arch *ka = &kvm->arch;
1506
1507         spin_lock(&ka->pvclock_gtod_sync_lock);
1508         kvm_make_mclock_inprogress_request(kvm);
1509         /* no guest entries from this point */
1510         pvclock_update_vm_gtod_copy(kvm);
1511
1512         kvm_for_each_vcpu(i, vcpu, kvm)
1513                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1514
1515         /* guest entries allowed */
1516         kvm_for_each_vcpu(i, vcpu, kvm)
1517                 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1518
1519         spin_unlock(&ka->pvclock_gtod_sync_lock);
1520 #endif
1521 }
1522
1523 static int kvm_guest_time_update(struct kvm_vcpu *v)
1524 {
1525         unsigned long flags, this_tsc_khz;
1526         struct kvm_vcpu_arch *vcpu = &v->arch;
1527         struct kvm_arch *ka = &v->kvm->arch;
1528         s64 kernel_ns;
1529         u64 tsc_timestamp, host_tsc;
1530         struct pvclock_vcpu_time_info guest_hv_clock;
1531         u8 pvclock_flags;
1532         bool use_master_clock;
1533
1534         kernel_ns = 0;
1535         host_tsc = 0;
1536
1537         /*
1538          * If the host uses TSC clock, then passthrough TSC as stable
1539          * to the guest.
1540          */
1541         spin_lock(&ka->pvclock_gtod_sync_lock);
1542         use_master_clock = ka->use_master_clock;
1543         if (use_master_clock) {
1544                 host_tsc = ka->master_cycle_now;
1545                 kernel_ns = ka->master_kernel_ns;
1546         }
1547         spin_unlock(&ka->pvclock_gtod_sync_lock);
1548
1549         /* Keep irq disabled to prevent changes to the clock */
1550         local_irq_save(flags);
1551         this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1552         if (unlikely(this_tsc_khz == 0)) {
1553                 local_irq_restore(flags);
1554                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1555                 return 1;
1556         }
1557         if (!use_master_clock) {
1558                 host_tsc = native_read_tsc();
1559                 kernel_ns = get_kernel_ns();
1560         }
1561
1562         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1563
1564         /*
1565          * We may have to catch up the TSC to match elapsed wall clock
1566          * time for two reasons, even if kvmclock is used.
1567          *   1) CPU could have been running below the maximum TSC rate
1568          *   2) Broken TSC compensation resets the base at each VCPU
1569          *      entry to avoid unknown leaps of TSC even when running
1570          *      again on the same CPU.  This may cause apparent elapsed
1571          *      time to disappear, and the guest to stand still or run
1572          *      very slowly.
1573          */
1574         if (vcpu->tsc_catchup) {
1575                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1576                 if (tsc > tsc_timestamp) {
1577                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1578                         tsc_timestamp = tsc;
1579                 }
1580         }
1581
1582         local_irq_restore(flags);
1583
1584         if (!vcpu->pv_time_enabled)
1585                 return 0;
1586
1587         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1588                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1589                                    &vcpu->hv_clock.tsc_shift,
1590                                    &vcpu->hv_clock.tsc_to_system_mul);
1591                 vcpu->hw_tsc_khz = this_tsc_khz;
1592         }
1593
1594         /* With all the info we got, fill in the values */
1595         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1596         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1597         vcpu->last_guest_tsc = tsc_timestamp;
1598
1599         /*
1600          * The interface expects us to write an even number signaling that the
1601          * update is finished. Since the guest won't see the intermediate
1602          * state, we just increase by 2 at the end.
1603          */
1604         vcpu->hv_clock.version += 2;
1605
1606         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1607                 &guest_hv_clock, sizeof(guest_hv_clock))))
1608                 return 0;
1609
1610         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1611         pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1612
1613         if (vcpu->pvclock_set_guest_stopped_request) {
1614                 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1615                 vcpu->pvclock_set_guest_stopped_request = false;
1616         }
1617
1618         /* If the host uses TSC clocksource, then it is stable */
1619         if (use_master_clock)
1620                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1621
1622         vcpu->hv_clock.flags = pvclock_flags;
1623
1624         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1625                                 &vcpu->hv_clock,
1626                                 sizeof(vcpu->hv_clock));
1627         return 0;
1628 }
1629
1630 /*
1631  * kvmclock updates which are isolated to a given vcpu, such as
1632  * vcpu->cpu migration, should not allow system_timestamp from
1633  * the rest of the vcpus to remain static. Otherwise ntp frequency
1634  * correction applies to one vcpu's system_timestamp but not
1635  * the others.
1636  *
1637  * So in those cases, request a kvmclock update for all vcpus.
1638  * We need to rate-limit these requests though, as they can
1639  * considerably slow guests that have a large number of vcpus.
1640  * The time for a remote vcpu to update its kvmclock is bound
1641  * by the delay we use to rate-limit the updates.
1642  */
1643
1644 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1645
1646 static void kvmclock_update_fn(struct work_struct *work)
1647 {
1648         int i;
1649         struct delayed_work *dwork = to_delayed_work(work);
1650         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1651                                            kvmclock_update_work);
1652         struct kvm *kvm = container_of(ka, struct kvm, arch);
1653         struct kvm_vcpu *vcpu;
1654
1655         kvm_for_each_vcpu(i, vcpu, kvm) {
1656                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1657                 kvm_vcpu_kick(vcpu);
1658         }
1659 }
1660
1661 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1662 {
1663         struct kvm *kvm = v->kvm;
1664
1665         set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1666         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1667                                         KVMCLOCK_UPDATE_DELAY);
1668 }
1669
1670 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1671
1672 static void kvmclock_sync_fn(struct work_struct *work)
1673 {
1674         struct delayed_work *dwork = to_delayed_work(work);
1675         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1676                                            kvmclock_sync_work);
1677         struct kvm *kvm = container_of(ka, struct kvm, arch);
1678
1679         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1680         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1681                                         KVMCLOCK_SYNC_PERIOD);
1682 }
1683
1684 static bool msr_mtrr_valid(unsigned msr)
1685 {
1686         switch (msr) {
1687         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1688         case MSR_MTRRfix64K_00000:
1689         case MSR_MTRRfix16K_80000:
1690         case MSR_MTRRfix16K_A0000:
1691         case MSR_MTRRfix4K_C0000:
1692         case MSR_MTRRfix4K_C8000:
1693         case MSR_MTRRfix4K_D0000:
1694         case MSR_MTRRfix4K_D8000:
1695         case MSR_MTRRfix4K_E0000:
1696         case MSR_MTRRfix4K_E8000:
1697         case MSR_MTRRfix4K_F0000:
1698         case MSR_MTRRfix4K_F8000:
1699         case MSR_MTRRdefType:
1700         case MSR_IA32_CR_PAT:
1701                 return true;
1702         case 0x2f8:
1703                 return true;
1704         }
1705         return false;
1706 }
1707
1708 static bool valid_pat_type(unsigned t)
1709 {
1710         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1711 }
1712
1713 static bool valid_mtrr_type(unsigned t)
1714 {
1715         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1716 }
1717
1718 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1719 {
1720         int i;
1721
1722         if (!msr_mtrr_valid(msr))
1723                 return false;
1724
1725         if (msr == MSR_IA32_CR_PAT) {
1726                 for (i = 0; i < 8; i++)
1727                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1728                                 return false;
1729                 return true;
1730         } else if (msr == MSR_MTRRdefType) {
1731                 if (data & ~0xcff)
1732                         return false;
1733                 return valid_mtrr_type(data & 0xff);
1734         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1735                 for (i = 0; i < 8 ; i++)
1736                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1737                                 return false;
1738                 return true;
1739         }
1740
1741         /* variable MTRRs */
1742         return valid_mtrr_type(data & 0xff);
1743 }
1744
1745 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1746 {
1747         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1748
1749         if (!mtrr_valid(vcpu, msr, data))
1750                 return 1;
1751
1752         if (msr == MSR_MTRRdefType) {
1753                 vcpu->arch.mtrr_state.def_type = data;
1754                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1755         } else if (msr == MSR_MTRRfix64K_00000)
1756                 p[0] = data;
1757         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1758                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1759         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1760                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1761         else if (msr == MSR_IA32_CR_PAT)
1762                 vcpu->arch.pat = data;
1763         else {  /* Variable MTRRs */
1764                 int idx, is_mtrr_mask;
1765                 u64 *pt;
1766
1767                 idx = (msr - 0x200) / 2;
1768                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1769                 if (!is_mtrr_mask)
1770                         pt =
1771                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1772                 else
1773                         pt =
1774                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1775                 *pt = data;
1776         }
1777
1778         kvm_mmu_reset_context(vcpu);
1779         return 0;
1780 }
1781
1782 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1783 {
1784         u64 mcg_cap = vcpu->arch.mcg_cap;
1785         unsigned bank_num = mcg_cap & 0xff;
1786
1787         switch (msr) {
1788         case MSR_IA32_MCG_STATUS:
1789                 vcpu->arch.mcg_status = data;
1790                 break;
1791         case MSR_IA32_MCG_CTL:
1792                 if (!(mcg_cap & MCG_CTL_P))
1793                         return 1;
1794                 if (data != 0 && data != ~(u64)0)
1795                         return -1;
1796                 vcpu->arch.mcg_ctl = data;
1797                 break;
1798         default:
1799                 if (msr >= MSR_IA32_MC0_CTL &&
1800                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1801                         u32 offset = msr - MSR_IA32_MC0_CTL;
1802                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1803                          * some Linux kernels though clear bit 10 in bank 4 to
1804                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1805                          * this to avoid an uncatched #GP in the guest
1806                          */
1807                         if ((offset & 0x3) == 0 &&
1808                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1809                                 return -1;
1810                         vcpu->arch.mce_banks[offset] = data;
1811                         break;
1812                 }
1813                 return 1;
1814         }
1815         return 0;
1816 }
1817
1818 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1819 {
1820         struct kvm *kvm = vcpu->kvm;
1821         int lm = is_long_mode(vcpu);
1822         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1823                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1824         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1825                 : kvm->arch.xen_hvm_config.blob_size_32;
1826         u32 page_num = data & ~PAGE_MASK;
1827         u64 page_addr = data & PAGE_MASK;
1828         u8 *page;
1829         int r;
1830
1831         r = -E2BIG;
1832         if (page_num >= blob_size)
1833                 goto out;
1834         r = -ENOMEM;
1835         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1836         if (IS_ERR(page)) {
1837                 r = PTR_ERR(page);
1838                 goto out;
1839         }
1840         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1841                 goto out_free;
1842         r = 0;
1843 out_free:
1844         kfree(page);
1845 out:
1846         return r;
1847 }
1848
1849 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1850 {
1851         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1852 }
1853
1854 static bool kvm_hv_msr_partition_wide(u32 msr)
1855 {
1856         bool r = false;
1857         switch (msr) {
1858         case HV_X64_MSR_GUEST_OS_ID:
1859         case HV_X64_MSR_HYPERCALL:
1860         case HV_X64_MSR_REFERENCE_TSC:
1861         case HV_X64_MSR_TIME_REF_COUNT:
1862                 r = true;
1863                 break;
1864         }
1865
1866         return r;
1867 }
1868
1869 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1870 {
1871         struct kvm *kvm = vcpu->kvm;
1872
1873         switch (msr) {
1874         case HV_X64_MSR_GUEST_OS_ID:
1875                 kvm->arch.hv_guest_os_id = data;
1876                 /* setting guest os id to zero disables hypercall page */
1877                 if (!kvm->arch.hv_guest_os_id)
1878                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1879                 break;
1880         case HV_X64_MSR_HYPERCALL: {
1881                 u64 gfn;
1882                 unsigned long addr;
1883                 u8 instructions[4];
1884
1885                 /* if guest os id is not set hypercall should remain disabled */
1886                 if (!kvm->arch.hv_guest_os_id)
1887                         break;
1888                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1889                         kvm->arch.hv_hypercall = data;
1890                         break;
1891                 }
1892                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1893                 addr = gfn_to_hva(kvm, gfn);
1894                 if (kvm_is_error_hva(addr))
1895                         return 1;
1896                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1897                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1898                 if (__copy_to_user((void __user *)addr, instructions, 4))
1899                         return 1;
1900                 kvm->arch.hv_hypercall = data;
1901                 mark_page_dirty(kvm, gfn);
1902                 break;
1903         }
1904         case HV_X64_MSR_REFERENCE_TSC: {
1905                 u64 gfn;
1906                 HV_REFERENCE_TSC_PAGE tsc_ref;
1907                 memset(&tsc_ref, 0, sizeof(tsc_ref));
1908                 kvm->arch.hv_tsc_page = data;
1909                 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1910                         break;
1911                 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1912                 if (kvm_write_guest(kvm, data,
1913                         &tsc_ref, sizeof(tsc_ref)))
1914                         return 1;
1915                 mark_page_dirty(kvm, gfn);
1916                 break;
1917         }
1918         default:
1919                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1920                             "data 0x%llx\n", msr, data);
1921                 return 1;
1922         }
1923         return 0;
1924 }
1925
1926 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1927 {
1928         switch (msr) {
1929         case HV_X64_MSR_APIC_ASSIST_PAGE: {
1930                 u64 gfn;
1931                 unsigned long addr;
1932
1933                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1934                         vcpu->arch.hv_vapic = data;
1935                         break;
1936                 }
1937                 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1938                 addr = gfn_to_hva(vcpu->kvm, gfn);
1939                 if (kvm_is_error_hva(addr))
1940                         return 1;
1941                 if (__clear_user((void __user *)addr, PAGE_SIZE))
1942                         return 1;
1943                 vcpu->arch.hv_vapic = data;
1944                 mark_page_dirty(vcpu->kvm, gfn);
1945                 break;
1946         }
1947         case HV_X64_MSR_EOI:
1948                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1949         case HV_X64_MSR_ICR:
1950                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1951         case HV_X64_MSR_TPR:
1952                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1953         default:
1954                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1955                             "data 0x%llx\n", msr, data);
1956                 return 1;
1957         }
1958
1959         return 0;
1960 }
1961
1962 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1963 {
1964         gpa_t gpa = data & ~0x3f;
1965
1966         /* Bits 2:5 are reserved, Should be zero */
1967         if (data & 0x3c)
1968                 return 1;
1969
1970         vcpu->arch.apf.msr_val = data;
1971
1972         if (!(data & KVM_ASYNC_PF_ENABLED)) {
1973                 kvm_clear_async_pf_completion_queue(vcpu);
1974                 kvm_async_pf_hash_reset(vcpu);
1975                 return 0;
1976         }
1977
1978         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1979                                         sizeof(u32)))
1980                 return 1;
1981
1982         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1983         kvm_async_pf_wakeup_all(vcpu);
1984         return 0;
1985 }
1986
1987 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1988 {
1989         vcpu->arch.pv_time_enabled = false;
1990 }
1991
1992 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1993 {
1994         u64 delta;
1995
1996         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1997                 return;
1998
1999         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2000         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2001         vcpu->arch.st.accum_steal = delta;
2002 }
2003
2004 static void record_steal_time(struct kvm_vcpu *vcpu)
2005 {
2006         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2007                 return;
2008
2009         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2010                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2011                 return;
2012
2013         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2014         vcpu->arch.st.steal.version += 2;
2015         vcpu->arch.st.accum_steal = 0;
2016
2017         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2018                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2019 }
2020
2021 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2022 {
2023         bool pr = false;
2024         u32 msr = msr_info->index;
2025         u64 data = msr_info->data;
2026
2027         switch (msr) {
2028         case MSR_AMD64_NB_CFG:
2029         case MSR_IA32_UCODE_REV:
2030         case MSR_IA32_UCODE_WRITE:
2031         case MSR_VM_HSAVE_PA:
2032         case MSR_AMD64_PATCH_LOADER:
2033         case MSR_AMD64_BU_CFG2:
2034                 break;
2035
2036         case MSR_EFER:
2037                 return set_efer(vcpu, data);
2038         case MSR_K7_HWCR:
2039                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2040                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2041                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2042                 if (data != 0) {
2043                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2044                                     data);
2045                         return 1;
2046                 }
2047                 break;
2048         case MSR_FAM10H_MMIO_CONF_BASE:
2049                 if (data != 0) {
2050                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2051                                     "0x%llx\n", data);
2052                         return 1;
2053                 }
2054                 break;
2055         case MSR_IA32_DEBUGCTLMSR:
2056                 if (!data) {
2057                         /* We support the non-activated case already */
2058                         break;
2059                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2060                         /* Values other than LBR and BTF are vendor-specific,
2061                            thus reserved and should throw a #GP */
2062                         return 1;
2063                 }
2064                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2065                             __func__, data);
2066                 break;
2067         case 0x200 ... 0x2ff:
2068                 return set_msr_mtrr(vcpu, msr, data);
2069         case MSR_IA32_APICBASE:
2070                 return kvm_set_apic_base(vcpu, msr_info);
2071         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2072                 return kvm_x2apic_msr_write(vcpu, msr, data);
2073         case MSR_IA32_TSCDEADLINE:
2074                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2075                 break;
2076         case MSR_IA32_TSC_ADJUST:
2077                 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2078                         if (!msr_info->host_initiated) {
2079                                 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2080                                 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2081                         }
2082                         vcpu->arch.ia32_tsc_adjust_msr = data;
2083                 }
2084                 break;
2085         case MSR_IA32_MISC_ENABLE:
2086                 vcpu->arch.ia32_misc_enable_msr = data;
2087                 break;
2088         case MSR_KVM_WALL_CLOCK_NEW:
2089         case MSR_KVM_WALL_CLOCK:
2090                 vcpu->kvm->arch.wall_clock = data;
2091                 kvm_write_wall_clock(vcpu->kvm, data);
2092                 break;
2093         case MSR_KVM_SYSTEM_TIME_NEW:
2094         case MSR_KVM_SYSTEM_TIME: {
2095                 u64 gpa_offset;
2096                 kvmclock_reset(vcpu);
2097
2098                 vcpu->arch.time = data;
2099                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2100
2101                 /* we verify if the enable bit is set... */
2102                 if (!(data & 1))
2103                         break;
2104
2105                 gpa_offset = data & ~(PAGE_MASK | 1);
2106
2107                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2108                      &vcpu->arch.pv_time, data & ~1ULL,
2109                      sizeof(struct pvclock_vcpu_time_info)))
2110                         vcpu->arch.pv_time_enabled = false;
2111                 else
2112                         vcpu->arch.pv_time_enabled = true;
2113
2114                 break;
2115         }
2116         case MSR_KVM_ASYNC_PF_EN:
2117                 if (kvm_pv_enable_async_pf(vcpu, data))
2118                         return 1;
2119                 break;
2120         case MSR_KVM_STEAL_TIME:
2121
2122                 if (unlikely(!sched_info_on()))
2123                         return 1;
2124
2125                 if (data & KVM_STEAL_RESERVED_MASK)
2126                         return 1;
2127
2128                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2129                                                 data & KVM_STEAL_VALID_BITS,
2130                                                 sizeof(struct kvm_steal_time)))
2131                         return 1;
2132
2133                 vcpu->arch.st.msr_val = data;
2134
2135                 if (!(data & KVM_MSR_ENABLED))
2136                         break;
2137
2138                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2139
2140                 preempt_disable();
2141                 accumulate_steal_time(vcpu);
2142                 preempt_enable();
2143
2144                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2145
2146                 break;
2147         case MSR_KVM_PV_EOI_EN:
2148                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2149                         return 1;
2150                 break;
2151
2152         case MSR_IA32_MCG_CTL:
2153         case MSR_IA32_MCG_STATUS:
2154         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2155                 return set_msr_mce(vcpu, msr, data);
2156
2157         /* Performance counters are not protected by a CPUID bit,
2158          * so we should check all of them in the generic path for the sake of
2159          * cross vendor migration.
2160          * Writing a zero into the event select MSRs disables them,
2161          * which we perfectly emulate ;-). Any other value should be at least
2162          * reported, some guests depend on them.
2163          */
2164         case MSR_K7_EVNTSEL0:
2165         case MSR_K7_EVNTSEL1:
2166         case MSR_K7_EVNTSEL2:
2167         case MSR_K7_EVNTSEL3:
2168                 if (data != 0)
2169                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2170                                     "0x%x data 0x%llx\n", msr, data);
2171                 break;
2172         /* at least RHEL 4 unconditionally writes to the perfctr registers,
2173          * so we ignore writes to make it happy.
2174          */
2175         case MSR_K7_PERFCTR0:
2176         case MSR_K7_PERFCTR1:
2177         case MSR_K7_PERFCTR2:
2178         case MSR_K7_PERFCTR3:
2179                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2180                             "0x%x data 0x%llx\n", msr, data);
2181                 break;
2182         case MSR_P6_PERFCTR0:
2183         case MSR_P6_PERFCTR1:
2184                 pr = true;
2185         case MSR_P6_EVNTSEL0:
2186         case MSR_P6_EVNTSEL1:
2187                 if (kvm_pmu_msr(vcpu, msr))
2188                         return kvm_pmu_set_msr(vcpu, msr_info);
2189
2190                 if (pr || data != 0)
2191                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2192                                     "0x%x data 0x%llx\n", msr, data);
2193                 break;
2194         case MSR_K7_CLK_CTL:
2195                 /*
2196                  * Ignore all writes to this no longer documented MSR.
2197                  * Writes are only relevant for old K7 processors,
2198                  * all pre-dating SVM, but a recommended workaround from
2199                  * AMD for these chips. It is possible to specify the
2200                  * affected processor models on the command line, hence
2201                  * the need to ignore the workaround.
2202                  */
2203                 break;
2204         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2205                 if (kvm_hv_msr_partition_wide(msr)) {
2206                         int r;
2207                         mutex_lock(&vcpu->kvm->lock);
2208                         r = set_msr_hyperv_pw(vcpu, msr, data);
2209                         mutex_unlock(&vcpu->kvm->lock);
2210                         return r;
2211                 } else
2212                         return set_msr_hyperv(vcpu, msr, data);
2213                 break;
2214         case MSR_IA32_BBL_CR_CTL3:
2215                 /* Drop writes to this legacy MSR -- see rdmsr
2216                  * counterpart for further detail.
2217                  */
2218                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2219                 break;
2220         case MSR_AMD64_OSVW_ID_LENGTH:
2221                 if (!guest_cpuid_has_osvw(vcpu))
2222                         return 1;
2223                 vcpu->arch.osvw.length = data;
2224                 break;
2225         case MSR_AMD64_OSVW_STATUS:
2226                 if (!guest_cpuid_has_osvw(vcpu))
2227                         return 1;
2228                 vcpu->arch.osvw.status = data;
2229                 break;
2230         default:
2231                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2232                         return xen_hvm_config(vcpu, data);
2233                 if (kvm_pmu_msr(vcpu, msr))
2234                         return kvm_pmu_set_msr(vcpu, msr_info);
2235                 if (!ignore_msrs) {
2236                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2237                                     msr, data);
2238                         return 1;
2239                 } else {
2240                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2241                                     msr, data);
2242                         break;
2243                 }
2244         }
2245         return 0;
2246 }
2247 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2248
2249
2250 /*
2251  * Reads an msr value (of 'msr_index') into 'pdata'.
2252  * Returns 0 on success, non-0 otherwise.
2253  * Assumes vcpu_load() was already called.
2254  */
2255 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2256 {
2257         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2258 }
2259
2260 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2261 {
2262         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2263
2264         if (!msr_mtrr_valid(msr))
2265                 return 1;
2266
2267         if (msr == MSR_MTRRdefType)
2268                 *pdata = vcpu->arch.mtrr_state.def_type +
2269                          (vcpu->arch.mtrr_state.enabled << 10);
2270         else if (msr == MSR_MTRRfix64K_00000)
2271                 *pdata = p[0];
2272         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2273                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2274         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2275                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2276         else if (msr == MSR_IA32_CR_PAT)
2277                 *pdata = vcpu->arch.pat;
2278         else {  /* Variable MTRRs */
2279                 int idx, is_mtrr_mask;
2280                 u64 *pt;
2281
2282                 idx = (msr - 0x200) / 2;
2283                 is_mtrr_mask = msr - 0x200 - 2 * idx;
2284                 if (!is_mtrr_mask)
2285                         pt =
2286                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2287                 else
2288                         pt =
2289                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2290                 *pdata = *pt;
2291         }
2292
2293         return 0;
2294 }
2295
2296 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2297 {
2298         u64 data;
2299         u64 mcg_cap = vcpu->arch.mcg_cap;
2300         unsigned bank_num = mcg_cap & 0xff;
2301
2302         switch (msr) {
2303         case MSR_IA32_P5_MC_ADDR:
2304         case MSR_IA32_P5_MC_TYPE:
2305                 data = 0;
2306                 break;
2307         case MSR_IA32_MCG_CAP:
2308                 data = vcpu->arch.mcg_cap;
2309                 break;
2310         case MSR_IA32_MCG_CTL:
2311                 if (!(mcg_cap & MCG_CTL_P))
2312                         return 1;
2313                 data = vcpu->arch.mcg_ctl;
2314                 break;
2315         case MSR_IA32_MCG_STATUS:
2316                 data = vcpu->arch.mcg_status;
2317                 break;
2318         default:
2319                 if (msr >= MSR_IA32_MC0_CTL &&
2320                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2321                         u32 offset = msr - MSR_IA32_MC0_CTL;
2322                         data = vcpu->arch.mce_banks[offset];
2323                         break;
2324                 }
2325                 return 1;
2326         }
2327         *pdata = data;
2328         return 0;
2329 }
2330
2331 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2332 {
2333         u64 data = 0;
2334         struct kvm *kvm = vcpu->kvm;
2335
2336         switch (msr) {
2337         case HV_X64_MSR_GUEST_OS_ID:
2338                 data = kvm->arch.hv_guest_os_id;
2339                 break;
2340         case HV_X64_MSR_HYPERCALL:
2341                 data = kvm->arch.hv_hypercall;
2342                 break;
2343         case HV_X64_MSR_TIME_REF_COUNT: {
2344                 data =
2345                      div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2346                 break;
2347         }
2348         case HV_X64_MSR_REFERENCE_TSC:
2349                 data = kvm->arch.hv_tsc_page;
2350                 break;
2351         default:
2352                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2353                 return 1;
2354         }
2355
2356         *pdata = data;
2357         return 0;
2358 }
2359
2360 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2361 {
2362         u64 data = 0;
2363
2364         switch (msr) {
2365         case HV_X64_MSR_VP_INDEX: {
2366                 int r;
2367                 struct kvm_vcpu *v;
2368                 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2369                         if (v == vcpu) {
2370                                 data = r;
2371                                 break;
2372                         }
2373                 }
2374                 break;
2375         }
2376         case HV_X64_MSR_EOI:
2377                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2378         case HV_X64_MSR_ICR:
2379                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2380         case HV_X64_MSR_TPR:
2381                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2382         case HV_X64_MSR_APIC_ASSIST_PAGE:
2383                 data = vcpu->arch.hv_vapic;
2384                 break;
2385         default:
2386                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2387                 return 1;
2388         }
2389         *pdata = data;
2390         return 0;
2391 }
2392
2393 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2394 {
2395         u64 data;
2396
2397         switch (msr) {
2398         case MSR_IA32_PLATFORM_ID:
2399         case MSR_IA32_EBL_CR_POWERON:
2400         case MSR_IA32_DEBUGCTLMSR:
2401         case MSR_IA32_LASTBRANCHFROMIP:
2402         case MSR_IA32_LASTBRANCHTOIP:
2403         case MSR_IA32_LASTINTFROMIP:
2404         case MSR_IA32_LASTINTTOIP:
2405         case MSR_K8_SYSCFG:
2406         case MSR_K7_HWCR:
2407         case MSR_VM_HSAVE_PA:
2408         case MSR_K7_EVNTSEL0:
2409         case MSR_K7_PERFCTR0:
2410         case MSR_K8_INT_PENDING_MSG:
2411         case MSR_AMD64_NB_CFG:
2412         case MSR_FAM10H_MMIO_CONF_BASE:
2413         case MSR_AMD64_BU_CFG2:
2414                 data = 0;
2415                 break;
2416         case MSR_P6_PERFCTR0:
2417         case MSR_P6_PERFCTR1:
2418         case MSR_P6_EVNTSEL0:
2419         case MSR_P6_EVNTSEL1:
2420                 if (kvm_pmu_msr(vcpu, msr))
2421                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2422                 data = 0;
2423                 break;
2424         case MSR_IA32_UCODE_REV:
2425                 data = 0x100000000ULL;
2426                 break;
2427         case MSR_MTRRcap:
2428                 data = 0x500 | KVM_NR_VAR_MTRR;
2429                 break;
2430         case 0x200 ... 0x2ff:
2431                 return get_msr_mtrr(vcpu, msr, pdata);
2432         case 0xcd: /* fsb frequency */
2433                 data = 3;
2434                 break;
2435                 /*
2436                  * MSR_EBC_FREQUENCY_ID
2437                  * Conservative value valid for even the basic CPU models.
2438                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2439                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2440                  * and 266MHz for model 3, or 4. Set Core Clock
2441                  * Frequency to System Bus Frequency Ratio to 1 (bits
2442                  * 31:24) even though these are only valid for CPU
2443                  * models > 2, however guests may end up dividing or
2444                  * multiplying by zero otherwise.
2445                  */
2446         case MSR_EBC_FREQUENCY_ID:
2447                 data = 1 << 24;
2448                 break;
2449         case MSR_IA32_APICBASE:
2450                 data = kvm_get_apic_base(vcpu);
2451                 break;
2452         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2453                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2454                 break;
2455         case MSR_IA32_TSCDEADLINE:
2456                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2457                 break;
2458         case MSR_IA32_TSC_ADJUST:
2459                 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2460                 break;
2461         case MSR_IA32_MISC_ENABLE:
2462                 data = vcpu->arch.ia32_misc_enable_msr;
2463                 break;
2464         case MSR_IA32_PERF_STATUS:
2465                 /* TSC increment by tick */
2466                 data = 1000ULL;
2467                 /* CPU multiplier */
2468                 data |= (((uint64_t)4ULL) << 40);
2469                 break;
2470         case MSR_EFER:
2471                 data = vcpu->arch.efer;
2472                 break;
2473         case MSR_KVM_WALL_CLOCK:
2474         case MSR_KVM_WALL_CLOCK_NEW:
2475                 data = vcpu->kvm->arch.wall_clock;
2476                 break;
2477         case MSR_KVM_SYSTEM_TIME:
2478         case MSR_KVM_SYSTEM_TIME_NEW:
2479                 data = vcpu->arch.time;
2480                 break;
2481         case MSR_KVM_ASYNC_PF_EN:
2482                 data = vcpu->arch.apf.msr_val;
2483                 break;
2484         case MSR_KVM_STEAL_TIME:
2485                 data = vcpu->arch.st.msr_val;
2486                 break;
2487         case MSR_KVM_PV_EOI_EN:
2488                 data = vcpu->arch.pv_eoi.msr_val;
2489                 break;
2490         case MSR_IA32_P5_MC_ADDR:
2491         case MSR_IA32_P5_MC_TYPE:
2492         case MSR_IA32_MCG_CAP:
2493         case MSR_IA32_MCG_CTL:
2494         case MSR_IA32_MCG_STATUS:
2495         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2496                 return get_msr_mce(vcpu, msr, pdata);
2497         case MSR_K7_CLK_CTL:
2498                 /*
2499                  * Provide expected ramp-up count for K7. All other
2500                  * are set to zero, indicating minimum divisors for
2501                  * every field.
2502                  *
2503                  * This prevents guest kernels on AMD host with CPU
2504                  * type 6, model 8 and higher from exploding due to
2505                  * the rdmsr failing.
2506                  */
2507                 data = 0x20000000;
2508                 break;
2509         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2510                 if (kvm_hv_msr_partition_wide(msr)) {
2511                         int r;
2512                         mutex_lock(&vcpu->kvm->lock);
2513                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2514                         mutex_unlock(&vcpu->kvm->lock);
2515                         return r;
2516                 } else
2517                         return get_msr_hyperv(vcpu, msr, pdata);
2518                 break;
2519         case MSR_IA32_BBL_CR_CTL3:
2520                 /* This legacy MSR exists but isn't fully documented in current
2521                  * silicon.  It is however accessed by winxp in very narrow
2522                  * scenarios where it sets bit #19, itself documented as
2523                  * a "reserved" bit.  Best effort attempt to source coherent
2524                  * read data here should the balance of the register be
2525                  * interpreted by the guest:
2526                  *
2527                  * L2 cache control register 3: 64GB range, 256KB size,
2528                  * enabled, latency 0x1, configured
2529                  */
2530                 data = 0xbe702111;
2531                 break;
2532         case MSR_AMD64_OSVW_ID_LENGTH:
2533                 if (!guest_cpuid_has_osvw(vcpu))
2534                         return 1;
2535                 data = vcpu->arch.osvw.length;
2536                 break;
2537         case MSR_AMD64_OSVW_STATUS:
2538                 if (!guest_cpuid_has_osvw(vcpu))
2539                         return 1;
2540                 data = vcpu->arch.osvw.status;
2541                 break;
2542         default:
2543                 if (kvm_pmu_msr(vcpu, msr))
2544                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2545                 if (!ignore_msrs) {
2546                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2547                         return 1;
2548                 } else {
2549                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2550                         data = 0;
2551                 }
2552                 break;
2553         }
2554         *pdata = data;
2555         return 0;
2556 }
2557 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2558
2559 /*
2560  * Read or write a bunch of msrs. All parameters are kernel addresses.
2561  *
2562  * @return number of msrs set successfully.
2563  */
2564 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2565                     struct kvm_msr_entry *entries,
2566                     int (*do_msr)(struct kvm_vcpu *vcpu,
2567                                   unsigned index, u64 *data))
2568 {
2569         int i, idx;
2570
2571         idx = srcu_read_lock(&vcpu->kvm->srcu);
2572         for (i = 0; i < msrs->nmsrs; ++i)
2573                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2574                         break;
2575         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2576
2577         return i;
2578 }
2579
2580 /*
2581  * Read or write a bunch of msrs. Parameters are user addresses.
2582  *
2583  * @return number of msrs set successfully.
2584  */
2585 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2586                   int (*do_msr)(struct kvm_vcpu *vcpu,
2587                                 unsigned index, u64 *data),
2588                   int writeback)
2589 {
2590         struct kvm_msrs msrs;
2591         struct kvm_msr_entry *entries;
2592         int r, n;
2593         unsigned size;
2594
2595         r = -EFAULT;
2596         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2597                 goto out;
2598
2599         r = -E2BIG;
2600         if (msrs.nmsrs >= MAX_IO_MSRS)
2601                 goto out;
2602
2603         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2604         entries = memdup_user(user_msrs->entries, size);
2605         if (IS_ERR(entries)) {
2606                 r = PTR_ERR(entries);
2607                 goto out;
2608         }
2609
2610         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2611         if (r < 0)
2612                 goto out_free;
2613
2614         r = -EFAULT;
2615         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2616                 goto out_free;
2617
2618         r = n;
2619
2620 out_free:
2621         kfree(entries);
2622 out:
2623         return r;
2624 }
2625
2626 int kvm_dev_ioctl_check_extension(long ext)
2627 {
2628         int r;
2629
2630         switch (ext) {
2631         case KVM_CAP_IRQCHIP:
2632         case KVM_CAP_HLT:
2633         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2634         case KVM_CAP_SET_TSS_ADDR:
2635         case KVM_CAP_EXT_CPUID:
2636         case KVM_CAP_EXT_EMUL_CPUID:
2637         case KVM_CAP_CLOCKSOURCE:
2638         case KVM_CAP_PIT:
2639         case KVM_CAP_NOP_IO_DELAY:
2640         case KVM_CAP_MP_STATE:
2641         case KVM_CAP_SYNC_MMU:
2642         case KVM_CAP_USER_NMI:
2643         case KVM_CAP_REINJECT_CONTROL:
2644         case KVM_CAP_IRQ_INJECT_STATUS:
2645         case KVM_CAP_IRQFD:
2646         case KVM_CAP_IOEVENTFD:
2647         case KVM_CAP_PIT2:
2648         case KVM_CAP_PIT_STATE2:
2649         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2650         case KVM_CAP_XEN_HVM:
2651         case KVM_CAP_ADJUST_CLOCK:
2652         case KVM_CAP_VCPU_EVENTS:
2653         case KVM_CAP_HYPERV:
2654         case KVM_CAP_HYPERV_VAPIC:
2655         case KVM_CAP_HYPERV_SPIN:
2656         case KVM_CAP_PCI_SEGMENT:
2657         case KVM_CAP_DEBUGREGS:
2658         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2659         case KVM_CAP_XSAVE:
2660         case KVM_CAP_ASYNC_PF:
2661         case KVM_CAP_GET_TSC_KHZ:
2662         case KVM_CAP_KVMCLOCK_CTRL:
2663         case KVM_CAP_READONLY_MEM:
2664         case KVM_CAP_HYPERV_TIME:
2665         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2666 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2667         case KVM_CAP_ASSIGN_DEV_IRQ:
2668         case KVM_CAP_PCI_2_3:
2669 #endif
2670                 r = 1;
2671                 break;
2672         case KVM_CAP_COALESCED_MMIO:
2673                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2674                 break;
2675         case KVM_CAP_VAPIC:
2676                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2677                 break;
2678         case KVM_CAP_NR_VCPUS:
2679                 r = KVM_SOFT_MAX_VCPUS;
2680                 break;
2681         case KVM_CAP_MAX_VCPUS:
2682                 r = KVM_MAX_VCPUS;
2683                 break;
2684         case KVM_CAP_NR_MEMSLOTS:
2685                 r = KVM_USER_MEM_SLOTS;
2686                 break;
2687         case KVM_CAP_PV_MMU:    /* obsolete */
2688                 r = 0;
2689                 break;
2690 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2691         case KVM_CAP_IOMMU:
2692                 r = iommu_present(&pci_bus_type);
2693                 break;
2694 #endif
2695         case KVM_CAP_MCE:
2696                 r = KVM_MAX_MCE_BANKS;
2697                 break;
2698         case KVM_CAP_XCRS:
2699                 r = cpu_has_xsave;
2700                 break;
2701         case KVM_CAP_TSC_CONTROL:
2702                 r = kvm_has_tsc_control;
2703                 break;
2704         case KVM_CAP_TSC_DEADLINE_TIMER:
2705                 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2706                 break;
2707         default:
2708                 r = 0;
2709                 break;
2710         }
2711         return r;
2712
2713 }
2714
2715 long kvm_arch_dev_ioctl(struct file *filp,
2716                         unsigned int ioctl, unsigned long arg)
2717 {
2718         void __user *argp = (void __user *)arg;
2719         long r;
2720
2721         switch (ioctl) {
2722         case KVM_GET_MSR_INDEX_LIST: {
2723                 struct kvm_msr_list __user *user_msr_list = argp;
2724                 struct kvm_msr_list msr_list;
2725                 unsigned n;
2726
2727                 r = -EFAULT;
2728                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2729                         goto out;
2730                 n = msr_list.nmsrs;
2731                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2732                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2733                         goto out;
2734                 r = -E2BIG;
2735                 if (n < msr_list.nmsrs)
2736                         goto out;
2737                 r = -EFAULT;
2738                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2739                                  num_msrs_to_save * sizeof(u32)))
2740                         goto out;
2741                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2742                                  &emulated_msrs,
2743                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2744                         goto out;
2745                 r = 0;
2746                 break;
2747         }
2748         case KVM_GET_SUPPORTED_CPUID:
2749         case KVM_GET_EMULATED_CPUID: {
2750                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2751                 struct kvm_cpuid2 cpuid;
2752
2753                 r = -EFAULT;
2754                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2755                         goto out;
2756
2757                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2758                                             ioctl);
2759                 if (r)
2760                         goto out;
2761
2762                 r = -EFAULT;
2763                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2764                         goto out;
2765                 r = 0;
2766                 break;
2767         }
2768         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2769                 u64 mce_cap;
2770
2771                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2772                 r = -EFAULT;
2773                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2774                         goto out;
2775                 r = 0;
2776                 break;
2777         }
2778         default:
2779                 r = -EINVAL;
2780         }
2781 out:
2782         return r;
2783 }
2784
2785 static void wbinvd_ipi(void *garbage)
2786 {
2787         wbinvd();
2788 }
2789
2790 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2791 {
2792         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2793 }
2794
2795 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2796 {
2797         /* Address WBINVD may be executed by guest */
2798         if (need_emulate_wbinvd(vcpu)) {
2799                 if (kvm_x86_ops->has_wbinvd_exit())
2800                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2801                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2802                         smp_call_function_single(vcpu->cpu,
2803                                         wbinvd_ipi, NULL, 1);
2804         }
2805
2806         kvm_x86_ops->vcpu_load(vcpu, cpu);
2807
2808         /* Apply any externally detected TSC adjustments (due to suspend) */
2809         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2810                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2811                 vcpu->arch.tsc_offset_adjustment = 0;
2812                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2813         }
2814
2815         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2816                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2817                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2818                 if (tsc_delta < 0)
2819                         mark_tsc_unstable("KVM discovered backwards TSC");
2820                 if (check_tsc_unstable()) {
2821                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2822                                                 vcpu->arch.last_guest_tsc);
2823                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2824                         vcpu->arch.tsc_catchup = 1;
2825                 }
2826                 /*
2827                  * On a host with synchronized TSC, there is no need to update
2828                  * kvmclock on vcpu->cpu migration
2829                  */
2830                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2831                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2832                 if (vcpu->cpu != cpu)
2833                         kvm_migrate_timers(vcpu);
2834                 vcpu->cpu = cpu;
2835         }
2836
2837         accumulate_steal_time(vcpu);
2838         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2839 }
2840
2841 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2842 {
2843         kvm_x86_ops->vcpu_put(vcpu);
2844         kvm_put_guest_fpu(vcpu);
2845         vcpu->arch.last_host_tsc = native_read_tsc();
2846 }
2847
2848 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2849                                     struct kvm_lapic_state *s)
2850 {
2851         kvm_x86_ops->sync_pir_to_irr(vcpu);
2852         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2853
2854         return 0;
2855 }
2856
2857 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2858                                     struct kvm_lapic_state *s)
2859 {
2860         kvm_apic_post_state_restore(vcpu, s);
2861         update_cr8_intercept(vcpu);
2862
2863         return 0;
2864 }
2865
2866 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2867                                     struct kvm_interrupt *irq)
2868 {
2869         if (irq->irq >= KVM_NR_INTERRUPTS)
2870                 return -EINVAL;
2871         if (irqchip_in_kernel(vcpu->kvm))
2872                 return -ENXIO;
2873
2874         kvm_queue_interrupt(vcpu, irq->irq, false);
2875         kvm_make_request(KVM_REQ_EVENT, vcpu);
2876
2877         return 0;
2878 }
2879
2880 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2881 {
2882         kvm_inject_nmi(vcpu);
2883
2884         return 0;
2885 }
2886
2887 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2888                                            struct kvm_tpr_access_ctl *tac)
2889 {
2890         if (tac->flags)
2891                 return -EINVAL;
2892         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2893         return 0;
2894 }
2895
2896 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2897                                         u64 mcg_cap)
2898 {
2899         int r;
2900         unsigned bank_num = mcg_cap & 0xff, bank;
2901
2902         r = -EINVAL;
2903         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2904                 goto out;
2905         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2906                 goto out;
2907         r = 0;
2908         vcpu->arch.mcg_cap = mcg_cap;
2909         /* Init IA32_MCG_CTL to all 1s */
2910         if (mcg_cap & MCG_CTL_P)
2911                 vcpu->arch.mcg_ctl = ~(u64)0;
2912         /* Init IA32_MCi_CTL to all 1s */
2913         for (bank = 0; bank < bank_num; bank++)
2914                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2915 out:
2916         return r;
2917 }
2918
2919 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2920                                       struct kvm_x86_mce *mce)
2921 {
2922         u64 mcg_cap = vcpu->arch.mcg_cap;
2923         unsigned bank_num = mcg_cap & 0xff;
2924         u64 *banks = vcpu->arch.mce_banks;
2925
2926         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2927                 return -EINVAL;
2928         /*
2929          * if IA32_MCG_CTL is not all 1s, the uncorrected error
2930          * reporting is disabled
2931          */
2932         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2933             vcpu->arch.mcg_ctl != ~(u64)0)
2934                 return 0;
2935         banks += 4 * mce->bank;
2936         /*
2937          * if IA32_MCi_CTL is not all 1s, the uncorrected error
2938          * reporting is disabled for the bank
2939          */
2940         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2941                 return 0;
2942         if (mce->status & MCI_STATUS_UC) {
2943                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2944                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2945                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2946                         return 0;
2947                 }
2948                 if (banks[1] & MCI_STATUS_VAL)
2949                         mce->status |= MCI_STATUS_OVER;
2950                 banks[2] = mce->addr;
2951                 banks[3] = mce->misc;
2952                 vcpu->arch.mcg_status = mce->mcg_status;
2953                 banks[1] = mce->status;
2954                 kvm_queue_exception(vcpu, MC_VECTOR);
2955         } else if (!(banks[1] & MCI_STATUS_VAL)
2956                    || !(banks[1] & MCI_STATUS_UC)) {
2957                 if (banks[1] & MCI_STATUS_VAL)
2958                         mce->status |= MCI_STATUS_OVER;
2959                 banks[2] = mce->addr;
2960                 banks[3] = mce->misc;
2961                 banks[1] = mce->status;
2962         } else
2963                 banks[1] |= MCI_STATUS_OVER;
2964         return 0;
2965 }
2966
2967 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2968                                                struct kvm_vcpu_events *events)
2969 {
2970         process_nmi(vcpu);
2971         events->exception.injected =
2972                 vcpu->arch.exception.pending &&
2973                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2974         events->exception.nr = vcpu->arch.exception.nr;
2975         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2976         events->exception.pad = 0;
2977         events->exception.error_code = vcpu->arch.exception.error_code;
2978
2979         events->interrupt.injected =
2980                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2981         events->interrupt.nr = vcpu->arch.interrupt.nr;
2982         events->interrupt.soft = 0;
2983         events->interrupt.shadow =
2984                 kvm_x86_ops->get_interrupt_shadow(vcpu,
2985                         KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2986
2987         events->nmi.injected = vcpu->arch.nmi_injected;
2988         events->nmi.pending = vcpu->arch.nmi_pending != 0;
2989         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2990         events->nmi.pad = 0;
2991
2992         events->sipi_vector = 0; /* never valid when reporting to user space */
2993
2994         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2995                          | KVM_VCPUEVENT_VALID_SHADOW);
2996         memset(&events->reserved, 0, sizeof(events->reserved));
2997 }
2998
2999 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3000                                               struct kvm_vcpu_events *events)
3001 {
3002         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3003                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3004                               | KVM_VCPUEVENT_VALID_SHADOW))
3005                 return -EINVAL;
3006
3007         process_nmi(vcpu);
3008         vcpu->arch.exception.pending = events->exception.injected;
3009         vcpu->arch.exception.nr = events->exception.nr;
3010         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3011         vcpu->arch.exception.error_code = events->exception.error_code;
3012
3013         vcpu->arch.interrupt.pending = events->interrupt.injected;
3014         vcpu->arch.interrupt.nr = events->interrupt.nr;
3015         vcpu->arch.interrupt.soft = events->interrupt.soft;
3016         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3017                 kvm_x86_ops->set_interrupt_shadow(vcpu,
3018                                                   events->interrupt.shadow);
3019
3020         vcpu->arch.nmi_injected = events->nmi.injected;
3021         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3022                 vcpu->arch.nmi_pending = events->nmi.pending;
3023         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3024
3025         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3026             kvm_vcpu_has_lapic(vcpu))
3027                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3028
3029         kvm_make_request(KVM_REQ_EVENT, vcpu);
3030
3031         return 0;
3032 }
3033
3034 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3035                                              struct kvm_debugregs *dbgregs)
3036 {
3037         unsigned long val;
3038
3039         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3040         _kvm_get_dr(vcpu, 6, &val);
3041         dbgregs->dr6 = val;
3042         dbgregs->dr7 = vcpu->arch.dr7;
3043         dbgregs->flags = 0;
3044         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3045 }
3046
3047 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3048                                             struct kvm_debugregs *dbgregs)
3049 {
3050         if (dbgregs->flags)
3051                 return -EINVAL;
3052
3053         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3054         vcpu->arch.dr6 = dbgregs->dr6;
3055         kvm_update_dr6(vcpu);
3056         vcpu->arch.dr7 = dbgregs->dr7;
3057         kvm_update_dr7(vcpu);
3058
3059         return 0;
3060 }
3061
3062 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3063                                          struct kvm_xsave *guest_xsave)
3064 {
3065         if (cpu_has_xsave) {
3066                 memcpy(guest_xsave->region,
3067                         &vcpu->arch.guest_fpu.state->xsave,
3068                         vcpu->arch.guest_xstate_size);
3069                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3070                         vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3071         } else {
3072                 memcpy(guest_xsave->region,
3073                         &vcpu->arch.guest_fpu.state->fxsave,
3074                         sizeof(struct i387_fxsave_struct));
3075                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3076                         XSTATE_FPSSE;
3077         }
3078 }
3079
3080 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3081                                         struct kvm_xsave *guest_xsave)
3082 {
3083         u64 xstate_bv =
3084                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3085
3086         if (cpu_has_xsave) {
3087                 /*
3088                  * Here we allow setting states that are not present in
3089                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3090                  * with old userspace.
3091                  */
3092                 if (xstate_bv & ~kvm_supported_xcr0())
3093                         return -EINVAL;
3094                 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3095                         guest_xsave->region, vcpu->arch.guest_xstate_size);
3096         } else {
3097                 if (xstate_bv & ~XSTATE_FPSSE)
3098                         return -EINVAL;
3099                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3100                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
3101         }
3102         return 0;
3103 }
3104
3105 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3106                                         struct kvm_xcrs *guest_xcrs)
3107 {
3108         if (!cpu_has_xsave) {
3109                 guest_xcrs->nr_xcrs = 0;
3110                 return;
3111         }
3112
3113         guest_xcrs->nr_xcrs = 1;
3114         guest_xcrs->flags = 0;
3115         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3116         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3117 }
3118
3119 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3120                                        struct kvm_xcrs *guest_xcrs)
3121 {
3122         int i, r = 0;
3123
3124         if (!cpu_has_xsave)
3125                 return -EINVAL;
3126
3127         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3128                 return -EINVAL;
3129
3130         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3131                 /* Only support XCR0 currently */
3132                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3133                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3134                                 guest_xcrs->xcrs[i].value);
3135                         break;
3136                 }
3137         if (r)
3138                 r = -EINVAL;
3139         return r;
3140 }
3141
3142 /*
3143  * kvm_set_guest_paused() indicates to the guest kernel that it has been
3144  * stopped by the hypervisor.  This function will be called from the host only.
3145  * EINVAL is returned when the host attempts to set the flag for a guest that
3146  * does not support pv clocks.
3147  */
3148 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3149 {
3150         if (!vcpu->arch.pv_time_enabled)
3151                 return -EINVAL;
3152         vcpu->arch.pvclock_set_guest_stopped_request = true;
3153         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3154         return 0;
3155 }
3156
3157 long kvm_arch_vcpu_ioctl(struct file *filp,
3158                          unsigned int ioctl, unsigned long arg)
3159 {
3160         struct kvm_vcpu *vcpu = filp->private_data;
3161         void __user *argp = (void __user *)arg;
3162         int r;
3163         union {
3164                 struct kvm_lapic_state *lapic;
3165                 struct kvm_xsave *xsave;
3166                 struct kvm_xcrs *xcrs;
3167                 void *buffer;
3168         } u;
3169
3170         u.buffer = NULL;
3171         switch (ioctl) {
3172         case KVM_GET_LAPIC: {
3173                 r = -EINVAL;
3174                 if (!vcpu->arch.apic)
3175                         goto out;
3176                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3177
3178                 r = -ENOMEM;
3179                 if (!u.lapic)
3180                         goto out;
3181                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3182                 if (r)
3183                         goto out;
3184                 r = -EFAULT;
3185                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3186                         goto out;
3187                 r = 0;
3188                 break;
3189         }
3190         case KVM_SET_LAPIC: {
3191                 r = -EINVAL;
3192                 if (!vcpu->arch.apic)
3193                         goto out;
3194                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3195                 if (IS_ERR(u.lapic))
3196                         return PTR_ERR(u.lapic);
3197
3198                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3199                 break;
3200         }
3201         case KVM_INTERRUPT: {
3202                 struct kvm_interrupt irq;
3203
3204                 r = -EFAULT;
3205                 if (copy_from_user(&irq, argp, sizeof irq))
3206                         goto out;
3207                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3208                 break;
3209         }
3210         case KVM_NMI: {
3211                 r = kvm_vcpu_ioctl_nmi(vcpu);
3212                 break;
3213         }
3214         case KVM_SET_CPUID: {
3215                 struct kvm_cpuid __user *cpuid_arg = argp;
3216                 struct kvm_cpuid cpuid;
3217
3218                 r = -EFAULT;
3219                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3220                         goto out;
3221                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3222                 break;
3223         }
3224         case KVM_SET_CPUID2: {
3225                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3226                 struct kvm_cpuid2 cpuid;
3227
3228                 r = -EFAULT;
3229                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3230                         goto out;
3231                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3232                                               cpuid_arg->entries);
3233                 break;
3234         }
3235         case KVM_GET_CPUID2: {
3236                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3237                 struct kvm_cpuid2 cpuid;
3238
3239                 r = -EFAULT;
3240                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3241                         goto out;
3242                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3243                                               cpuid_arg->entries);
3244                 if (r)
3245                         goto out;
3246                 r = -EFAULT;
3247                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3248                         goto out;
3249                 r = 0;
3250                 break;
3251         }
3252         case KVM_GET_MSRS:
3253                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3254                 break;
3255         case KVM_SET_MSRS:
3256                 r = msr_io(vcpu, argp, do_set_msr, 0);
3257                 break;
3258         case KVM_TPR_ACCESS_REPORTING: {
3259                 struct kvm_tpr_access_ctl tac;
3260
3261                 r = -EFAULT;
3262                 if (copy_from_user(&tac, argp, sizeof tac))
3263                         goto out;
3264                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3265                 if (r)
3266                         goto out;
3267                 r = -EFAULT;
3268                 if (copy_to_user(argp, &tac, sizeof tac))
3269                         goto out;
3270                 r = 0;
3271                 break;
3272         };
3273         case KVM_SET_VAPIC_ADDR: {
3274                 struct kvm_vapic_addr va;
3275
3276                 r = -EINVAL;
3277                 if (!irqchip_in_kernel(vcpu->kvm))
3278                         goto out;
3279                 r = -EFAULT;
3280                 if (copy_from_user(&va, argp, sizeof va))
3281                         goto out;
3282                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3283                 break;
3284         }
3285         case KVM_X86_SETUP_MCE: {
3286                 u64 mcg_cap;
3287
3288                 r = -EFAULT;
3289                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3290                         goto out;
3291                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3292                 break;
3293         }
3294         case KVM_X86_SET_MCE: {
3295                 struct kvm_x86_mce mce;
3296
3297                 r = -EFAULT;
3298                 if (copy_from_user(&mce, argp, sizeof mce))
3299                         goto out;
3300                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3301                 break;
3302         }
3303         case KVM_GET_VCPU_EVENTS: {
3304                 struct kvm_vcpu_events events;
3305
3306                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3307
3308                 r = -EFAULT;
3309                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3310                         break;
3311                 r = 0;
3312                 break;
3313         }
3314         case KVM_SET_VCPU_EVENTS: {
3315                 struct kvm_vcpu_events events;
3316
3317                 r = -EFAULT;
3318                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3319                         break;
3320
3321                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3322                 break;
3323         }
3324         case KVM_GET_DEBUGREGS: {
3325                 struct kvm_debugregs dbgregs;
3326
3327                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3328
3329                 r = -EFAULT;
3330                 if (copy_to_user(argp, &dbgregs,
3331                                  sizeof(struct kvm_debugregs)))
3332                         break;
3333                 r = 0;
3334                 break;
3335         }
3336         case KVM_SET_DEBUGREGS: {
3337                 struct kvm_debugregs dbgregs;
3338
3339                 r = -EFAULT;
3340                 if (copy_from_user(&dbgregs, argp,
3341                                    sizeof(struct kvm_debugregs)))
3342                         break;
3343
3344                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3345                 break;
3346         }
3347         case KVM_GET_XSAVE: {
3348                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3349                 r = -ENOMEM;
3350                 if (!u.xsave)
3351                         break;
3352
3353                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3354
3355                 r = -EFAULT;
3356                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3357                         break;
3358                 r = 0;
3359                 break;
3360         }
3361         case KVM_SET_XSAVE: {
3362                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3363                 if (IS_ERR(u.xsave))
3364                         return PTR_ERR(u.xsave);
3365
3366                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3367                 break;
3368         }
3369         case KVM_GET_XCRS: {
3370                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3371                 r = -ENOMEM;
3372                 if (!u.xcrs)
3373                         break;
3374
3375                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3376
3377                 r = -EFAULT;
3378                 if (copy_to_user(argp, u.xcrs,
3379                                  sizeof(struct kvm_xcrs)))
3380                         break;
3381                 r = 0;
3382                 break;
3383         }
3384         case KVM_SET_XCRS: {
3385                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3386                 if (IS_ERR(u.xcrs))
3387                         return PTR_ERR(u.xcrs);
3388
3389                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3390                 break;
3391         }
3392         case KVM_SET_TSC_KHZ: {
3393                 u32 user_tsc_khz;
3394
3395                 r = -EINVAL;
3396                 user_tsc_khz = (u32)arg;
3397
3398                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3399                         goto out;
3400
3401                 if (user_tsc_khz == 0)
3402                         user_tsc_khz = tsc_khz;
3403
3404                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3405
3406                 r = 0;
3407                 goto out;
3408         }
3409         case KVM_GET_TSC_KHZ: {
3410                 r = vcpu->arch.virtual_tsc_khz;
3411                 goto out;
3412         }
3413         case KVM_KVMCLOCK_CTRL: {
3414                 r = kvm_set_guest_paused(vcpu);
3415                 goto out;
3416         }
3417         default:
3418                 r = -EINVAL;
3419         }
3420 out:
3421         kfree(u.buffer);
3422         return r;
3423 }
3424
3425 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3426 {
3427         return VM_FAULT_SIGBUS;
3428 }
3429
3430 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3431 {
3432         int ret;
3433
3434         if (addr > (unsigned int)(-3 * PAGE_SIZE))
3435                 return -EINVAL;
3436         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3437         return ret;
3438 }
3439
3440 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3441                                               u64 ident_addr)
3442 {
3443         kvm->arch.ept_identity_map_addr = ident_addr;
3444         return 0;
3445 }
3446
3447 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3448                                           u32 kvm_nr_mmu_pages)
3449 {
3450         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3451                 return -EINVAL;
3452
3453         mutex_lock(&kvm->slots_lock);
3454
3455         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3456         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3457
3458         mutex_unlock(&kvm->slots_lock);
3459         return 0;
3460 }
3461
3462 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3463 {
3464         return kvm->arch.n_max_mmu_pages;
3465 }
3466
3467 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3468 {
3469         int r;
3470
3471         r = 0;
3472         switch (chip->chip_id) {
3473         case KVM_IRQCHIP_PIC_MASTER:
3474                 memcpy(&chip->chip.pic,
3475                         &pic_irqchip(kvm)->pics[0],
3476                         sizeof(struct kvm_pic_state));
3477                 break;
3478         case KVM_IRQCHIP_PIC_SLAVE:
3479                 memcpy(&chip->chip.pic,
3480                         &pic_irqchip(kvm)->pics[1],
3481                         sizeof(struct kvm_pic_state));
3482                 break;
3483         case KVM_IRQCHIP_IOAPIC:
3484                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3485                 break;
3486         default:
3487                 r = -EINVAL;
3488                 break;
3489         }
3490         return r;
3491 }
3492
3493 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3494 {
3495         int r;
3496
3497         r = 0;
3498         switch (chip->chip_id) {
3499         case KVM_IRQCHIP_PIC_MASTER:
3500                 spin_lock(&pic_irqchip(kvm)->lock);
3501                 memcpy(&pic_irqchip(kvm)->pics[0],
3502                         &chip->chip.pic,
3503                         sizeof(struct kvm_pic_state));
3504                 spin_unlock(&pic_irqchip(kvm)->lock);
3505                 break;
3506         case KVM_IRQCHIP_PIC_SLAVE:
3507                 spin_lock(&pic_irqchip(kvm)->lock);
3508                 memcpy(&pic_irqchip(kvm)->pics[1],
3509                         &chip->chip.pic,
3510                         sizeof(struct kvm_pic_state));
3511                 spin_unlock(&pic_irqchip(kvm)->lock);
3512                 break;
3513         case KVM_IRQCHIP_IOAPIC:
3514                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3515                 break;
3516         default:
3517                 r = -EINVAL;
3518                 break;
3519         }
3520         kvm_pic_update_irq(pic_irqchip(kvm));
3521         return r;
3522 }
3523
3524 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3525 {
3526         int r = 0;
3527
3528         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3529         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3530         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3531         return r;
3532 }
3533
3534 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3535 {
3536         int r = 0;
3537
3538         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3539         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3540         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3541         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3542         return r;
3543 }
3544
3545 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3546 {
3547         int r = 0;
3548
3549         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3550         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3551                 sizeof(ps->channels));
3552         ps->flags = kvm->arch.vpit->pit_state.flags;
3553         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3554         memset(&ps->reserved, 0, sizeof(ps->reserved));
3555         return r;
3556 }
3557
3558 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3559 {
3560         int r = 0, start = 0;
3561         u32 prev_legacy, cur_legacy;
3562         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3563         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3564         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3565         if (!prev_legacy && cur_legacy)
3566                 start = 1;
3567         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3568                sizeof(kvm->arch.vpit->pit_state.channels));
3569         kvm->arch.vpit->pit_state.flags = ps->flags;
3570         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3571         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3572         return r;
3573 }
3574
3575 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3576                                  struct kvm_reinject_control *control)
3577 {
3578         if (!kvm->arch.vpit)
3579                 return -ENXIO;
3580         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3581         kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3582         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3583         return 0;
3584 }
3585
3586 /**
3587  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3588  * @kvm: kvm instance
3589  * @log: slot id and address to which we copy the log
3590  *
3591  * We need to keep it in mind that VCPU threads can write to the bitmap
3592  * concurrently.  So, to avoid losing data, we keep the following order for
3593  * each bit:
3594  *
3595  *   1. Take a snapshot of the bit and clear it if needed.
3596  *   2. Write protect the corresponding page.
3597  *   3. Flush TLB's if needed.
3598  *   4. Copy the snapshot to the userspace.
3599  *
3600  * Between 2 and 3, the guest may write to the page using the remaining TLB
3601  * entry.  This is not a problem because the page will be reported dirty at
3602  * step 4 using the snapshot taken before and step 3 ensures that successive
3603  * writes will be logged for the next call.
3604  */
3605 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3606 {
3607         int r;
3608         struct kvm_memory_slot *memslot;
3609         unsigned long n, i;
3610         unsigned long *dirty_bitmap;
3611         unsigned long *dirty_bitmap_buffer;
3612         bool is_dirty = false;
3613
3614         mutex_lock(&kvm->slots_lock);
3615
3616         r = -EINVAL;
3617         if (log->slot >= KVM_USER_MEM_SLOTS)
3618                 goto out;
3619
3620         memslot = id_to_memslot(kvm->memslots, log->slot);
3621
3622         dirty_bitmap = memslot->dirty_bitmap;
3623         r = -ENOENT;
3624         if (!dirty_bitmap)
3625                 goto out;
3626
3627         n = kvm_dirty_bitmap_bytes(memslot);
3628
3629         dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3630         memset(dirty_bitmap_buffer, 0, n);
3631
3632         spin_lock(&kvm->mmu_lock);
3633
3634         for (i = 0; i < n / sizeof(long); i++) {
3635                 unsigned long mask;
3636                 gfn_t offset;
3637
3638                 if (!dirty_bitmap[i])
3639                         continue;
3640
3641                 is_dirty = true;
3642
3643                 mask = xchg(&dirty_bitmap[i], 0);
3644                 dirty_bitmap_buffer[i] = mask;
3645
3646                 offset = i * BITS_PER_LONG;
3647                 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3648         }
3649         if (is_dirty)
3650                 kvm_flush_remote_tlbs(kvm);
3651
3652         spin_unlock(&kvm->mmu_lock);
3653
3654         r = -EFAULT;
3655         if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3656                 goto out;
3657
3658         r = 0;
3659 out:
3660         mutex_unlock(&kvm->slots_lock);
3661         return r;
3662 }
3663
3664 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3665                         bool line_status)
3666 {
3667         if (!irqchip_in_kernel(kvm))
3668                 return -ENXIO;
3669
3670         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3671                                         irq_event->irq, irq_event->level,
3672                                         line_status);
3673         return 0;
3674 }
3675
3676 long kvm_arch_vm_ioctl(struct file *filp,
3677                        unsigned int ioctl, unsigned long arg)
3678 {
3679         struct kvm *kvm = filp->private_data;
3680         void __user *argp = (void __user *)arg;
3681         int r = -ENOTTY;
3682         /*
3683          * This union makes it completely explicit to gcc-3.x
3684          * that these two variables' stack usage should be
3685          * combined, not added together.
3686          */
3687         union {
3688                 struct kvm_pit_state ps;
3689                 struct kvm_pit_state2 ps2;
3690                 struct kvm_pit_config pit_config;
3691         } u;
3692
3693         switch (ioctl) {
3694         case KVM_SET_TSS_ADDR:
3695                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3696                 break;
3697         case KVM_SET_IDENTITY_MAP_ADDR: {
3698                 u64 ident_addr;
3699
3700                 r = -EFAULT;
3701                 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3702                         goto out;
3703                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3704                 break;
3705         }
3706         case KVM_SET_NR_MMU_PAGES:
3707                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3708                 break;
3709         case KVM_GET_NR_MMU_PAGES:
3710                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3711                 break;
3712         case KVM_CREATE_IRQCHIP: {
3713                 struct kvm_pic *vpic;
3714
3715                 mutex_lock(&kvm->lock);
3716                 r = -EEXIST;
3717                 if (kvm->arch.vpic)
3718                         goto create_irqchip_unlock;
3719                 r = -EINVAL;
3720                 if (atomic_read(&kvm->online_vcpus))
3721                         goto create_irqchip_unlock;
3722                 r = -ENOMEM;
3723                 vpic = kvm_create_pic(kvm);
3724                 if (vpic) {
3725                         r = kvm_ioapic_init(kvm);
3726                         if (r) {
3727                                 mutex_lock(&kvm->slots_lock);
3728                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3729                                                           &vpic->dev_master);
3730                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3731                                                           &vpic->dev_slave);
3732                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3733                                                           &vpic->dev_eclr);
3734                                 mutex_unlock(&kvm->slots_lock);
3735                                 kfree(vpic);
3736                                 goto create_irqchip_unlock;
3737                         }
3738                 } else
3739                         goto create_irqchip_unlock;
3740                 smp_wmb();
3741                 kvm->arch.vpic = vpic;
3742                 smp_wmb();
3743                 r = kvm_setup_default_irq_routing(kvm);
3744                 if (r) {
3745                         mutex_lock(&kvm->slots_lock);
3746                         mutex_lock(&kvm->irq_lock);
3747                         kvm_ioapic_destroy(kvm);
3748                         kvm_destroy_pic(kvm);
3749                         mutex_unlock(&kvm->irq_lock);
3750                         mutex_unlock(&kvm->slots_lock);
3751                 }
3752         create_irqchip_unlock:
3753                 mutex_unlock(&kvm->lock);
3754                 break;
3755         }
3756         case KVM_CREATE_PIT:
3757                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3758                 goto create_pit;
3759         case KVM_CREATE_PIT2:
3760                 r = -EFAULT;
3761                 if (copy_from_user(&u.pit_config, argp,
3762                                    sizeof(struct kvm_pit_config)))
3763                         goto out;
3764         create_pit:
3765                 mutex_lock(&kvm->slots_lock);
3766                 r = -EEXIST;
3767                 if (kvm->arch.vpit)
3768                         goto create_pit_unlock;
3769                 r = -ENOMEM;
3770                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3771                 if (kvm->arch.vpit)
3772                         r = 0;
3773         create_pit_unlock:
3774                 mutex_unlock(&kvm->slots_lock);
3775                 break;
3776         case KVM_GET_IRQCHIP: {
3777                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3778                 struct kvm_irqchip *chip;
3779
3780                 chip = memdup_user(argp, sizeof(*chip));
3781                 if (IS_ERR(chip)) {
3782                         r = PTR_ERR(chip);
3783                         goto out;
3784                 }
3785
3786                 r = -ENXIO;
3787                 if (!irqchip_in_kernel(kvm))
3788                         goto get_irqchip_out;
3789                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3790                 if (r)
3791                         goto get_irqchip_out;
3792                 r = -EFAULT;
3793                 if (copy_to_user(argp, chip, sizeof *chip))
3794                         goto get_irqchip_out;
3795                 r = 0;
3796         get_irqchip_out:
3797                 kfree(chip);
3798                 break;
3799         }
3800         case KVM_SET_IRQCHIP: {
3801                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3802                 struct kvm_irqchip *chip;
3803
3804                 chip = memdup_user(argp, sizeof(*chip));
3805                 if (IS_ERR(chip)) {
3806                         r = PTR_ERR(chip);
3807                         goto out;
3808                 }
3809
3810                 r = -ENXIO;
3811                 if (!irqchip_in_kernel(kvm))
3812                         goto set_irqchip_out;
3813                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3814                 if (r)
3815                         goto set_irqchip_out;
3816                 r = 0;
3817         set_irqchip_out:
3818                 kfree(chip);
3819                 break;
3820         }
3821         case KVM_GET_PIT: {
3822                 r = -EFAULT;
3823                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3824                         goto out;
3825                 r = -ENXIO;
3826                 if (!kvm->arch.vpit)
3827                         goto out;
3828                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3829                 if (r)
3830                         goto out;
3831                 r = -EFAULT;
3832                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3833                         goto out;
3834                 r = 0;
3835                 break;
3836         }
3837         case KVM_SET_PIT: {
3838                 r = -EFAULT;
3839                 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3840                         goto out;
3841                 r = -ENXIO;
3842                 if (!kvm->arch.vpit)
3843                         goto out;
3844                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3845                 break;
3846         }
3847         case KVM_GET_PIT2: {
3848                 r = -ENXIO;
3849                 if (!kvm->arch.vpit)
3850                         goto out;
3851                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3852                 if (r)
3853                         goto out;
3854                 r = -EFAULT;
3855                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3856                         goto out;
3857                 r = 0;
3858                 break;
3859         }
3860         case KVM_SET_PIT2: {
3861                 r = -EFAULT;
3862                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3863                         goto out;
3864                 r = -ENXIO;
3865                 if (!kvm->arch.vpit)
3866                         goto out;
3867                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3868                 break;
3869         }
3870         case KVM_REINJECT_CONTROL: {
3871                 struct kvm_reinject_control control;
3872                 r =  -EFAULT;
3873                 if (copy_from_user(&control, argp, sizeof(control)))
3874                         goto out;
3875                 r = kvm_vm_ioctl_reinject(kvm, &control);
3876                 break;
3877         }
3878         case KVM_XEN_HVM_CONFIG: {
3879                 r = -EFAULT;
3880                 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3881                                    sizeof(struct kvm_xen_hvm_config)))
3882                         goto out;
3883                 r = -EINVAL;
3884                 if (kvm->arch.xen_hvm_config.flags)
3885                         goto out;
3886                 r = 0;
3887                 break;
3888         }
3889         case KVM_SET_CLOCK: {
3890                 struct kvm_clock_data user_ns;
3891                 u64 now_ns;
3892                 s64 delta;
3893
3894                 r = -EFAULT;
3895                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3896                         goto out;
3897
3898                 r = -EINVAL;
3899                 if (user_ns.flags)
3900                         goto out;
3901
3902                 r = 0;
3903                 local_irq_disable();
3904                 now_ns = get_kernel_ns();
3905                 delta = user_ns.clock - now_ns;
3906                 local_irq_enable();
3907                 kvm->arch.kvmclock_offset = delta;
3908                 kvm_gen_update_masterclock(kvm);
3909                 break;
3910         }
3911         case KVM_GET_CLOCK: {
3912                 struct kvm_clock_data user_ns;
3913                 u64 now_ns;
3914
3915                 local_irq_disable();
3916                 now_ns = get_kernel_ns();
3917                 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3918                 local_irq_enable();
3919                 user_ns.flags = 0;
3920                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3921
3922                 r = -EFAULT;
3923                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3924                         goto out;
3925                 r = 0;
3926                 break;
3927         }
3928
3929         default:
3930                 ;
3931         }
3932 out:
3933         return r;
3934 }
3935
3936 static void kvm_init_msr_list(void)
3937 {
3938         u32 dummy[2];
3939         unsigned i, j;
3940
3941         /* skip the first msrs in the list. KVM-specific */
3942         for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3943                 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3944                         continue;
3945
3946                 /*
3947                  * Even MSRs that are valid in the host may not be exposed
3948                  * to the guests in some cases.  We could work around this
3949                  * in VMX with the generic MSR save/load machinery, but it
3950                  * is not really worthwhile since it will really only
3951                  * happen with nested virtualization.
3952                  */
3953                 switch (msrs_to_save[i]) {
3954                 case MSR_IA32_BNDCFGS:
3955                         if (!kvm_x86_ops->mpx_supported())
3956                                 continue;
3957                         break;
3958                 default:
3959                         break;
3960                 }
3961
3962                 if (j < i)
3963                         msrs_to_save[j] = msrs_to_save[i];
3964                 j++;
3965         }
3966         num_msrs_to_save = j;
3967 }
3968
3969 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3970                            const void *v)
3971 {
3972         int handled = 0;
3973         int n;
3974
3975         do {
3976                 n = min(len, 8);
3977                 if (!(vcpu->arch.apic &&
3978                       !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3979                     && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3980                         break;
3981                 handled += n;
3982                 addr += n;
3983                 len -= n;
3984                 v += n;
3985         } while (len);
3986
3987         return handled;
3988 }
3989
3990 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3991 {
3992         int handled = 0;
3993         int n;
3994
3995         do {
3996                 n = min(len, 8);
3997                 if (!(vcpu->arch.apic &&
3998                       !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3999                     && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4000                         break;
4001                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4002                 handled += n;
4003                 addr += n;
4004                 len -= n;
4005                 v += n;
4006         } while (len);
4007
4008         return handled;
4009 }
4010
4011 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4012                         struct kvm_segment *var, int seg)
4013 {
4014         kvm_x86_ops->set_segment(vcpu, var, seg);
4015 }
4016
4017 void kvm_get_segment(struct kvm_vcpu *vcpu,
4018                      struct kvm_segment *var, int seg)
4019 {
4020         kvm_x86_ops->get_segment(vcpu, var, seg);
4021 }
4022
4023 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
4024 {
4025         gpa_t t_gpa;
4026         struct x86_exception exception;
4027
4028         BUG_ON(!mmu_is_nested(vcpu));
4029
4030         /* NPT walks are always user-walks */
4031         access |= PFERR_USER_MASK;
4032         t_gpa  = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
4033
4034         return t_gpa;
4035 }
4036
4037 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4038                               struct x86_exception *exception)
4039 {
4040         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4041         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4042 }
4043
4044  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4045                                 struct x86_exception *exception)
4046 {
4047         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4048         access |= PFERR_FETCH_MASK;
4049         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4050 }
4051
4052 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4053                                struct x86_exception *exception)
4054 {
4055         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4056         access |= PFERR_WRITE_MASK;
4057         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4058 }
4059
4060 /* uses this to access any guest's mapped memory without checking CPL */
4061 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4062                                 struct x86_exception *exception)
4063 {
4064         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4065 }
4066
4067 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4068                                       struct kvm_vcpu *vcpu, u32 access,
4069                                       struct x86_exception *exception)
4070 {
4071         void *data = val;
4072         int r = X86EMUL_CONTINUE;
4073
4074         while (bytes) {
4075                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4076                                                             exception);
4077                 unsigned offset = addr & (PAGE_SIZE-1);
4078                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4079                 int ret;
4080
4081                 if (gpa == UNMAPPED_GVA)
4082                         return X86EMUL_PROPAGATE_FAULT;
4083                 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
4084                 if (ret < 0) {
4085                         r = X86EMUL_IO_NEEDED;
4086                         goto out;
4087                 }
4088
4089                 bytes -= toread;
4090                 data += toread;
4091                 addr += toread;
4092         }
4093 out:
4094         return r;
4095 }
4096
4097 /* used for instruction fetching */
4098 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4099                                 gva_t addr, void *val, unsigned int bytes,
4100                                 struct x86_exception *exception)
4101 {
4102         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4103         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4104
4105         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4106                                           access | PFERR_FETCH_MASK,
4107                                           exception);
4108 }
4109
4110 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4111                                gva_t addr, void *val, unsigned int bytes,
4112                                struct x86_exception *exception)
4113 {
4114         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4115         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4116
4117         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4118                                           exception);
4119 }
4120 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4121
4122 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4123                                       gva_t addr, void *val, unsigned int bytes,
4124                                       struct x86_exception *exception)
4125 {
4126         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4127         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4128 }
4129
4130 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4131                                        gva_t addr, void *val,
4132                                        unsigned int bytes,
4133                                        struct x86_exception *exception)
4134 {
4135         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4136         void *data = val;
4137         int r = X86EMUL_CONTINUE;
4138
4139         while (bytes) {
4140                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4141                                                              PFERR_WRITE_MASK,
4142                                                              exception);
4143                 unsigned offset = addr & (PAGE_SIZE-1);
4144                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4145                 int ret;
4146
4147                 if (gpa == UNMAPPED_GVA)
4148                         return X86EMUL_PROPAGATE_FAULT;
4149                 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4150                 if (ret < 0) {
4151                         r = X86EMUL_IO_NEEDED;
4152                         goto out;
4153                 }
4154
4155                 bytes -= towrite;
4156                 data += towrite;
4157                 addr += towrite;
4158         }
4159 out:
4160         return r;
4161 }
4162 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4163
4164 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4165                                 gpa_t *gpa, struct x86_exception *exception,
4166                                 bool write)
4167 {
4168         u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4169                 | (write ? PFERR_WRITE_MASK : 0);
4170
4171         if (vcpu_match_mmio_gva(vcpu, gva)
4172             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4173                                  vcpu->arch.access, access)) {
4174                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4175                                         (gva & (PAGE_SIZE - 1));
4176                 trace_vcpu_match_mmio(gva, *gpa, write, false);
4177                 return 1;
4178         }
4179
4180         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4181
4182         if (*gpa == UNMAPPED_GVA)
4183                 return -1;
4184
4185         /* For APIC access vmexit */
4186         if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4187                 return 1;
4188
4189         if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4190                 trace_vcpu_match_mmio(gva, *gpa, write, true);
4191                 return 1;
4192         }
4193
4194         return 0;
4195 }
4196
4197 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4198                         const void *val, int bytes)
4199 {
4200         int ret;
4201
4202         ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4203         if (ret < 0)
4204                 return 0;
4205         kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4206         return 1;
4207 }
4208
4209 struct read_write_emulator_ops {
4210         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4211                                   int bytes);
4212         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4213                                   void *val, int bytes);
4214         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4215                                int bytes, void *val);
4216         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4217                                     void *val, int bytes);
4218         bool write;
4219 };
4220
4221 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4222 {
4223         if (vcpu->mmio_read_completed) {
4224                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4225                                vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4226                 vcpu->mmio_read_completed = 0;
4227                 return 1;
4228         }
4229
4230         return 0;
4231 }
4232
4233 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4234                         void *val, int bytes)
4235 {
4236         return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4237 }
4238
4239 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4240                          void *val, int bytes)
4241 {
4242         return emulator_write_phys(vcpu, gpa, val, bytes);
4243 }
4244
4245 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4246 {
4247         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4248         return vcpu_mmio_write(vcpu, gpa, bytes, val);
4249 }
4250
4251 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4252                           void *val, int bytes)
4253 {
4254         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4255         return X86EMUL_IO_NEEDED;
4256 }
4257
4258 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4259                            void *val, int bytes)
4260 {
4261         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4262
4263         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4264         return X86EMUL_CONTINUE;
4265 }
4266
4267 static const struct read_write_emulator_ops read_emultor = {
4268         .read_write_prepare = read_prepare,
4269         .read_write_emulate = read_emulate,
4270         .read_write_mmio = vcpu_mmio_read,
4271         .read_write_exit_mmio = read_exit_mmio,
4272 };
4273
4274 static const struct read_write_emulator_ops write_emultor = {
4275         .read_write_emulate = write_emulate,
4276         .read_write_mmio = write_mmio,
4277         .read_write_exit_mmio = write_exit_mmio,
4278         .write = true,
4279 };
4280
4281 static int emulator_read_write_onepage(unsigned long addr, void *val,
4282                                        unsigned int bytes,
4283                                        struct x86_exception *exception,
4284                                        struct kvm_vcpu *vcpu,
4285                                        const struct read_write_emulator_ops *ops)
4286 {
4287         gpa_t gpa;
4288         int handled, ret;
4289         bool write = ops->write;
4290         struct kvm_mmio_fragment *frag;
4291
4292         ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4293
4294         if (ret < 0)
4295                 return X86EMUL_PROPAGATE_FAULT;
4296
4297         /* For APIC access vmexit */
4298         if (ret)
4299                 goto mmio;
4300
4301         if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4302                 return X86EMUL_CONTINUE;
4303
4304 mmio:
4305         /*
4306          * Is this MMIO handled locally?
4307          */
4308         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4309         if (handled == bytes)
4310                 return X86EMUL_CONTINUE;
4311
4312         gpa += handled;
4313         bytes -= handled;
4314         val += handled;
4315
4316         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4317         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4318         frag->gpa = gpa;
4319         frag->data = val;
4320         frag->len = bytes;
4321         return X86EMUL_CONTINUE;
4322 }
4323
4324 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4325                         void *val, unsigned int bytes,
4326                         struct x86_exception *exception,
4327                         const struct read_write_emulator_ops *ops)
4328 {
4329         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4330         gpa_t gpa;
4331         int rc;
4332
4333         if (ops->read_write_prepare &&
4334                   ops->read_write_prepare(vcpu, val, bytes))
4335                 return X86EMUL_CONTINUE;
4336
4337         vcpu->mmio_nr_fragments = 0;
4338
4339         /* Crossing a page boundary? */
4340         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4341                 int now;
4342
4343                 now = -addr & ~PAGE_MASK;
4344                 rc = emulator_read_write_onepage(addr, val, now, exception,
4345                                                  vcpu, ops);
4346
4347                 if (rc != X86EMUL_CONTINUE)
4348                         return rc;
4349                 addr += now;
4350                 val += now;
4351                 bytes -= now;
4352         }
4353
4354         rc = emulator_read_write_onepage(addr, val, bytes, exception,
4355                                          vcpu, ops);
4356         if (rc != X86EMUL_CONTINUE)
4357                 return rc;
4358
4359         if (!vcpu->mmio_nr_fragments)
4360                 return rc;
4361
4362         gpa = vcpu->mmio_fragments[0].gpa;
4363
4364         vcpu->mmio_needed = 1;
4365         vcpu->mmio_cur_fragment = 0;
4366
4367         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4368         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4369         vcpu->run->exit_reason = KVM_EXIT_MMIO;
4370         vcpu->run->mmio.phys_addr = gpa;
4371
4372         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4373 }
4374
4375 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4376                                   unsigned long addr,
4377                                   void *val,
4378                                   unsigned int bytes,
4379                                   struct x86_exception *exception)
4380 {
4381         return emulator_read_write(ctxt, addr, val, bytes,
4382                                    exception, &read_emultor);
4383 }
4384
4385 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4386                             unsigned long addr,
4387                             const void *val,
4388                             unsigned int bytes,
4389                             struct x86_exception *exception)
4390 {
4391         return emulator_read_write(ctxt, addr, (void *)val, bytes,
4392                                    exception, &write_emultor);
4393 }
4394
4395 #define CMPXCHG_TYPE(t, ptr, old, new) \
4396         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4397
4398 #ifdef CONFIG_X86_64
4399 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4400 #else
4401 #  define CMPXCHG64(ptr, old, new) \
4402         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4403 #endif
4404
4405 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4406                                      unsigned long addr,
4407                                      const void *old,
4408                                      const void *new,
4409                                      unsigned int bytes,
4410                                      struct x86_exception *exception)
4411 {
4412         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4413         gpa_t gpa;
4414         struct page *page;
4415         char *kaddr;
4416         bool exchanged;
4417
4418         /* guests cmpxchg8b have to be emulated atomically */
4419         if (bytes > 8 || (bytes & (bytes - 1)))
4420                 goto emul_write;
4421
4422         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4423
4424         if (gpa == UNMAPPED_GVA ||
4425             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4426                 goto emul_write;
4427
4428         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4429                 goto emul_write;
4430
4431         page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4432         if (is_error_page(page))
4433                 goto emul_write;
4434
4435         kaddr = kmap_atomic(page);
4436         kaddr += offset_in_page(gpa);
4437         switch (bytes) {
4438         case 1:
4439                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4440                 break;
4441         case 2:
4442                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4443                 break;
4444         case 4:
4445                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4446                 break;
4447         case 8:
4448                 exchanged = CMPXCHG64(kaddr, old, new);
4449                 break;
4450         default:
4451                 BUG();
4452         }
4453         kunmap_atomic(kaddr);
4454         kvm_release_page_dirty(page);
4455
4456         if (!exchanged)
4457                 return X86EMUL_CMPXCHG_FAILED;
4458
4459         mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
4460         kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4461
4462         return X86EMUL_CONTINUE;
4463
4464 emul_write:
4465         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4466
4467         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4468 }
4469
4470 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4471 {
4472         /* TODO: String I/O for in kernel device */
4473         int r;
4474
4475         if (vcpu->arch.pio.in)
4476                 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4477                                     vcpu->arch.pio.size, pd);
4478         else
4479                 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4480                                      vcpu->arch.pio.port, vcpu->arch.pio.size,
4481                                      pd);
4482         return r;
4483 }
4484
4485 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4486                                unsigned short port, void *val,
4487                                unsigned int count, bool in)
4488 {
4489         trace_kvm_pio(!in, port, size, count);
4490
4491         vcpu->arch.pio.port = port;
4492         vcpu->arch.pio.in = in;
4493         vcpu->arch.pio.count  = count;
4494         vcpu->arch.pio.size = size;
4495
4496         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4497                 vcpu->arch.pio.count = 0;
4498                 return 1;
4499         }
4500
4501         vcpu->run->exit_reason = KVM_EXIT_IO;
4502         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4503         vcpu->run->io.size = size;
4504         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4505         vcpu->run->io.count = count;
4506         vcpu->run->io.port = port;
4507
4508         return 0;
4509 }
4510
4511 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4512                                     int size, unsigned short port, void *val,
4513                                     unsigned int count)
4514 {
4515         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4516         int ret;
4517
4518         if (vcpu->arch.pio.count)
4519                 goto data_avail;
4520
4521         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4522         if (ret) {
4523 data_avail:
4524                 memcpy(val, vcpu->arch.pio_data, size * count);
4525                 vcpu->arch.pio.count = 0;
4526                 return 1;
4527         }
4528
4529         return 0;
4530 }
4531
4532 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4533                                      int size, unsigned short port,
4534                                      const void *val, unsigned int count)
4535 {
4536         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4537
4538         memcpy(vcpu->arch.pio_data, val, size * count);
4539         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4540 }
4541
4542 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4543 {
4544         return kvm_x86_ops->get_segment_base(vcpu, seg);
4545 }
4546
4547 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4548 {
4549         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4550 }
4551
4552 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4553 {
4554         if (!need_emulate_wbinvd(vcpu))
4555                 return X86EMUL_CONTINUE;
4556
4557         if (kvm_x86_ops->has_wbinvd_exit()) {
4558                 int cpu = get_cpu();
4559
4560                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4561                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4562                                 wbinvd_ipi, NULL, 1);
4563                 put_cpu();
4564                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4565         } else
4566                 wbinvd();
4567         return X86EMUL_CONTINUE;
4568 }
4569 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4570
4571 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4572 {
4573         kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4574 }
4575
4576 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4577 {
4578         return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4579 }
4580
4581 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4582 {
4583
4584         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4585 }
4586
4587 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4588 {
4589         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4590 }
4591
4592 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4593 {
4594         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4595         unsigned long value;
4596
4597         switch (cr) {
4598         case 0:
4599                 value = kvm_read_cr0(vcpu);
4600                 break;
4601         case 2:
4602                 value = vcpu->arch.cr2;
4603                 break;
4604         case 3:
4605                 value = kvm_read_cr3(vcpu);
4606                 break;
4607         case 4:
4608                 value = kvm_read_cr4(vcpu);
4609                 break;
4610         case 8:
4611                 value = kvm_get_cr8(vcpu);
4612                 break;
4613         default:
4614                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4615                 return 0;
4616         }
4617
4618         return value;
4619 }
4620
4621 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4622 {
4623         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4624         int res = 0;
4625
4626         switch (cr) {
4627         case 0:
4628                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4629                 break;
4630         case 2:
4631                 vcpu->arch.cr2 = val;
4632                 break;
4633         case 3:
4634                 res = kvm_set_cr3(vcpu, val);
4635                 break;
4636         case 4:
4637                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4638                 break;
4639         case 8:
4640                 res = kvm_set_cr8(vcpu, val);
4641                 break;
4642         default:
4643                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4644                 res = -1;
4645         }
4646
4647         return res;
4648 }
4649
4650 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4651 {
4652         kvm_set_rflags(emul_to_vcpu(ctxt), val);
4653 }
4654
4655 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4656 {
4657         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4658 }
4659
4660 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4661 {
4662         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4663 }
4664
4665 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4666 {
4667         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4668 }
4669
4670 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4671 {
4672         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4673 }
4674
4675 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4676 {
4677         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4678 }
4679
4680 static unsigned long emulator_get_cached_segment_base(
4681         struct x86_emulate_ctxt *ctxt, int seg)
4682 {
4683         return get_segment_base(emul_to_vcpu(ctxt), seg);
4684 }
4685
4686 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4687                                  struct desc_struct *desc, u32 *base3,
4688                                  int seg)
4689 {
4690         struct kvm_segment var;
4691
4692         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4693         *selector = var.selector;
4694
4695         if (var.unusable) {
4696                 memset(desc, 0, sizeof(*desc));
4697                 return false;
4698         }
4699
4700         if (var.g)
4701                 var.limit >>= 12;
4702         set_desc_limit(desc, var.limit);
4703         set_desc_base(desc, (unsigned long)var.base);
4704 #ifdef CONFIG_X86_64
4705         if (base3)
4706                 *base3 = var.base >> 32;
4707 #endif
4708         desc->type = var.type;
4709         desc->s = var.s;
4710         desc->dpl = var.dpl;
4711         desc->p = var.present;
4712         desc->avl = var.avl;
4713         desc->l = var.l;
4714         desc->d = var.db;
4715         desc->g = var.g;
4716
4717         return true;
4718 }
4719
4720 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4721                                  struct desc_struct *desc, u32 base3,
4722                                  int seg)
4723 {
4724         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4725         struct kvm_segment var;
4726
4727         var.selector = selector;
4728         var.base = get_desc_base(desc);
4729 #ifdef CONFIG_X86_64
4730         var.base |= ((u64)base3) << 32;
4731 #endif
4732         var.limit = get_desc_limit(desc);
4733         if (desc->g)
4734                 var.limit = (var.limit << 12) | 0xfff;
4735         var.type = desc->type;
4736         var.present = desc->p;
4737         var.dpl = desc->dpl;
4738         var.db = desc->d;
4739         var.s = desc->s;
4740         var.l = desc->l;
4741         var.g = desc->g;
4742         var.avl = desc->avl;
4743         var.present = desc->p;
4744         var.unusable = !var.present;
4745         var.padding = 0;
4746
4747         kvm_set_segment(vcpu, &var, seg);
4748         return;
4749 }
4750
4751 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4752                             u32 msr_index, u64 *pdata)
4753 {
4754         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4755 }
4756
4757 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4758                             u32 msr_index, u64 data)
4759 {
4760         struct msr_data msr;
4761
4762         msr.data = data;
4763         msr.index = msr_index;
4764         msr.host_initiated = false;
4765         return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4766 }
4767
4768 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4769                              u32 pmc, u64 *pdata)
4770 {
4771         return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4772 }
4773
4774 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4775 {
4776         emul_to_vcpu(ctxt)->arch.halt_request = 1;
4777 }
4778
4779 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4780 {
4781         preempt_disable();
4782         kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4783         /*
4784          * CR0.TS may reference the host fpu state, not the guest fpu state,
4785          * so it may be clear at this point.
4786          */
4787         clts();
4788 }
4789
4790 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4791 {
4792         preempt_enable();
4793 }
4794
4795 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4796                               struct x86_instruction_info *info,
4797                               enum x86_intercept_stage stage)
4798 {
4799         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4800 }
4801
4802 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4803                                u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4804 {
4805         kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4806 }
4807
4808 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4809 {
4810         return kvm_register_read(emul_to_vcpu(ctxt), reg);
4811 }
4812
4813 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4814 {
4815         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4816 }
4817
4818 static const struct x86_emulate_ops emulate_ops = {
4819         .read_gpr            = emulator_read_gpr,
4820         .write_gpr           = emulator_write_gpr,
4821         .read_std            = kvm_read_guest_virt_system,
4822         .write_std           = kvm_write_guest_virt_system,
4823         .fetch               = kvm_fetch_guest_virt,
4824         .read_emulated       = emulator_read_emulated,
4825         .write_emulated      = emulator_write_emulated,
4826         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
4827         .invlpg              = emulator_invlpg,
4828         .pio_in_emulated     = emulator_pio_in_emulated,
4829         .pio_out_emulated    = emulator_pio_out_emulated,
4830         .get_segment         = emulator_get_segment,
4831         .set_segment         = emulator_set_segment,
4832         .get_cached_segment_base = emulator_get_cached_segment_base,
4833         .get_gdt             = emulator_get_gdt,
4834         .get_idt             = emulator_get_idt,
4835         .set_gdt             = emulator_set_gdt,
4836         .set_idt             = emulator_set_idt,
4837         .get_cr              = emulator_get_cr,
4838         .set_cr              = emulator_set_cr,
4839         .set_rflags          = emulator_set_rflags,
4840         .cpl                 = emulator_get_cpl,
4841         .get_dr              = emulator_get_dr,
4842         .set_dr              = emulator_set_dr,
4843         .set_msr             = emulator_set_msr,
4844         .get_msr             = emulator_get_msr,
4845         .read_pmc            = emulator_read_pmc,
4846         .halt                = emulator_halt,
4847         .wbinvd              = emulator_wbinvd,
4848         .fix_hypercall       = emulator_fix_hypercall,
4849         .get_fpu             = emulator_get_fpu,
4850         .put_fpu             = emulator_put_fpu,
4851         .intercept           = emulator_intercept,
4852         .get_cpuid           = emulator_get_cpuid,
4853 };
4854
4855 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4856 {
4857         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4858         /*
4859          * an sti; sti; sequence only disable interrupts for the first
4860          * instruction. So, if the last instruction, be it emulated or
4861          * not, left the system with the INT_STI flag enabled, it
4862          * means that the last instruction is an sti. We should not
4863          * leave the flag on in this case. The same goes for mov ss
4864          */
4865         if (!(int_shadow & mask))
4866                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4867 }
4868
4869 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4870 {
4871         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4872         if (ctxt->exception.vector == PF_VECTOR)
4873                 kvm_propagate_fault(vcpu, &ctxt->exception);
4874         else if (ctxt->exception.error_code_valid)
4875                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4876                                       ctxt->exception.error_code);
4877         else
4878                 kvm_queue_exception(vcpu, ctxt->exception.vector);
4879 }
4880
4881 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4882 {
4883         memset(&ctxt->opcode_len, 0,
4884                (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
4885
4886         ctxt->fetch.start = 0;
4887         ctxt->fetch.end = 0;
4888         ctxt->io_read.pos = 0;
4889         ctxt->io_read.end = 0;
4890         ctxt->mem_read.pos = 0;
4891         ctxt->mem_read.end = 0;
4892 }
4893
4894 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4895 {
4896         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4897         int cs_db, cs_l;
4898
4899         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4900
4901         ctxt->eflags = kvm_get_rflags(vcpu);
4902         ctxt->eip = kvm_rip_read(vcpu);
4903         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
4904                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
4905                      cs_l                               ? X86EMUL_MODE_PROT64 :
4906                      cs_db                              ? X86EMUL_MODE_PROT32 :
4907                                                           X86EMUL_MODE_PROT16;
4908         ctxt->guest_mode = is_guest_mode(vcpu);
4909
4910         init_decode_cache(ctxt);
4911         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4912 }
4913
4914 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4915 {
4916         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4917         int ret;
4918
4919         init_emulate_ctxt(vcpu);
4920
4921         ctxt->op_bytes = 2;
4922         ctxt->ad_bytes = 2;
4923         ctxt->_eip = ctxt->eip + inc_eip;
4924         ret = emulate_int_real(ctxt, irq);
4925
4926         if (ret != X86EMUL_CONTINUE)
4927                 return EMULATE_FAIL;
4928
4929         ctxt->eip = ctxt->_eip;
4930         kvm_rip_write(vcpu, ctxt->eip);
4931         kvm_set_rflags(vcpu, ctxt->eflags);
4932
4933         if (irq == NMI_VECTOR)
4934                 vcpu->arch.nmi_pending = 0;
4935         else
4936                 vcpu->arch.interrupt.pending = false;
4937
4938         return EMULATE_DONE;
4939 }
4940 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4941
4942 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4943 {
4944         int r = EMULATE_DONE;
4945
4946         ++vcpu->stat.insn_emulation_fail;
4947         trace_kvm_emulate_insn_failed(vcpu);
4948         if (!is_guest_mode(vcpu)) {
4949                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4950                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4951                 vcpu->run->internal.ndata = 0;
4952                 r = EMULATE_FAIL;
4953         }
4954         kvm_queue_exception(vcpu, UD_VECTOR);
4955
4956         return r;
4957 }
4958
4959 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4960                                   bool write_fault_to_shadow_pgtable,
4961                                   int emulation_type)
4962 {
4963         gpa_t gpa = cr2;
4964         pfn_t pfn;
4965
4966         if (emulation_type & EMULTYPE_NO_REEXECUTE)
4967                 return false;
4968
4969         if (!vcpu->arch.mmu.direct_map) {
4970                 /*
4971                  * Write permission should be allowed since only
4972                  * write access need to be emulated.
4973                  */
4974                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4975
4976                 /*
4977                  * If the mapping is invalid in guest, let cpu retry
4978                  * it to generate fault.
4979                  */
4980                 if (gpa == UNMAPPED_GVA)
4981                         return true;
4982         }
4983
4984         /*
4985          * Do not retry the unhandleable instruction if it faults on the
4986          * readonly host memory, otherwise it will goto a infinite loop:
4987          * retry instruction -> write #PF -> emulation fail -> retry
4988          * instruction -> ...
4989          */
4990         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4991
4992         /*
4993          * If the instruction failed on the error pfn, it can not be fixed,
4994          * report the error to userspace.
4995          */
4996         if (is_error_noslot_pfn(pfn))
4997                 return false;
4998
4999         kvm_release_pfn_clean(pfn);
5000
5001         /* The instructions are well-emulated on direct mmu. */
5002         if (vcpu->arch.mmu.direct_map) {
5003                 unsigned int indirect_shadow_pages;
5004
5005                 spin_lock(&vcpu->kvm->mmu_lock);
5006                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5007                 spin_unlock(&vcpu->kvm->mmu_lock);
5008
5009                 if (indirect_shadow_pages)
5010                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5011
5012                 return true;
5013         }
5014
5015         /*
5016          * if emulation was due to access to shadowed page table
5017          * and it failed try to unshadow page and re-enter the
5018          * guest to let CPU execute the instruction.
5019          */
5020         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5021
5022         /*
5023          * If the access faults on its page table, it can not
5024          * be fixed by unprotecting shadow page and it should
5025          * be reported to userspace.
5026          */
5027         return !write_fault_to_shadow_pgtable;
5028 }
5029
5030 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5031                               unsigned long cr2,  int emulation_type)
5032 {
5033         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5034         unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5035
5036         last_retry_eip = vcpu->arch.last_retry_eip;
5037         last_retry_addr = vcpu->arch.last_retry_addr;
5038
5039         /*
5040          * If the emulation is caused by #PF and it is non-page_table
5041          * writing instruction, it means the VM-EXIT is caused by shadow
5042          * page protected, we can zap the shadow page and retry this
5043          * instruction directly.
5044          *
5045          * Note: if the guest uses a non-page-table modifying instruction
5046          * on the PDE that points to the instruction, then we will unmap
5047          * the instruction and go to an infinite loop. So, we cache the
5048          * last retried eip and the last fault address, if we meet the eip
5049          * and the address again, we can break out of the potential infinite
5050          * loop.
5051          */
5052         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5053
5054         if (!(emulation_type & EMULTYPE_RETRY))
5055                 return false;
5056
5057         if (x86_page_table_writing_insn(ctxt))
5058                 return false;
5059
5060         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5061                 return false;
5062
5063         vcpu->arch.last_retry_eip = ctxt->eip;
5064         vcpu->arch.last_retry_addr = cr2;
5065
5066         if (!vcpu->arch.mmu.direct_map)
5067                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5068
5069         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5070
5071         return true;
5072 }
5073
5074 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5075 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5076
5077 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5078                                 unsigned long *db)
5079 {
5080         u32 dr6 = 0;
5081         int i;
5082         u32 enable, rwlen;
5083
5084         enable = dr7;
5085         rwlen = dr7 >> 16;
5086         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5087                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5088                         dr6 |= (1 << i);
5089         return dr6;
5090 }
5091
5092 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5093 {
5094         struct kvm_run *kvm_run = vcpu->run;
5095
5096         /*
5097          * Use the "raw" value to see if TF was passed to the processor.
5098          * Note that the new value of the flags has not been saved yet.
5099          *
5100          * This is correct even for TF set by the guest, because "the
5101          * processor will not generate this exception after the instruction
5102          * that sets the TF flag".
5103          */
5104         unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5105
5106         if (unlikely(rflags & X86_EFLAGS_TF)) {
5107                 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5108                         kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5109                         kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5110                         kvm_run->debug.arch.exception = DB_VECTOR;
5111                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
5112                         *r = EMULATE_USER_EXIT;
5113                 } else {
5114                         vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5115                         /*
5116                          * "Certain debug exceptions may clear bit 0-3.  The
5117                          * remaining contents of the DR6 register are never
5118                          * cleared by the processor".
5119                          */
5120                         vcpu->arch.dr6 &= ~15;
5121                         vcpu->arch.dr6 |= DR6_BS;
5122                         kvm_queue_exception(vcpu, DB_VECTOR);
5123                 }
5124         }
5125 }
5126
5127 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5128 {
5129         struct kvm_run *kvm_run = vcpu->run;
5130         unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5131         u32 dr6 = 0;
5132
5133         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5134             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5135                 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5136                                            vcpu->arch.guest_debug_dr7,
5137                                            vcpu->arch.eff_db);
5138
5139                 if (dr6 != 0) {
5140                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5141                         kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5142                                 get_segment_base(vcpu, VCPU_SREG_CS);
5143
5144                         kvm_run->debug.arch.exception = DB_VECTOR;
5145                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
5146                         *r = EMULATE_USER_EXIT;
5147                         return true;
5148                 }
5149         }
5150
5151         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5152                 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5153                                            vcpu->arch.dr7,
5154                                            vcpu->arch.db);
5155
5156                 if (dr6 != 0) {
5157                         vcpu->arch.dr6 &= ~15;
5158                         vcpu->arch.dr6 |= dr6;
5159                         kvm_queue_exception(vcpu, DB_VECTOR);
5160                         *r = EMULATE_DONE;
5161                         return true;
5162                 }
5163         }
5164
5165         return false;
5166 }
5167
5168 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5169                             unsigned long cr2,
5170                             int emulation_type,
5171                             void *insn,
5172                             int insn_len)
5173 {
5174         int r;
5175         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5176         bool writeback = true;
5177         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5178
5179         /*
5180          * Clear write_fault_to_shadow_pgtable here to ensure it is
5181          * never reused.
5182          */
5183         vcpu->arch.write_fault_to_shadow_pgtable = false;
5184         kvm_clear_exception_queue(vcpu);
5185
5186         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5187                 init_emulate_ctxt(vcpu);
5188
5189                 /*
5190                  * We will reenter on the same instruction since
5191                  * we do not set complete_userspace_io.  This does not
5192                  * handle watchpoints yet, those would be handled in
5193                  * the emulate_ops.
5194                  */
5195                 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5196                         return r;
5197
5198                 ctxt->interruptibility = 0;
5199                 ctxt->have_exception = false;
5200                 ctxt->perm_ok = false;
5201
5202                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5203
5204                 r = x86_decode_insn(ctxt, insn, insn_len);
5205
5206                 trace_kvm_emulate_insn_start(vcpu);
5207                 ++vcpu->stat.insn_emulation;
5208                 if (r != EMULATION_OK)  {
5209                         if (emulation_type & EMULTYPE_TRAP_UD)
5210                                 return EMULATE_FAIL;
5211                         if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5212                                                 emulation_type))
5213                                 return EMULATE_DONE;
5214                         if (emulation_type & EMULTYPE_SKIP)
5215                                 return EMULATE_FAIL;
5216                         return handle_emulation_failure(vcpu);
5217                 }
5218         }
5219
5220         if (emulation_type & EMULTYPE_SKIP) {
5221                 kvm_rip_write(vcpu, ctxt->_eip);
5222                 return EMULATE_DONE;
5223         }
5224
5225         if (retry_instruction(ctxt, cr2, emulation_type))
5226                 return EMULATE_DONE;
5227
5228         /* this is needed for vmware backdoor interface to work since it
5229            changes registers values  during IO operation */
5230         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5231                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5232                 emulator_invalidate_register_cache(ctxt);
5233         }
5234
5235 restart:
5236         r = x86_emulate_insn(ctxt);
5237
5238         if (r == EMULATION_INTERCEPTED)
5239                 return EMULATE_DONE;
5240
5241         if (r == EMULATION_FAILED) {
5242                 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5243                                         emulation_type))
5244                         return EMULATE_DONE;
5245
5246                 return handle_emulation_failure(vcpu);
5247         }
5248
5249         if (ctxt->have_exception) {
5250                 inject_emulated_exception(vcpu);
5251                 r = EMULATE_DONE;
5252         } else if (vcpu->arch.pio.count) {
5253                 if (!vcpu->arch.pio.in) {
5254                         /* FIXME: return into emulator if single-stepping.  */
5255                         vcpu->arch.pio.count = 0;
5256                 } else {
5257                         writeback = false;
5258                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
5259                 }
5260                 r = EMULATE_USER_EXIT;
5261         } else if (vcpu->mmio_needed) {
5262                 if (!vcpu->mmio_is_write)
5263                         writeback = false;
5264                 r = EMULATE_USER_EXIT;
5265                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5266         } else if (r == EMULATION_RESTART)
5267                 goto restart;
5268         else
5269                 r = EMULATE_DONE;
5270
5271         if (writeback) {
5272                 toggle_interruptibility(vcpu, ctxt->interruptibility);
5273                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5274                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5275                 kvm_rip_write(vcpu, ctxt->eip);
5276                 if (r == EMULATE_DONE)
5277                         kvm_vcpu_check_singlestep(vcpu, &r);
5278                 kvm_set_rflags(vcpu, ctxt->eflags);
5279         } else
5280                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5281
5282         return r;
5283 }
5284 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5285
5286 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5287 {
5288         unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5289         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5290                                             size, port, &val, 1);
5291         /* do not return to emulator after return from userspace */
5292         vcpu->arch.pio.count = 0;
5293         return ret;
5294 }
5295 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5296
5297 static void tsc_bad(void *info)
5298 {
5299         __this_cpu_write(cpu_tsc_khz, 0);
5300 }
5301
5302 static void tsc_khz_changed(void *data)
5303 {
5304         struct cpufreq_freqs *freq = data;
5305         unsigned long khz = 0;
5306
5307         if (data)
5308                 khz = freq->new;
5309         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5310                 khz = cpufreq_quick_get(raw_smp_processor_id());
5311         if (!khz)
5312                 khz = tsc_khz;
5313         __this_cpu_write(cpu_tsc_khz, khz);
5314 }
5315
5316 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5317                                      void *data)
5318 {
5319         struct cpufreq_freqs *freq = data;
5320         struct kvm *kvm;
5321         struct kvm_vcpu *vcpu;
5322         int i, send_ipi = 0;
5323
5324         /*
5325          * We allow guests to temporarily run on slowing clocks,
5326          * provided we notify them after, or to run on accelerating
5327          * clocks, provided we notify them before.  Thus time never
5328          * goes backwards.
5329          *
5330          * However, we have a problem.  We can't atomically update
5331          * the frequency of a given CPU from this function; it is
5332          * merely a notifier, which can be called from any CPU.
5333          * Changing the TSC frequency at arbitrary points in time
5334          * requires a recomputation of local variables related to
5335          * the TSC for each VCPU.  We must flag these local variables
5336          * to be updated and be sure the update takes place with the
5337          * new frequency before any guests proceed.
5338          *
5339          * Unfortunately, the combination of hotplug CPU and frequency
5340          * change creates an intractable locking scenario; the order
5341          * of when these callouts happen is undefined with respect to
5342          * CPU hotplug, and they can race with each other.  As such,
5343          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5344          * undefined; you can actually have a CPU frequency change take
5345          * place in between the computation of X and the setting of the
5346          * variable.  To protect against this problem, all updates of
5347          * the per_cpu tsc_khz variable are done in an interrupt
5348          * protected IPI, and all callers wishing to update the value
5349          * must wait for a synchronous IPI to complete (which is trivial
5350          * if the caller is on the CPU already).  This establishes the
5351          * necessary total order on variable updates.
5352          *
5353          * Note that because a guest time update may take place
5354          * anytime after the setting of the VCPU's request bit, the
5355          * correct TSC value must be set before the request.  However,
5356          * to ensure the update actually makes it to any guest which
5357          * starts running in hardware virtualization between the set
5358          * and the acquisition of the spinlock, we must also ping the
5359          * CPU after setting the request bit.
5360          *
5361          */
5362
5363         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5364                 return 0;
5365         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5366                 return 0;
5367
5368         smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5369
5370         spin_lock(&kvm_lock);
5371         list_for_each_entry(kvm, &vm_list, vm_list) {
5372                 kvm_for_each_vcpu(i, vcpu, kvm) {
5373                         if (vcpu->cpu != freq->cpu)
5374                                 continue;
5375                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5376                         if (vcpu->cpu != smp_processor_id())
5377                                 send_ipi = 1;
5378                 }
5379         }
5380         spin_unlock(&kvm_lock);
5381
5382         if (freq->old < freq->new && send_ipi) {
5383                 /*
5384                  * We upscale the frequency.  Must make the guest
5385                  * doesn't see old kvmclock values while running with
5386                  * the new frequency, otherwise we risk the guest sees
5387                  * time go backwards.
5388                  *
5389                  * In case we update the frequency for another cpu
5390                  * (which might be in guest context) send an interrupt
5391                  * to kick the cpu out of guest context.  Next time
5392                  * guest context is entered kvmclock will be updated,
5393                  * so the guest will not see stale values.
5394                  */
5395                 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5396         }
5397         return 0;
5398 }
5399
5400 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5401         .notifier_call  = kvmclock_cpufreq_notifier
5402 };
5403
5404 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5405                                         unsigned long action, void *hcpu)
5406 {
5407         unsigned int cpu = (unsigned long)hcpu;
5408
5409         switch (action) {
5410                 case CPU_ONLINE:
5411                 case CPU_DOWN_FAILED:
5412                         smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5413                         break;
5414                 case CPU_DOWN_PREPARE:
5415                         smp_call_function_single(cpu, tsc_bad, NULL, 1);
5416                         break;
5417         }
5418         return NOTIFY_OK;
5419 }
5420
5421 static struct notifier_block kvmclock_cpu_notifier_block = {
5422         .notifier_call  = kvmclock_cpu_notifier,
5423         .priority = -INT_MAX
5424 };
5425
5426 static void kvm_timer_init(void)
5427 {
5428         int cpu;
5429
5430         max_tsc_khz = tsc_khz;
5431
5432         cpu_notifier_register_begin();
5433         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5434 #ifdef CONFIG_CPU_FREQ
5435                 struct cpufreq_policy policy;
5436                 memset(&policy, 0, sizeof(policy));
5437                 cpu = get_cpu();
5438                 cpufreq_get_policy(&policy, cpu);
5439                 if (policy.cpuinfo.max_freq)
5440                         max_tsc_khz = policy.cpuinfo.max_freq;
5441                 put_cpu();
5442 #endif
5443                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5444                                           CPUFREQ_TRANSITION_NOTIFIER);
5445         }
5446         pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5447         for_each_online_cpu(cpu)
5448                 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5449
5450         __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5451         cpu_notifier_register_done();
5452
5453 }
5454
5455 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5456
5457 int kvm_is_in_guest(void)
5458 {
5459         return __this_cpu_read(current_vcpu) != NULL;
5460 }
5461
5462 static int kvm_is_user_mode(void)
5463 {
5464         int user_mode = 3;
5465
5466         if (__this_cpu_read(current_vcpu))
5467                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5468
5469         return user_mode != 0;
5470 }
5471
5472 static unsigned long kvm_get_guest_ip(void)
5473 {
5474         unsigned long ip = 0;
5475
5476         if (__this_cpu_read(current_vcpu))
5477                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5478
5479         return ip;
5480 }
5481
5482 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5483         .is_in_guest            = kvm_is_in_guest,
5484         .is_user_mode           = kvm_is_user_mode,
5485         .get_guest_ip           = kvm_get_guest_ip,
5486 };
5487
5488 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5489 {
5490         __this_cpu_write(current_vcpu, vcpu);
5491 }
5492 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5493
5494 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5495 {
5496         __this_cpu_write(current_vcpu, NULL);
5497 }
5498 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5499
5500 static void kvm_set_mmio_spte_mask(void)
5501 {
5502         u64 mask;
5503         int maxphyaddr = boot_cpu_data.x86_phys_bits;
5504
5505         /*
5506          * Set the reserved bits and the present bit of an paging-structure
5507          * entry to generate page fault with PFER.RSV = 1.
5508          */
5509          /* Mask the reserved physical address bits. */
5510         mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5511
5512         /* Bit 62 is always reserved for 32bit host. */
5513         mask |= 0x3ull << 62;
5514
5515         /* Set the present bit. */
5516         mask |= 1ull;
5517
5518 #ifdef CONFIG_X86_64
5519         /*
5520          * If reserved bit is not supported, clear the present bit to disable
5521          * mmio page fault.
5522          */
5523         if (maxphyaddr == 52)
5524                 mask &= ~1ull;
5525 #endif
5526
5527         kvm_mmu_set_mmio_spte_mask(mask);
5528 }
5529
5530 #ifdef CONFIG_X86_64
5531 static void pvclock_gtod_update_fn(struct work_struct *work)
5532 {
5533         struct kvm *kvm;
5534
5535         struct kvm_vcpu *vcpu;
5536         int i;
5537
5538         spin_lock(&kvm_lock);
5539         list_for_each_entry(kvm, &vm_list, vm_list)
5540                 kvm_for_each_vcpu(i, vcpu, kvm)
5541                         set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5542         atomic_set(&kvm_guest_has_master_clock, 0);
5543         spin_unlock(&kvm_lock);
5544 }
5545
5546 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5547
5548 /*
5549  * Notification about pvclock gtod data update.
5550  */
5551 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5552                                void *priv)
5553 {
5554         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5555         struct timekeeper *tk = priv;
5556
5557         update_pvclock_gtod(tk);
5558
5559         /* disable master clock if host does not trust, or does not
5560          * use, TSC clocksource
5561          */
5562         if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5563             atomic_read(&kvm_guest_has_master_clock) != 0)
5564                 queue_work(system_long_wq, &pvclock_gtod_work);
5565
5566         return 0;
5567 }
5568
5569 static struct notifier_block pvclock_gtod_notifier = {
5570         .notifier_call = pvclock_gtod_notify,
5571 };
5572 #endif
5573
5574 int kvm_arch_init(void *opaque)
5575 {
5576         int r;
5577         struct kvm_x86_ops *ops = opaque;
5578
5579         if (kvm_x86_ops) {
5580                 printk(KERN_ERR "kvm: already loaded the other module\n");
5581                 r = -EEXIST;
5582                 goto out;
5583         }
5584
5585         if (!ops->cpu_has_kvm_support()) {
5586                 printk(KERN_ERR "kvm: no hardware support\n");
5587                 r = -EOPNOTSUPP;
5588                 goto out;
5589         }
5590         if (ops->disabled_by_bios()) {
5591                 printk(KERN_ERR "kvm: disabled by bios\n");
5592                 r = -EOPNOTSUPP;
5593                 goto out;
5594         }
5595
5596         r = -ENOMEM;
5597         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5598         if (!shared_msrs) {
5599                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5600                 goto out;
5601         }
5602
5603         r = kvm_mmu_module_init();
5604         if (r)
5605                 goto out_free_percpu;
5606
5607         kvm_set_mmio_spte_mask();
5608
5609         kvm_x86_ops = ops;
5610         kvm_init_msr_list();
5611
5612         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5613                         PT_DIRTY_MASK, PT64_NX_MASK, 0);
5614
5615         kvm_timer_init();
5616
5617         perf_register_guest_info_callbacks(&kvm_guest_cbs);
5618
5619         if (cpu_has_xsave)
5620                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5621
5622         kvm_lapic_init();
5623 #ifdef CONFIG_X86_64
5624         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5625 #endif
5626
5627         return 0;
5628
5629 out_free_percpu:
5630         free_percpu(shared_msrs);
5631 out:
5632         return r;
5633 }
5634
5635 void kvm_arch_exit(void)
5636 {
5637         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5638
5639         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5640                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5641                                             CPUFREQ_TRANSITION_NOTIFIER);
5642         unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5643 #ifdef CONFIG_X86_64
5644         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5645 #endif
5646         kvm_x86_ops = NULL;
5647         kvm_mmu_module_exit();
5648         free_percpu(shared_msrs);
5649 }
5650
5651 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5652 {
5653         ++vcpu->stat.halt_exits;
5654         if (irqchip_in_kernel(vcpu->kvm)) {
5655                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5656                 return 1;
5657         } else {
5658                 vcpu->run->exit_reason = KVM_EXIT_HLT;
5659                 return 0;
5660         }
5661 }
5662 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5663
5664 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5665 {
5666         u64 param, ingpa, outgpa, ret;
5667         uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5668         bool fast, longmode;
5669         int cs_db, cs_l;
5670
5671         /*
5672          * hypercall generates UD from non zero cpl and real mode
5673          * per HYPER-V spec
5674          */
5675         if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5676                 kvm_queue_exception(vcpu, UD_VECTOR);
5677                 return 0;
5678         }
5679
5680         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5681         longmode = is_long_mode(vcpu) && cs_l == 1;
5682
5683         if (!longmode) {
5684                 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5685                         (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5686                 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5687                         (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5688                 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5689                         (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5690         }
5691 #ifdef CONFIG_X86_64
5692         else {
5693                 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5694                 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5695                 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5696         }
5697 #endif
5698
5699         code = param & 0xffff;
5700         fast = (param >> 16) & 0x1;
5701         rep_cnt = (param >> 32) & 0xfff;
5702         rep_idx = (param >> 48) & 0xfff;
5703
5704         trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5705
5706         switch (code) {
5707         case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5708                 kvm_vcpu_on_spin(vcpu);
5709                 break;
5710         default:
5711                 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5712                 break;
5713         }
5714
5715         ret = res | (((u64)rep_done & 0xfff) << 32);
5716         if (longmode) {
5717                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5718         } else {
5719                 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5720                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5721         }
5722
5723         return 1;
5724 }
5725
5726 /*
5727  * kvm_pv_kick_cpu_op:  Kick a vcpu.
5728  *
5729  * @apicid - apicid of vcpu to be kicked.
5730  */
5731 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5732 {
5733         struct kvm_lapic_irq lapic_irq;
5734
5735         lapic_irq.shorthand = 0;
5736         lapic_irq.dest_mode = 0;
5737         lapic_irq.dest_id = apicid;
5738
5739         lapic_irq.delivery_mode = APIC_DM_REMRD;
5740         kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5741 }
5742
5743 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5744 {
5745         unsigned long nr, a0, a1, a2, a3, ret;
5746         int r = 1;
5747
5748         if (kvm_hv_hypercall_enabled(vcpu->kvm))
5749                 return kvm_hv_hypercall(vcpu);
5750
5751         nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5752         a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5753         a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5754         a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5755         a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5756
5757         trace_kvm_hypercall(nr, a0, a1, a2, a3);
5758
5759         if (!is_long_mode(vcpu)) {
5760                 nr &= 0xFFFFFFFF;
5761                 a0 &= 0xFFFFFFFF;
5762                 a1 &= 0xFFFFFFFF;
5763                 a2 &= 0xFFFFFFFF;
5764                 a3 &= 0xFFFFFFFF;
5765         }
5766
5767         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5768                 ret = -KVM_EPERM;
5769                 goto out;
5770         }
5771
5772         switch (nr) {
5773         case KVM_HC_VAPIC_POLL_IRQ:
5774                 ret = 0;
5775                 break;
5776         case KVM_HC_KICK_CPU:
5777                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5778                 ret = 0;
5779                 break;
5780         default:
5781                 ret = -KVM_ENOSYS;
5782                 break;
5783         }
5784 out:
5785         kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5786         ++vcpu->stat.hypercalls;
5787         return r;
5788 }
5789 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5790
5791 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5792 {
5793         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5794         char instruction[3];
5795         unsigned long rip = kvm_rip_read(vcpu);
5796
5797         kvm_x86_ops->patch_hypercall(vcpu, instruction);
5798
5799         return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5800 }
5801
5802 /*
5803  * Check if userspace requested an interrupt window, and that the
5804  * interrupt window is open.
5805  *
5806  * No need to exit to userspace if we already have an interrupt queued.
5807  */
5808 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5809 {
5810         return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5811                 vcpu->run->request_interrupt_window &&
5812                 kvm_arch_interrupt_allowed(vcpu));
5813 }
5814
5815 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5816 {
5817         struct kvm_run *kvm_run = vcpu->run;
5818
5819         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5820         kvm_run->cr8 = kvm_get_cr8(vcpu);
5821         kvm_run->apic_base = kvm_get_apic_base(vcpu);
5822         if (irqchip_in_kernel(vcpu->kvm))
5823                 kvm_run->ready_for_interrupt_injection = 1;
5824         else
5825                 kvm_run->ready_for_interrupt_injection =
5826                         kvm_arch_interrupt_allowed(vcpu) &&
5827                         !kvm_cpu_has_interrupt(vcpu) &&
5828                         !kvm_event_needs_reinjection(vcpu);
5829 }
5830
5831 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5832 {
5833         int max_irr, tpr;
5834
5835         if (!kvm_x86_ops->update_cr8_intercept)
5836                 return;
5837
5838         if (!vcpu->arch.apic)
5839                 return;
5840
5841         if (!vcpu->arch.apic->vapic_addr)
5842                 max_irr = kvm_lapic_find_highest_irr(vcpu);
5843         else
5844                 max_irr = -1;
5845
5846         if (max_irr != -1)
5847                 max_irr >>= 4;
5848
5849         tpr = kvm_lapic_get_cr8(vcpu);
5850
5851         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5852 }
5853
5854 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5855 {
5856         int r;
5857
5858         /* try to reinject previous events if any */
5859         if (vcpu->arch.exception.pending) {
5860                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5861                                         vcpu->arch.exception.has_error_code,
5862                                         vcpu->arch.exception.error_code);
5863                 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5864                                           vcpu->arch.exception.has_error_code,
5865                                           vcpu->arch.exception.error_code,
5866                                           vcpu->arch.exception.reinject);
5867                 return 0;
5868         }
5869
5870         if (vcpu->arch.nmi_injected) {
5871                 kvm_x86_ops->set_nmi(vcpu);
5872                 return 0;
5873         }
5874
5875         if (vcpu->arch.interrupt.pending) {
5876                 kvm_x86_ops->set_irq(vcpu);
5877                 return 0;
5878         }
5879
5880         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5881                 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5882                 if (r != 0)
5883                         return r;
5884         }
5885
5886         /* try to inject new event if pending */
5887         if (vcpu->arch.nmi_pending) {
5888                 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5889                         --vcpu->arch.nmi_pending;
5890                         vcpu->arch.nmi_injected = true;
5891                         kvm_x86_ops->set_nmi(vcpu);
5892                 }
5893         } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5894                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5895                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5896                                             false);
5897                         kvm_x86_ops->set_irq(vcpu);
5898                 }
5899         }
5900         return 0;
5901 }
5902
5903 static void process_nmi(struct kvm_vcpu *vcpu)
5904 {
5905         unsigned limit = 2;
5906
5907         /*
5908          * x86 is limited to one NMI running, and one NMI pending after it.
5909          * If an NMI is already in progress, limit further NMIs to just one.
5910          * Otherwise, allow two (and we'll inject the first one immediately).
5911          */
5912         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5913                 limit = 1;
5914
5915         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5916         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5917         kvm_make_request(KVM_REQ_EVENT, vcpu);
5918 }
5919
5920 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5921 {
5922         u64 eoi_exit_bitmap[4];
5923         u32 tmr[8];
5924
5925         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5926                 return;
5927
5928         memset(eoi_exit_bitmap, 0, 32);
5929         memset(tmr, 0, 32);
5930
5931         kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5932         kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5933         kvm_apic_update_tmr(vcpu, tmr);
5934 }
5935
5936 /*
5937  * Returns 1 to let __vcpu_run() continue the guest execution loop without
5938  * exiting to the userspace.  Otherwise, the value will be returned to the
5939  * userspace.
5940  */
5941 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5942 {
5943         int r;
5944         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5945                 vcpu->run->request_interrupt_window;
5946         bool req_immediate_exit = false;
5947
5948         if (vcpu->requests) {
5949                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5950                         kvm_mmu_unload(vcpu);
5951                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5952                         __kvm_migrate_timers(vcpu);
5953                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5954                         kvm_gen_update_masterclock(vcpu->kvm);
5955                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5956                         kvm_gen_kvmclock_update(vcpu);
5957                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5958                         r = kvm_guest_time_update(vcpu);
5959                         if (unlikely(r))
5960                                 goto out;
5961                 }
5962                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5963                         kvm_mmu_sync_roots(vcpu);
5964                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5965                         kvm_x86_ops->tlb_flush(vcpu);
5966                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5967                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5968                         r = 0;
5969                         goto out;
5970                 }
5971                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5972                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5973                         r = 0;
5974                         goto out;
5975                 }
5976                 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5977                         vcpu->fpu_active = 0;
5978                         kvm_x86_ops->fpu_deactivate(vcpu);
5979                 }
5980                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5981                         /* Page is swapped out. Do synthetic halt */
5982                         vcpu->arch.apf.halted = true;
5983                         r = 1;
5984                         goto out;
5985                 }
5986                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5987                         record_steal_time(vcpu);
5988                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5989                         process_nmi(vcpu);
5990                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5991                         kvm_handle_pmu_event(vcpu);
5992                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5993                         kvm_deliver_pmi(vcpu);
5994                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5995                         vcpu_scan_ioapic(vcpu);
5996         }
5997
5998         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5999                 kvm_apic_accept_events(vcpu);
6000                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6001                         r = 1;
6002                         goto out;
6003                 }
6004
6005                 if (inject_pending_event(vcpu, req_int_win) != 0)
6006                         req_immediate_exit = true;
6007                 /* enable NMI/IRQ window open exits if needed */
6008                 else if (vcpu->arch.nmi_pending)
6009                         kvm_x86_ops->enable_nmi_window(vcpu);
6010                 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6011                         kvm_x86_ops->enable_irq_window(vcpu);
6012
6013                 if (kvm_lapic_enabled(vcpu)) {
6014                         /*
6015                          * Update architecture specific hints for APIC
6016                          * virtual interrupt delivery.
6017                          */
6018                         if (kvm_x86_ops->hwapic_irr_update)
6019                                 kvm_x86_ops->hwapic_irr_update(vcpu,
6020                                         kvm_lapic_find_highest_irr(vcpu));
6021                         update_cr8_intercept(vcpu);
6022                         kvm_lapic_sync_to_vapic(vcpu);
6023                 }
6024         }
6025
6026         r = kvm_mmu_reload(vcpu);
6027         if (unlikely(r)) {
6028                 goto cancel_injection;
6029         }
6030
6031         preempt_disable();
6032
6033         kvm_x86_ops->prepare_guest_switch(vcpu);
6034         if (vcpu->fpu_active)
6035                 kvm_load_guest_fpu(vcpu);
6036         kvm_load_guest_xcr0(vcpu);
6037
6038         vcpu->mode = IN_GUEST_MODE;
6039
6040         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6041
6042         /* We should set ->mode before check ->requests,
6043          * see the comment in make_all_cpus_request.
6044          */
6045         smp_mb__after_srcu_read_unlock();
6046
6047         local_irq_disable();
6048
6049         if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6050             || need_resched() || signal_pending(current)) {
6051                 vcpu->mode = OUTSIDE_GUEST_MODE;
6052                 smp_wmb();
6053                 local_irq_enable();
6054                 preempt_enable();
6055                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6056                 r = 1;
6057                 goto cancel_injection;
6058         }
6059
6060         if (req_immediate_exit)
6061                 smp_send_reschedule(vcpu->cpu);
6062
6063         kvm_guest_enter();
6064
6065         if (unlikely(vcpu->arch.switch_db_regs)) {
6066                 set_debugreg(0, 7);
6067                 set_debugreg(vcpu->arch.eff_db[0], 0);
6068                 set_debugreg(vcpu->arch.eff_db[1], 1);
6069                 set_debugreg(vcpu->arch.eff_db[2], 2);
6070                 set_debugreg(vcpu->arch.eff_db[3], 3);
6071                 set_debugreg(vcpu->arch.dr6, 6);
6072         }
6073
6074         trace_kvm_entry(vcpu->vcpu_id);
6075         kvm_x86_ops->run(vcpu);
6076
6077         /*
6078          * Do this here before restoring debug registers on the host.  And
6079          * since we do this before handling the vmexit, a DR access vmexit
6080          * can (a) read the correct value of the debug registers, (b) set
6081          * KVM_DEBUGREG_WONT_EXIT again.
6082          */
6083         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6084                 int i;
6085
6086                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6087                 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6088                 for (i = 0; i < KVM_NR_DB_REGS; i++)
6089                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6090         }
6091
6092         /*
6093          * If the guest has used debug registers, at least dr7
6094          * will be disabled while returning to the host.
6095          * If we don't have active breakpoints in the host, we don't
6096          * care about the messed up debug address registers. But if
6097          * we have some of them active, restore the old state.
6098          */
6099         if (hw_breakpoint_active())
6100                 hw_breakpoint_restore();
6101
6102         vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6103                                                            native_read_tsc());
6104
6105         vcpu->mode = OUTSIDE_GUEST_MODE;
6106         smp_wmb();
6107
6108         /* Interrupt is enabled by handle_external_intr() */
6109         kvm_x86_ops->handle_external_intr(vcpu);
6110
6111         ++vcpu->stat.exits;
6112
6113         /*
6114          * We must have an instruction between local_irq_enable() and
6115          * kvm_guest_exit(), so the timer interrupt isn't delayed by
6116          * the interrupt shadow.  The stat.exits increment will do nicely.
6117          * But we need to prevent reordering, hence this barrier():
6118          */
6119         barrier();
6120
6121         kvm_guest_exit();
6122
6123         preempt_enable();
6124
6125         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6126
6127         /*
6128          * Profile KVM exit RIPs:
6129          */
6130         if (unlikely(prof_on == KVM_PROFILING)) {
6131                 unsigned long rip = kvm_rip_read(vcpu);
6132                 profile_hit(KVM_PROFILING, (void *)rip);
6133         }
6134
6135         if (unlikely(vcpu->arch.tsc_always_catchup))
6136                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6137
6138         if (vcpu->arch.apic_attention)
6139                 kvm_lapic_sync_from_vapic(vcpu);
6140
6141         r = kvm_x86_ops->handle_exit(vcpu);
6142         return r;
6143
6144 cancel_injection:
6145         kvm_x86_ops->cancel_injection(vcpu);
6146         if (unlikely(vcpu->arch.apic_attention))
6147                 kvm_lapic_sync_from_vapic(vcpu);
6148 out:
6149         return r;
6150 }
6151
6152
6153 static int __vcpu_run(struct kvm_vcpu *vcpu)
6154 {
6155         int r;
6156         struct kvm *kvm = vcpu->kvm;
6157
6158         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6159
6160         r = 1;
6161         while (r > 0) {
6162                 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6163                     !vcpu->arch.apf.halted)
6164                         r = vcpu_enter_guest(vcpu);
6165                 else {
6166                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6167                         kvm_vcpu_block(vcpu);
6168                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6169                         if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6170                                 kvm_apic_accept_events(vcpu);
6171                                 switch(vcpu->arch.mp_state) {
6172                                 case KVM_MP_STATE_HALTED:
6173                                         vcpu->arch.pv.pv_unhalted = false;
6174                                         vcpu->arch.mp_state =
6175                                                 KVM_MP_STATE_RUNNABLE;
6176                                 case KVM_MP_STATE_RUNNABLE:
6177                                         vcpu->arch.apf.halted = false;
6178                                         break;
6179                                 case KVM_MP_STATE_INIT_RECEIVED:
6180                                         break;
6181                                 default:
6182                                         r = -EINTR;
6183                                         break;
6184                                 }
6185                         }
6186                 }
6187
6188                 if (r <= 0)
6189                         break;
6190
6191                 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6192                 if (kvm_cpu_has_pending_timer(vcpu))
6193                         kvm_inject_pending_timer_irqs(vcpu);
6194
6195                 if (dm_request_for_irq_injection(vcpu)) {
6196                         r = -EINTR;
6197                         vcpu->run->exit_reason = KVM_EXIT_INTR;
6198                         ++vcpu->stat.request_irq_exits;
6199                 }
6200
6201                 kvm_check_async_pf_completion(vcpu);
6202
6203                 if (signal_pending(current)) {
6204                         r = -EINTR;
6205                         vcpu->run->exit_reason = KVM_EXIT_INTR;
6206                         ++vcpu->stat.signal_exits;
6207                 }
6208                 if (need_resched()) {
6209                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6210                         cond_resched();
6211                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6212                 }
6213         }
6214
6215         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6216
6217         return r;
6218 }
6219
6220 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6221 {
6222         int r;
6223         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6224         r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6225         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6226         if (r != EMULATE_DONE)
6227                 return 0;
6228         return 1;
6229 }
6230
6231 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6232 {
6233         BUG_ON(!vcpu->arch.pio.count);
6234
6235         return complete_emulated_io(vcpu);
6236 }
6237
6238 /*
6239  * Implements the following, as a state machine:
6240  *
6241  * read:
6242  *   for each fragment
6243  *     for each mmio piece in the fragment
6244  *       write gpa, len
6245  *       exit
6246  *       copy data
6247  *   execute insn
6248  *
6249  * write:
6250  *   for each fragment
6251  *     for each mmio piece in the fragment
6252  *       write gpa, len
6253  *       copy data
6254  *       exit
6255  */
6256 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6257 {
6258         struct kvm_run *run = vcpu->run;
6259         struct kvm_mmio_fragment *frag;
6260         unsigned len;
6261
6262         BUG_ON(!vcpu->mmio_needed);
6263
6264         /* Complete previous fragment */
6265         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6266         len = min(8u, frag->len);
6267         if (!vcpu->mmio_is_write)
6268                 memcpy(frag->data, run->mmio.data, len);
6269
6270         if (frag->len <= 8) {
6271                 /* Switch to the next fragment. */
6272                 frag++;
6273                 vcpu->mmio_cur_fragment++;
6274         } else {
6275                 /* Go forward to the next mmio piece. */
6276                 frag->data += len;
6277                 frag->gpa += len;
6278                 frag->len -= len;
6279         }
6280
6281         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6282                 vcpu->mmio_needed = 0;
6283
6284                 /* FIXME: return into emulator if single-stepping.  */
6285                 if (vcpu->mmio_is_write)
6286                         return 1;
6287                 vcpu->mmio_read_completed = 1;
6288                 return complete_emulated_io(vcpu);
6289         }
6290
6291         run->exit_reason = KVM_EXIT_MMIO;
6292         run->mmio.phys_addr = frag->gpa;
6293         if (vcpu->mmio_is_write)
6294                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6295         run->mmio.len = min(8u, frag->len);
6296         run->mmio.is_write = vcpu->mmio_is_write;
6297         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6298         return 0;
6299 }
6300
6301
6302 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6303 {
6304         int r;
6305         sigset_t sigsaved;
6306
6307         if (!tsk_used_math(current) && init_fpu(current))
6308                 return -ENOMEM;
6309
6310         if (vcpu->sigset_active)
6311                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6312
6313         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6314                 kvm_vcpu_block(vcpu);
6315                 kvm_apic_accept_events(vcpu);
6316                 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6317                 r = -EAGAIN;
6318                 goto out;
6319         }
6320
6321         /* re-sync apic's tpr */
6322         if (!irqchip_in_kernel(vcpu->kvm)) {
6323                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6324                         r = -EINVAL;
6325                         goto out;
6326                 }
6327         }
6328
6329         if (unlikely(vcpu->arch.complete_userspace_io)) {
6330                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6331                 vcpu->arch.complete_userspace_io = NULL;
6332                 r = cui(vcpu);
6333                 if (r <= 0)
6334                         goto out;
6335         } else
6336                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6337
6338         r = __vcpu_run(vcpu);
6339
6340 out:
6341         post_kvm_run_save(vcpu);
6342         if (vcpu->sigset_active)
6343                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6344
6345         return r;
6346 }
6347
6348 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6349 {
6350         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6351                 /*
6352                  * We are here if userspace calls get_regs() in the middle of
6353                  * instruction emulation. Registers state needs to be copied
6354                  * back from emulation context to vcpu. Userspace shouldn't do
6355                  * that usually, but some bad designed PV devices (vmware
6356                  * backdoor interface) need this to work
6357                  */
6358                 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6359                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6360         }
6361         regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6362         regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6363         regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6364         regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6365         regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6366         regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6367         regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6368         regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6369 #ifdef CONFIG_X86_64
6370         regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6371         regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6372         regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6373         regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6374         regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6375         regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6376         regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6377         regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6378 #endif
6379
6380         regs->rip = kvm_rip_read(vcpu);
6381         regs->rflags = kvm_get_rflags(vcpu);
6382
6383         return 0;
6384 }
6385
6386 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6387 {
6388         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6389         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6390
6391         kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6392         kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6393         kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6394         kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6395         kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6396         kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6397         kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6398         kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6399 #ifdef CONFIG_X86_64
6400         kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6401         kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6402         kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6403         kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6404         kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6405         kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6406         kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6407         kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6408 #endif
6409
6410         kvm_rip_write(vcpu, regs->rip);
6411         kvm_set_rflags(vcpu, regs->rflags);
6412
6413         vcpu->arch.exception.pending = false;
6414
6415         kvm_make_request(KVM_REQ_EVENT, vcpu);
6416
6417         return 0;
6418 }
6419
6420 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6421 {
6422         struct kvm_segment cs;
6423
6424         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6425         *db = cs.db;
6426         *l = cs.l;
6427 }
6428 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6429
6430 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6431                                   struct kvm_sregs *sregs)
6432 {
6433         struct desc_ptr dt;
6434
6435         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6436         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6437         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6438         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6439         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6440         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6441
6442         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6443         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6444
6445         kvm_x86_ops->get_idt(vcpu, &dt);
6446         sregs->idt.limit = dt.size;
6447         sregs->idt.base = dt.address;
6448         kvm_x86_ops->get_gdt(vcpu, &dt);
6449         sregs->gdt.limit = dt.size;
6450         sregs->gdt.base = dt.address;
6451
6452         sregs->cr0 = kvm_read_cr0(vcpu);
6453         sregs->cr2 = vcpu->arch.cr2;
6454         sregs->cr3 = kvm_read_cr3(vcpu);
6455         sregs->cr4 = kvm_read_cr4(vcpu);
6456         sregs->cr8 = kvm_get_cr8(vcpu);
6457         sregs->efer = vcpu->arch.efer;
6458         sregs->apic_base = kvm_get_apic_base(vcpu);
6459
6460         memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6461
6462         if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6463                 set_bit(vcpu->arch.interrupt.nr,
6464                         (unsigned long *)sregs->interrupt_bitmap);
6465
6466         return 0;
6467 }
6468
6469 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6470                                     struct kvm_mp_state *mp_state)
6471 {
6472         kvm_apic_accept_events(vcpu);
6473         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6474                                         vcpu->arch.pv.pv_unhalted)
6475                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6476         else
6477                 mp_state->mp_state = vcpu->arch.mp_state;
6478
6479         return 0;
6480 }
6481
6482 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6483                                     struct kvm_mp_state *mp_state)
6484 {
6485         if (!kvm_vcpu_has_lapic(vcpu) &&
6486             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6487                 return -EINVAL;
6488
6489         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6490                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6491                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6492         } else
6493                 vcpu->arch.mp_state = mp_state->mp_state;
6494         kvm_make_request(KVM_REQ_EVENT, vcpu);
6495         return 0;
6496 }
6497
6498 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6499                     int reason, bool has_error_code, u32 error_code)
6500 {
6501         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6502         int ret;
6503
6504         init_emulate_ctxt(vcpu);
6505
6506         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6507                                    has_error_code, error_code);
6508
6509         if (ret)
6510                 return EMULATE_FAIL;
6511
6512         kvm_rip_write(vcpu, ctxt->eip);
6513         kvm_set_rflags(vcpu, ctxt->eflags);
6514         kvm_make_request(KVM_REQ_EVENT, vcpu);
6515         return EMULATE_DONE;
6516 }
6517 EXPORT_SYMBOL_GPL(kvm_task_switch);
6518
6519 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6520                                   struct kvm_sregs *sregs)
6521 {
6522         struct msr_data apic_base_msr;
6523         int mmu_reset_needed = 0;
6524         int pending_vec, max_bits, idx;
6525         struct desc_ptr dt;
6526
6527         if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6528                 return -EINVAL;
6529
6530         dt.size = sregs->idt.limit;
6531         dt.address = sregs->idt.base;
6532         kvm_x86_ops->set_idt(vcpu, &dt);
6533         dt.size = sregs->gdt.limit;
6534         dt.address = sregs->gdt.base;
6535         kvm_x86_ops->set_gdt(vcpu, &dt);
6536
6537         vcpu->arch.cr2 = sregs->cr2;
6538         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6539         vcpu->arch.cr3 = sregs->cr3;
6540         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6541
6542         kvm_set_cr8(vcpu, sregs->cr8);
6543
6544         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6545         kvm_x86_ops->set_efer(vcpu, sregs->efer);
6546         apic_base_msr.data = sregs->apic_base;
6547         apic_base_msr.host_initiated = true;
6548         kvm_set_apic_base(vcpu, &apic_base_msr);
6549
6550         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6551         kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6552         vcpu->arch.cr0 = sregs->cr0;
6553
6554         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6555         kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6556         if (sregs->cr4 & X86_CR4_OSXSAVE)
6557                 kvm_update_cpuid(vcpu);
6558
6559         idx = srcu_read_lock(&vcpu->kvm->srcu);
6560         if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6561                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6562                 mmu_reset_needed = 1;
6563         }
6564         srcu_read_unlock(&vcpu->kvm->srcu, idx);
6565
6566         if (mmu_reset_needed)
6567                 kvm_mmu_reset_context(vcpu);
6568
6569         max_bits = KVM_NR_INTERRUPTS;
6570         pending_vec = find_first_bit(
6571                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6572         if (pending_vec < max_bits) {
6573                 kvm_queue_interrupt(vcpu, pending_vec, false);
6574                 pr_debug("Set back pending irq %d\n", pending_vec);
6575         }
6576
6577         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6578         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6579         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6580         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6581         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6582         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6583
6584         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6585         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6586
6587         update_cr8_intercept(vcpu);
6588
6589         /* Older userspace won't unhalt the vcpu on reset. */
6590         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6591             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6592             !is_protmode(vcpu))
6593                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6594
6595         kvm_make_request(KVM_REQ_EVENT, vcpu);
6596
6597         return 0;
6598 }
6599
6600 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6601                                         struct kvm_guest_debug *dbg)
6602 {
6603         unsigned long rflags;
6604         int i, r;
6605
6606         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6607                 r = -EBUSY;
6608                 if (vcpu->arch.exception.pending)
6609                         goto out;
6610                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6611                         kvm_queue_exception(vcpu, DB_VECTOR);
6612                 else
6613                         kvm_queue_exception(vcpu, BP_VECTOR);
6614         }
6615
6616         /*
6617          * Read rflags as long as potentially injected trace flags are still
6618          * filtered out.
6619          */
6620         rflags = kvm_get_rflags(vcpu);
6621
6622         vcpu->guest_debug = dbg->control;
6623         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6624                 vcpu->guest_debug = 0;
6625
6626         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6627                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6628                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6629                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6630         } else {
6631                 for (i = 0; i < KVM_NR_DB_REGS; i++)
6632                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6633         }
6634         kvm_update_dr7(vcpu);
6635
6636         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6637                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6638                         get_segment_base(vcpu, VCPU_SREG_CS);
6639
6640         /*
6641          * Trigger an rflags update that will inject or remove the trace
6642          * flags.
6643          */
6644         kvm_set_rflags(vcpu, rflags);
6645
6646         kvm_x86_ops->update_db_bp_intercept(vcpu);
6647
6648         r = 0;
6649
6650 out:
6651
6652         return r;
6653 }
6654
6655 /*
6656  * Translate a guest virtual address to a guest physical address.
6657  */
6658 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6659                                     struct kvm_translation *tr)
6660 {
6661         unsigned long vaddr = tr->linear_address;
6662         gpa_t gpa;
6663         int idx;
6664
6665         idx = srcu_read_lock(&vcpu->kvm->srcu);
6666         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6667         srcu_read_unlock(&vcpu->kvm->srcu, idx);
6668         tr->physical_address = gpa;
6669         tr->valid = gpa != UNMAPPED_GVA;
6670         tr->writeable = 1;
6671         tr->usermode = 0;
6672
6673         return 0;
6674 }
6675
6676 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6677 {
6678         struct i387_fxsave_struct *fxsave =
6679                         &vcpu->arch.guest_fpu.state->fxsave;
6680
6681         memcpy(fpu->fpr, fxsave->st_space, 128);
6682         fpu->fcw = fxsave->cwd;
6683         fpu->fsw = fxsave->swd;
6684         fpu->ftwx = fxsave->twd;
6685         fpu->last_opcode = fxsave->fop;
6686         fpu->last_ip = fxsave->rip;
6687         fpu->last_dp = fxsave->rdp;
6688         memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6689
6690         return 0;
6691 }
6692
6693 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6694 {
6695         struct i387_fxsave_struct *fxsave =
6696                         &vcpu->arch.guest_fpu.state->fxsave;
6697
6698         memcpy(fxsave->st_space, fpu->fpr, 128);
6699         fxsave->cwd = fpu->fcw;
6700         fxsave->swd = fpu->fsw;
6701         fxsave->twd = fpu->ftwx;
6702         fxsave->fop = fpu->last_opcode;
6703         fxsave->rip = fpu->last_ip;
6704         fxsave->rdp = fpu->last_dp;
6705         memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6706
6707         return 0;
6708 }
6709
6710 int fx_init(struct kvm_vcpu *vcpu)
6711 {
6712         int err;
6713
6714         err = fpu_alloc(&vcpu->arch.guest_fpu);
6715         if (err)
6716                 return err;
6717
6718         fpu_finit(&vcpu->arch.guest_fpu);
6719
6720         /*
6721          * Ensure guest xcr0 is valid for loading
6722          */
6723         vcpu->arch.xcr0 = XSTATE_FP;
6724
6725         vcpu->arch.cr0 |= X86_CR0_ET;
6726
6727         return 0;
6728 }
6729 EXPORT_SYMBOL_GPL(fx_init);
6730
6731 static void fx_free(struct kvm_vcpu *vcpu)
6732 {
6733         fpu_free(&vcpu->arch.guest_fpu);
6734 }
6735
6736 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6737 {
6738         if (vcpu->guest_fpu_loaded)
6739                 return;
6740
6741         /*
6742          * Restore all possible states in the guest,
6743          * and assume host would use all available bits.
6744          * Guest xcr0 would be loaded later.
6745          */
6746         kvm_put_guest_xcr0(vcpu);
6747         vcpu->guest_fpu_loaded = 1;
6748         __kernel_fpu_begin();
6749         fpu_restore_checking(&vcpu->arch.guest_fpu);
6750         trace_kvm_fpu(1);
6751 }
6752
6753 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6754 {
6755         kvm_put_guest_xcr0(vcpu);
6756
6757         if (!vcpu->guest_fpu_loaded)
6758                 return;
6759
6760         vcpu->guest_fpu_loaded = 0;
6761         fpu_save_init(&vcpu->arch.guest_fpu);
6762         __kernel_fpu_end();
6763         ++vcpu->stat.fpu_reload;
6764         kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6765         trace_kvm_fpu(0);
6766 }
6767
6768 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6769 {
6770         kvmclock_reset(vcpu);
6771
6772         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6773         fx_free(vcpu);
6774         kvm_x86_ops->vcpu_free(vcpu);
6775 }
6776
6777 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6778                                                 unsigned int id)
6779 {
6780         if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6781                 printk_once(KERN_WARNING
6782                 "kvm: SMP vm created on host with unstable TSC; "
6783                 "guest TSC will not be reliable\n");
6784         return kvm_x86_ops->vcpu_create(kvm, id);
6785 }
6786
6787 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6788 {
6789         int r;
6790
6791         vcpu->arch.mtrr_state.have_fixed = 1;
6792         r = vcpu_load(vcpu);
6793         if (r)
6794                 return r;
6795         kvm_vcpu_reset(vcpu);
6796         kvm_mmu_setup(vcpu);
6797         vcpu_put(vcpu);
6798
6799         return r;
6800 }
6801
6802 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6803 {
6804         int r;
6805         struct msr_data msr;
6806         struct kvm *kvm = vcpu->kvm;
6807
6808         r = vcpu_load(vcpu);
6809         if (r)
6810                 return r;
6811         msr.data = 0x0;
6812         msr.index = MSR_IA32_TSC;
6813         msr.host_initiated = true;
6814         kvm_write_tsc(vcpu, &msr);
6815         vcpu_put(vcpu);
6816
6817         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6818                                         KVMCLOCK_SYNC_PERIOD);
6819
6820         return r;
6821 }
6822
6823 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6824 {
6825         int r;
6826         vcpu->arch.apf.msr_val = 0;
6827
6828         r = vcpu_load(vcpu);
6829         BUG_ON(r);
6830         kvm_mmu_unload(vcpu);
6831         vcpu_put(vcpu);
6832
6833         fx_free(vcpu);
6834         kvm_x86_ops->vcpu_free(vcpu);
6835 }
6836
6837 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6838 {
6839         atomic_set(&vcpu->arch.nmi_queued, 0);
6840         vcpu->arch.nmi_pending = 0;
6841         vcpu->arch.nmi_injected = false;
6842
6843         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6844         vcpu->arch.dr6 = DR6_FIXED_1;
6845         kvm_update_dr6(vcpu);
6846         vcpu->arch.dr7 = DR7_FIXED_1;
6847         kvm_update_dr7(vcpu);
6848
6849         kvm_make_request(KVM_REQ_EVENT, vcpu);
6850         vcpu->arch.apf.msr_val = 0;
6851         vcpu->arch.st.msr_val = 0;
6852
6853         kvmclock_reset(vcpu);
6854
6855         kvm_clear_async_pf_completion_queue(vcpu);
6856         kvm_async_pf_hash_reset(vcpu);
6857         vcpu->arch.apf.halted = false;
6858
6859         kvm_pmu_reset(vcpu);
6860
6861         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6862         vcpu->arch.regs_avail = ~0;
6863         vcpu->arch.regs_dirty = ~0;
6864
6865         kvm_x86_ops->vcpu_reset(vcpu);
6866 }
6867
6868 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6869 {
6870         struct kvm_segment cs;
6871
6872         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6873         cs.selector = vector << 8;
6874         cs.base = vector << 12;
6875         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6876         kvm_rip_write(vcpu, 0);
6877 }
6878
6879 int kvm_arch_hardware_enable(void *garbage)
6880 {
6881         struct kvm *kvm;
6882         struct kvm_vcpu *vcpu;
6883         int i;
6884         int ret;
6885         u64 local_tsc;
6886         u64 max_tsc = 0;
6887         bool stable, backwards_tsc = false;
6888
6889         kvm_shared_msr_cpu_online();
6890         ret = kvm_x86_ops->hardware_enable(garbage);
6891         if (ret != 0)
6892                 return ret;
6893
6894         local_tsc = native_read_tsc();
6895         stable = !check_tsc_unstable();
6896         list_for_each_entry(kvm, &vm_list, vm_list) {
6897                 kvm_for_each_vcpu(i, vcpu, kvm) {
6898                         if (!stable && vcpu->cpu == smp_processor_id())
6899                                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6900                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6901                                 backwards_tsc = true;
6902                                 if (vcpu->arch.last_host_tsc > max_tsc)
6903                                         max_tsc = vcpu->arch.last_host_tsc;
6904                         }
6905                 }
6906         }
6907
6908         /*
6909          * Sometimes, even reliable TSCs go backwards.  This happens on
6910          * platforms that reset TSC during suspend or hibernate actions, but
6911          * maintain synchronization.  We must compensate.  Fortunately, we can
6912          * detect that condition here, which happens early in CPU bringup,
6913          * before any KVM threads can be running.  Unfortunately, we can't
6914          * bring the TSCs fully up to date with real time, as we aren't yet far
6915          * enough into CPU bringup that we know how much real time has actually
6916          * elapsed; our helper function, get_kernel_ns() will be using boot
6917          * variables that haven't been updated yet.
6918          *
6919          * So we simply find the maximum observed TSC above, then record the
6920          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
6921          * the adjustment will be applied.  Note that we accumulate
6922          * adjustments, in case multiple suspend cycles happen before some VCPU
6923          * gets a chance to run again.  In the event that no KVM threads get a
6924          * chance to run, we will miss the entire elapsed period, as we'll have
6925          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6926          * loose cycle time.  This isn't too big a deal, since the loss will be
6927          * uniform across all VCPUs (not to mention the scenario is extremely
6928          * unlikely). It is possible that a second hibernate recovery happens
6929          * much faster than a first, causing the observed TSC here to be
6930          * smaller; this would require additional padding adjustment, which is
6931          * why we set last_host_tsc to the local tsc observed here.
6932          *
6933          * N.B. - this code below runs only on platforms with reliable TSC,
6934          * as that is the only way backwards_tsc is set above.  Also note
6935          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6936          * have the same delta_cyc adjustment applied if backwards_tsc
6937          * is detected.  Note further, this adjustment is only done once,
6938          * as we reset last_host_tsc on all VCPUs to stop this from being
6939          * called multiple times (one for each physical CPU bringup).
6940          *
6941          * Platforms with unreliable TSCs don't have to deal with this, they
6942          * will be compensated by the logic in vcpu_load, which sets the TSC to
6943          * catchup mode.  This will catchup all VCPUs to real time, but cannot
6944          * guarantee that they stay in perfect synchronization.
6945          */
6946         if (backwards_tsc) {
6947                 u64 delta_cyc = max_tsc - local_tsc;
6948                 list_for_each_entry(kvm, &vm_list, vm_list) {
6949                         kvm_for_each_vcpu(i, vcpu, kvm) {
6950                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6951                                 vcpu->arch.last_host_tsc = local_tsc;
6952                                 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6953                                         &vcpu->requests);
6954                         }
6955
6956                         /*
6957                          * We have to disable TSC offset matching.. if you were
6958                          * booting a VM while issuing an S4 host suspend....
6959                          * you may have some problem.  Solving this issue is
6960                          * left as an exercise to the reader.
6961                          */
6962                         kvm->arch.last_tsc_nsec = 0;
6963                         kvm->arch.last_tsc_write = 0;
6964                 }
6965
6966         }
6967         return 0;
6968 }
6969
6970 void kvm_arch_hardware_disable(void *garbage)
6971 {
6972         kvm_x86_ops->hardware_disable(garbage);
6973         drop_user_return_notifiers(garbage);
6974 }
6975
6976 int kvm_arch_hardware_setup(void)
6977 {
6978         return kvm_x86_ops->hardware_setup();
6979 }
6980
6981 void kvm_arch_hardware_unsetup(void)
6982 {
6983         kvm_x86_ops->hardware_unsetup();
6984 }
6985
6986 void kvm_arch_check_processor_compat(void *rtn)
6987 {
6988         kvm_x86_ops->check_processor_compatibility(rtn);
6989 }
6990
6991 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6992 {
6993         return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6994 }
6995
6996 struct static_key kvm_no_apic_vcpu __read_mostly;
6997
6998 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6999 {
7000         struct page *page;
7001         struct kvm *kvm;
7002         int r;
7003
7004         BUG_ON(vcpu->kvm == NULL);
7005         kvm = vcpu->kvm;
7006
7007         vcpu->arch.pv.pv_unhalted = false;
7008         vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7009         if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
7010                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7011         else
7012                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7013
7014         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7015         if (!page) {
7016                 r = -ENOMEM;
7017                 goto fail;
7018         }
7019         vcpu->arch.pio_data = page_address(page);
7020
7021         kvm_set_tsc_khz(vcpu, max_tsc_khz);
7022
7023         r = kvm_mmu_create(vcpu);
7024         if (r < 0)
7025                 goto fail_free_pio_data;
7026
7027         if (irqchip_in_kernel(kvm)) {
7028                 r = kvm_create_lapic(vcpu);
7029                 if (r < 0)
7030                         goto fail_mmu_destroy;
7031         } else
7032                 static_key_slow_inc(&kvm_no_apic_vcpu);
7033
7034         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7035                                        GFP_KERNEL);
7036         if (!vcpu->arch.mce_banks) {
7037                 r = -ENOMEM;
7038                 goto fail_free_lapic;
7039         }
7040         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7041
7042         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7043                 r = -ENOMEM;
7044                 goto fail_free_mce_banks;
7045         }
7046
7047         r = fx_init(vcpu);
7048         if (r)
7049                 goto fail_free_wbinvd_dirty_mask;
7050
7051         vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7052         vcpu->arch.pv_time_enabled = false;
7053
7054         vcpu->arch.guest_supported_xcr0 = 0;
7055         vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7056
7057         kvm_async_pf_hash_reset(vcpu);
7058         kvm_pmu_init(vcpu);
7059
7060         return 0;
7061 fail_free_wbinvd_dirty_mask:
7062         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7063 fail_free_mce_banks:
7064         kfree(vcpu->arch.mce_banks);
7065 fail_free_lapic:
7066         kvm_free_lapic(vcpu);
7067 fail_mmu_destroy:
7068         kvm_mmu_destroy(vcpu);
7069 fail_free_pio_data:
7070         free_page((unsigned long)vcpu->arch.pio_data);
7071 fail:
7072         return r;
7073 }
7074
7075 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7076 {
7077         int idx;
7078
7079         kvm_pmu_destroy(vcpu);
7080         kfree(vcpu->arch.mce_banks);
7081         kvm_free_lapic(vcpu);
7082         idx = srcu_read_lock(&vcpu->kvm->srcu);
7083         kvm_mmu_destroy(vcpu);
7084         srcu_read_unlock(&vcpu->kvm->srcu, idx);
7085         free_page((unsigned long)vcpu->arch.pio_data);
7086         if (!irqchip_in_kernel(vcpu->kvm))
7087                 static_key_slow_dec(&kvm_no_apic_vcpu);
7088 }
7089
7090 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7091 {
7092         if (type)
7093                 return -EINVAL;
7094
7095         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7096         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7097         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7098         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7099
7100         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7101         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7102         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7103         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7104                 &kvm->arch.irq_sources_bitmap);
7105
7106         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7107         mutex_init(&kvm->arch.apic_map_lock);
7108         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7109
7110         pvclock_update_vm_gtod_copy(kvm);
7111
7112         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7113         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7114
7115         return 0;
7116 }
7117
7118 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7119 {
7120         int r;
7121         r = vcpu_load(vcpu);
7122         BUG_ON(r);
7123         kvm_mmu_unload(vcpu);
7124         vcpu_put(vcpu);
7125 }
7126
7127 static void kvm_free_vcpus(struct kvm *kvm)
7128 {
7129         unsigned int i;
7130         struct kvm_vcpu *vcpu;
7131
7132         /*
7133          * Unpin any mmu pages first.
7134          */
7135         kvm_for_each_vcpu(i, vcpu, kvm) {
7136                 kvm_clear_async_pf_completion_queue(vcpu);
7137                 kvm_unload_vcpu_mmu(vcpu);
7138         }
7139         kvm_for_each_vcpu(i, vcpu, kvm)
7140                 kvm_arch_vcpu_free(vcpu);
7141
7142         mutex_lock(&kvm->lock);
7143         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7144                 kvm->vcpus[i] = NULL;
7145
7146         atomic_set(&kvm->online_vcpus, 0);
7147         mutex_unlock(&kvm->lock);
7148 }
7149
7150 void kvm_arch_sync_events(struct kvm *kvm)
7151 {
7152         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7153         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7154         kvm_free_all_assigned_devices(kvm);
7155         kvm_free_pit(kvm);
7156 }
7157
7158 void kvm_arch_destroy_vm(struct kvm *kvm)
7159 {
7160         if (current->mm == kvm->mm) {
7161                 /*
7162                  * Free memory regions allocated on behalf of userspace,
7163                  * unless the the memory map has changed due to process exit
7164                  * or fd copying.
7165                  */
7166                 struct kvm_userspace_memory_region mem;
7167                 memset(&mem, 0, sizeof(mem));
7168                 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7169                 kvm_set_memory_region(kvm, &mem);
7170
7171                 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7172                 kvm_set_memory_region(kvm, &mem);
7173
7174                 mem.slot = TSS_PRIVATE_MEMSLOT;
7175                 kvm_set_memory_region(kvm, &mem);
7176         }
7177         kvm_iommu_unmap_guest(kvm);
7178         kfree(kvm->arch.vpic);
7179         kfree(kvm->arch.vioapic);
7180         kvm_free_vcpus(kvm);
7181         if (kvm->arch.apic_access_page)
7182                 put_page(kvm->arch.apic_access_page);
7183         if (kvm->arch.ept_identity_pagetable)
7184                 put_page(kvm->arch.ept_identity_pagetable);
7185         kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7186 }
7187
7188 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7189                            struct kvm_memory_slot *dont)
7190 {
7191         int i;
7192
7193         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7194                 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7195                         kvm_kvfree(free->arch.rmap[i]);
7196                         free->arch.rmap[i] = NULL;
7197                 }
7198                 if (i == 0)
7199                         continue;
7200
7201                 if (!dont || free->arch.lpage_info[i - 1] !=
7202                              dont->arch.lpage_info[i - 1]) {
7203                         kvm_kvfree(free->arch.lpage_info[i - 1]);
7204                         free->arch.lpage_info[i - 1] = NULL;
7205                 }
7206         }
7207 }
7208
7209 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7210                             unsigned long npages)
7211 {
7212         int i;
7213
7214         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7215                 unsigned long ugfn;
7216                 int lpages;
7217                 int level = i + 1;
7218
7219                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7220                                       slot->base_gfn, level) + 1;
7221
7222                 slot->arch.rmap[i] =
7223                         kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7224                 if (!slot->arch.rmap[i])
7225                         goto out_free;
7226                 if (i == 0)
7227                         continue;
7228
7229                 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7230                                         sizeof(*slot->arch.lpage_info[i - 1]));
7231                 if (!slot->arch.lpage_info[i - 1])
7232                         goto out_free;
7233
7234                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7235                         slot->arch.lpage_info[i - 1][0].write_count = 1;
7236                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7237                         slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7238                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7239                 /*
7240                  * If the gfn and userspace address are not aligned wrt each
7241                  * other, or if explicitly asked to, disable large page
7242                  * support for this slot
7243                  */
7244                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7245                     !kvm_largepages_enabled()) {
7246                         unsigned long j;
7247
7248                         for (j = 0; j < lpages; ++j)
7249                                 slot->arch.lpage_info[i - 1][j].write_count = 1;
7250                 }
7251         }
7252
7253         return 0;
7254
7255 out_free:
7256         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7257                 kvm_kvfree(slot->arch.rmap[i]);
7258                 slot->arch.rmap[i] = NULL;
7259                 if (i == 0)
7260                         continue;
7261
7262                 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7263                 slot->arch.lpage_info[i - 1] = NULL;
7264         }
7265         return -ENOMEM;
7266 }
7267
7268 void kvm_arch_memslots_updated(struct kvm *kvm)
7269 {
7270         /*
7271          * memslots->generation has been incremented.
7272          * mmio generation may have reached its maximum value.
7273          */
7274         kvm_mmu_invalidate_mmio_sptes(kvm);
7275 }
7276
7277 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7278                                 struct kvm_memory_slot *memslot,
7279                                 struct kvm_userspace_memory_region *mem,
7280                                 enum kvm_mr_change change)
7281 {
7282         /*
7283          * Only private memory slots need to be mapped here since
7284          * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7285          */
7286         if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7287                 unsigned long userspace_addr;
7288
7289                 /*
7290                  * MAP_SHARED to prevent internal slot pages from being moved
7291                  * by fork()/COW.
7292                  */
7293                 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7294                                          PROT_READ | PROT_WRITE,
7295                                          MAP_SHARED | MAP_ANONYMOUS, 0);
7296
7297                 if (IS_ERR((void *)userspace_addr))
7298                         return PTR_ERR((void *)userspace_addr);
7299
7300                 memslot->userspace_addr = userspace_addr;
7301         }
7302
7303         return 0;
7304 }
7305
7306 void kvm_arch_commit_memory_region(struct kvm *kvm,
7307                                 struct kvm_userspace_memory_region *mem,
7308                                 const struct kvm_memory_slot *old,
7309                                 enum kvm_mr_change change)
7310 {
7311
7312         int nr_mmu_pages = 0;
7313
7314         if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7315                 int ret;
7316
7317                 ret = vm_munmap(old->userspace_addr,
7318                                 old->npages * PAGE_SIZE);
7319                 if (ret < 0)
7320                         printk(KERN_WARNING
7321                                "kvm_vm_ioctl_set_memory_region: "
7322                                "failed to munmap memory\n");
7323         }
7324
7325         if (!kvm->arch.n_requested_mmu_pages)
7326                 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7327
7328         if (nr_mmu_pages)
7329                 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7330         /*
7331          * Write protect all pages for dirty logging.
7332          * Existing largepage mappings are destroyed here and new ones will
7333          * not be created until the end of the logging.
7334          */
7335         if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7336                 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7337 }
7338
7339 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7340 {
7341         kvm_mmu_invalidate_zap_all_pages(kvm);
7342 }
7343
7344 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7345                                    struct kvm_memory_slot *slot)
7346 {
7347         kvm_mmu_invalidate_zap_all_pages(kvm);
7348 }
7349
7350 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7351 {
7352         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7353                 kvm_x86_ops->check_nested_events(vcpu, false);
7354
7355         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7356                 !vcpu->arch.apf.halted)
7357                 || !list_empty_careful(&vcpu->async_pf.done)
7358                 || kvm_apic_has_events(vcpu)
7359                 || vcpu->arch.pv.pv_unhalted
7360                 || atomic_read(&vcpu->arch.nmi_queued) ||
7361                 (kvm_arch_interrupt_allowed(vcpu) &&
7362                  kvm_cpu_has_interrupt(vcpu));
7363 }
7364
7365 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7366 {
7367         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7368 }
7369
7370 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7371 {
7372         return kvm_x86_ops->interrupt_allowed(vcpu);
7373 }
7374
7375 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7376 {
7377         unsigned long current_rip = kvm_rip_read(vcpu) +
7378                 get_segment_base(vcpu, VCPU_SREG_CS);
7379
7380         return current_rip == linear_rip;
7381 }
7382 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7383
7384 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7385 {
7386         unsigned long rflags;
7387
7388         rflags = kvm_x86_ops->get_rflags(vcpu);
7389         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7390                 rflags &= ~X86_EFLAGS_TF;
7391         return rflags;
7392 }
7393 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7394
7395 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7396 {
7397         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7398             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7399                 rflags |= X86_EFLAGS_TF;
7400         kvm_x86_ops->set_rflags(vcpu, rflags);
7401         kvm_make_request(KVM_REQ_EVENT, vcpu);
7402 }
7403 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7404
7405 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7406 {
7407         int r;
7408
7409         if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7410               work->wakeup_all)
7411                 return;
7412
7413         r = kvm_mmu_reload(vcpu);
7414         if (unlikely(r))
7415                 return;
7416
7417         if (!vcpu->arch.mmu.direct_map &&
7418               work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7419                 return;
7420
7421         vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7422 }
7423
7424 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7425 {
7426         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7427 }
7428
7429 static inline u32 kvm_async_pf_next_probe(u32 key)
7430 {
7431         return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7432 }
7433
7434 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7435 {
7436         u32 key = kvm_async_pf_hash_fn(gfn);
7437
7438         while (vcpu->arch.apf.gfns[key] != ~0)
7439                 key = kvm_async_pf_next_probe(key);
7440
7441         vcpu->arch.apf.gfns[key] = gfn;
7442 }
7443
7444 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7445 {
7446         int i;
7447         u32 key = kvm_async_pf_hash_fn(gfn);
7448
7449         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7450                      (vcpu->arch.apf.gfns[key] != gfn &&
7451                       vcpu->arch.apf.gfns[key] != ~0); i++)
7452                 key = kvm_async_pf_next_probe(key);
7453
7454         return key;
7455 }
7456
7457 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7458 {
7459         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7460 }
7461
7462 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7463 {
7464         u32 i, j, k;
7465
7466         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7467         while (true) {
7468                 vcpu->arch.apf.gfns[i] = ~0;
7469                 do {
7470                         j = kvm_async_pf_next_probe(j);
7471                         if (vcpu->arch.apf.gfns[j] == ~0)
7472                                 return;
7473                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7474                         /*
7475                          * k lies cyclically in ]i,j]
7476                          * |    i.k.j |
7477                          * |....j i.k.| or  |.k..j i...|
7478                          */
7479                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7480                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7481                 i = j;
7482         }
7483 }
7484
7485 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7486 {
7487
7488         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7489                                       sizeof(val));
7490 }
7491
7492 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7493                                      struct kvm_async_pf *work)
7494 {
7495         struct x86_exception fault;
7496
7497         trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7498         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7499
7500         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7501             (vcpu->arch.apf.send_user_only &&
7502              kvm_x86_ops->get_cpl(vcpu) == 0))
7503                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7504         else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7505                 fault.vector = PF_VECTOR;
7506                 fault.error_code_valid = true;
7507                 fault.error_code = 0;
7508                 fault.nested_page_fault = false;
7509                 fault.address = work->arch.token;
7510                 kvm_inject_page_fault(vcpu, &fault);
7511         }
7512 }
7513
7514 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7515                                  struct kvm_async_pf *work)
7516 {
7517         struct x86_exception fault;
7518
7519         trace_kvm_async_pf_ready(work->arch.token, work->gva);
7520         if (work->wakeup_all)
7521                 work->arch.token = ~0; /* broadcast wakeup */
7522         else
7523                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7524
7525         if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7526             !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7527                 fault.vector = PF_VECTOR;
7528                 fault.error_code_valid = true;
7529                 fault.error_code = 0;
7530                 fault.nested_page_fault = false;
7531                 fault.address = work->arch.token;
7532                 kvm_inject_page_fault(vcpu, &fault);
7533         }
7534         vcpu->arch.apf.halted = false;
7535         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7536 }
7537
7538 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7539 {
7540         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7541                 return true;
7542         else
7543                 return !kvm_event_needs_reinjection(vcpu) &&
7544                         kvm_x86_ops->interrupt_allowed(vcpu);
7545 }
7546
7547 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7548 {
7549         atomic_inc(&kvm->arch.noncoherent_dma_count);
7550 }
7551 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7552
7553 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7554 {
7555         atomic_dec(&kvm->arch.noncoherent_dma_count);
7556 }
7557 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7558
7559 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7560 {
7561         return atomic_read(&kvm->arch.noncoherent_dma_count);
7562 }
7563 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7564
7565 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7566 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7567 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7568 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7569 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7570 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);