2 * Common interrupt code for 32 and 64 bit
5 #include <linux/interrupt.h>
6 #include <linux/kernel_stat.h>
8 #include <linux/seq_file.h>
10 #include <linux/ftrace.h>
11 #include <linux/delay.h>
12 #include <linux/export.h>
15 #include <asm/io_apic.h>
19 #include <asm/hw_irq.h>
21 #define CREATE_TRACE_POINTS
22 #include <asm/trace/irq_vectors.h>
24 atomic_t irq_err_count;
26 /* Function pointer for generic interrupt vector handling */
27 void (*x86_platform_ipi_callback)(void) = NULL;
30 * 'what should we do if we get a hw irq event on an illegal vector'.
31 * each architecture has to answer this themselves.
33 void ack_bad_irq(unsigned int irq)
35 if (printk_ratelimit())
36 pr_err("unexpected IRQ trap at vector %02x\n", irq);
39 * Currently unexpected vectors happen only on SMP and APIC.
40 * We _must_ ack these because every local APIC has only N
41 * irq slots per priority level, and a 'hanging, unacked' IRQ
42 * holds up an irq slot - in excessive cases (when multiple
43 * unexpected vectors occur) that might lock up the APIC
45 * But only ack when the APIC is enabled -AK
50 #define irq_stats(x) (&per_cpu(irq_stat, x))
52 * /proc/interrupts printing for arch specific interrupts
54 int arch_show_interrupts(struct seq_file *p, int prec)
58 seq_printf(p, "%*s: ", prec, "NMI");
59 for_each_online_cpu(j)
60 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
61 seq_printf(p, " Non-maskable interrupts\n");
62 #ifdef CONFIG_X86_LOCAL_APIC
63 seq_printf(p, "%*s: ", prec, "LOC");
64 for_each_online_cpu(j)
65 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
66 seq_printf(p, " Local timer interrupts\n");
68 seq_printf(p, "%*s: ", prec, "SPU");
69 for_each_online_cpu(j)
70 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
71 seq_printf(p, " Spurious interrupts\n");
72 seq_printf(p, "%*s: ", prec, "PMI");
73 for_each_online_cpu(j)
74 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
75 seq_printf(p, " Performance monitoring interrupts\n");
76 seq_printf(p, "%*s: ", prec, "IWI");
77 for_each_online_cpu(j)
78 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
79 seq_printf(p, " IRQ work interrupts\n");
80 seq_printf(p, "%*s: ", prec, "RTR");
81 for_each_online_cpu(j)
82 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
83 seq_printf(p, " APIC ICR read retries\n");
85 if (x86_platform_ipi_callback) {
86 seq_printf(p, "%*s: ", prec, "PLT");
87 for_each_online_cpu(j)
88 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
89 seq_printf(p, " Platform interrupts\n");
92 seq_printf(p, "%*s: ", prec, "RES");
93 for_each_online_cpu(j)
94 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
95 seq_printf(p, " Rescheduling interrupts\n");
96 seq_printf(p, "%*s: ", prec, "CAL");
97 for_each_online_cpu(j)
98 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
99 irq_stats(j)->irq_tlb_count);
100 seq_printf(p, " Function call interrupts\n");
101 seq_printf(p, "%*s: ", prec, "TLB");
102 for_each_online_cpu(j)
103 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
104 seq_printf(p, " TLB shootdowns\n");
106 #ifdef CONFIG_X86_THERMAL_VECTOR
107 seq_printf(p, "%*s: ", prec, "TRM");
108 for_each_online_cpu(j)
109 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
110 seq_printf(p, " Thermal event interrupts\n");
112 #ifdef CONFIG_X86_MCE_THRESHOLD
113 seq_printf(p, "%*s: ", prec, "THR");
114 for_each_online_cpu(j)
115 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
116 seq_printf(p, " Threshold APIC interrupts\n");
118 #ifdef CONFIG_X86_MCE
119 seq_printf(p, "%*s: ", prec, "MCE");
120 for_each_online_cpu(j)
121 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
122 seq_printf(p, " Machine check exceptions\n");
123 seq_printf(p, "%*s: ", prec, "MCP");
124 for_each_online_cpu(j)
125 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
126 seq_printf(p, " Machine check polls\n");
128 #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
129 seq_printf(p, "%*s: ", prec, "THR");
130 for_each_online_cpu(j)
131 seq_printf(p, "%10u ", irq_stats(j)->irq_hv_callback_count);
132 seq_printf(p, " Hypervisor callback interrupts\n");
134 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
135 #if defined(CONFIG_X86_IO_APIC)
136 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
144 u64 arch_irq_stat_cpu(unsigned int cpu)
146 u64 sum = irq_stats(cpu)->__nmi_count;
148 #ifdef CONFIG_X86_LOCAL_APIC
149 sum += irq_stats(cpu)->apic_timer_irqs;
150 sum += irq_stats(cpu)->irq_spurious_count;
151 sum += irq_stats(cpu)->apic_perf_irqs;
152 sum += irq_stats(cpu)->apic_irq_work_irqs;
153 sum += irq_stats(cpu)->icr_read_retry_count;
155 if (x86_platform_ipi_callback)
156 sum += irq_stats(cpu)->x86_platform_ipis;
158 sum += irq_stats(cpu)->irq_resched_count;
159 sum += irq_stats(cpu)->irq_call_count;
161 #ifdef CONFIG_X86_THERMAL_VECTOR
162 sum += irq_stats(cpu)->irq_thermal_count;
164 #ifdef CONFIG_X86_MCE_THRESHOLD
165 sum += irq_stats(cpu)->irq_threshold_count;
167 #ifdef CONFIG_X86_MCE
168 sum += per_cpu(mce_exception_count, cpu);
169 sum += per_cpu(mce_poll_count, cpu);
174 u64 arch_irq_stat(void)
176 u64 sum = atomic_read(&irq_err_count);
182 * do_IRQ handles all normal device IRQ's (the special
183 * SMP cross-CPU interrupts have their own specific
186 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
188 struct pt_regs *old_regs = set_irq_regs(regs);
190 /* high bit used in ret_from_ code */
191 unsigned vector = ~regs->orig_ax;
197 irq = __this_cpu_read(vector_irq[vector]);
199 if (!handle_irq(irq, regs)) {
202 if (irq != VECTOR_RETRIGGERED) {
203 pr_emerg_ratelimited("%s: %d.%d No irq handler for vector (irq %d)\n",
204 __func__, smp_processor_id(),
207 __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
213 set_irq_regs(old_regs);
218 * Handler for X86_PLATFORM_IPI_VECTOR.
220 void __smp_x86_platform_ipi(void)
222 inc_irq_stat(x86_platform_ipis);
224 if (x86_platform_ipi_callback)
225 x86_platform_ipi_callback();
228 __visible void smp_x86_platform_ipi(struct pt_regs *regs)
230 struct pt_regs *old_regs = set_irq_regs(regs);
233 __smp_x86_platform_ipi();
235 set_irq_regs(old_regs);
238 #ifdef CONFIG_HAVE_KVM
240 * Handler for POSTED_INTERRUPT_VECTOR.
242 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
244 struct pt_regs *old_regs = set_irq_regs(regs);
252 inc_irq_stat(kvm_posted_intr_ipis);
256 set_irq_regs(old_regs);
260 __visible void smp_trace_x86_platform_ipi(struct pt_regs *regs)
262 struct pt_regs *old_regs = set_irq_regs(regs);
265 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
266 __smp_x86_platform_ipi();
267 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
269 set_irq_regs(old_regs);
272 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
274 #ifdef CONFIG_HOTPLUG_CPU
276 /* These two declarations are only used in check_irq_vectors_for_cpu_disable()
277 * below, which is protected by stop_machine(). Putting them on the stack
278 * results in a stack frame overflow. Dynamically allocating could result in a
279 * failure so declare these two cpumasks as global.
281 static struct cpumask affinity_new, online_new;
284 * This cpu is going to be removed and its vectors migrated to the remaining
285 * online cpus. Check to see if there are enough vectors in the remaining cpus.
286 * This function is protected by stop_machine().
288 int check_irq_vectors_for_cpu_disable(void)
291 unsigned int this_cpu, vector, this_count, count;
292 struct irq_desc *desc;
293 struct irq_data *data;
295 this_cpu = smp_processor_id();
296 cpumask_copy(&online_new, cpu_online_mask);
297 cpu_clear(this_cpu, online_new);
300 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
301 irq = __this_cpu_read(vector_irq[vector]);
303 desc = irq_to_desc(irq);
304 data = irq_desc_get_irq_data(desc);
305 cpumask_copy(&affinity_new, data->affinity);
306 cpu_clear(this_cpu, affinity_new);
308 /* Do not count inactive or per-cpu irqs. */
309 if (!irq_has_action(irq) || irqd_is_per_cpu(data))
313 * A single irq may be mapped to multiple
314 * cpu's vector_irq[] (for example IOAPIC cluster
315 * mode). In this case we have two
318 * 1) the resulting affinity mask is empty; that is
319 * this the down'd cpu is the last cpu in the irq's
322 * 2) the resulting affinity mask is no longer
323 * a subset of the online cpus but the affinity
324 * mask is not zero; that is the down'd cpu is the
325 * last online cpu in a user set affinity mask.
327 if (cpumask_empty(&affinity_new) ||
328 !cpumask_subset(&affinity_new, &online_new))
334 for_each_online_cpu(cpu) {
337 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
339 if (per_cpu(vector_irq, cpu)[vector] < 0)
344 if (count < this_count) {
345 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
346 this_cpu, this_count, count);
352 /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
353 void fixup_irqs(void)
355 unsigned int irq, vector;
357 struct irq_desc *desc;
358 struct irq_data *data;
359 struct irq_chip *chip;
361 for_each_irq_desc(irq, desc) {
362 int break_affinity = 0;
363 int set_affinity = 1;
364 const struct cpumask *affinity;
371 /* interrupt's are disabled at this point */
372 raw_spin_lock(&desc->lock);
374 data = irq_desc_get_irq_data(desc);
375 affinity = data->affinity;
376 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
377 cpumask_subset(affinity, cpu_online_mask)) {
378 raw_spin_unlock(&desc->lock);
383 * Complete the irq move. This cpu is going down and for
384 * non intr-remapping case, we can't wait till this interrupt
385 * arrives at this cpu before completing the irq move.
387 irq_force_complete_move(irq);
389 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
391 affinity = cpu_online_mask;
394 chip = irq_data_get_irq_chip(data);
395 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
396 chip->irq_mask(data);
398 if (chip->irq_set_affinity)
399 chip->irq_set_affinity(data, affinity, true);
400 else if (!(warned++))
404 * We unmask if the irq was not marked masked by the
405 * core code. That respects the lazy irq disable
408 if (!irqd_can_move_in_process_context(data) &&
409 !irqd_irq_masked(data) && chip->irq_unmask)
410 chip->irq_unmask(data);
412 raw_spin_unlock(&desc->lock);
414 if (break_affinity && set_affinity)
415 pr_notice("Broke affinity for irq %i\n", irq);
416 else if (!set_affinity)
417 pr_notice("Cannot set affinity for irq %i\n", irq);
421 * We can remove mdelay() and then send spuriuous interrupts to
422 * new cpu targets for all the irqs that were handled previously by
423 * this cpu. While it works, I have seen spurious interrupt messages
424 * (nothing wrong but still...).
426 * So for now, retain mdelay(1) and check the IRR and then send those
427 * interrupts to new targets as this cpu is already offlined...
431 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
434 if (__this_cpu_read(vector_irq[vector]) <= VECTOR_UNDEFINED)
437 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
438 if (irr & (1 << (vector % 32))) {
439 irq = __this_cpu_read(vector_irq[vector]);
441 desc = irq_to_desc(irq);
442 data = irq_desc_get_irq_data(desc);
443 chip = irq_data_get_irq_chip(data);
444 raw_spin_lock(&desc->lock);
445 if (chip->irq_retrigger) {
446 chip->irq_retrigger(data);
447 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
449 raw_spin_unlock(&desc->lock);
451 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
452 __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);