arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/slab.h>
  21 #include <linux/cpu.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdebug.h>
  26 #include <linux/delay.h>
  27 #include <linux/crash_dump.h>
  28 #include <linux/reboot.h>
  29
  30 #include <asm/uv/uv_mmrs.h>
  31 #include <asm/uv/uv_hub.h>
  32 #include <asm/current.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/uv/bios.h>
  35 #include <asm/uv/uv.h>
  36 #include <asm/apic.h>
  37 #include <asm/ipi.h>
  38 #include <asm/smp.h>
  39 #include <asm/x86_init.h>
  40 #include <asm/nmi.h>
  41
  42 DEFINE_PER_CPU(int, x2apic_extra_bits);
  43
  44 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
  45
  46 static enum uv_system_type uv_system_type;
  47 static u64 gru_start_paddr, gru_end_paddr;
  48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
  49 static u64 gru_dist_lmask, gru_dist_umask;
  50 static union uvh_apicid uvh_apicid;
  51 int uv_min_hub_revision_id;
  52 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  53 unsigned int uv_apicid_hibits;
  54 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
  55
  56 static struct apic apic_x2apic_uv_x;
  57
  58 static unsigned long __init uv_early_read_mmr(unsigned long addr)
  59 {
  60         unsigned long val, *mmr;
  61
  62         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
  63         val = *mmr;
  64         early_iounmap(mmr, sizeof(*mmr));
  65         return val;
  66 }
  67
  68 static inline bool is_GRU_range(u64 start, u64 end)
  69 {
  70         if (gru_dist_base) {
  71                 u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
  72                 u64 sl = start & gru_dist_lmask; /* base offset bits */
  73                 u64 eu = end & gru_dist_umask;
  74                 u64 el = end & gru_dist_lmask;
  75
  76                 /* Must reside completely within a single GRU range */
  77                 return (sl == gru_dist_base && el == gru_dist_base &&
  78                         su >= gru_first_node_paddr &&
  79                         su <= gru_last_node_paddr &&
  80                         eu == su);
  81         } else {
  82                 return start >= gru_start_paddr && end <= gru_end_paddr;
  83         }
  84 }
  85
  86 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  87 {
  88         return is_ISA_range(start, end) || is_GRU_range(start, end);
  89 }
  90
  91 static int __init early_get_pnodeid(void)
  92 {
  93         union uvh_node_id_u node_id;
  94         union uvh_rh_gam_config_mmr_u  m_n_config;
  95         int pnode;
  96
  97         /* Currently, all blades have same revision number */
  98         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
  99         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
 100         uv_min_hub_revision_id = node_id.s.revision;
 101
 102         switch (node_id.s.part_number) {
 103         case UV2_HUB_PART_NUMBER:
 104         case UV2_HUB_PART_NUMBER_X:
 105                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
 106                 break;
 107         case UV3_HUB_PART_NUMBER:
 108         case UV3_HUB_PART_NUMBER_X:
 109                 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
 110                 break;
 111         }
 112
 113         uv_hub_info->hub_revision = uv_min_hub_revision_id;
 114         pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
 115         return pnode;
 116 }
 117
 118 static void __init early_get_apic_pnode_shift(void)
 119 {
 120         uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
 121         if (!uvh_apicid.v)
 122                 /*
 123                  * Old bios, use default value
 124                  */
 125                 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
 126 }
 127
 128 /*
 129  * Add an extra bit as dictated by bios to the destination apicid of
 130  * interrupts potentially passing through the UV HUB.  This prevents
 131  * a deadlock between interrupts and IO port operations.
 132  */
 133 static void __init uv_set_apicid_hibit(void)
 134 {
 135         union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
 136
 137         if (is_uv1_hub()) {
 138                 apicid_mask.v =
 139                         uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
 140                 uv_apicid_hibits =
 141                         apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
 142         }
 143 }
 144
 145 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 146 {
 147         int pnodeid, is_uv1, is_uv2, is_uv3;
 148
 149         is_uv1 = !strcmp(oem_id, "SGI");
 150         is_uv2 = !strcmp(oem_id, "SGI2");
 151         is_uv3 = !strncmp(oem_id, "SGI3", 4);   /* there are varieties of UV3 */
 152         if (is_uv1 || is_uv2 || is_uv3) {
 153                 uv_hub_info->hub_revision =
 154                         (is_uv1 ? UV1_HUB_REVISION_BASE :
 155                         (is_uv2 ? UV2_HUB_REVISION_BASE :
 156                                   UV3_HUB_REVISION_BASE));
 157                 pnodeid = early_get_pnodeid();
 158                 early_get_apic_pnode_shift();
 159                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
 160                 x86_platform.nmi_init = uv_nmi_init;
 161                 if (!strcmp(oem_table_id, "UVL"))
 162                         uv_system_type = UV_LEGACY_APIC;
 163                 else if (!strcmp(oem_table_id, "UVX"))
 164                         uv_system_type = UV_X2APIC;
 165                 else if (!strcmp(oem_table_id, "UVH")) {
 166                         __this_cpu_write(x2apic_extra_bits,
 167                                 pnodeid << uvh_apicid.s.pnode_shift);
 168                         uv_system_type = UV_NON_UNIQUE_APIC;
 169                         uv_set_apicid_hibit();
 170                         return 1;
 171                 }
 172         }
 173         return 0;
 174 }
 175
 176 enum uv_system_type get_uv_system_type(void)
 177 {
 178         return uv_system_type;
 179 }
 180
 181 int is_uv_system(void)
 182 {
 183         return uv_system_type != UV_NONE;
 184 }
 185 EXPORT_SYMBOL_GPL(is_uv_system);
 186
 187 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 188 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
 189
 190 struct uv_blade_info *uv_blade_info;
 191 EXPORT_SYMBOL_GPL(uv_blade_info);
 192
 193 short *uv_node_to_blade;
 194 EXPORT_SYMBOL_GPL(uv_node_to_blade);
 195
 196 short *uv_cpu_to_blade;
 197 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
 198
 199 short uv_possible_blades;
 200 EXPORT_SYMBOL_GPL(uv_possible_blades);
 201
 202 unsigned long sn_rtc_cycles_per_second;
 203 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 204
 205 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 206 {
 207 #ifdef CONFIG_SMP
 208         unsigned long val;
 209         int pnode;
 210
 211         pnode = uv_apicid_to_pnode(phys_apicid);
 212         phys_apicid |= uv_apicid_hibits;
 213         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 214             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 215             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 216             APIC_DM_INIT;
 217         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 218
 219         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 220             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 221             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 222             APIC_DM_STARTUP;
 223         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 224
 225         atomic_set(&init_deasserted, 1);
 226 #endif
 227         return 0;
 228 }
 229
 230 static void uv_send_IPI_one(int cpu, int vector)
 231 {
 232         unsigned long apicid;
 233         int pnode;
 234
 235         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 236         pnode = uv_apicid_to_pnode(apicid);
 237         uv_hub_send_ipi(pnode, apicid, vector);
 238 }
 239
 240 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 241 {
 242         unsigned int cpu;
 243
 244         for_each_cpu(cpu, mask)
 245                 uv_send_IPI_one(cpu, vector);
 246 }
 247
 248 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 249 {
 250         unsigned int this_cpu = smp_processor_id();
 251         unsigned int cpu;
 252
 253         for_each_cpu(cpu, mask) {
 254                 if (cpu != this_cpu)
 255                         uv_send_IPI_one(cpu, vector);
 256         }
 257 }
 258
 259 static void uv_send_IPI_allbutself(int vector)
 260 {
 261         unsigned int this_cpu = smp_processor_id();
 262         unsigned int cpu;
 263
 264         for_each_online_cpu(cpu) {
 265                 if (cpu != this_cpu)
 266                         uv_send_IPI_one(cpu, vector);
 267         }
 268 }
 269
 270 static void uv_send_IPI_all(int vector)
 271 {
 272         uv_send_IPI_mask(cpu_online_mask, vector);
 273 }
 274
 275 static int uv_apic_id_valid(int apicid)
 276 {
 277         return 1;
 278 }
 279
 280 static int uv_apic_id_registered(void)
 281 {
 282         return 1;
 283 }
 284
 285 static void uv_init_apic_ldr(void)
 286 {
 287 }
 288
 289 static int
 290 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 291                           const struct cpumask *andmask,
 292                           unsigned int *apicid)
 293 {
 294         int unsigned cpu;
 295
 296         /*
 297          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 298          * May as well be the first.
 299          */
 300         for_each_cpu_and(cpu, cpumask, andmask) {
 301                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 302                         break;
 303         }
 304
 305         if (likely(cpu < nr_cpu_ids)) {
 306                 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
 307                 return 0;
 308         }
 309
 310         return -EINVAL;
 311 }
 312
 313 static unsigned int x2apic_get_apic_id(unsigned long x)
 314 {
 315         unsigned int id;
 316
 317         WARN_ON(preemptible() && num_online_cpus() > 1);
 318         id = x | __this_cpu_read(x2apic_extra_bits);
 319
 320         return id;
 321 }
 322
 323 static unsigned long set_apic_id(unsigned int id)
 324 {
 325         unsigned long x;
 326
 327         /* maskout x2apic_extra_bits ? */
 328         x = id;
 329         return x;
 330 }
 331
 332 static unsigned int uv_read_apic_id(void)
 333 {
 334
 335         return x2apic_get_apic_id(apic_read(APIC_ID));
 336 }
 337
 338 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 339 {
 340         return uv_read_apic_id() >> index_msb;
 341 }
 342
 343 static void uv_send_IPI_self(int vector)
 344 {
 345         apic_write(APIC_SELF_IPI, vector);
 346 }
 347
 348 static int uv_probe(void)
 349 {
 350         return apic == &apic_x2apic_uv_x;
 351 }
 352
 353 static struct apic __refdata apic_x2apic_uv_x = {
 354
 355         .name                           = "UV large system",
 356         .probe                          = uv_probe,
 357         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 358         .apic_id_valid                  = uv_apic_id_valid,
 359         .apic_id_registered             = uv_apic_id_registered,
 360
 361         .irq_delivery_mode              = dest_Fixed,
 362         .irq_dest_mode                  = 0, /* physical */
 363
 364         .target_cpus                    = online_target_cpus,
 365         .disable_esr                    = 0,
 366         .dest_logical                   = APIC_DEST_LOGICAL,
 367         .check_apicid_used              = NULL,
 368         .check_apicid_present           = NULL,
 369
 370         .vector_allocation_domain       = default_vector_allocation_domain,
 371         .init_apic_ldr                  = uv_init_apic_ldr,
 372
 373         .ioapic_phys_id_map             = NULL,
 374         .setup_apic_routing             = NULL,
 375         .multi_timer_check              = NULL,
 376         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 377         .apicid_to_cpu_present          = NULL,
 378         .setup_portio_remap             = NULL,
 379         .check_phys_apicid_present      = default_check_phys_apicid_present,
 380         .enable_apic_mode               = NULL,
 381         .phys_pkg_id                    = uv_phys_pkg_id,
 382         .mps_oem_check                  = NULL,
 383
 384         .get_apic_id                    = x2apic_get_apic_id,
 385         .set_apic_id                    = set_apic_id,
 386         .apic_id_mask                   = 0xFFFFFFFFu,
 387
 388         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 389
 390         .send_IPI_mask                  = uv_send_IPI_mask,
 391         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 392         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 393         .send_IPI_all                   = uv_send_IPI_all,
 394         .send_IPI_self                  = uv_send_IPI_self,
 395
 396         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 397         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 398         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 399         .wait_for_init_deassert         = NULL,
 400         .smp_callin_clear_local_apic    = NULL,
 401         .inquire_remote_apic            = NULL,
 402
 403         .read                           = native_apic_msr_read,
 404         .write                          = native_apic_msr_write,
 405         .eoi_write                      = native_apic_msr_eoi_write,
 406         .icr_read                       = native_x2apic_icr_read,
 407         .icr_write                      = native_x2apic_icr_write,
 408         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 409         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 410 };
 411
 412 static void set_x2apic_extra_bits(int pnode)
 413 {
 414         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
 415 }
 416
 417 /*
 418  * Called on boot cpu.
 419  */
 420 static __init int boot_pnode_to_blade(int pnode)
 421 {
 422         int blade;
 423
 424         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 425                 if (pnode == uv_blade_info[blade].pnode)
 426                         return blade;
 427         BUG();
 428 }
 429
 430 struct redir_addr {
 431         unsigned long redirect;
 432         unsigned long alias;
 433 };
 434
 435 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 436
 437 static __initdata struct redir_addr redir_addrs[] = {
 438         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
 439         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
 440         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
 441 };
 442
 443 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 444 {
 445         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
 446         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 447         int i;
 448
 449         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 450                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 451                 if (alias.s.enable && alias.s.base == 0) {
 452                         *size = (1UL << alias.s.m_alias);
 453                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 454                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 455                         return;
 456                 }
 457         }
 458         *base = *size = 0;
 459 }
 460
 461 enum map_type {map_wb, map_uc};
 462
 463 static __init void map_high(char *id, unsigned long base, int pshift,
 464                         int bshift, int max_pnode, enum map_type map_type)
 465 {
 466         unsigned long bytes, paddr;
 467
 468         paddr = base << pshift;
 469         bytes = (1UL << bshift) * (max_pnode + 1);
 470         if (!paddr) {
 471                 pr_info("UV: Map %s_HI base address NULL\n", id);
 472                 return;
 473         }
 474         pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
 475         if (map_type == map_uc)
 476                 init_extra_mapping_uc(paddr, bytes);
 477         else
 478                 init_extra_mapping_wb(paddr, bytes);
 479 }
 480
 481 static __init void map_gru_distributed(unsigned long c)
 482 {
 483         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 484         u64 paddr;
 485         unsigned long bytes;
 486         int nid;
 487
 488         gru.v = c;
 489         /* only base bits 42:28 relevant in dist mode */
 490         gru_dist_base = gru.v & 0x000007fff0000000UL;
 491         if (!gru_dist_base) {
 492                 pr_info("UV: Map GRU_DIST base address NULL\n");
 493                 return;
 494         }
 495         bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 496         gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
 497         gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
 498         gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
 499         for_each_online_node(nid) {
 500                 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
 501                                 gru_dist_base;
 502                 init_extra_mapping_wb(paddr, bytes);
 503                 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
 504                 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
 505         }
 506         /* Save upper (63:M) bits of address only for is_GRU_range */
 507         gru_first_node_paddr &= gru_dist_umask;
 508         gru_last_node_paddr &= gru_dist_umask;
 509         pr_debug("UV: Map GRU_DIST base 0x%016llx  0x%016llx - 0x%016llx\n",
 510                 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
 511 }
 512
 513 static __init void map_gru_high(int max_pnode)
 514 {
 515         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 516         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 517
 518         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 519         if (!gru.s.enable) {
 520                 pr_info("UV: GRU disabled\n");
 521                 return;
 522         }
 523
 524         if (is_uv3_hub() && gru.s3.mode) {
 525                 map_gru_distributed(gru.v);
 526                 return;
 527         }
 528         map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
 529         gru_start_paddr = ((u64)gru.s.base << shift);
 530         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 531 }
 532
 533 static __init void map_mmr_high(int max_pnode)
 534 {
 535         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 536         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 537
 538         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 539         if (mmr.s.enable)
 540                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 541         else
 542                 pr_info("UV: MMR disabled\n");
 543 }
 544
 545 /*
 546  * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
 547  * and REDIRECT MMR regs are exactly the same on UV3.
 548  */
 549 struct mmioh_config {
 550         unsigned long overlay;
 551         unsigned long redirect;
 552         char *id;
 553 };
 554
 555 static __initdata struct mmioh_config mmiohs[] = {
 556         {
 557                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
 558                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
 559                 "MMIOH0"
 560         },
 561         {
 562                 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
 563                 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
 564                 "MMIOH1"
 565         },
 566 };
 567
 568 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
 569 {
 570         union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
 571         unsigned long mmr;
 572         unsigned long base;
 573         int i, n, shift, m_io, max_io;
 574         int nasid, lnasid, fi, li;
 575         char *id;
 576
 577         id = mmiohs[index].id;
 578         overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
 579         pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
 580                 id, overlay.v, overlay.s3.base, overlay.s3.m_io);
 581         if (!overlay.s3.enable) {
 582                 pr_info("UV: %s disabled\n", id);
 583                 return;
 584         }
 585
 586         shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
 587         base = (unsigned long)overlay.s3.base;
 588         m_io = overlay.s3.m_io;
 589         mmr = mmiohs[index].redirect;
 590         n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
 591         min_pnode *= 2;                         /* convert to NASID */
 592         max_pnode *= 2;
 593         max_io = lnasid = fi = li = -1;
 594
 595         for (i = 0; i < n; i++) {
 596                 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
 597
 598                 redirect.v = uv_read_local_mmr(mmr + i * 8);
 599                 nasid = redirect.s3.nasid;
 600                 if (nasid < min_pnode || max_pnode < nasid)
 601                         nasid = -1;             /* invalid NASID */
 602
 603                 if (nasid == lnasid) {
 604                         li = i;
 605                         if (i != n-1)           /* last entry check */
 606                                 continue;
 607                 }
 608
 609                 /* check if we have a cached (or last) redirect to print */
 610                 if (lnasid != -1 || (i == n-1 && nasid != -1))  {
 611                         unsigned long addr1, addr2;
 612                         int f, l;
 613
 614                         if (lnasid == -1) {
 615                                 f = l = i;
 616                                 lnasid = nasid;
 617                         } else {
 618                                 f = fi;
 619                                 l = li;
 620                         }
 621                         addr1 = (base << shift) +
 622                                 f * (unsigned long)(1 << m_io);
 623                         addr2 = (base << shift) +
 624                                 (l + 1) * (unsigned long)(1 << m_io);
 625                         pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
 626                                 id, fi, li, lnasid, addr1, addr2);
 627                         if (max_io < l)
 628                                 max_io = l;
 629                 }
 630                 fi = li = i;
 631                 lnasid = nasid;
 632         }
 633
 634         pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
 635                 id, base, shift, m_io, max_io);
 636
 637         if (max_io >= 0)
 638                 map_high(id, base, shift, m_io, max_io, map_uc);
 639 }
 640
 641 static __init void map_mmioh_high(int min_pnode, int max_pnode)
 642 {
 643         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 644         unsigned long mmr, base;
 645         int shift, enable, m_io, n_io;
 646
 647         if (is_uv3_hub()) {
 648                 /* Map both MMIOH Regions */
 649                 map_mmioh_high_uv3(0, min_pnode, max_pnode);
 650                 map_mmioh_high_uv3(1, min_pnode, max_pnode);
 651                 return;
 652         }
 653
 654         if (is_uv1_hub()) {
 655                 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 656                 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 657                 mmioh.v = uv_read_local_mmr(mmr);
 658                 enable = !!mmioh.s1.enable;
 659                 base = mmioh.s1.base;
 660                 m_io = mmioh.s1.m_io;
 661                 n_io = mmioh.s1.n_io;
 662         } else if (is_uv2_hub()) {
 663                 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 664                 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 665                 mmioh.v = uv_read_local_mmr(mmr);
 666                 enable = !!mmioh.s2.enable;
 667                 base = mmioh.s2.base;
 668                 m_io = mmioh.s2.m_io;
 669                 n_io = mmioh.s2.n_io;
 670         } else
 671                 return;
 672
 673         if (enable) {
 674                 max_pnode &= (1 << n_io) - 1;
 675                 pr_info(
 676                     "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
 677                         base, shift, m_io, n_io, max_pnode);
 678                 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
 679         } else {
 680                 pr_info("UV: MMIOH disabled\n");
 681         }
 682 }
 683
 684 static __init void map_low_mmrs(void)
 685 {
 686         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 687         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 688 }
 689
 690 static __init void uv_rtc_init(void)
 691 {
 692         long status;
 693         u64 ticks_per_sec;
 694
 695         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 696                                         &ticks_per_sec);
 697         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 698                 printk(KERN_WARNING
 699                         "unable to determine platform RTC clock frequency, "
 700                         "guessing.\n");
 701                 /* BIOS gives wrong value for clock freq. so guess */
 702                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 703         } else
 704                 sn_rtc_cycles_per_second = ticks_per_sec;
 705 }
 706
 707 /*
 708  * percpu heartbeat timer
 709  */
 710 static void uv_heartbeat(unsigned long ignored)
 711 {
 712         struct timer_list *timer = &uv_hub_info->scir.timer;
 713         unsigned char bits = uv_hub_info->scir.state;
 714
 715         /* flip heartbeat bit */
 716         bits ^= SCIR_CPU_HEARTBEAT;
 717
 718         /* is this cpu idle? */
 719         if (idle_cpu(raw_smp_processor_id()))
 720                 bits &= ~SCIR_CPU_ACTIVITY;
 721         else
 722                 bits |= SCIR_CPU_ACTIVITY;
 723
 724         /* update system controller interface reg */
 725         uv_set_scir_bits(bits);
 726
 727         /* enable next timer period */
 728         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 729 }
 730
 731 static void uv_heartbeat_enable(int cpu)
 732 {
 733         while (!uv_cpu_hub_info(cpu)->scir.enabled) {
 734                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 735
 736                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 737                 setup_timer(timer, uv_heartbeat, cpu);
 738                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 739                 add_timer_on(timer, cpu);
 740                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 741
 742                 /* also ensure that boot cpu is enabled */
 743                 cpu = 0;
 744         }
 745 }
 746
 747 #ifdef CONFIG_HOTPLUG_CPU
 748 static void uv_heartbeat_disable(int cpu)
 749 {
 750         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 751                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 752                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 753         }
 754         uv_set_cpu_scir_bits(cpu, 0xff);
 755 }
 756
 757 /*
 758  * cpu hotplug notifier
 759  */
 760 static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action,
 761                               void *hcpu)
 762 {
 763         long cpu = (long)hcpu;
 764
 765         switch (action) {
 766         case CPU_ONLINE:
 767                 uv_heartbeat_enable(cpu);
 768                 break;
 769         case CPU_DOWN_PREPARE:
 770                 uv_heartbeat_disable(cpu);
 771                 break;
 772         default:
 773                 break;
 774         }
 775         return NOTIFY_OK;
 776 }
 777
 778 static __init void uv_scir_register_cpu_notifier(void)
 779 {
 780         hotcpu_notifier(uv_scir_cpu_notify, 0);
 781 }
 782
 783 #else /* !CONFIG_HOTPLUG_CPU */
 784
 785 static __init void uv_scir_register_cpu_notifier(void)
 786 {
 787 }
 788
 789 static __init int uv_init_heartbeat(void)
 790 {
 791         int cpu;
 792
 793         if (is_uv_system())
 794                 for_each_online_cpu(cpu)
 795                         uv_heartbeat_enable(cpu);
 796         return 0;
 797 }
 798
 799 late_initcall(uv_init_heartbeat);
 800
 801 #endif /* !CONFIG_HOTPLUG_CPU */
 802
 803 /* Direct Legacy VGA I/O traffic to designated IOH */
 804 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
 805                       unsigned int command_bits, u32 flags)
 806 {
 807         int domain, bus, rc;
 808
 809         PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
 810                         pdev->devfn, decode, command_bits, flags);
 811
 812         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
 813                 return 0;
 814
 815         if ((command_bits & PCI_COMMAND_IO) == 0)
 816                 return 0;
 817
 818         domain = pci_domain_nr(pdev->bus);
 819         bus = pdev->bus->number;
 820
 821         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
 822         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
 823
 824         return rc;
 825 }
 826
 827 /*
 828  * Called on each cpu to initialize the per_cpu UV data area.
 829  * FIXME: hotplug not supported yet
 830  */
 831 void uv_cpu_init(void)
 832 {
 833         /* CPU 0 initilization will be done via uv_system_init. */
 834         if (!uv_blade_info)
 835                 return;
 836
 837         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 838
 839         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 840                 set_x2apic_extra_bits(uv_hub_info->pnode);
 841 }
 842
 843 void __init uv_system_init(void)
 844 {
 845         union uvh_rh_gam_config_mmr_u  m_n_config;
 846         union uvh_node_id_u node_id;
 847         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 848         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 849         int gnode_extra, min_pnode = 999999, max_pnode = -1;
 850         unsigned long mmr_base, present, paddr;
 851         unsigned short pnode_mask;
 852         char *hub = (is_uv1_hub() ? "UV1" :
 853                     (is_uv2_hub() ? "UV2" :
 854                                     "UV3"));
 855
 856         pr_info("UV: Found %s hub\n", hub);
 857         map_low_mmrs();
 858
 859         m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
 860         m_val = m_n_config.s.m_skt;
 861         n_val = m_n_config.s.n_skt;
 862         pnode_mask = (1 << n_val) - 1;
 863         mmr_base =
 864             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 865             ~UV_MMR_ENABLE;
 866
 867         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 868         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 869         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 870         pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x\n",
 871                         n_val, m_val, pnode_mask, gnode_upper, gnode_extra);
 872
 873         pr_info("UV: global MMR base 0x%lx\n", mmr_base);
 874
 875         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 876                 uv_possible_blades +=
 877                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 878
 879         /* uv_num_possible_blades() is really the hub count */
 880         pr_info("UV: Found %d blades, %d hubs\n",
 881                         is_uv1_hub() ? uv_num_possible_blades() :
 882                         (uv_num_possible_blades() + 1) / 2,
 883                         uv_num_possible_blades());
 884
 885         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 886         uv_blade_info = kzalloc(bytes, GFP_KERNEL);
 887         BUG_ON(!uv_blade_info);
 888
 889         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 890                 uv_blade_info[blade].memory_nid = -1;
 891
 892         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 893
 894         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 895         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 896         BUG_ON(!uv_node_to_blade);
 897         memset(uv_node_to_blade, 255, bytes);
 898
 899         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 900         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 901         BUG_ON(!uv_cpu_to_blade);
 902         memset(uv_cpu_to_blade, 255, bytes);
 903
 904         blade = 0;
 905         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 906                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 907                 for (j = 0; j < 64; j++) {
 908                         if (!test_bit(j, &present))
 909                                 continue;
 910                         pnode = (i * 64 + j) & pnode_mask;
 911                         uv_blade_info[blade].pnode = pnode;
 912                         uv_blade_info[blade].nr_possible_cpus = 0;
 913                         uv_blade_info[blade].nr_online_cpus = 0;
 914                         spin_lock_init(&uv_blade_info[blade].nmi_lock);
 915                         min_pnode = min(pnode, min_pnode);
 916                         max_pnode = max(pnode, max_pnode);
 917                         blade++;
 918                 }
 919         }
 920
 921         uv_bios_init();
 922         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
 923                             &sn_region_size, &system_serial_number);
 924         uv_rtc_init();
 925
 926         for_each_present_cpu(cpu) {
 927                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 928
 929                 nid = cpu_to_node(cpu);
 930                 /*
 931                  * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
 932                  */
 933                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 934                 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
 935                 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
 936
 937                 uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
 938                 uv_cpu_hub_info(cpu)->n_lshift = is_uv2_1_hub() ?
 939                                 (m_val == 40 ? 40 : 39) : m_val;
 940
 941                 pnode = uv_apicid_to_pnode(apicid);
 942                 blade = boot_pnode_to_blade(pnode);
 943                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 944                 uv_blade_info[blade].nr_possible_cpus++;
 945
 946                 /* Any node on the blade, else will contain -1. */
 947                 uv_blade_info[blade].memory_nid = nid;
 948
 949                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 950                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 951                 uv_cpu_hub_info(cpu)->m_val = m_val;
 952                 uv_cpu_hub_info(cpu)->n_val = n_val;
 953                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 954                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 955                 uv_cpu_hub_info(cpu)->pnode = pnode;
 956                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 957                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 958                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 959                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 960                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 961                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
 962                 uv_node_to_blade[nid] = blade;
 963                 uv_cpu_to_blade[cpu] = blade;
 964         }
 965
 966         /* Add blade/pnode info for nodes without cpus */
 967         for_each_online_node(nid) {
 968                 if (uv_node_to_blade[nid] >= 0)
 969                         continue;
 970                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
 971                 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
 972                 blade = boot_pnode_to_blade(pnode);
 973                 uv_node_to_blade[nid] = blade;
 974         }
 975
 976         map_gru_high(max_pnode);
 977         map_mmr_high(max_pnode);
 978         map_mmioh_high(min_pnode, max_pnode);
 979
 980         uv_nmi_setup();
 981         uv_cpu_init();
 982         uv_scir_register_cpu_notifier();
 983         proc_mkdir("sgi_uv", NULL);
 984
 985         /* register Legacy VGA I/O redirection handler */
 986         pci_register_set_vga_state(uv_set_vga_state);
 987
 988         /*
 989          * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
 990          * EFI is not enabled in the kdump kernel.
 991          */
 992         if (is_kdump_kernel())
 993                 reboot_type = BOOT_ACPI;
 994 }
 995
 996 apic_driver(apic_x2apic_uv_x);