arch/sparc/kernel/irq_64.c

   1 /* irq.c: UltraSparc IRQ handling/init/registry.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   5  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/sched.h>
  10 #include <linux/linkage.h>
  11 #include <linux/ptrace.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel_stat.h>
  14 #include <linux/signal.h>
  15 #include <linux/mm.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/slab.h>
  18 #include <linux/random.h>
  19 #include <linux/init.h>
  20 #include <linux/delay.h>
  21 #include <linux/proc_fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/ftrace.h>
  24 #include <linux/irq.h>
  25 #include <linux/kmemleak.h>
  26
  27 #include <asm/ptrace.h>
  28 #include <asm/processor.h>
  29 #include <asm/atomic.h>
  30 #include <asm/system.h>
  31 #include <asm/irq.h>
  32 #include <asm/io.h>
  33 #include <asm/iommu.h>
  34 #include <asm/upa.h>
  35 #include <asm/oplib.h>
  36 #include <asm/prom.h>
  37 #include <asm/timer.h>
  38 #include <asm/smp.h>
  39 #include <asm/starfire.h>
  40 #include <asm/uaccess.h>
  41 #include <asm/cache.h>
  42 #include <asm/cpudata.h>
  43 #include <asm/auxio.h>
  44 #include <asm/head.h>
  45 #include <asm/hypervisor.h>
  46 #include <asm/cacheflush.h>
  47
  48 #include "entry.h"
  49 #include "cpumap.h"
  50 #include "kstack.h"
  51
  52 #define NUM_IVECS       (IMAP_INR + 1)
  53
  54 struct ino_bucket *ivector_table;
  55 unsigned long ivector_table_pa;
  56
  57 /* On several sun4u processors, it is illegal to mix bypass and
  58  * non-bypass accesses.  Therefore we access all INO buckets
  59  * using bypass accesses only.
  60  */
  61 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
  62 {
  63         unsigned long ret;
  64
  65         __asm__ __volatile__("ldxa      [%1] %2, %0"
  66                              : "=&r" (ret)
  67                              : "r" (bucket_pa +
  68                                     offsetof(struct ino_bucket,
  69                                              __irq_chain_pa)),
  70                                "i" (ASI_PHYS_USE_EC));
  71
  72         return ret;
  73 }
  74
  75 static void bucket_clear_chain_pa(unsigned long bucket_pa)
  76 {
  77         __asm__ __volatile__("stxa      %%g0, [%0] %1"
  78                              : /* no outputs */
  79                              : "r" (bucket_pa +
  80                                     offsetof(struct ino_bucket,
  81                                              __irq_chain_pa)),
  82                                "i" (ASI_PHYS_USE_EC));
  83 }
  84
  85 static unsigned int bucket_get_irq(unsigned long bucket_pa)
  86 {
  87         unsigned int ret;
  88
  89         __asm__ __volatile__("lduwa     [%1] %2, %0"
  90                              : "=&r" (ret)
  91                              : "r" (bucket_pa +
  92                                     offsetof(struct ino_bucket,
  93                                              __irq)),
  94                                "i" (ASI_PHYS_USE_EC));
  95
  96         return ret;
  97 }
  98
  99 static void bucket_set_irq(unsigned long bucket_pa, unsigned int irq)
 100 {
 101         __asm__ __volatile__("stwa      %0, [%1] %2"
 102                              : /* no outputs */
 103                              : "r" (irq),
 104                                "r" (bucket_pa +
 105                                     offsetof(struct ino_bucket,
 106                                              __irq)),
 107                                "i" (ASI_PHYS_USE_EC));
 108 }
 109
 110 #define irq_work_pa(__cpu)      &(trap_block[(__cpu)].irq_worklist_pa)
 111
 112 static struct {
 113         unsigned int dev_handle;
 114         unsigned int dev_ino;
 115         unsigned int in_use;
 116 } irq_table[NR_IRQS];
 117 static DEFINE_SPINLOCK(irq_alloc_lock);
 118
 119 unsigned char irq_alloc(unsigned int dev_handle, unsigned int dev_ino)
 120 {
 121         unsigned long flags;
 122         unsigned char ent;
 123
 124         BUILD_BUG_ON(NR_IRQS >= 256);
 125
 126         spin_lock_irqsave(&irq_alloc_lock, flags);
 127
 128         for (ent = 1; ent < NR_IRQS; ent++) {
 129                 if (!irq_table[ent].in_use)
 130                         break;
 131         }
 132         if (ent >= NR_IRQS) {
 133                 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
 134                 ent = 0;
 135         } else {
 136                 irq_table[ent].dev_handle = dev_handle;
 137                 irq_table[ent].dev_ino = dev_ino;
 138                 irq_table[ent].in_use = 1;
 139         }
 140
 141         spin_unlock_irqrestore(&irq_alloc_lock, flags);
 142
 143         return ent;
 144 }
 145
 146 #ifdef CONFIG_PCI_MSI
 147 void irq_free(unsigned int irq)
 148 {
 149         unsigned long flags;
 150
 151         if (irq >= NR_IRQS)
 152                 return;
 153
 154         spin_lock_irqsave(&irq_alloc_lock, flags);
 155
 156         irq_table[irq].in_use = 0;
 157
 158         spin_unlock_irqrestore(&irq_alloc_lock, flags);
 159 }
 160 #endif
 161
 162 /*
 163  * /proc/interrupts printing:
 164  */
 165
 166 int show_interrupts(struct seq_file *p, void *v)
 167 {
 168         int i = *(loff_t *) v, j;
 169         struct irqaction * action;
 170         unsigned long flags;
 171
 172         if (i == 0) {
 173                 seq_printf(p, "           ");
 174                 for_each_online_cpu(j)
 175                         seq_printf(p, "CPU%d       ",j);
 176                 seq_putc(p, '\n');
 177         }
 178
 179         if (i < NR_IRQS) {
 180                 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
 181                 action = irq_desc[i].action;
 182                 if (!action)
 183                         goto skip;
 184                 seq_printf(p, "%3d: ",i);
 185 #ifndef CONFIG_SMP
 186                 seq_printf(p, "%10u ", kstat_irqs(i));
 187 #else
 188                 for_each_online_cpu(j)
 189                         seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
 190 #endif
 191                 seq_printf(p, " %9s", irq_desc[i].irq_data.chip->name);
 192                 seq_printf(p, "  %s", action->name);
 193
 194                 for (action=action->next; action; action = action->next)
 195                         seq_printf(p, ", %s", action->name);
 196
 197                 seq_putc(p, '\n');
 198 skip:
 199                 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
 200         } else if (i == NR_IRQS) {
 201                 seq_printf(p, "NMI: ");
 202                 for_each_online_cpu(j)
 203                         seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
 204                 seq_printf(p, "     Non-maskable interrupts\n");
 205         }
 206         return 0;
 207 }
 208
 209 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
 210 {
 211         unsigned int tid;
 212
 213         if (this_is_starfire) {
 214                 tid = starfire_translate(imap, cpuid);
 215                 tid <<= IMAP_TID_SHIFT;
 216                 tid &= IMAP_TID_UPA;
 217         } else {
 218                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 219                         unsigned long ver;
 220
 221                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 222                         if ((ver >> 32UL) == __JALAPENO_ID ||
 223                             (ver >> 32UL) == __SERRANO_ID) {
 224                                 tid = cpuid << IMAP_TID_SHIFT;
 225                                 tid &= IMAP_TID_JBUS;
 226                         } else {
 227                                 unsigned int a = cpuid & 0x1f;
 228                                 unsigned int n = (cpuid >> 5) & 0x1f;
 229
 230                                 tid = ((a << IMAP_AID_SHIFT) |
 231                                        (n << IMAP_NID_SHIFT));
 232                                 tid &= (IMAP_AID_SAFARI |
 233                                         IMAP_NID_SAFARI);
 234                         }
 235                 } else {
 236                         tid = cpuid << IMAP_TID_SHIFT;
 237                         tid &= IMAP_TID_UPA;
 238                 }
 239         }
 240
 241         return tid;
 242 }
 243
 244 struct irq_handler_data {
 245         unsigned long   iclr;
 246         unsigned long   imap;
 247
 248         void            (*pre_handler)(unsigned int, void *, void *);
 249         void            *arg1;
 250         void            *arg2;
 251 };
 252
 253 #ifdef CONFIG_SMP
 254 static int irq_choose_cpu(unsigned int irq, const struct cpumask *affinity)
 255 {
 256         cpumask_t mask;
 257         int cpuid;
 258
 259         cpumask_copy(&mask, affinity);
 260         if (cpus_equal(mask, cpu_online_map)) {
 261                 cpuid = map_to_cpu(irq);
 262         } else {
 263                 cpumask_t tmp;
 264
 265                 cpus_and(tmp, cpu_online_map, mask);
 266                 cpuid = cpus_empty(tmp) ? map_to_cpu(irq) : first_cpu(tmp);
 267         }
 268
 269         return cpuid;
 270 }
 271 #else
 272 #define irq_choose_cpu(irq, affinity)   \
 273         real_hard_smp_processor_id()
 274 #endif
 275
 276 static void sun4u_irq_enable(struct irq_data *data)
 277 {
 278         struct irq_handler_data *handler_data = data->handler_data;
 279
 280         if (likely(handler_data)) {
 281                 unsigned long cpuid, imap, val;
 282                 unsigned int tid;
 283
 284                 cpuid = irq_choose_cpu(data->irq, data->affinity);
 285                 imap = handler_data->imap;
 286
 287                 tid = sun4u_compute_tid(imap, cpuid);
 288
 289                 val = upa_readq(imap);
 290                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
 291                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
 292                 val |= tid | IMAP_VALID;
 293                 upa_writeq(val, imap);
 294                 upa_writeq(ICLR_IDLE, handler_data->iclr);
 295         }
 296 }
 297
 298 static int sun4u_set_affinity(struct irq_data *data,
 299                                const struct cpumask *mask, bool force)
 300 {
 301         struct irq_handler_data *handler_data = data->handler_data;
 302
 303         if (likely(handler_data)) {
 304                 unsigned long cpuid, imap, val;
 305                 unsigned int tid;
 306
 307                 cpuid = irq_choose_cpu(data->irq, mask);
 308                 imap = handler_data->imap;
 309
 310                 tid = sun4u_compute_tid(imap, cpuid);
 311
 312                 val = upa_readq(imap);
 313                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
 314                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
 315                 val |= tid | IMAP_VALID;
 316                 upa_writeq(val, imap);
 317                 upa_writeq(ICLR_IDLE, handler_data->iclr);
 318         }
 319
 320         return 0;
 321 }
 322
 323 /* Don't do anything.  The desc->status check for IRQ_DISABLED in
 324  * handler_irq() will skip the handler call and that will leave the
 325  * interrupt in the sent state.  The next ->enable() call will hit the
 326  * ICLR register to reset the state machine.
 327  *
 328  * This scheme is necessary, instead of clearing the Valid bit in the
 329  * IMAP register, to handle the case of IMAP registers being shared by
 330  * multiple INOs (and thus ICLR registers).  Since we use a different
 331  * virtual IRQ for each shared IMAP instance, the generic code thinks
 332  * there is only one user so it prematurely calls ->disable() on
 333  * free_irq().
 334  *
 335  * We have to provide an explicit ->disable() method instead of using
 336  * NULL to get the default.  The reason is that if the generic code
 337  * sees that, it also hooks up a default ->shutdown method which
 338  * invokes ->mask() which we do not want.  See irq_chip_set_defaults().
 339  */
 340 static void sun4u_irq_disable(struct irq_data *data)
 341 {
 342 }
 343
 344 static void sun4u_irq_eoi(struct irq_data *data)
 345 {
 346         struct irq_handler_data *handler_data = data->handler_data;
 347
 348         if (likely(handler_data))
 349                 upa_writeq(ICLR_IDLE, handler_data->iclr);
 350 }
 351
 352 static void sun4v_irq_enable(struct irq_data *data)
 353 {
 354         unsigned int ino = irq_table[data->irq].dev_ino;
 355         unsigned long cpuid = irq_choose_cpu(data->irq, data->affinity);
 356         int err;
 357
 358         err = sun4v_intr_settarget(ino, cpuid);
 359         if (err != HV_EOK)
 360                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 361                        "err(%d)\n", ino, cpuid, err);
 362         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 363         if (err != HV_EOK)
 364                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 365                        "err(%d)\n", ino, err);
 366         err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 367         if (err != HV_EOK)
 368                 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
 369                        ino, err);
 370 }
 371
 372 static int sun4v_set_affinity(struct irq_data *data,
 373                                const struct cpumask *mask, bool force)
 374 {
 375         unsigned int ino = irq_table[data->irq].dev_ino;
 376         unsigned long cpuid = irq_choose_cpu(data->irq, mask);
 377         int err;
 378
 379         err = sun4v_intr_settarget(ino, cpuid);
 380         if (err != HV_EOK)
 381                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 382                        "err(%d)\n", ino, cpuid, err);
 383
 384         return 0;
 385 }
 386
 387 static void sun4v_irq_disable(struct irq_data *data)
 388 {
 389         unsigned int ino = irq_table[data->irq].dev_ino;
 390         int err;
 391
 392         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 393         if (err != HV_EOK)
 394                 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
 395                        "err(%d)\n", ino, err);
 396 }
 397
 398 static void sun4v_irq_eoi(struct irq_data *data)
 399 {
 400         unsigned int ino = irq_table[data->irq].dev_ino;
 401         int err;
 402
 403         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 404         if (err != HV_EOK)
 405                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 406                        "err(%d)\n", ino, err);
 407 }
 408
 409 static void sun4v_virq_enable(struct irq_data *data)
 410 {
 411         unsigned long cpuid, dev_handle, dev_ino;
 412         int err;
 413
 414         cpuid = irq_choose_cpu(data->irq, data->affinity);
 415
 416         dev_handle = irq_table[data->irq].dev_handle;
 417         dev_ino = irq_table[data->irq].dev_ino;
 418
 419         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 420         if (err != HV_EOK)
 421                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 422                        "err(%d)\n",
 423                        dev_handle, dev_ino, cpuid, err);
 424         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 425                                     HV_INTR_STATE_IDLE);
 426         if (err != HV_EOK)
 427                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 428                        "HV_INTR_STATE_IDLE): err(%d)\n",
 429                        dev_handle, dev_ino, err);
 430         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 431                                     HV_INTR_ENABLED);
 432         if (err != HV_EOK)
 433                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 434                        "HV_INTR_ENABLED): err(%d)\n",
 435                        dev_handle, dev_ino, err);
 436 }
 437
 438 static int sun4v_virt_set_affinity(struct irq_data *data,
 439                                     const struct cpumask *mask, bool force)
 440 {
 441         unsigned long cpuid, dev_handle, dev_ino;
 442         int err;
 443
 444         cpuid = irq_choose_cpu(data->irq, mask);
 445
 446         dev_handle = irq_table[data->irq].dev_handle;
 447         dev_ino = irq_table[data->irq].dev_ino;
 448
 449         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 450         if (err != HV_EOK)
 451                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 452                        "err(%d)\n",
 453                        dev_handle, dev_ino, cpuid, err);
 454
 455         return 0;
 456 }
 457
 458 static void sun4v_virq_disable(struct irq_data *data)
 459 {
 460         unsigned long dev_handle, dev_ino;
 461         int err;
 462
 463         dev_handle = irq_table[data->irq].dev_handle;
 464         dev_ino = irq_table[data->irq].dev_ino;
 465
 466         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 467                                     HV_INTR_DISABLED);
 468         if (err != HV_EOK)
 469                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 470                        "HV_INTR_DISABLED): err(%d)\n",
 471                        dev_handle, dev_ino, err);
 472 }
 473
 474 static void sun4v_virq_eoi(struct irq_data *data)
 475 {
 476         unsigned long dev_handle, dev_ino;
 477         int err;
 478
 479         dev_handle = irq_table[data->irq].dev_handle;
 480         dev_ino = irq_table[data->irq].dev_ino;
 481
 482         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 483                                     HV_INTR_STATE_IDLE);
 484         if (err != HV_EOK)
 485                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 486                        "HV_INTR_STATE_IDLE): err(%d)\n",
 487                        dev_handle, dev_ino, err);
 488 }
 489
 490 static struct irq_chip sun4u_irq = {
 491         .name                   = "sun4u",
 492         .irq_enable             = sun4u_irq_enable,
 493         .irq_disable            = sun4u_irq_disable,
 494         .irq_eoi                = sun4u_irq_eoi,
 495         .irq_set_affinity       = sun4u_set_affinity,
 496         .flags                  = IRQCHIP_EOI_IF_HANDLED,
 497 };
 498
 499 static struct irq_chip sun4v_irq = {
 500         .name                   = "sun4v",
 501         .irq_enable             = sun4v_irq_enable,
 502         .irq_disable            = sun4v_irq_disable,
 503         .irq_eoi                = sun4v_irq_eoi,
 504         .irq_set_affinity       = sun4v_set_affinity,
 505         .flags                  = IRQCHIP_EOI_IF_HANDLED,
 506 };
 507
 508 static struct irq_chip sun4v_virq = {
 509         .name                   = "vsun4v",
 510         .irq_enable             = sun4v_virq_enable,
 511         .irq_disable            = sun4v_virq_disable,
 512         .irq_eoi                = sun4v_virq_eoi,
 513         .irq_set_affinity       = sun4v_virt_set_affinity,
 514         .flags                  = IRQCHIP_EOI_IF_HANDLED,
 515 };
 516
 517 static void pre_flow_handler(struct irq_data *d)
 518 {
 519         struct irq_handler_data *handler_data = irq_data_get_irq_handler_data(d);
 520         unsigned int ino = irq_table[d->irq].dev_ino;
 521
 522         handler_data->pre_handler(ino, handler_data->arg1, handler_data->arg2);
 523 }
 524
 525 void irq_install_pre_handler(int irq,
 526                              void (*func)(unsigned int, void *, void *),
 527                              void *arg1, void *arg2)
 528 {
 529         struct irq_handler_data *handler_data = irq_get_handler_data(irq);
 530
 531         handler_data->pre_handler = func;
 532         handler_data->arg1 = arg1;
 533         handler_data->arg2 = arg2;
 534
 535         __irq_set_preflow_handler(irq, pre_flow_handler);
 536 }
 537
 538 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
 539 {
 540         struct ino_bucket *bucket;
 541         struct irq_handler_data *handler_data;
 542         unsigned int irq;
 543         int ino;
 544
 545         BUG_ON(tlb_type == hypervisor);
 546
 547         ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 548         bucket = &ivector_table[ino];
 549         irq = bucket_get_irq(__pa(bucket));
 550         if (!irq) {
 551                 irq = irq_alloc(0, ino);
 552                 bucket_set_irq(__pa(bucket), irq);
 553                 irq_set_chip_and_handler_name(irq, &sun4u_irq,
 554                                               handle_fasteoi_irq, "IVEC");
 555         }
 556
 557         handler_data = irq_get_handler_data(irq);
 558         if (unlikely(handler_data))
 559                 goto out;
 560
 561         handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 562         if (unlikely(!handler_data)) {
 563                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 564                 prom_halt();
 565         }
 566         irq_set_handler_data(irq, handler_data);
 567
 568         handler_data->imap  = imap;
 569         handler_data->iclr  = iclr;
 570
 571 out:
 572         return irq;
 573 }
 574
 575 static unsigned int sun4v_build_common(unsigned long sysino,
 576                                        struct irq_chip *chip)
 577 {
 578         struct ino_bucket *bucket;
 579         struct irq_handler_data *handler_data;
 580         unsigned int irq;
 581
 582         BUG_ON(tlb_type != hypervisor);
 583
 584         bucket = &ivector_table[sysino];
 585         irq = bucket_get_irq(__pa(bucket));
 586         if (!irq) {
 587                 irq = irq_alloc(0, sysino);
 588                 bucket_set_irq(__pa(bucket), irq);
 589                 irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq,
 590                                               "IVEC");
 591         }
 592
 593         handler_data = irq_get_handler_data(irq);
 594         if (unlikely(handler_data))
 595                 goto out;
 596
 597         handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 598         if (unlikely(!handler_data)) {
 599                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 600                 prom_halt();
 601         }
 602         irq_set_handler_data(irq, handler_data);
 603
 604         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 605          * is done by hypervisor calls on sun4v platforms, not by direct
 606          * register accesses.
 607          */
 608         handler_data->imap = ~0UL;
 609         handler_data->iclr = ~0UL;
 610
 611 out:
 612         return irq;
 613 }
 614
 615 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
 616 {
 617         unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
 618
 619         return sun4v_build_common(sysino, &sun4v_irq);
 620 }
 621
 622 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
 623 {
 624         struct irq_handler_data *handler_data;
 625         unsigned long hv_err, cookie;
 626         struct ino_bucket *bucket;
 627         unsigned int irq;
 628
 629         bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
 630         if (unlikely(!bucket))
 631                 return 0;
 632
 633         /* The only reference we store to the IRQ bucket is
 634          * by physical address which kmemleak can't see, tell
 635          * it that this object explicitly is not a leak and
 636          * should be scanned.
 637          */
 638         kmemleak_not_leak(bucket);
 639
 640         __flush_dcache_range((unsigned long) bucket,
 641                              ((unsigned long) bucket +
 642                               sizeof(struct ino_bucket)));
 643
 644         irq = irq_alloc(devhandle, devino);
 645         bucket_set_irq(__pa(bucket), irq);
 646
 647         irq_set_chip_and_handler_name(irq, &sun4v_virq, handle_fasteoi_irq,
 648                                       "IVEC");
 649
 650         handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 651         if (unlikely(!handler_data))
 652                 return 0;
 653
 654         /* In order to make the LDC channel startup sequence easier,
 655          * especially wrt. locking, we do not let request_irq() enable
 656          * the interrupt.
 657          */
 658         irq_set_status_flags(irq, IRQ_NOAUTOEN);
 659         irq_set_handler_data(irq, handler_data);
 660
 661         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 662          * is done by hypervisor calls on sun4v platforms, not by direct
 663          * register accesses.
 664          */
 665         handler_data->imap = ~0UL;
 666         handler_data->iclr = ~0UL;
 667
 668         cookie = ~__pa(bucket);
 669         hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie);
 670         if (hv_err) {
 671                 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
 672                             "err=%lu\n", devhandle, devino, hv_err);
 673                 prom_halt();
 674         }
 675
 676         return irq;
 677 }
 678
 679 void ack_bad_irq(unsigned int irq)
 680 {
 681         unsigned int ino = irq_table[irq].dev_ino;
 682
 683         if (!ino)
 684                 ino = 0xdeadbeef;
 685
 686         printk(KERN_CRIT "Unexpected IRQ from ino[%x] irq[%u]\n",
 687                ino, irq);
 688 }
 689
 690 void *hardirq_stack[NR_CPUS];
 691 void *softirq_stack[NR_CPUS];
 692
 693 void __irq_entry handler_irq(int pil, struct pt_regs *regs)
 694 {
 695         unsigned long pstate, bucket_pa;
 696         struct pt_regs *old_regs;
 697         void *orig_sp;
 698
 699         clear_softint(1 << pil);
 700
 701         old_regs = set_irq_regs(regs);
 702         irq_enter();
 703
 704         /* Grab an atomic snapshot of the pending IVECs.  */
 705         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
 706                              "wrpr      %0, %3, %%pstate\n\t"
 707                              "ldx       [%2], %1\n\t"
 708                              "stx       %%g0, [%2]\n\t"
 709                              "wrpr      %0, 0x0, %%pstate\n\t"
 710                              : "=&r" (pstate), "=&r" (bucket_pa)
 711                              : "r" (irq_work_pa(smp_processor_id())),
 712                                "i" (PSTATE_IE)
 713                              : "memory");
 714
 715         orig_sp = set_hardirq_stack();
 716
 717         while (bucket_pa) {
 718                 unsigned long next_pa;
 719                 unsigned int irq;
 720
 721                 next_pa = bucket_get_chain_pa(bucket_pa);
 722                 irq = bucket_get_irq(bucket_pa);
 723                 bucket_clear_chain_pa(bucket_pa);
 724
 725                 generic_handle_irq(irq);
 726
 727                 bucket_pa = next_pa;
 728         }
 729
 730         restore_hardirq_stack(orig_sp);
 731
 732         irq_exit();
 733         set_irq_regs(old_regs);
 734 }
 735
 736 void do_softirq(void)
 737 {
 738         unsigned long flags;
 739
 740         if (in_interrupt())
 741                 return;
 742
 743         local_irq_save(flags);
 744
 745         if (local_softirq_pending()) {
 746                 void *orig_sp, *sp = softirq_stack[smp_processor_id()];
 747
 748                 sp += THREAD_SIZE - 192 - STACK_BIAS;
 749
 750                 __asm__ __volatile__("mov %%sp, %0\n\t"
 751                                      "mov %1, %%sp"
 752                                      : "=&r" (orig_sp)
 753                                      : "r" (sp));
 754                 __do_softirq();
 755                 __asm__ __volatile__("mov %0, %%sp"
 756                                      : : "r" (orig_sp));
 757         }
 758
 759         local_irq_restore(flags);
 760 }
 761
 762 #ifdef CONFIG_HOTPLUG_CPU
 763 void fixup_irqs(void)
 764 {
 765         unsigned int irq;
 766
 767         for (irq = 0; irq < NR_IRQS; irq++) {
 768                 struct irq_desc *desc = irq_to_desc(irq);
 769                 struct irq_data *data = irq_desc_get_irq_data(desc);
 770                 unsigned long flags;
 771
 772                 raw_spin_lock_irqsave(&desc->lock, flags);
 773                 if (desc->action && !irqd_is_per_cpu(data)) {
 774                         if (data->chip->irq_set_affinity)
 775                                 data->chip->irq_set_affinity(data,
 776                                                              data->affinity,
 777                                                              false);
 778                 }
 779                 raw_spin_unlock_irqrestore(&desc->lock, flags);
 780         }
 781
 782         tick_ops->disable_irq();
 783 }
 784 #endif
 785
 786 struct sun5_timer {
 787         u64     count0;
 788         u64     limit0;
 789         u64     count1;
 790         u64     limit1;
 791 };
 792
 793 static struct sun5_timer *prom_timers;
 794 static u64 prom_limit0, prom_limit1;
 795
 796 static void map_prom_timers(void)
 797 {
 798         struct device_node *dp;
 799         const unsigned int *addr;
 800
 801         /* PROM timer node hangs out in the top level of device siblings... */
 802         dp = of_find_node_by_path("/");
 803         dp = dp->child;
 804         while (dp) {
 805                 if (!strcmp(dp->name, "counter-timer"))
 806                         break;
 807                 dp = dp->sibling;
 808         }
 809
 810         /* Assume if node is not present, PROM uses different tick mechanism
 811          * which we should not care about.
 812          */
 813         if (!dp) {
 814                 prom_timers = (struct sun5_timer *) 0;
 815                 return;
 816         }
 817
 818         /* If PROM is really using this, it must be mapped by him. */
 819         addr = of_get_property(dp, "address", NULL);
 820         if (!addr) {
 821                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 822                 prom_timers = (struct sun5_timer *) 0;
 823                 return;
 824         }
 825         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 826 }
 827
 828 static void kill_prom_timer(void)
 829 {
 830         if (!prom_timers)
 831                 return;
 832
 833         /* Save them away for later. */
 834         prom_limit0 = prom_timers->limit0;
 835         prom_limit1 = prom_timers->limit1;
 836
 837         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 838          * We turn both off here just to be paranoid.
 839          */
 840         prom_timers->limit0 = 0;
 841         prom_timers->limit1 = 0;
 842
 843         /* Wheee, eat the interrupt packet too... */
 844         __asm__ __volatile__(
 845 "       mov     0x40, %%g2\n"
 846 "       ldxa    [%%g0] %0, %%g1\n"
 847 "       ldxa    [%%g2] %1, %%g1\n"
 848 "       stxa    %%g0, [%%g0] %0\n"
 849 "       membar  #Sync\n"
 850         : /* no outputs */
 851         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 852         : "g1", "g2");
 853 }
 854
 855 void notrace init_irqwork_curcpu(void)
 856 {
 857         int cpu = hard_smp_processor_id();
 858
 859         trap_block[cpu].irq_worklist_pa = 0UL;
 860 }
 861
 862 /* Please be very careful with register_one_mondo() and
 863  * sun4v_register_mondo_queues().
 864  *
 865  * On SMP this gets invoked from the CPU trampoline before
 866  * the cpu has fully taken over the trap table from OBP,
 867  * and it's kernel stack + %g6 thread register state is
 868  * not fully cooked yet.
 869  *
 870  * Therefore you cannot make any OBP calls, not even prom_printf,
 871  * from these two routines.
 872  */
 873 static void __cpuinit notrace register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
 874 {
 875         unsigned long num_entries = (qmask + 1) / 64;
 876         unsigned long status;
 877
 878         status = sun4v_cpu_qconf(type, paddr, num_entries);
 879         if (status != HV_EOK) {
 880                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
 881                             "err %lu\n", type, paddr, num_entries, status);
 882                 prom_halt();
 883         }
 884 }
 885
 886 void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu)
 887 {
 888         struct trap_per_cpu *tb = &trap_block[this_cpu];
 889
 890         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
 891                            tb->cpu_mondo_qmask);
 892         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
 893                            tb->dev_mondo_qmask);
 894         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
 895                            tb->resum_qmask);
 896         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
 897                            tb->nonresum_qmask);
 898 }
 899
 900 /* Each queue region must be a power of 2 multiple of 64 bytes in
 901  * size.  The base real address must be aligned to the size of the
 902  * region.  Thus, an 8KB queue must be 8KB aligned, for example.
 903  */
 904 static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask)
 905 {
 906         unsigned long size = PAGE_ALIGN(qmask + 1);
 907         unsigned long order = get_order(size);
 908         unsigned long p;
 909
 910         p = __get_free_pages(GFP_KERNEL, order);
 911         if (!p) {
 912                 prom_printf("SUN4V: Error, cannot allocate queue.\n");
 913                 prom_halt();
 914         }
 915
 916         *pa_ptr = __pa(p);
 917 }
 918
 919 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
 920 {
 921 #ifdef CONFIG_SMP
 922         unsigned long page;
 923
 924         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
 925
 926         page = get_zeroed_page(GFP_KERNEL);
 927         if (!page) {
 928                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
 929                 prom_halt();
 930         }
 931
 932         tb->cpu_mondo_block_pa = __pa(page);
 933         tb->cpu_list_pa = __pa(page + 64);
 934 #endif
 935 }
 936
 937 /* Allocate mondo and error queues for all possible cpus.  */
 938 static void __init sun4v_init_mondo_queues(void)
 939 {
 940         int cpu;
 941
 942         for_each_possible_cpu(cpu) {
 943                 struct trap_per_cpu *tb = &trap_block[cpu];
 944
 945                 alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
 946                 alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
 947                 alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask);
 948                 alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask);
 949                 alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
 950                 alloc_one_queue(&tb->nonresum_kernel_buf_pa,
 951                                 tb->nonresum_qmask);
 952         }
 953 }
 954
 955 static void __init init_send_mondo_info(void)
 956 {
 957         int cpu;
 958
 959         for_each_possible_cpu(cpu) {
 960                 struct trap_per_cpu *tb = &trap_block[cpu];
 961
 962                 init_cpu_send_mondo_info(tb);
 963         }
 964 }
 965
 966 static struct irqaction timer_irq_action = {
 967         .name = "timer",
 968 };
 969
 970 /* Only invoked on boot processor. */
 971 void __init init_IRQ(void)
 972 {
 973         unsigned long size;
 974
 975         map_prom_timers();
 976         kill_prom_timer();
 977
 978         size = sizeof(struct ino_bucket) * NUM_IVECS;
 979         ivector_table = kzalloc(size, GFP_KERNEL);
 980         if (!ivector_table) {
 981                 prom_printf("Fatal error, cannot allocate ivector_table\n");
 982                 prom_halt();
 983         }
 984         __flush_dcache_range((unsigned long) ivector_table,
 985                              ((unsigned long) ivector_table) + size);
 986
 987         ivector_table_pa = __pa(ivector_table);
 988
 989         if (tlb_type == hypervisor)
 990                 sun4v_init_mondo_queues();
 991
 992         init_send_mondo_info();
 993
 994         if (tlb_type == hypervisor) {
 995                 /* Load up the boot cpu's entries.  */
 996                 sun4v_register_mondo_queues(hard_smp_processor_id());
 997         }
 998
 999         /* We need to clear any IRQ's pending in the soft interrupt
1000          * registers, a spurious one could be left around from the
1001          * PROM timer which we just disabled.
1002          */
1003         clear_softint(get_softint());
1004
1005         /* Now that ivector table is initialized, it is safe
1006          * to receive IRQ vector traps.  We will normally take
1007          * one or two right now, in case some device PROM used
1008          * to boot us wants to speak to us.  We just ignore them.
1009          */
1010         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1011                              "or        %%g1, %0, %%g1\n\t"
1012                              "wrpr      %%g1, 0x0, %%pstate"
1013                              : /* No outputs */
1014                              : "i" (PSTATE_IE)
1015                              : "g1");
1016
1017         irq_to_desc(0)->action = &timer_irq_action;
1018 }