2 * Freescale LBC and UPM routines.
4 * Copyright © 2007-2008 MontaVista Software, Inc.
5 * Copyright © 2010 Freescale Semiconductor
7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 * Author: Jack Lan <Jack.Lan@freescale.com>
9 * Author: Roy Zang <tie-fei.zang@freescale.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/init.h>
18 #include <linux/export.h>
19 #include <linux/kernel.h>
20 #include <linux/compiler.h>
21 #include <linux/spinlock.h>
22 #include <linux/types.h>
25 #include <linux/slab.h>
26 #include <linux/sched.h>
27 #include <linux/platform_device.h>
28 #include <linux/interrupt.h>
29 #include <linux/mod_devicetable.h>
31 #include <asm/fsl_lbc.h>
33 static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
34 struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
35 EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
38 * fsl_lbc_addr - convert the base address
39 * @addr_base: base address of the memory bank
41 * This function converts a base address of lbc into the right format for the
42 * BR register. If the SOC has eLBC then it returns 32bit physical address
43 * else it convers a 34bit local bus physical address to correct format of
44 * 32bit address for BR register (Example: MPC8641).
46 u32 fsl_lbc_addr(phys_addr_t addr_base)
48 struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
49 u32 addr = addr_base & 0xffff8000;
51 if (of_device_is_compatible(np, "fsl,elbc"))
54 return addr | ((addr_base & 0x300000000ull) >> 19);
56 EXPORT_SYMBOL(fsl_lbc_addr);
59 * fsl_lbc_find - find Localbus bank
60 * @addr_base: base address of the memory bank
62 * This function walks LBC banks comparing "Base address" field of the BR
63 * registers with the supplied addr_base argument. When bases match this
64 * function returns bank number (starting with 0), otherwise it returns
65 * appropriate errno value.
67 int fsl_lbc_find(phys_addr_t addr_base)
70 struct fsl_lbc_regs __iomem *lbc;
72 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
75 lbc = fsl_lbc_ctrl_dev->regs;
76 for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
77 u32 br = in_be32(&lbc->bank[i].br);
78 u32 or = in_be32(&lbc->bank[i].or);
80 if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
86 EXPORT_SYMBOL(fsl_lbc_find);
89 * fsl_upm_find - find pre-programmed UPM via base address
90 * @addr_base: base address of the memory bank controlled by the UPM
91 * @upm: pointer to the allocated fsl_upm structure
93 * This function fills fsl_upm structure so you can use it with the rest of
94 * UPM API. On success this function returns 0, otherwise it returns
95 * appropriate errno value.
97 int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
101 struct fsl_lbc_regs __iomem *lbc;
103 bank = fsl_lbc_find(addr_base);
107 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
110 lbc = fsl_lbc_ctrl_dev->regs;
111 br = in_be32(&lbc->bank[bank].br);
113 switch (br & BR_MSEL) {
115 upm->mxmr = &lbc->mamr;
118 upm->mxmr = &lbc->mbmr;
121 upm->mxmr = &lbc->mcmr;
127 switch (br & BR_PS) {
143 EXPORT_SYMBOL(fsl_upm_find);
146 * fsl_upm_run_pattern - actually run an UPM pattern
147 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
148 * @io_base: remapped pointer to where memory access should happen
149 * @mar: MAR register content during pattern execution
151 * This function triggers dummy write to the memory specified by the io_base,
152 * thus UPM pattern actually executed. Note that mar usage depends on the
153 * pre-programmed AMX bits in the UPM RAM.
155 int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
160 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
163 spin_lock_irqsave(&fsl_lbc_lock, flags);
165 out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
167 switch (upm->width) {
172 out_be16(io_base, 0x0);
175 out_be32(io_base, 0x0);
182 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
186 EXPORT_SYMBOL(fsl_upm_run_pattern);
188 static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
189 struct device_node *node)
191 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
193 /* clear event registers */
194 setbits32(&lbc->ltesr, LTESR_CLEAR);
195 out_be32(&lbc->lteatr, 0);
196 out_be32(&lbc->ltear, 0);
197 out_be32(&lbc->lteccr, LTECCR_CLEAR);
198 out_be32(&lbc->ltedr, LTEDR_ENABLE);
200 /* Set the monitor timeout value to the maximum for erratum A001 */
201 if (of_device_is_compatible(node, "fsl,elbc"))
202 clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
208 * NOTE: This interrupt is used to report localbus events of various kinds,
209 * such as transaction errors on the chipselects.
212 static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
214 struct fsl_lbc_ctrl *ctrl = data;
215 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
219 spin_lock_irqsave(&fsl_lbc_lock, flags);
220 status = in_be32(&lbc->ltesr);
222 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
226 out_be32(&lbc->ltesr, LTESR_CLEAR);
227 out_be32(&lbc->lteatr, 0);
228 out_be32(&lbc->ltear, 0);
229 ctrl->irq_status = status;
231 if (status & LTESR_BM)
232 dev_err(ctrl->dev, "Local bus monitor time-out: "
233 "LTESR 0x%08X\n", status);
234 if (status & LTESR_WP)
235 dev_err(ctrl->dev, "Write protect error: "
236 "LTESR 0x%08X\n", status);
237 if (status & LTESR_ATMW)
238 dev_err(ctrl->dev, "Atomic write error: "
239 "LTESR 0x%08X\n", status);
240 if (status & LTESR_ATMR)
241 dev_err(ctrl->dev, "Atomic read error: "
242 "LTESR 0x%08X\n", status);
243 if (status & LTESR_CS)
244 dev_err(ctrl->dev, "Chip select error: "
245 "LTESR 0x%08X\n", status);
246 if (status & LTESR_FCT) {
247 dev_err(ctrl->dev, "FCM command time-out: "
248 "LTESR 0x%08X\n", status);
250 wake_up(&ctrl->irq_wait);
252 if (status & LTESR_PAR) {
253 dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
254 "LTESR 0x%08X\n", status);
256 wake_up(&ctrl->irq_wait);
258 if (status & LTESR_CC) {
260 wake_up(&ctrl->irq_wait);
262 if (status & ~LTESR_MASK)
263 dev_err(ctrl->dev, "Unknown error: "
264 "LTESR 0x%08X\n", status);
265 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
272 * called by device layer when it finds a device matching
273 * one our driver can handled. This code allocates all of
274 * the resources needed for the controller only. The
275 * resources for the NAND banks themselves are allocated
276 * in the chip probe function.
279 static int fsl_lbc_ctrl_probe(struct platform_device *dev)
283 if (!dev->dev.of_node) {
284 dev_err(&dev->dev, "Device OF-Node is NULL");
288 fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
289 if (!fsl_lbc_ctrl_dev)
292 dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
294 spin_lock_init(&fsl_lbc_ctrl_dev->lock);
295 init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
297 fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
298 if (!fsl_lbc_ctrl_dev->regs) {
299 dev_err(&dev->dev, "failed to get memory region\n");
304 fsl_lbc_ctrl_dev->irq[0] = irq_of_parse_and_map(dev->dev.of_node, 0);
305 if (!fsl_lbc_ctrl_dev->irq[0]) {
306 dev_err(&dev->dev, "failed to get irq resource\n");
311 fsl_lbc_ctrl_dev->dev = &dev->dev;
313 ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, dev->dev.of_node);
317 ret = request_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_irq, 0,
318 "fsl-lbc", fsl_lbc_ctrl_dev);
320 dev_err(&dev->dev, "failed to install irq (%d)\n",
321 fsl_lbc_ctrl_dev->irq[0]);
322 ret = fsl_lbc_ctrl_dev->irq[0];
326 fsl_lbc_ctrl_dev->irq[1] = irq_of_parse_and_map(dev->dev.of_node, 1);
327 if (fsl_lbc_ctrl_dev->irq[1]) {
328 ret = request_irq(fsl_lbc_ctrl_dev->irq[1], fsl_lbc_ctrl_irq,
329 IRQF_SHARED, "fsl-lbc-err", fsl_lbc_ctrl_dev);
331 dev_err(&dev->dev, "failed to install irq (%d)\n",
332 fsl_lbc_ctrl_dev->irq[1]);
333 ret = fsl_lbc_ctrl_dev->irq[1];
338 /* Enable interrupts for any detected events */
339 out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE);
344 free_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_dev);
346 iounmap(fsl_lbc_ctrl_dev->regs);
347 kfree(fsl_lbc_ctrl_dev);
348 fsl_lbc_ctrl_dev = NULL;
352 #ifdef CONFIG_SUSPEND
354 /* save lbc registers */
355 static int fsl_lbc_suspend(struct platform_device *pdev, pm_message_t state)
357 struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
358 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
360 ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL);
361 if (!ctrl->saved_regs)
364 _memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs));
368 /* restore lbc registers */
369 static int fsl_lbc_resume(struct platform_device *pdev)
371 struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
372 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
374 if (ctrl->saved_regs) {
375 _memcpy_toio(lbc, ctrl->saved_regs,
376 sizeof(struct fsl_lbc_regs));
377 kfree(ctrl->saved_regs);
378 ctrl->saved_regs = NULL;
382 #endif /* CONFIG_SUSPEND */
384 static const struct of_device_id fsl_lbc_match[] = {
385 { .compatible = "fsl,elbc", },
386 { .compatible = "fsl,pq3-localbus", },
387 { .compatible = "fsl,pq2-localbus", },
388 { .compatible = "fsl,pq2pro-localbus", },
392 static struct platform_driver fsl_lbc_ctrl_driver = {
395 .of_match_table = fsl_lbc_match,
397 .probe = fsl_lbc_ctrl_probe,
398 #ifdef CONFIG_SUSPEND
399 .suspend = fsl_lbc_suspend,
400 .resume = fsl_lbc_resume,
404 static int __init fsl_lbc_init(void)
406 return platform_driver_register(&fsl_lbc_ctrl_driver);
408 subsys_initcall(fsl_lbc_init);