arch/mips/netlogic/xlp/nlm_hal.c

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/types.h>
  36 #include <linux/kernel.h>
  37 #include <linux/mm.h>
  38 #include <linux/delay.h>
  39
  40 #include <asm/mipsregs.h>
  41 #include <asm/time.h>
  42
  43 #include <asm/netlogic/common.h>
  44 #include <asm/netlogic/haldefs.h>
  45 #include <asm/netlogic/xlp-hal/iomap.h>
  46 #include <asm/netlogic/xlp-hal/xlp.h>
  47 #include <asm/netlogic/xlp-hal/bridge.h>
  48 #include <asm/netlogic/xlp-hal/pic.h>
  49 #include <asm/netlogic/xlp-hal/sys.h>
  50
  51 /* Main initialization */
  52 void nlm_node_init(int node)
  53 {
  54         struct nlm_soc_info *nodep;
  55
  56         nodep = nlm_get_node(node);
  57         if (node == 0)
  58                 nodep->coremask = 1;    /* node 0, boot cpu */
  59         nodep->sysbase = nlm_get_sys_regbase(node);
  60         nodep->picbase = nlm_get_pic_regbase(node);
  61         nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
  62         if (cpu_is_xlp9xx())
  63                 nodep->socbus = xlp9xx_get_socbus(node);
  64         else
  65                 nodep->socbus = 0;
  66         spin_lock_init(&nodep->piclock);
  67 }
  68
  69 static int xlp9xx_irq_to_irt(int irq)
  70 {
  71         switch (irq) {
  72         case PIC_GPIO_IRQ:
  73                 return 12;
  74         case PIC_9XX_XHCI_0_IRQ:
  75                 return 114;
  76         case PIC_9XX_XHCI_1_IRQ:
  77                 return 115;
  78         case PIC_UART_0_IRQ:
  79                 return 133;
  80         case PIC_UART_1_IRQ:
  81                 return 134;
  82         case PIC_SATA_IRQ:
  83                 return 143;
  84         case PIC_SPI_IRQ:
  85                 return 152;
  86         case PIC_MMC_IRQ:
  87                 return 153;
  88         case PIC_PCIE_LINK_LEGACY_IRQ(0):
  89         case PIC_PCIE_LINK_LEGACY_IRQ(1):
  90         case PIC_PCIE_LINK_LEGACY_IRQ(2):
  91         case PIC_PCIE_LINK_LEGACY_IRQ(3):
  92                 return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE;
  93         }
  94         return -1;
  95 }
  96
  97 static int xlp_irq_to_irt(int irq)
  98 {
  99         uint64_t pcibase;
 100         int devoff, irt;
 101
 102         devoff = 0;
 103         switch (irq) {
 104         case PIC_UART_0_IRQ:
 105                 devoff = XLP_IO_UART0_OFFSET(0);
 106                 break;
 107         case PIC_UART_1_IRQ:
 108                 devoff = XLP_IO_UART1_OFFSET(0);
 109                 break;
 110         case PIC_MMC_IRQ:
 111                 devoff = XLP_IO_MMC_OFFSET(0);
 112                 break;
 113         case PIC_I2C_0_IRQ:     /* I2C will be fixed up */
 114         case PIC_I2C_1_IRQ:
 115         case PIC_I2C_2_IRQ:
 116         case PIC_I2C_3_IRQ:
 117                 if (cpu_is_xlpii())
 118                         devoff = XLP2XX_IO_I2C_OFFSET(0);
 119                 else
 120                         devoff = XLP_IO_I2C0_OFFSET(0);
 121                 break;
 122         case PIC_SATA_IRQ:
 123                 devoff = XLP_IO_SATA_OFFSET(0);
 124                 break;
 125         case PIC_GPIO_IRQ:
 126                 devoff = XLP_IO_GPIO_OFFSET(0);
 127                 break;
 128         case PIC_NAND_IRQ:
 129                 devoff = XLP_IO_NAND_OFFSET(0);
 130                 break;
 131         case PIC_SPI_IRQ:
 132                 devoff = XLP_IO_SPI_OFFSET(0);
 133                 break;
 134         default:
 135                 if (cpu_is_xlpii()) {
 136                         switch (irq) {
 137                                 /* XLP2XX has three XHCI USB controller */
 138                         case PIC_2XX_XHCI_0_IRQ:
 139                                 devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
 140                                 break;
 141                         case PIC_2XX_XHCI_1_IRQ:
 142                                 devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
 143                                 break;
 144                         case PIC_2XX_XHCI_2_IRQ:
 145                                 devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
 146                                 break;
 147                         }
 148                 } else {
 149                         switch (irq) {
 150                         case PIC_EHCI_0_IRQ:
 151                                 devoff = XLP_IO_USB_EHCI0_OFFSET(0);
 152                                 break;
 153                         case PIC_EHCI_1_IRQ:
 154                                 devoff = XLP_IO_USB_EHCI1_OFFSET(0);
 155                                 break;
 156                         case PIC_OHCI_0_IRQ:
 157                                 devoff = XLP_IO_USB_OHCI0_OFFSET(0);
 158                                 break;
 159                         case PIC_OHCI_1_IRQ:
 160                                 devoff = XLP_IO_USB_OHCI1_OFFSET(0);
 161                                 break;
 162                         case PIC_OHCI_2_IRQ:
 163                                 devoff = XLP_IO_USB_OHCI2_OFFSET(0);
 164                                 break;
 165                         case PIC_OHCI_3_IRQ:
 166                                 devoff = XLP_IO_USB_OHCI3_OFFSET(0);
 167                                 break;
 168                         }
 169                 }
 170         }
 171
 172         if (devoff != 0) {
 173                 uint32_t val;
 174
 175                 pcibase = nlm_pcicfg_base(devoff);
 176                 val = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG);
 177                 if (val == 0xffffffff) {
 178                         irt = -1;
 179                 } else {
 180                         irt = val & 0xffff;
 181                         /* HW weirdness, I2C IRT entry has to be fixed up */
 182                         switch (irq) {
 183                         case PIC_I2C_1_IRQ:
 184                                 irt = irt + 1; break;
 185                         case PIC_I2C_2_IRQ:
 186                                 irt = irt + 2; break;
 187                         case PIC_I2C_3_IRQ:
 188                                 irt = irt + 3; break;
 189                         }
 190                 }
 191         } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
 192                         irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
 193                 /* HW bug, PCI IRT entries are bad on early silicon, fix */
 194                 irt = PIC_IRT_PCIE_LINK_INDEX(irq -
 195                                         PIC_PCIE_LINK_LEGACY_IRQ_BASE);
 196         } else {
 197                 irt = -1;
 198         }
 199         return irt;
 200 }
 201
 202 int nlm_irq_to_irt(int irq)
 203 {
 204         /* return -2 for irqs without 1-1 mapping */
 205         if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) && irq <= PIC_PCIE_LINK_MSI_IRQ(3))
 206                 return -2;
 207         if (irq >= PIC_PCIE_MSIX_IRQ(0) && irq <= PIC_PCIE_MSIX_IRQ(3))
 208                 return -2;
 209
 210         if (cpu_is_xlp9xx())
 211                 return xlp9xx_irq_to_irt(irq);
 212         else
 213                 return xlp_irq_to_irt(irq);
 214 }
 215
 216 static unsigned int nlm_xlp2_get_core_frequency(int node, int core)
 217 {
 218         unsigned int pll_post_div, ctrl_val0, ctrl_val1, denom;
 219         uint64_t num, sysbase, clockbase;
 220
 221         if (cpu_is_xlp9xx()) {
 222                 clockbase = nlm_get_clock_regbase(node);
 223                 ctrl_val0 = nlm_read_sys_reg(clockbase,
 224                                         SYS_9XX_CPU_PLL_CTRL0(core));
 225                 ctrl_val1 = nlm_read_sys_reg(clockbase,
 226                                         SYS_9XX_CPU_PLL_CTRL1(core));
 227         } else {
 228                 sysbase = nlm_get_node(node)->sysbase;
 229                 ctrl_val0 = nlm_read_sys_reg(sysbase,
 230                                                 SYS_CPU_PLL_CTRL0(core));
 231                 ctrl_val1 = nlm_read_sys_reg(sysbase,
 232                                                 SYS_CPU_PLL_CTRL1(core));
 233         }
 234
 235         /* Find PLL post divider value */
 236         switch ((ctrl_val0 >> 24) & 0x7) {
 237         case 1:
 238                 pll_post_div = 2;
 239                 break;
 240         case 3:
 241                 pll_post_div = 4;
 242                 break;
 243         case 7:
 244                 pll_post_div = 8;
 245                 break;
 246         case 6:
 247                 pll_post_div = 16;
 248                 break;
 249         case 0:
 250         default:
 251                 pll_post_div = 1;
 252                 break;
 253         }
 254
 255         num = 1000000ULL * (400 * 3 + 100 * (ctrl_val1 & 0x3f));
 256         denom = 3 * pll_post_div;
 257         do_div(num, denom);
 258
 259         return (unsigned int)num;
 260 }
 261
 262 static unsigned int nlm_xlp_get_core_frequency(int node, int core)
 263 {
 264         unsigned int pll_divf, pll_divr, dfs_div, ext_div;
 265         unsigned int rstval, dfsval, denom;
 266         uint64_t num, sysbase;
 267
 268         sysbase = nlm_get_node(node)->sysbase;
 269         rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
 270         dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
 271         pll_divf = ((rstval >> 10) & 0x7f) + 1;
 272         pll_divr = ((rstval >> 8)  & 0x3) + 1;
 273         ext_div  = ((rstval >> 30) & 0x3) + 1;
 274         dfs_div  = ((dfsval >> (core * 4)) & 0xf) + 1;
 275
 276         num = 800000000ULL * pll_divf;
 277         denom = 3 * pll_divr * ext_div * dfs_div;
 278         do_div(num, denom);
 279
 280         return (unsigned int)num;
 281 }
 282
 283 unsigned int nlm_get_core_frequency(int node, int core)
 284 {
 285         if (cpu_is_xlpii())
 286                 return nlm_xlp2_get_core_frequency(node, core);
 287         else
 288                 return nlm_xlp_get_core_frequency(node, core);
 289 }
 290
 291 /*
 292  * Calculate PIC frequency from PLL registers.
 293  * freq_out = (ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13) /
 294  *              ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
 295  */
 296 static unsigned int nlm_xlp2_get_pic_frequency(int node)
 297 {
 298         u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div, cpu_xlp9xx;
 299         u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
 300         u64 sysbase, pll_out_freq_num, ref_clk_select, clockbase, ref_clk;
 301
 302         sysbase = nlm_get_node(node)->sysbase;
 303         clockbase = nlm_get_clock_regbase(node);
 304         cpu_xlp9xx = cpu_is_xlp9xx();
 305
 306         /* Find ref_clk_base */
 307         if (cpu_xlp9xx)
 308                 ref_clk_select = (nlm_read_sys_reg(sysbase,
 309                                 SYS_9XX_POWER_ON_RESET_CFG) >> 18) & 0x3;
 310         else
 311                 ref_clk_select = (nlm_read_sys_reg(sysbase,
 312                                         SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
 313         switch (ref_clk_select) {
 314         case 0:
 315                 ref_clk = 200000000ULL;
 316                 ref_div = 3;
 317                 break;
 318         case 1:
 319                 ref_clk = 100000000ULL;
 320                 ref_div = 1;
 321                 break;
 322         case 2:
 323                 ref_clk = 125000000ULL;
 324                 ref_div = 1;
 325                 break;
 326         case 3:
 327                 ref_clk = 400000000ULL;
 328                 ref_div = 3;
 329                 break;
 330         }
 331
 332         /* Find the clock source PLL device for PIC */
 333         if (cpu_xlp9xx) {
 334                 reg_select = nlm_read_sys_reg(clockbase,
 335                                 SYS_9XX_CLK_DEV_SEL_REG) & 0x3;
 336                 switch (reg_select) {
 337                 case 0:
 338                         ctrl_val0 = nlm_read_sys_reg(clockbase,
 339                                         SYS_9XX_PLL_CTRL0);
 340                         ctrl_val2 = nlm_read_sys_reg(clockbase,
 341                                         SYS_9XX_PLL_CTRL2);
 342                         break;
 343                 case 1:
 344                         ctrl_val0 = nlm_read_sys_reg(clockbase,
 345                                         SYS_9XX_PLL_CTRL0_DEVX(0));
 346                         ctrl_val2 = nlm_read_sys_reg(clockbase,
 347                                         SYS_9XX_PLL_CTRL2_DEVX(0));
 348                         break;
 349                 case 2:
 350                         ctrl_val0 = nlm_read_sys_reg(clockbase,
 351                                         SYS_9XX_PLL_CTRL0_DEVX(1));
 352                         ctrl_val2 = nlm_read_sys_reg(clockbase,
 353                                         SYS_9XX_PLL_CTRL2_DEVX(1));
 354                         break;
 355                 case 3:
 356                         ctrl_val0 = nlm_read_sys_reg(clockbase,
 357                                         SYS_9XX_PLL_CTRL0_DEVX(2));
 358                         ctrl_val2 = nlm_read_sys_reg(clockbase,
 359                                         SYS_9XX_PLL_CTRL2_DEVX(2));
 360                         break;
 361                 }
 362         } else {
 363                 reg_select = (nlm_read_sys_reg(sysbase,
 364                                         SYS_CLK_DEV_SEL_REG) >> 22) & 0x3;
 365                 switch (reg_select) {
 366                 case 0:
 367                         ctrl_val0 = nlm_read_sys_reg(sysbase,
 368                                         SYS_PLL_CTRL0);
 369                         ctrl_val2 = nlm_read_sys_reg(sysbase,
 370                                         SYS_PLL_CTRL2);
 371                         break;
 372                 case 1:
 373                         ctrl_val0 = nlm_read_sys_reg(sysbase,
 374                                         SYS_PLL_CTRL0_DEVX(0));
 375                         ctrl_val2 = nlm_read_sys_reg(sysbase,
 376                                         SYS_PLL_CTRL2_DEVX(0));
 377                         break;
 378                 case 2:
 379                         ctrl_val0 = nlm_read_sys_reg(sysbase,
 380                                         SYS_PLL_CTRL0_DEVX(1));
 381                         ctrl_val2 = nlm_read_sys_reg(sysbase,
 382                                         SYS_PLL_CTRL2_DEVX(1));
 383                         break;
 384                 case 3:
 385                         ctrl_val0 = nlm_read_sys_reg(sysbase,
 386                                         SYS_PLL_CTRL0_DEVX(2));
 387                         ctrl_val2 = nlm_read_sys_reg(sysbase,
 388                                         SYS_PLL_CTRL2_DEVX(2));
 389                         break;
 390                 }
 391         }
 392
 393         vco_post_div = (ctrl_val0 >> 5) & 0x7;
 394         pll_post_div = (ctrl_val0 >> 24) & 0x7;
 395         mdiv = ctrl_val2 & 0xff;
 396         fdiv = (ctrl_val2 >> 8) & 0x1fff;
 397
 398         /* Find PLL post divider value */
 399         switch (pll_post_div) {
 400         case 1:
 401                 pll_post_div = 2;
 402                 break;
 403         case 3:
 404                 pll_post_div = 4;
 405                 break;
 406         case 7:
 407                 pll_post_div = 8;
 408                 break;
 409         case 6:
 410                 pll_post_div = 16;
 411                 break;
 412         case 0:
 413         default:
 414                 pll_post_div = 1;
 415                 break;
 416         }
 417
 418         fdiv = fdiv/(1 << 13);
 419         pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
 420         pll_out_freq_den = (1 << vco_post_div) * pll_post_div * ref_div;
 421
 422         if (pll_out_freq_den > 0)
 423                 do_div(pll_out_freq_num, pll_out_freq_den);
 424
 425         /* PIC post divider, which happens after PLL */
 426         if (cpu_xlp9xx)
 427                 pic_div = nlm_read_sys_reg(clockbase,
 428                                 SYS_9XX_CLK_DEV_DIV_REG) & 0x3;
 429         else
 430                 pic_div = (nlm_read_sys_reg(sysbase,
 431                                         SYS_CLK_DEV_DIV_REG) >> 22) & 0x3;
 432         do_div(pll_out_freq_num, 1 << pic_div);
 433
 434         return pll_out_freq_num;
 435 }
 436
 437 unsigned int nlm_get_pic_frequency(int node)
 438 {
 439         if (cpu_is_xlpii())
 440                 return nlm_xlp2_get_pic_frequency(node);
 441         else
 442                 return 133333333;
 443 }
 444
 445 unsigned int nlm_get_cpu_frequency(void)
 446 {
 447         return nlm_get_core_frequency(0, 0);
 448 }
 449
 450 /*
 451  * Fills upto 8 pairs of entries containing the DRAM map of a node
 452  * if n < 0, get dram map for all nodes
 453  */
 454 int xlp_get_dram_map(int n, uint64_t *dram_map)
 455 {
 456         uint64_t bridgebase, base, lim;
 457         uint32_t val;
 458         unsigned int barreg, limreg, xlatreg;
 459         int i, node, rv;
 460
 461         /* Look only at mapping on Node 0, we don't handle crazy configs */
 462         bridgebase = nlm_get_bridge_regbase(0);
 463         rv = 0;
 464         for (i = 0; i < 8; i++) {
 465                 if (cpu_is_xlp9xx()) {
 466                         barreg = BRIDGE_9XX_DRAM_BAR(i);
 467                         limreg = BRIDGE_9XX_DRAM_LIMIT(i);
 468                         xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i);
 469                 } else {
 470                         barreg = BRIDGE_DRAM_BAR(i);
 471                         limreg = BRIDGE_DRAM_LIMIT(i);
 472                         xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
 473                 }
 474                 if (n >= 0) {
 475                         /* node specified, get node mapping of BAR */
 476                         val = nlm_read_bridge_reg(bridgebase, xlatreg);
 477                         node = (val >> 1) & 0x3;
 478                         if (n != node)
 479                                 continue;
 480                 }
 481                 val = nlm_read_bridge_reg(bridgebase, barreg);
 482                 val = (val >>  12) & 0xfffff;
 483                 base = (uint64_t) val << 20;
 484                 val = nlm_read_bridge_reg(bridgebase, limreg);
 485                 val = (val >>  12) & 0xfffff;
 486                 if (val == 0)   /* BAR not used */
 487                         continue;
 488                 lim = ((uint64_t)val + 1) << 20;
 489                 dram_map[rv] = base;
 490                 dram_map[rv + 1] = lim;
 491                 rv += 2;
 492         }
 493         return rv;
 494 }