2 * Copyright (c) 2003-2012 Broadcom Corporation
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35 #ifndef __NLM_HAL_PCIBUS_H__
36 #define __NLM_HAL_PCIBUS_H__
38 /* PCIE Memory and IO regions */
39 #define PCIE_MEM_BASE 0xd0000000ULL
40 #define PCIE_MEM_LIMIT 0xdfffffffULL
41 #define PCIE_IO_BASE 0x14000000ULL
42 #define PCIE_IO_LIMIT 0x15ffffffULL
44 #define PCIE_BRIDGE_CMD 0x1
45 #define PCIE_BRIDGE_MSI_CAP 0x14
46 #define PCIE_BRIDGE_MSI_ADDRL 0x15
47 #define PCIE_BRIDGE_MSI_ADDRH 0x16
48 #define PCIE_BRIDGE_MSI_DATA 0x17
50 /* XLP Global PCIE configuration space registers */
51 #define PCIE_BYTE_SWAP_MEM_BASE 0x247
52 #define PCIE_BYTE_SWAP_MEM_LIM 0x248
53 #define PCIE_BYTE_SWAP_IO_BASE 0x249
54 #define PCIE_BYTE_SWAP_IO_LIM 0x24A
55 #define PCIE_MSI_STATUS 0x25A
56 #define PCIE_MSI_EN 0x25B
57 #define PCIE_INT_EN0 0x261
60 #define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
63 #define PCIE_MSI_INT_EN (1 << 9)
67 #define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
68 #define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
69 #define nlm_get_pcie_base(node, inst) \
70 nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
71 #define nlm_get_pcie_regbase(node, inst) \
72 (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
74 int xlp_pcie_link_irt(int link);
76 #endif /* __NLM_HAL_PCIBUS_H__ */