2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
22 /* MIPS KVM register ids */
23 #define MIPS_CP0_32(_R, _S) \
24 (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
26 #define MIPS_CP0_64(_R, _S) \
27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
29 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
30 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
31 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
32 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
33 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
34 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
35 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
36 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
37 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
38 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
39 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
40 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
41 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
42 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
43 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
44 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
45 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
46 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
47 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
48 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
49 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
50 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
51 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
52 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
55 #define KVM_MAX_VCPUS 1
56 #define KVM_USER_MEM_SLOTS 8
57 /* memory slots that does not exposed to userspace */
58 #define KVM_PRIVATE_MEM_SLOTS 0
60 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
64 /* Special address that contains the comm page, used for reducing # of traps */
65 #define KVM_GUEST_COMMPAGE_ADDR 0x0
67 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
68 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
70 #define KVM_GUEST_KUSEG 0x00000000UL
71 #define KVM_GUEST_KSEG0 0x40000000UL
72 #define KVM_GUEST_KSEG23 0x60000000UL
73 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
74 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
76 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
77 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
78 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
81 * Map an address to a certain kernel segment
83 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
84 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
85 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
87 #define KVM_INVALID_PAGE 0xdeadbeef
88 #define KVM_INVALID_INST 0xdeadbeef
89 #define KVM_INVALID_ADDR 0xdeadbeef
91 #define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL
93 #define GUEST_TICKS_PER_JIFFY (40000000/HZ)
94 #define MS_TO_NS(x) (x * 1E6L)
97 #define CAUSEF_DC (_ULCAST_(1) << 27)
99 extern atomic_t kvm_mips_instance;
100 extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
101 extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
102 extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
105 u32 remote_tlb_flush;
108 struct kvm_vcpu_stat {
113 u32 cop_unusable_exits;
115 u32 tlbmiss_ld_exits;
116 u32 tlbmiss_st_exits;
117 u32 addrerr_st_exits;
118 u32 addrerr_ld_exits;
120 u32 resvd_inst_exits;
121 u32 break_inst_exits;
123 u32 flush_dcache_exits;
124 u32 halt_successful_poll;
128 enum kvm_mips_exit_types {
144 MAX_KVM_MIPS_EXIT_TYPES
147 struct kvm_arch_memory_slot {
151 /* Guest GVA->HPA page table */
152 unsigned long *guest_pmap;
153 unsigned long guest_pmap_npages;
155 /* Wired host TLB used for the commpage */
159 #define N_MIPS_COPROC_REGS 32
160 #define N_MIPS_COPROC_SEL 8
163 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
164 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
165 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
170 * Coprocessor 0 register names
172 #define MIPS_CP0_TLB_INDEX 0
173 #define MIPS_CP0_TLB_RANDOM 1
174 #define MIPS_CP0_TLB_LOW 2
175 #define MIPS_CP0_TLB_LO0 2
176 #define MIPS_CP0_TLB_LO1 3
177 #define MIPS_CP0_TLB_CONTEXT 4
178 #define MIPS_CP0_TLB_PG_MASK 5
179 #define MIPS_CP0_TLB_WIRED 6
180 #define MIPS_CP0_HWRENA 7
181 #define MIPS_CP0_BAD_VADDR 8
182 #define MIPS_CP0_COUNT 9
183 #define MIPS_CP0_TLB_HI 10
184 #define MIPS_CP0_COMPARE 11
185 #define MIPS_CP0_STATUS 12
186 #define MIPS_CP0_CAUSE 13
187 #define MIPS_CP0_EXC_PC 14
188 #define MIPS_CP0_PRID 15
189 #define MIPS_CP0_CONFIG 16
190 #define MIPS_CP0_LLADDR 17
191 #define MIPS_CP0_WATCH_LO 18
192 #define MIPS_CP0_WATCH_HI 19
193 #define MIPS_CP0_TLB_XCONTEXT 20
194 #define MIPS_CP0_ECC 26
195 #define MIPS_CP0_CACHE_ERR 27
196 #define MIPS_CP0_TAG_LO 28
197 #define MIPS_CP0_TAG_HI 29
198 #define MIPS_CP0_ERROR_PC 30
199 #define MIPS_CP0_DEBUG 23
200 #define MIPS_CP0_DEPC 24
201 #define MIPS_CP0_PERFCNT 25
202 #define MIPS_CP0_ERRCTL 26
203 #define MIPS_CP0_DATA_LO 28
204 #define MIPS_CP0_DATA_HI 29
205 #define MIPS_CP0_DESAVE 31
207 #define MIPS_CP0_CONFIG_SEL 0
208 #define MIPS_CP0_CONFIG1_SEL 1
209 #define MIPS_CP0_CONFIG2_SEL 2
210 #define MIPS_CP0_CONFIG3_SEL 3
212 /* Config0 register bits */
226 /* Config1 register bits */
243 /* Config2 Register bits */
254 /* Config3 Register bits */
256 #define CP0C3_ISA_ON_EXC 16
257 #define CP0C3_ULRI 13
258 #define CP0C3_DSPP 10
267 /* Have config1, Cacheable, noncoherent, write-back, write allocate*/
268 #define MIPS_CONFIG0 \
269 ((1 << CP0C0_M) | (0x3 << CP0C0_K0))
271 /* Have config2, no coprocessor2 attached, no MDMX support attached,
272 no performance counters, watch registers present,
273 no code compression, EJTAG present, no FPU, no watch registers */
274 #define MIPS_CONFIG1 \
276 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
277 (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
280 /* Have config3, no tertiary/secondary caches implemented */
281 #define MIPS_CONFIG2 \
284 /* No config4, no DSP ASE, no large physaddr (PABITS),
285 no external interrupt controller, no vectored interrupts,
286 no 1kb pages, no SmartMIPS ASE, no trace logic */
287 #define MIPS_CONFIG3 \
288 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
289 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
290 (0 << CP0C3_SM) | (0 << CP0C3_TL))
292 /* MMU types, the first four entries have the same layout as the
294 enum mips_mmu_types {
307 #define T_INT 0 /* Interrupt pending */
308 #define T_TLB_MOD 1 /* TLB modified fault */
309 #define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
310 #define T_TLB_ST_MISS 3 /* TLB miss on a store */
311 #define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
312 #define T_ADDR_ERR_ST 5 /* Address error on a store */
313 #define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
314 #define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
315 #define T_SYSCALL 8 /* System call */
316 #define T_BREAK 9 /* Breakpoint */
317 #define T_RES_INST 10 /* Reserved instruction exception */
318 #define T_COP_UNUSABLE 11 /* Coprocessor unusable */
319 #define T_OVFLOW 12 /* Arithmetic overflow */
322 * Trap definitions added for r4000 port.
324 #define T_TRAP 13 /* Trap instruction */
325 #define T_VCEI 14 /* Virtual coherency exception */
326 #define T_FPE 15 /* Floating point exception */
327 #define T_MSADIS 21 /* MSA disabled exception */
328 #define T_WATCH 23 /* Watch address reference */
329 #define T_VCED 31 /* Virtual coherency data */
332 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
333 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
335 #define RESUME_GUEST 0
336 #define RESUME_GUEST_DR RESUME_FLAG_DR
337 #define RESUME_HOST RESUME_FLAG_HOST
339 enum emulation_result {
340 EMULATE_DONE, /* no further processing */
341 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
342 EMULATE_FAIL, /* can't emulate this instruction */
343 EMULATE_WAIT, /* WAIT instruction */
347 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
348 #define MIPS3_PG_V 0x00000002 /* Valid */
349 #define MIPS3_PG_NV 0x00000000
350 #define MIPS3_PG_D 0x00000004 /* Dirty */
352 #define mips3_paddr_to_tlbpfn(x) \
353 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
354 #define mips3_tlbpfn_to_paddr(x) \
355 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
357 #define MIPS3_PG_SHIFT 6
358 #define MIPS3_PG_FRAME 0x3fffffc0
360 #define VPN2_MASK 0xffffe000
361 #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \
362 ((x).tlb_lo1 & MIPS3_PG_G))
363 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
364 #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
365 #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
366 ? ((x).tlb_lo1 & MIPS3_PG_V) \
367 : ((x).tlb_lo0 & MIPS3_PG_V))
368 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
369 ((y) & VPN2_MASK & ~(x).tlb_mask))
370 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
371 TLB_ASID(x) == ((y) & ASID_MASK))
373 struct kvm_mips_tlb {
380 #define KVM_MIPS_GUEST_TLB_SIZE 64
381 struct kvm_vcpu_arch {
382 void *host_ebase, *guest_ebase;
383 unsigned long host_stack;
384 unsigned long host_gp;
386 /* Host CP0 registers used when handling exits from guest */
387 unsigned long host_cp0_badvaddr;
388 unsigned long host_cp0_cause;
389 unsigned long host_cp0_epc;
390 unsigned long host_cp0_entryhi;
394 unsigned long gprs[32];
400 struct mips_fpu_struct fpu;
403 struct mips_coproc *cop0;
405 /* Host KSEG0 address of the EI/DI offset */
406 void *kseg0_commpage;
408 u32 io_gpr; /* GPR used as IO source/target */
410 struct hrtimer comparecount_timer;
411 /* Count timer control KVM register */
413 /* Count bias from the raw time */
415 /* Frequency of timer in Hz */
417 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
420 ktime_t count_resume;
421 /* Period of timer tick in ns */
424 /* Bitmask of exceptions that are pending */
425 unsigned long pending_exceptions;
427 /* Bitmask of pending exceptions to be cleared */
428 unsigned long pending_exceptions_clr;
430 unsigned long pending_load_cause;
432 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
433 unsigned long preempt_entryhi;
435 /* S/W Based TLB for guest */
436 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
438 /* Cached guest kernel/user ASIDs */
439 uint32_t guest_user_asid[NR_CPUS];
440 uint32_t guest_kernel_asid[NR_CPUS];
441 struct mm_struct guest_kernel_mm, guest_user_mm;
450 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
451 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
452 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
453 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
454 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
455 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
456 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
457 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
458 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
459 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
460 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
461 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
462 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
463 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
464 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
465 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
466 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
467 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
468 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
469 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
470 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
471 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
472 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
473 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
474 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
475 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
476 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
477 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
478 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
479 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
480 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
481 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
482 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
483 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
484 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
485 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
486 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
487 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
488 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
489 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
490 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
491 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
492 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
493 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
494 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
495 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
498 * Some of the guest registers may be modified asynchronously (e.g. from a
499 * hrtimer callback in hard irq context) and therefore need stronger atomicity
500 * guarantees than other registers.
503 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
508 __asm__ __volatile__(
514 : "=&r" (temp), "+m" (*reg)
516 } while (unlikely(!temp));
519 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
524 __asm__ __volatile__(
530 : "=&r" (temp), "+m" (*reg)
532 } while (unlikely(!temp));
535 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
536 unsigned long change,
541 __asm__ __volatile__(
548 : "=&r" (temp), "+m" (*reg)
549 : "r" (~change), "r" (val & change));
550 } while (unlikely(!temp));
553 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
554 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
556 /* Cause can be modified asynchronously from hardirq hrtimer callback */
557 #define kvm_set_c0_guest_cause(cop0, val) \
558 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
559 #define kvm_clear_c0_guest_cause(cop0, val) \
560 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
561 #define kvm_change_c0_guest_cause(cop0, change, val) \
562 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
565 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
566 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
567 #define kvm_change_c0_guest_ebase(cop0, change, val) \
569 kvm_clear_c0_guest_ebase(cop0, change); \
570 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
574 struct kvm_mips_callbacks {
575 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
576 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
577 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
578 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
579 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
580 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
581 int (*handle_syscall)(struct kvm_vcpu *vcpu);
582 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
583 int (*handle_break)(struct kvm_vcpu *vcpu);
584 int (*handle_trap)(struct kvm_vcpu *vcpu);
585 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
586 int (*vm_init)(struct kvm *kvm);
587 int (*vcpu_init)(struct kvm_vcpu *vcpu);
588 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
589 gpa_t (*gva_to_gpa)(gva_t gva);
590 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
591 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
592 void (*queue_io_int)(struct kvm_vcpu *vcpu,
593 struct kvm_mips_interrupt *irq);
594 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
595 struct kvm_mips_interrupt *irq);
596 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
598 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
600 int (*get_one_reg)(struct kvm_vcpu *vcpu,
601 const struct kvm_one_reg *reg, s64 *v);
602 int (*set_one_reg)(struct kvm_vcpu *vcpu,
603 const struct kvm_one_reg *reg, s64 v);
605 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
606 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
608 /* Debug: dump vcpu state */
609 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
611 /* Trampoline ASM routine to start running in "Guest" context */
612 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
615 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
617 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
619 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
621 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
622 struct kvm_vcpu *vcpu);
624 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
625 struct kvm_vcpu *vcpu);
627 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
628 struct kvm_mips_tlb *tlb,
630 unsigned long *hpa1);
632 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
635 struct kvm_vcpu *vcpu);
637 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
640 struct kvm_vcpu *vcpu);
642 extern void kvm_mips_dump_host_tlbs(void);
643 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
644 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
645 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
646 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
648 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
649 unsigned long entryhi);
650 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
651 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
653 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
654 struct kvm_vcpu *vcpu);
655 extern void kvm_local_flush_tlb_all(void);
656 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
657 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
658 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
661 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
662 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
664 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
667 struct kvm_vcpu *vcpu);
669 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
672 struct kvm_vcpu *vcpu);
674 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
677 struct kvm_vcpu *vcpu);
679 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
682 struct kvm_vcpu *vcpu);
684 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
687 struct kvm_vcpu *vcpu);
689 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
692 struct kvm_vcpu *vcpu);
694 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
697 struct kvm_vcpu *vcpu);
699 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
702 struct kvm_vcpu *vcpu);
704 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
707 struct kvm_vcpu *vcpu);
709 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
712 struct kvm_vcpu *vcpu);
714 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
717 struct kvm_vcpu *vcpu);
719 extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
722 struct kvm_vcpu *vcpu);
724 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
725 struct kvm_run *run);
727 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu);
728 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count);
729 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare);
730 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
731 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
732 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
733 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
734 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
735 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
736 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
738 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
741 struct kvm_vcpu *vcpu);
743 enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
747 struct kvm_vcpu *vcpu);
748 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
752 struct kvm_vcpu *vcpu);
753 enum emulation_result kvm_mips_emulate_store(uint32_t inst,
756 struct kvm_vcpu *vcpu);
757 enum emulation_result kvm_mips_emulate_load(uint32_t inst,
760 struct kvm_vcpu *vcpu);
762 /* Dynamic binary translation */
763 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
764 struct kvm_vcpu *vcpu);
765 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
766 struct kvm_vcpu *vcpu);
767 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
768 struct kvm_vcpu *vcpu);
769 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
770 struct kvm_vcpu *vcpu);
773 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
774 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
776 static inline void kvm_arch_hardware_disable(void) {}
777 static inline void kvm_arch_hardware_unsetup(void) {}
778 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
779 static inline void kvm_arch_free_memslot(struct kvm *kvm,
780 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
781 static inline void kvm_arch_memslots_updated(struct kvm *kvm) {}
782 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
783 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
784 struct kvm_memory_slot *slot) {}
785 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
786 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
788 #endif /* __MIPS_KVM_HOST_H__ */