arch/mips/alchemy/devboards/db1200.c

   1 /*
   2  * DBAu1200/PBAu1200 board platform device registration
   3  *
   4  * Copyright (C) 2008-2011 Manuel Lauss
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/dma-mapping.h>
  22 #include <linux/gpio.h>
  23 #include <linux/i2c.h>
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/leds.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/partitions.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/serial_8250.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/spi/flash.h>
  37 #include <linux/smc91x.h>
  38 #include <asm/mach-au1x00/au1000.h>
  39 #include <asm/mach-au1x00/au1100_mmc.h>
  40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  41 #include <asm/mach-au1x00/au1200fb.h>
  42 #include <asm/mach-au1x00/au1550_spi.h>
  43 #include <asm/mach-db1x00/bcsr.h>
  44 #include <asm/mach-db1x00/db1200.h>
  45
  46 #include "platform.h"
  47
  48 const char *get_system_type(void);
  49
  50 static int __init db1200_detect_board(void)
  51 {
  52         int bid;
  53
  54         /* try the DB1200 first */
  55         bcsr_init(DB1200_BCSR_PHYS_ADDR,
  56                   DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
  57         if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
  58                 unsigned short t = bcsr_read(BCSR_HEXLEDS);
  59                 bcsr_write(BCSR_HEXLEDS, ~t);
  60                 if (bcsr_read(BCSR_HEXLEDS) != t) {
  61                         bcsr_write(BCSR_HEXLEDS, t);
  62                         return 0;
  63                 }
  64         }
  65
  66         /* okay, try the PB1200 then */
  67         bcsr_init(PB1200_BCSR_PHYS_ADDR,
  68                   PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
  69         bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
  70         if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
  71             (bid == BCSR_WHOAMI_PB1200_DDR2)) {
  72                 unsigned short t = bcsr_read(BCSR_HEXLEDS);
  73                 bcsr_write(BCSR_HEXLEDS, ~t);
  74                 if (bcsr_read(BCSR_HEXLEDS) != t) {
  75                         bcsr_write(BCSR_HEXLEDS, t);
  76                         return 0;
  77                 }
  78         }
  79
  80         return 1;       /* it's neither */
  81 }
  82
  83 int __init db1200_board_setup(void)
  84 {
  85         unsigned long freq0, clksrc, div, pfc;
  86         unsigned short whoami;
  87
  88         if (db1200_detect_board())
  89                 return -ENODEV;
  90
  91         whoami = bcsr_read(BCSR_WHOAMI);
  92         switch (BCSR_WHOAMI_BOARD(whoami)) {
  93         case BCSR_WHOAMI_PB1200_DDR1:
  94         case BCSR_WHOAMI_PB1200_DDR2:
  95         case BCSR_WHOAMI_DB1200:
  96                 break;
  97         default:
  98                 return -ENODEV;
  99         }
 100
 101         printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
 102                 "  Board-ID %d  Daughtercard ID %d\n", get_system_type(),
 103                 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
 104
 105         /* SMBus/SPI on PSC0, Audio on PSC1 */
 106         pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
 107         pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
 108         pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
 109         pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
 110         __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
 111         wmb();
 112
 113         /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
 114          * CPU clock; all other clock generators off/unused.
 115          */
 116         div = (get_au1x00_speed() + 25000000) / 50000000;
 117         if (div & 1)
 118                 div++;
 119         div = ((div >> 1) - 1) & 0xff;
 120
 121         freq0 = div << SYS_FC_FRDIV0_BIT;
 122         __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
 123         wmb();
 124         freq0 |= SYS_FC_FE0;    /* enable F0 */
 125         __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
 126         wmb();
 127
 128         /* psc0_intclk comes 1:1 from F0 */
 129         clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
 130         __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
 131         wmb();
 132
 133         return 0;
 134 }
 135
 136 /******************************************************************************/
 137
 138 static struct mtd_partition db1200_spiflash_parts[] = {
 139         {
 140                 .name   = "spi_flash",
 141                 .offset = 0,
 142                 .size   = MTDPART_SIZ_FULL,
 143         },
 144 };
 145
 146 static struct flash_platform_data db1200_spiflash_data = {
 147         .name           = "s25fl001",
 148         .parts          = db1200_spiflash_parts,
 149         .nr_parts       = ARRAY_SIZE(db1200_spiflash_parts),
 150         .type           = "m25p10",
 151 };
 152
 153 static struct spi_board_info db1200_spi_devs[] __initdata = {
 154         {
 155                 /* TI TMP121AIDBVR temp sensor */
 156                 .modalias       = "tmp121",
 157                 .max_speed_hz   = 2000000,
 158                 .bus_num        = 0,
 159                 .chip_select    = 0,
 160                 .mode           = 0,
 161         },
 162         {
 163                 /* Spansion S25FL001D0FMA SPI flash */
 164                 .modalias       = "m25p80",
 165                 .max_speed_hz   = 50000000,
 166                 .bus_num        = 0,
 167                 .chip_select    = 1,
 168                 .mode           = 0,
 169                 .platform_data  = &db1200_spiflash_data,
 170         },
 171 };
 172
 173 static struct i2c_board_info db1200_i2c_devs[] __initdata = {
 174         { I2C_BOARD_INFO("24c04", 0x52),  }, /* AT24C04-10 I2C eeprom */
 175         { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
 176         { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
 177 };
 178
 179 /**********************************************************************/
 180
 181 static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 182                                  unsigned int ctrl)
 183 {
 184         struct nand_chip *this = mtd->priv;
 185         unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
 186
 187         ioaddr &= 0xffffff00;
 188
 189         if (ctrl & NAND_CLE) {
 190                 ioaddr += MEM_STNAND_CMD;
 191         } else if (ctrl & NAND_ALE) {
 192                 ioaddr += MEM_STNAND_ADDR;
 193         } else {
 194                 /* assume we want to r/w real data  by default */
 195                 ioaddr += MEM_STNAND_DATA;
 196         }
 197         this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
 198         if (cmd != NAND_CMD_NONE) {
 199                 __raw_writeb(cmd, this->IO_ADDR_W);
 200                 wmb();
 201         }
 202 }
 203
 204 static int au1200_nand_device_ready(struct mtd_info *mtd)
 205 {
 206         return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
 207 }
 208
 209 static struct mtd_partition db1200_nand_parts[] = {
 210         {
 211                 .name   = "NAND FS 0",
 212                 .offset = 0,
 213                 .size   = 8 * 1024 * 1024,
 214         },
 215         {
 216                 .name   = "NAND FS 1",
 217                 .offset = MTDPART_OFS_APPEND,
 218                 .size   = MTDPART_SIZ_FULL
 219         },
 220 };
 221
 222 struct platform_nand_data db1200_nand_platdata = {
 223         .chip = {
 224                 .nr_chips       = 1,
 225                 .chip_offset    = 0,
 226                 .nr_partitions  = ARRAY_SIZE(db1200_nand_parts),
 227                 .partitions     = db1200_nand_parts,
 228                 .chip_delay     = 20,
 229         },
 230         .ctrl = {
 231                 .dev_ready      = au1200_nand_device_ready,
 232                 .cmd_ctrl       = au1200_nand_cmd_ctrl,
 233         },
 234 };
 235
 236 static struct resource db1200_nand_res[] = {
 237         [0] = {
 238                 .start  = DB1200_NAND_PHYS_ADDR,
 239                 .end    = DB1200_NAND_PHYS_ADDR + 0xff,
 240                 .flags  = IORESOURCE_MEM,
 241         },
 242 };
 243
 244 static struct platform_device db1200_nand_dev = {
 245         .name           = "gen_nand",
 246         .num_resources  = ARRAY_SIZE(db1200_nand_res),
 247         .resource       = db1200_nand_res,
 248         .id             = -1,
 249         .dev            = {
 250                 .platform_data = &db1200_nand_platdata,
 251         }
 252 };
 253
 254 /**********************************************************************/
 255
 256 static struct smc91x_platdata db1200_eth_data = {
 257         .flags  = SMC91X_NOWAIT | SMC91X_USE_16BIT,
 258         .leda   = RPC_LED_100_10,
 259         .ledb   = RPC_LED_TX_RX,
 260 };
 261
 262 static struct resource db1200_eth_res[] = {
 263         [0] = {
 264                 .start  = DB1200_ETH_PHYS_ADDR,
 265                 .end    = DB1200_ETH_PHYS_ADDR + 0xf,
 266                 .flags  = IORESOURCE_MEM,
 267         },
 268         [1] = {
 269                 .start  = DB1200_ETH_INT,
 270                 .end    = DB1200_ETH_INT,
 271                 .flags  = IORESOURCE_IRQ,
 272         },
 273 };
 274
 275 static struct platform_device db1200_eth_dev = {
 276         .dev    = {
 277                 .platform_data  = &db1200_eth_data,
 278         },
 279         .name           = "smc91x",
 280         .id             = -1,
 281         .num_resources  = ARRAY_SIZE(db1200_eth_res),
 282         .resource       = db1200_eth_res,
 283 };
 284
 285 /**********************************************************************/
 286
 287 static struct resource db1200_ide_res[] = {
 288         [0] = {
 289                 .start  = DB1200_IDE_PHYS_ADDR,
 290                 .end    = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
 291                 .flags  = IORESOURCE_MEM,
 292         },
 293         [1] = {
 294                 .start  = DB1200_IDE_INT,
 295                 .end    = DB1200_IDE_INT,
 296                 .flags  = IORESOURCE_IRQ,
 297         },
 298         [2] = {
 299                 .start  = AU1200_DSCR_CMD0_DMA_REQ1,
 300                 .end    = AU1200_DSCR_CMD0_DMA_REQ1,
 301                 .flags  = IORESOURCE_DMA,
 302         },
 303 };
 304
 305 static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
 306
 307 static struct platform_device db1200_ide_dev = {
 308         .name           = "au1200-ide",
 309         .id             = 0,
 310         .dev = {
 311                 .dma_mask               = &au1200_ide_dmamask,
 312                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 313         },
 314         .num_resources  = ARRAY_SIZE(db1200_ide_res),
 315         .resource       = db1200_ide_res,
 316 };
 317
 318 /**********************************************************************/
 319
 320 /* SD carddetects:  they're supposed to be edge-triggered, but ack
 321  * doesn't seem to work (CPLD Rev 2).  Instead, the screaming one
 322  * is disabled and its counterpart enabled.  The 500ms timeout is
 323  * because the carddetect isn't debounced in hardware.
 324  */
 325 static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
 326 {
 327         void(*mmc_cd)(struct mmc_host *, unsigned long);
 328
 329         if (irq == DB1200_SD0_INSERT_INT) {
 330                 disable_irq_nosync(DB1200_SD0_INSERT_INT);
 331                 enable_irq(DB1200_SD0_EJECT_INT);
 332         } else {
 333                 disable_irq_nosync(DB1200_SD0_EJECT_INT);
 334                 enable_irq(DB1200_SD0_INSERT_INT);
 335         }
 336
 337         /* link against CONFIG_MMC=m */
 338         mmc_cd = symbol_get(mmc_detect_change);
 339         if (mmc_cd) {
 340                 mmc_cd(ptr, msecs_to_jiffies(500));
 341                 symbol_put(mmc_detect_change);
 342         }
 343
 344         return IRQ_HANDLED;
 345 }
 346
 347 static int db1200_mmc_cd_setup(void *mmc_host, int en)
 348 {
 349         int ret;
 350
 351         if (en) {
 352                 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
 353                                   0, "sd_insert", mmc_host);
 354                 if (ret)
 355                         goto out;
 356
 357                 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
 358                                   0, "sd_eject", mmc_host);
 359                 if (ret) {
 360                         free_irq(DB1200_SD0_INSERT_INT, mmc_host);
 361                         goto out;
 362                 }
 363
 364                 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
 365                         enable_irq(DB1200_SD0_EJECT_INT);
 366                 else
 367                         enable_irq(DB1200_SD0_INSERT_INT);
 368
 369         } else {
 370                 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
 371                 free_irq(DB1200_SD0_EJECT_INT, mmc_host);
 372         }
 373         ret = 0;
 374 out:
 375         return ret;
 376 }
 377
 378 static void db1200_mmc_set_power(void *mmc_host, int state)
 379 {
 380         if (state) {
 381                 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
 382                 msleep(400);    /* stabilization time */
 383         } else
 384                 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
 385 }
 386
 387 static int db1200_mmc_card_readonly(void *mmc_host)
 388 {
 389         return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
 390 }
 391
 392 static int db1200_mmc_card_inserted(void *mmc_host)
 393 {
 394         return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
 395 }
 396
 397 static void db1200_mmcled_set(struct led_classdev *led,
 398                               enum led_brightness brightness)
 399 {
 400         if (brightness != LED_OFF)
 401                 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
 402         else
 403                 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
 404 }
 405
 406 static struct led_classdev db1200_mmc_led = {
 407         .brightness_set = db1200_mmcled_set,
 408 };
 409
 410 /* -- */
 411
 412 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
 413 {
 414         void(*mmc_cd)(struct mmc_host *, unsigned long);
 415
 416         if (irq == PB1200_SD1_INSERT_INT) {
 417                 disable_irq_nosync(PB1200_SD1_INSERT_INT);
 418                 enable_irq(PB1200_SD1_EJECT_INT);
 419         } else {
 420                 disable_irq_nosync(PB1200_SD1_EJECT_INT);
 421                 enable_irq(PB1200_SD1_INSERT_INT);
 422         }
 423
 424         /* link against CONFIG_MMC=m */
 425         mmc_cd = symbol_get(mmc_detect_change);
 426         if (mmc_cd) {
 427                 mmc_cd(ptr, msecs_to_jiffies(500));
 428                 symbol_put(mmc_detect_change);
 429         }
 430
 431         return IRQ_HANDLED;
 432 }
 433
 434 static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
 435 {
 436         int ret;
 437
 438         if (en) {
 439                 ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0,
 440                                   "sd1_insert", mmc_host);
 441                 if (ret)
 442                         goto out;
 443
 444                 ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0,
 445                                   "sd1_eject", mmc_host);
 446                 if (ret) {
 447                         free_irq(PB1200_SD1_INSERT_INT, mmc_host);
 448                         goto out;
 449                 }
 450
 451                 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
 452                         enable_irq(PB1200_SD1_EJECT_INT);
 453                 else
 454                         enable_irq(PB1200_SD1_INSERT_INT);
 455
 456         } else {
 457                 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
 458                 free_irq(PB1200_SD1_EJECT_INT, mmc_host);
 459         }
 460         ret = 0;
 461 out:
 462         return ret;
 463 }
 464
 465 static void pb1200_mmc1led_set(struct led_classdev *led,
 466                         enum led_brightness brightness)
 467 {
 468         if (brightness != LED_OFF)
 469                         bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
 470         else
 471                         bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
 472 }
 473
 474 static struct led_classdev pb1200_mmc1_led = {
 475         .brightness_set = pb1200_mmc1led_set,
 476 };
 477
 478 static void pb1200_mmc1_set_power(void *mmc_host, int state)
 479 {
 480         if (state) {
 481                 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
 482                 msleep(400);    /* stabilization time */
 483         } else
 484                 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
 485 }
 486
 487 static int pb1200_mmc1_card_readonly(void *mmc_host)
 488 {
 489         return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
 490 }
 491
 492 static int pb1200_mmc1_card_inserted(void *mmc_host)
 493 {
 494         return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
 495 }
 496
 497
 498 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
 499         [0] = {
 500                 .cd_setup       = db1200_mmc_cd_setup,
 501                 .set_power      = db1200_mmc_set_power,
 502                 .card_inserted  = db1200_mmc_card_inserted,
 503                 .card_readonly  = db1200_mmc_card_readonly,
 504                 .led            = &db1200_mmc_led,
 505         },
 506         [1] = {
 507                 .cd_setup       = pb1200_mmc1_cd_setup,
 508                 .set_power      = pb1200_mmc1_set_power,
 509                 .card_inserted  = pb1200_mmc1_card_inserted,
 510                 .card_readonly  = pb1200_mmc1_card_readonly,
 511                 .led            = &pb1200_mmc1_led,
 512         },
 513 };
 514
 515 static struct resource au1200_mmc0_resources[] = {
 516         [0] = {
 517                 .start  = AU1100_SD0_PHYS_ADDR,
 518                 .end    = AU1100_SD0_PHYS_ADDR + 0xfff,
 519                 .flags  = IORESOURCE_MEM,
 520         },
 521         [1] = {
 522                 .start  = AU1200_SD_INT,
 523                 .end    = AU1200_SD_INT,
 524                 .flags  = IORESOURCE_IRQ,
 525         },
 526         [2] = {
 527                 .start  = AU1200_DSCR_CMD0_SDMS_TX0,
 528                 .end    = AU1200_DSCR_CMD0_SDMS_TX0,
 529                 .flags  = IORESOURCE_DMA,
 530         },
 531         [3] = {
 532                 .start  = AU1200_DSCR_CMD0_SDMS_RX0,
 533                 .end    = AU1200_DSCR_CMD0_SDMS_RX0,
 534                 .flags  = IORESOURCE_DMA,
 535         }
 536 };
 537
 538 static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
 539
 540 static struct platform_device db1200_mmc0_dev = {
 541         .name           = "au1xxx-mmc",
 542         .id             = 0,
 543         .dev = {
 544                 .dma_mask               = &au1xxx_mmc_dmamask,
 545                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 546                 .platform_data          = &db1200_mmc_platdata[0],
 547         },
 548         .num_resources  = ARRAY_SIZE(au1200_mmc0_resources),
 549         .resource       = au1200_mmc0_resources,
 550 };
 551
 552 static struct resource au1200_mmc1_res[] = {
 553         [0] = {
 554                 .start  = AU1100_SD1_PHYS_ADDR,
 555                 .end    = AU1100_SD1_PHYS_ADDR + 0xfff,
 556                 .flags  = IORESOURCE_MEM,
 557         },
 558         [1] = {
 559                 .start  = AU1200_SD_INT,
 560                 .end    = AU1200_SD_INT,
 561                 .flags  = IORESOURCE_IRQ,
 562         },
 563         [2] = {
 564                 .start  = AU1200_DSCR_CMD0_SDMS_TX1,
 565                 .end    = AU1200_DSCR_CMD0_SDMS_TX1,
 566                 .flags  = IORESOURCE_DMA,
 567         },
 568         [3] = {
 569                 .start  = AU1200_DSCR_CMD0_SDMS_RX1,
 570                 .end    = AU1200_DSCR_CMD0_SDMS_RX1,
 571                 .flags  = IORESOURCE_DMA,
 572         }
 573 };
 574
 575 static struct platform_device pb1200_mmc1_dev = {
 576         .name           = "au1xxx-mmc",
 577         .id             = 1,
 578         .dev = {
 579                 .dma_mask               = &au1xxx_mmc_dmamask,
 580                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 581                 .platform_data          = &db1200_mmc_platdata[1],
 582         },
 583         .num_resources  = ARRAY_SIZE(au1200_mmc1_res),
 584         .resource       = au1200_mmc1_res,
 585 };
 586
 587 /**********************************************************************/
 588
 589 static int db1200fb_panel_index(void)
 590 {
 591         return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
 592 }
 593
 594 static int db1200fb_panel_init(void)
 595 {
 596         /* Apply power */
 597         bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
 598                                 BCSR_BOARD_LCDBL);
 599         return 0;
 600 }
 601
 602 static int db1200fb_panel_shutdown(void)
 603 {
 604         /* Remove power */
 605         bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
 606                              BCSR_BOARD_LCDBL, 0);
 607         return 0;
 608 }
 609
 610 static struct au1200fb_platdata db1200fb_pd = {
 611         .panel_index    = db1200fb_panel_index,
 612         .panel_init     = db1200fb_panel_init,
 613         .panel_shutdown = db1200fb_panel_shutdown,
 614 };
 615
 616 static struct resource au1200_lcd_res[] = {
 617         [0] = {
 618                 .start  = AU1200_LCD_PHYS_ADDR,
 619                 .end    = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
 620                 .flags  = IORESOURCE_MEM,
 621         },
 622         [1] = {
 623                 .start  = AU1200_LCD_INT,
 624                 .end    = AU1200_LCD_INT,
 625                 .flags  = IORESOURCE_IRQ,
 626         }
 627 };
 628
 629 static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
 630
 631 static struct platform_device au1200_lcd_dev = {
 632         .name           = "au1200-lcd",
 633         .id             = 0,
 634         .dev = {
 635                 .dma_mask               = &au1200_lcd_dmamask,
 636                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 637                 .platform_data          = &db1200fb_pd,
 638         },
 639         .num_resources  = ARRAY_SIZE(au1200_lcd_res),
 640         .resource       = au1200_lcd_res,
 641 };
 642
 643 /**********************************************************************/
 644
 645 static struct resource au1200_psc0_res[] = {
 646         [0] = {
 647                 .start  = AU1550_PSC0_PHYS_ADDR,
 648                 .end    = AU1550_PSC0_PHYS_ADDR + 0xfff,
 649                 .flags  = IORESOURCE_MEM,
 650         },
 651         [1] = {
 652                 .start  = AU1200_PSC0_INT,
 653                 .end    = AU1200_PSC0_INT,
 654                 .flags  = IORESOURCE_IRQ,
 655         },
 656         [2] = {
 657                 .start  = AU1200_DSCR_CMD0_PSC0_TX,
 658                 .end    = AU1200_DSCR_CMD0_PSC0_TX,
 659                 .flags  = IORESOURCE_DMA,
 660         },
 661         [3] = {
 662                 .start  = AU1200_DSCR_CMD0_PSC0_RX,
 663                 .end    = AU1200_DSCR_CMD0_PSC0_RX,
 664                 .flags  = IORESOURCE_DMA,
 665         },
 666 };
 667
 668 static struct platform_device db1200_i2c_dev = {
 669         .name           = "au1xpsc_smbus",
 670         .id             = 0,    /* bus number */
 671         .num_resources  = ARRAY_SIZE(au1200_psc0_res),
 672         .resource       = au1200_psc0_res,
 673 };
 674
 675 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
 676 {
 677         if (cs)
 678                 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
 679         else
 680                 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
 681 }
 682
 683 static struct au1550_spi_info db1200_spi_platdata = {
 684         .mainclk_hz     = 50000000,     /* PSC0 clock */
 685         .num_chipselect = 2,
 686         .activate_cs    = db1200_spi_cs_en,
 687 };
 688
 689 static u64 spi_dmamask = DMA_BIT_MASK(32);
 690
 691 static struct platform_device db1200_spi_dev = {
 692         .dev    = {
 693                 .dma_mask               = &spi_dmamask,
 694                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 695                 .platform_data          = &db1200_spi_platdata,
 696         },
 697         .name           = "au1550-spi",
 698         .id             = 0,    /* bus number */
 699         .num_resources  = ARRAY_SIZE(au1200_psc0_res),
 700         .resource       = au1200_psc0_res,
 701 };
 702
 703 static struct resource au1200_psc1_res[] = {
 704         [0] = {
 705                 .start  = AU1550_PSC1_PHYS_ADDR,
 706                 .end    = AU1550_PSC1_PHYS_ADDR + 0xfff,
 707                 .flags  = IORESOURCE_MEM,
 708         },
 709         [1] = {
 710                 .start  = AU1200_PSC1_INT,
 711                 .end    = AU1200_PSC1_INT,
 712                 .flags  = IORESOURCE_IRQ,
 713         },
 714         [2] = {
 715                 .start  = AU1200_DSCR_CMD0_PSC1_TX,
 716                 .end    = AU1200_DSCR_CMD0_PSC1_TX,
 717                 .flags  = IORESOURCE_DMA,
 718         },
 719         [3] = {
 720                 .start  = AU1200_DSCR_CMD0_PSC1_RX,
 721                 .end    = AU1200_DSCR_CMD0_PSC1_RX,
 722                 .flags  = IORESOURCE_DMA,
 723         },
 724 };
 725
 726 /* AC97 or I2S device */
 727 static struct platform_device db1200_audio_dev = {
 728         /* name assigned later based on switch setting */
 729         .id             = 1,    /* PSC ID */
 730         .num_resources  = ARRAY_SIZE(au1200_psc1_res),
 731         .resource       = au1200_psc1_res,
 732 };
 733
 734 /* DB1200 ASoC card device */
 735 static struct platform_device db1200_sound_dev = {
 736         /* name assigned later based on switch setting */
 737         .id             = 1,    /* PSC ID */
 738 };
 739
 740 static struct platform_device db1200_stac_dev = {
 741         .name           = "ac97-codec",
 742         .id             = 1,    /* on PSC1 */
 743 };
 744
 745 static struct platform_device db1200_audiodma_dev = {
 746         .name           = "au1xpsc-pcm",
 747         .id             = 1,    /* PSC ID */
 748 };
 749
 750 static struct platform_device *db1200_devs[] __initdata = {
 751         NULL,           /* PSC0, selected by S6.8 */
 752         &db1200_ide_dev,
 753         &db1200_mmc0_dev,
 754         &au1200_lcd_dev,
 755         &db1200_eth_dev,
 756         &db1200_nand_dev,
 757         &db1200_audiodma_dev,
 758         &db1200_audio_dev,
 759         &db1200_stac_dev,
 760         &db1200_sound_dev,
 761 };
 762
 763 static struct platform_device *pb1200_devs[] __initdata = {
 764         &pb1200_mmc1_dev,
 765 };
 766
 767 /* Some peripheral base addresses differ on the PB1200 */
 768 static int __init pb1200_res_fixup(void)
 769 {
 770         /* CPLD Revs earlier than 4 cause problems */
 771         if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
 772                 printk(KERN_ERR "WARNING!!!\n");
 773                 printk(KERN_ERR "WARNING!!!\n");
 774                 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
 775                 printk(KERN_ERR "the board updated to latest revisions.\n");
 776                 printk(KERN_ERR "This software will not work reliably\n");
 777                 printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
 778                 printk(KERN_ERR "WARNING!!!\n");
 779                 printk(KERN_ERR "WARNING!!!\n");
 780                 return 1;
 781         }
 782
 783         db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
 784         db1200_nand_res[0].end   = PB1200_NAND_PHYS_ADDR + 0xff;
 785         db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
 786         db1200_ide_res[0].end   = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
 787         db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
 788         db1200_eth_res[0].end   = PB1200_ETH_PHYS_ADDR + 0xff;
 789         return 0;
 790 }
 791
 792 int __init db1200_dev_setup(void)
 793 {
 794         unsigned long pfc;
 795         unsigned short sw;
 796         int swapped, bid;
 797
 798         bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
 799         if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
 800             (bid == BCSR_WHOAMI_PB1200_DDR2)) {
 801                 if (pb1200_res_fixup())
 802                         return -ENODEV;
 803         }
 804
 805         /* GPIO7 is low-level triggered CPLD cascade */
 806         irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
 807         bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
 808
 809         /* insert/eject pairs: one of both is always screaming.  To avoid
 810          * issues they must not be automatically enabled when initially
 811          * requested.
 812          */
 813         irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
 814         irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
 815         irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
 816         irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
 817         irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
 818         irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
 819
 820         i2c_register_board_info(0, db1200_i2c_devs,
 821                                 ARRAY_SIZE(db1200_i2c_devs));
 822         spi_register_board_info(db1200_spi_devs,
 823                                 ARRAY_SIZE(db1200_i2c_devs));
 824
 825         /* SWITCHES:    S6.8 I2C/SPI selector  (OFF=I2C  ON=SPI)
 826          *              S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
 827          *              or S12 on the PB1200.
 828          */
 829
 830         /* NOTE: GPIO215 controls OTG VBUS supply.  In SPI mode however
 831          * this pin is claimed by PSC0 (unused though, but pinmux doesn't
 832          * allow to free it without crippling the SPI interface).
 833          * As a result, in SPI mode, OTG simply won't work (PSC0 uses
 834          * it as an input pin which is pulled high on the boards).
 835          */
 836         pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
 837
 838         /* switch off OTG VBUS supply */
 839         gpio_request(215, "otg-vbus");
 840         gpio_direction_output(215, 1);
 841
 842         printk(KERN_INFO "%s device configuration:\n", get_system_type());
 843
 844         sw = bcsr_read(BCSR_SWITCHES);
 845         if (sw & BCSR_SWITCHES_DIP_8) {
 846                 db1200_devs[0] = &db1200_i2c_dev;
 847                 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
 848
 849                 pfc |= (2 << 17);       /* GPIO2 block owns GPIO215 */
 850
 851                 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
 852                 printk(KERN_INFO "   OTG port VBUS supply available!\n");
 853         } else {
 854                 db1200_devs[0] = &db1200_spi_dev;
 855                 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
 856
 857                 pfc |= (1 << 17);       /* PSC0 owns GPIO215 */
 858
 859                 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
 860                 printk(KERN_INFO "   OTG port VBUS supply disabled\n");
 861         }
 862         __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
 863         wmb();
 864
 865         /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
 866          * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
 867          */
 868         sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
 869         if (sw == BCSR_SWITCHES_DIP_8) {
 870                 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
 871                 db1200_audio_dev.name = "au1xpsc_i2s";
 872                 db1200_sound_dev.name = "db1200-i2s";
 873                 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
 874         } else {
 875                 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
 876                 db1200_audio_dev.name = "au1xpsc_ac97";
 877                 db1200_sound_dev.name = "db1200-ac97";
 878                 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
 879         }
 880
 881         /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
 882         __raw_writel(PSC_SEL_CLK_SERCLK,
 883             (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
 884         wmb();
 885
 886         db1x_register_pcmcia_socket(
 887                 AU1000_PCMCIA_ATTR_PHYS_ADDR,
 888                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
 889                 AU1000_PCMCIA_MEM_PHYS_ADDR,
 890                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
 891                 AU1000_PCMCIA_IO_PHYS_ADDR,
 892                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
 893                 DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
 894                 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
 895
 896         db1x_register_pcmcia_socket(
 897                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
 898                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
 899                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
 900                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
 901                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
 902                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
 903                 DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
 904                 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
 905
 906         swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
 907         db1x_register_norflash(64 << 20, 2, swapped);
 908
 909         platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
 910
 911         /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
 912         if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
 913             (bid == BCSR_WHOAMI_PB1200_DDR2))
 914                 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
 915
 916         return 0;
 917 }