2 * direct.c - Low-level direct PCI config space access
6 #include <linux/init.h>
11 * Functions for accessing PCI configuration space with type 1 accesses
14 #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
15 (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
17 int pci_conf1_read(unsigned int seg, unsigned int bus,
18 unsigned int devfn, int reg, int len, u32 *value)
22 if (!value || (bus > 255) || (devfn > 255) || (reg > 255))
25 spin_lock_irqsave(&pci_config_lock, flags);
27 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
31 *value = inb(0xCFC + (reg & 3));
34 *value = inw(0xCFC + (reg & 2));
41 spin_unlock_irqrestore(&pci_config_lock, flags);
46 int pci_conf1_write(unsigned int seg, unsigned int bus,
47 unsigned int devfn, int reg, int len, u32 value)
51 if ((bus > 255) || (devfn > 255) || (reg > 255))
54 spin_lock_irqsave(&pci_config_lock, flags);
56 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
60 outb((u8)value, 0xCFC + (reg & 3));
63 outw((u16)value, 0xCFC + (reg & 2));
66 outl((u32)value, 0xCFC);
70 spin_unlock_irqrestore(&pci_config_lock, flags);
75 #undef PCI_CONF1_ADDRESS
77 struct pci_raw_ops pci_direct_conf1 = {
78 .read = pci_conf1_read,
79 .write = pci_conf1_write,
84 * Functions for accessing PCI configuration space with type 2 accesses
87 #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg)
89 static int pci_conf2_read(unsigned int seg, unsigned int bus,
90 unsigned int devfn, int reg, int len, u32 *value)
95 if (!value || (bus > 255) || (devfn > 255) || (reg > 255))
98 dev = PCI_SLOT(devfn);
102 return PCIBIOS_DEVICE_NOT_FOUND;
104 spin_lock_irqsave(&pci_config_lock, flags);
106 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
107 outb((u8)bus, 0xCFA);
111 *value = inb(PCI_CONF2_ADDRESS(dev, reg));
114 *value = inw(PCI_CONF2_ADDRESS(dev, reg));
117 *value = inl(PCI_CONF2_ADDRESS(dev, reg));
123 spin_unlock_irqrestore(&pci_config_lock, flags);
128 static int pci_conf2_write(unsigned int seg, unsigned int bus,
129 unsigned int devfn, int reg, int len, u32 value)
134 if ((bus > 255) || (devfn > 255) || (reg > 255))
137 dev = PCI_SLOT(devfn);
138 fn = PCI_FUNC(devfn);
141 return PCIBIOS_DEVICE_NOT_FOUND;
143 spin_lock_irqsave(&pci_config_lock, flags);
145 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
146 outb((u8)bus, 0xCFA);
150 outb((u8)value, PCI_CONF2_ADDRESS(dev, reg));
153 outw((u16)value, PCI_CONF2_ADDRESS(dev, reg));
156 outl((u32)value, PCI_CONF2_ADDRESS(dev, reg));
162 spin_unlock_irqrestore(&pci_config_lock, flags);
167 #undef PCI_CONF2_ADDRESS
169 static struct pci_raw_ops pci_direct_conf2 = {
170 .read = pci_conf2_read,
171 .write = pci_conf2_write,
176 * Before we decide to use direct hardware access mechanisms, we try to do some
177 * trivial checks to ensure it at least _seems_ to be working -- we just test
178 * whether bus 00 contains a host bridge (this is similar to checking
179 * techniques used in XFree86, but ours should be more reliable since we
180 * attempt to make use of direct access hints provided by the PCI BIOS).
182 * This should be close to trivial, but it isn't, because there are buggy
183 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
185 static int __init pci_sanity_check(struct pci_raw_ops *o)
190 if (pci_probe & PCI_NO_CHECKS)
192 /* Assume Type 1 works for newer systems.
193 This handles machines that don't have anything on PCI Bus 0. */
194 if (dmi_get_year(DMI_BIOS_DATE) >= 2001)
197 for (devfn = 0; devfn < 0x100; devfn++) {
198 if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x))
200 if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)
203 if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x))
205 if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)
209 DBG(KERN_WARNING "PCI: Sanity check failed\n");
213 static int __init pci_check_type1(void)
219 local_irq_save(flags);
223 outl(0x80000000, 0xCF8);
224 if (inl(0xCF8) == 0x80000000 && pci_sanity_check(&pci_direct_conf1)) {
228 local_irq_restore(flags);
233 static int __init pci_check_type2(void)
238 local_irq_save(flags);
243 if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 &&
244 pci_sanity_check(&pci_direct_conf2)) {
248 local_irq_restore(flags);
253 void __init pci_direct_init(void)
255 struct resource *region, *region2;
257 if ((pci_probe & PCI_PROBE_CONF1) == 0)
259 region = request_region(0xCF8, 8, "PCI conf1");
263 if (pci_check_type1()) {
264 printk(KERN_INFO "PCI: Using configuration type 1\n");
265 raw_pci_ops = &pci_direct_conf1;
268 release_resource(region);
271 if ((pci_probe & PCI_PROBE_CONF2) == 0)
273 region = request_region(0xCF8, 4, "PCI conf2");
276 region2 = request_region(0xC000, 0x1000, "PCI conf2");
280 if (pci_check_type2()) {
281 printk(KERN_INFO "PCI: Using configuration type 2\n");
282 raw_pci_ops = &pci_direct_conf2;
286 release_resource(region2);
288 release_resource(region);