2 * file: include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
8 * blackfin serial driver head file
14 * bugs: enter bugs at http://blackfin.uclinux.org/
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
32 #include <linux/serial.h>
34 #include <asm/portmux.h>
36 #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37 #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38 #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
39 #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
40 #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
41 #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
42 #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43 #define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR))
44 #define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR))
46 #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
47 #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
48 #define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
49 #define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
50 #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
51 #define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
52 #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
53 #define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
54 #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
55 #define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
57 #define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
58 #define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
60 #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
61 #define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS))
62 #define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS))
63 #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
64 #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
66 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
67 # define CONFIG_SERIAL_BFIN_CTSRTS
69 # ifndef CONFIG_UART0_CTS_PIN
70 # define CONFIG_UART0_CTS_PIN -1
73 # ifndef CONFIG_UART0_RTS_PIN
74 # define CONFIG_UART0_RTS_PIN -1
77 # ifndef CONFIG_UART1_CTS_PIN
78 # define CONFIG_UART1_CTS_PIN -1
81 # ifndef CONFIG_UART1_RTS_PIN
82 # define CONFIG_UART1_RTS_PIN -1
86 * The pin configuration is different from schematic
88 struct bfin_serial_port {
89 struct uart_port port;
90 unsigned int old_status;
91 #ifdef CONFIG_SERIAL_BFIN_DMA
94 struct circ_buf rx_dma_buf;
95 struct timer_list rx_dma_timer;
97 unsigned int tx_dma_channel;
98 unsigned int rx_dma_channel;
99 struct work_struct tx_dma_workqueue;
101 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
102 struct timer_list cts_timer;
108 struct bfin_serial_res {
109 unsigned long uart_base_addr;
111 #ifdef CONFIG_SERIAL_BFIN_DMA
112 unsigned int uart_tx_dma_channel;
113 unsigned int uart_rx_dma_channel;
115 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
121 struct bfin_serial_res bfin_serial_resource[] = {
122 #ifdef CONFIG_SERIAL_BFIN_UART0
126 #ifdef CONFIG_SERIAL_BFIN_DMA
130 #ifdef CONFIG_BFIN_UART0_CTSRTS
131 CONFIG_UART0_CTS_PIN,
132 CONFIG_UART0_RTS_PIN,
136 #ifdef CONFIG_SERIAL_BFIN_UART1
140 #ifdef CONFIG_SERIAL_BFIN_DMA
146 #ifdef CONFIG_SERIAL_BFIN_UART2
150 #ifdef CONFIG_SERIAL_BFIN_DMA
154 #ifdef CONFIG_BFIN_UART2_CTSRTS
155 CONFIG_UART2_CTS_PIN,
156 CONFIG_UART2_RTS_PIN,
160 #ifdef CONFIG_SERIAL_BFIN_UART3
164 #ifdef CONFIG_SERIAL_BFIN_DMA
172 #define DRIVER_NAME "bfin-uart"
174 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
176 #ifdef CONFIG_SERIAL_BFIN_UART0
177 peripheral_request(P_UART0_TX, DRIVER_NAME);
178 peripheral_request(P_UART0_RX, DRIVER_NAME);
181 #ifdef CONFIG_SERIAL_BFIN_UART1
182 peripheral_request(P_UART1_TX, DRIVER_NAME);
183 peripheral_request(P_UART1_RX, DRIVER_NAME);
185 #ifdef CONFIG_BFIN_UART1_CTSRTS
186 peripheral_request(P_UART1_RTS, DRIVER_NAME);
187 peripheral_request(P_UART1_CTS, DRIVER_NAME);
191 #ifdef CONFIG_SERIAL_BFIN_UART2
192 peripheral_request(P_UART2_TX, DRIVER_NAME);
193 peripheral_request(P_UART2_RX, DRIVER_NAME);
196 #ifdef CONFIG_SERIAL_BFIN_UART3
197 peripheral_request(P_UART3_TX, DRIVER_NAME);
198 peripheral_request(P_UART3_RX, DRIVER_NAME);
200 #ifdef CONFIG_BFIN_UART3_CTSRTS
201 peripheral_request(P_UART3_RTS, DRIVER_NAME);
202 peripheral_request(P_UART3_CTS, DRIVER_NAME);
206 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
207 if (uart->cts_pin >= 0) {
208 gpio_request(uart->cts_pin, DRIVER_NAME);
209 gpio_direction_input(uart->cts_pin);
212 if (uart->rts_pin >= 0) {
213 gpio_request(uart->rts_pin, DRIVER_NAME);
214 gpio_direction_output(uart->rts_pin, 0);