arch/arm/mach-shmobile/clock-r8a73a4.c

   1 /*
   2  * r8a73a4 clock framework support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/sh_clk.h>
  24 #include <linux/clkdev.h>
  25 #include <mach/clock.h>
  26 #include <mach/common.h>
  27
  28 #define CPG_BASE 0xe6150000
  29 #define CPG_LEN 0x270
  30
  31 #define SMSTPCR2 0xe6150138
  32 #define SMSTPCR3 0xe615013c
  33 #define SMSTPCR5 0xe6150144
  34
  35 #define FRQCRA          0xE6150000
  36 #define FRQCRB          0xE6150004
  37 #define FRQCRC          0xE61500E0
  38 #define VCLKCR1         0xE6150008
  39 #define VCLKCR2         0xE615000C
  40 #define VCLKCR3         0xE615001C
  41 #define VCLKCR4         0xE6150014
  42 #define VCLKCR5         0xE6150034
  43 #define ZBCKCR          0xE6150010
  44 #define SD0CKCR         0xE6150074
  45 #define SD1CKCR         0xE6150078
  46 #define SD2CKCR         0xE615007C
  47 #define MMC0CKCR        0xE6150240
  48 #define MMC1CKCR        0xE6150244
  49 #define FSIACKCR        0xE6150018
  50 #define FSIBCKCR        0xE6150090
  51 #define MPCKCR          0xe6150080
  52 #define SPUVCKCR        0xE6150094
  53 #define HSICKCR         0xE615026C
  54 #define M4CKCR          0xE6150098
  55 #define PLLECR          0xE61500D0
  56 #define PLL0CR          0xE61500D8
  57 #define PLL1CR          0xE6150028
  58 #define PLL2CR          0xE615002C
  59 #define PLL2SCR         0xE61501F4
  60 #define PLL2HCR         0xE61501E4
  61 #define CKSCR           0xE61500C0
  62
  63 #define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
  64
  65 static struct clk_mapping cpg_mapping = {
  66         .phys   = CPG_BASE,
  67         .len    = CPG_LEN,
  68 };
  69
  70 static struct clk extalr_clk = {
  71         .rate   = 32768,
  72         .mapping        = &cpg_mapping,
  73 };
  74
  75 static struct clk extal1_clk = {
  76         .rate   = 26000000,
  77         .mapping        = &cpg_mapping,
  78 };
  79
  80 static struct clk extal2_clk = {
  81         .rate   = 48000000,
  82         .mapping        = &cpg_mapping,
  83 };
  84
  85 static struct sh_clk_ops followparent_clk_ops = {
  86         .recalc = followparent_recalc,
  87 };
  88
  89 static struct clk main_clk = {
  90         /* .parent will be set r8a73a4_clock_init */
  91         .ops    = &followparent_clk_ops,
  92 };
  93
  94 SH_CLK_RATIO(div2,      1, 2);
  95 SH_CLK_RATIO(div4,      1, 4);
  96
  97 SH_FIXED_RATIO_CLK(main_div2_clk,       main_clk,               div2);
  98 SH_FIXED_RATIO_CLK(extal1_div2_clk,     extal1_clk,             div2);
  99 SH_FIXED_RATIO_CLK(extal2_div2_clk,     extal2_clk,             div2);
 100 SH_FIXED_RATIO_CLK(extal2_div4_clk,     extal2_clk,             div4);
 101
 102 /* External FSIACK/FSIBCK clock */
 103 static struct clk fsiack_clk = {
 104 };
 105
 106 static struct clk fsibck_clk = {
 107 };
 108
 109 /*
 110  *              PLL clocks
 111  */
 112 static struct clk *pll_parent_main[] = {
 113         [0] = &main_clk,
 114         [1] = &main_div2_clk
 115 };
 116
 117 static struct clk *pll_parent_main_extal[8] = {
 118         [0] = &main_div2_clk,
 119         [1] = &extal2_div2_clk,
 120         [3] = &extal2_div4_clk,
 121         [4] = &main_clk,
 122         [5] = &extal2_clk,
 123 };
 124
 125 static unsigned long pll_recalc(struct clk *clk)
 126 {
 127         unsigned long mult = 1;
 128
 129         if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
 130                 mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
 131
 132         return clk->parent->rate * mult;
 133 }
 134
 135 static int pll_set_parent(struct clk *clk, struct clk *parent)
 136 {
 137         u32 val;
 138         int i, ret;
 139
 140         if (!clk->parent_table || !clk->parent_num)
 141                 return -EINVAL;
 142
 143         /* Search the parent */
 144         for (i = 0; i < clk->parent_num; i++)
 145                 if (clk->parent_table[i] == parent)
 146                         break;
 147
 148         if (i == clk->parent_num)
 149                 return -ENODEV;
 150
 151         ret = clk_reparent(clk, parent);
 152         if (ret < 0)
 153                 return ret;
 154
 155         val = ioread32(clk->mapped_reg) &
 156                 ~(((1 << clk->src_width) - 1) << clk->src_shift);
 157
 158         iowrite32(val | i << clk->src_shift, clk->mapped_reg);
 159
 160         return 0;
 161 }
 162
 163 static struct sh_clk_ops pll_clk_ops = {
 164         .recalc         = pll_recalc,
 165         .set_parent     = pll_set_parent,
 166 };
 167
 168 #define PLL_CLOCK(name, p, pt, w, s, reg, e)            \
 169         static struct clk name = {                      \
 170                 .ops            = &pll_clk_ops,         \
 171                 .flags          = CLK_ENABLE_ON_INIT,   \
 172                 .parent         = p,                    \
 173                 .parent_table   = pt,                   \
 174                 .parent_num     = ARRAY_SIZE(pt),       \
 175                 .src_width      = w,                    \
 176                 .src_shift      = s,                    \
 177                 .enable_reg     = (void __iomem *)reg,  \
 178                 .enable_bit     = e,                    \
 179                 .mapping        = &cpg_mapping,         \
 180         }
 181
 182 PLL_CLOCK(pll0_clk,  &main_clk,      pll_parent_main,      1, 20, PLL0CR,  0);
 183 PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
 184 PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
 185 PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
 186 PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
 187
 188 SH_FIXED_RATIO_CLK(pll1_div2_clk,       pll1_clk,       div2);
 189
 190 static atomic_t frqcr_lock;
 191
 192 /* Several clocks need to access FRQCRB, have to lock */
 193 static bool frqcr_kick_check(struct clk *clk)
 194 {
 195         return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31));
 196 }
 197
 198 static int frqcr_kick_do(struct clk *clk)
 199 {
 200         int i;
 201
 202         /* set KICK bit in FRQCRB to update hardware setting, check success */
 203         iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
 204         for (i = 1000; i; i--)
 205                 if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
 206                         cpu_relax();
 207                 else
 208                         return 0;
 209
 210         return -ETIMEDOUT;
 211 }
 212
 213 static int zclk_set_rate(struct clk *clk, unsigned long rate)
 214 {
 215         void __iomem *frqcrc;
 216         int ret;
 217         unsigned long step, p_rate;
 218         u32 val;
 219
 220         if (!clk->parent || !__clk_get(clk->parent))
 221                 return -ENODEV;
 222
 223         if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) {
 224                 ret = -EBUSY;
 225                 goto done;
 226         }
 227
 228         /*
 229          * Users are supposed to first call clk_set_rate() only with
 230          * clk_round_rate() results. So, we don't fix wrong rates here, but
 231          * guard against them anyway
 232          */
 233
 234         p_rate = clk_get_rate(clk->parent);
 235         if (rate == p_rate) {
 236                 val = 0;
 237         } else {
 238                 step = DIV_ROUND_CLOSEST(p_rate, 32);
 239
 240                 if (rate > p_rate || rate < step) {
 241                         ret = -EINVAL;
 242                         goto done;
 243                 }
 244
 245                 val = 32 - rate / step;
 246         }
 247
 248         frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
 249
 250         iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
 251                   (val << clk->enable_bit), frqcrc);
 252
 253         ret = frqcr_kick_do(clk);
 254
 255 done:
 256         atomic_dec(&frqcr_lock);
 257         __clk_put(clk->parent);
 258         return ret;
 259 }
 260
 261 static long zclk_round_rate(struct clk *clk, unsigned long rate)
 262 {
 263         /*
 264          * theoretical rate = parent rate * multiplier / 32,
 265          * where 1 <= multiplier <= 32. Therefore we should do
 266          * multiplier = rate * 32 / parent rate
 267          * rounded rate = parent rate * multiplier / 32.
 268          * However, multiplication before division won't fit in 32 bits, so
 269          * we sacrifice some precision by first dividing and then multiplying.
 270          * To find the nearest divisor we calculate both and pick up the best
 271          * one. This avoids 64-bit arithmetics.
 272          */
 273         unsigned long step, mul_min, mul_max, rate_min, rate_max;
 274
 275         rate_max = clk_get_rate(clk->parent);
 276
 277         /* output freq <= parent */
 278         if (rate >= rate_max)
 279                 return rate_max;
 280
 281         step = DIV_ROUND_CLOSEST(rate_max, 32);
 282         /* output freq >= parent / 32 */
 283         if (step >= rate)
 284                 return step;
 285
 286         mul_min = rate / step;
 287         mul_max = DIV_ROUND_UP(rate, step);
 288         rate_min = step * mul_min;
 289         if (mul_max == mul_min)
 290                 return rate_min;
 291
 292         rate_max = step * mul_max;
 293
 294         if (rate_max - rate <  rate - rate_min)
 295                 return rate_max;
 296
 297         return rate_min;
 298 }
 299
 300 static unsigned long zclk_recalc(struct clk *clk)
 301 {
 302         void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
 303         unsigned int max = clk->div_mask + 1;
 304         unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
 305                              clk->div_mask);
 306
 307         return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
 308                 (max - val);
 309 }
 310
 311 static struct sh_clk_ops zclk_ops = {
 312         .recalc = zclk_recalc,
 313         .set_rate = zclk_set_rate,
 314         .round_rate = zclk_round_rate,
 315 };
 316
 317 static struct clk z_clk = {
 318         .parent = &pll0_clk,
 319         .div_mask = 0x1f,
 320         .enable_bit = 8,
 321         /* We'll need to access FRQCRB and FRQCRC */
 322         .enable_reg = (void __iomem *)FRQCRB,
 323         .ops = &zclk_ops,
 324 };
 325
 326 /*
 327  * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
 328  * switching is only available in auto-DVFS mode
 329  */
 330 SH_FIXED_RATIO_CLK(pll0_div2_clk,       pll0_clk,               div2);
 331
 332 static struct clk z2_clk = {
 333         .parent = &pll0_div2_clk,
 334         .div_mask = 0x1f,
 335         .enable_bit = 0,
 336         /* We'll need to access FRQCRB and FRQCRC */
 337         .enable_reg = (void __iomem *)FRQCRB,
 338         .ops = &zclk_ops,
 339 };
 340
 341 static struct clk *main_clks[] = {
 342         &extalr_clk,
 343         &extal1_clk,
 344         &extal1_div2_clk,
 345         &extal2_clk,
 346         &extal2_div2_clk,
 347         &extal2_div4_clk,
 348         &main_clk,
 349         &main_div2_clk,
 350         &fsiack_clk,
 351         &fsibck_clk,
 352         &pll0_clk,
 353         &pll1_clk,
 354         &pll1_div2_clk,
 355         &pll2_clk,
 356         &pll2s_clk,
 357         &pll2h_clk,
 358         &z_clk,
 359         &pll0_div2_clk,
 360         &z2_clk,
 361 };
 362
 363 /* DIV4 */
 364 static void div4_kick(struct clk *clk)
 365 {
 366         if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n"))
 367                 frqcr_kick_do(clk);
 368         atomic_dec(&frqcr_lock);
 369 }
 370
 371 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
 372
 373 static struct clk_div_mult_table div4_div_mult_table = {
 374         .divisors       = divisors,
 375         .nr_divisors    = ARRAY_SIZE(divisors),
 376 };
 377
 378 static struct clk_div4_table div4_table = {
 379         .div_mult_table = &div4_div_mult_table,
 380         .kick           = div4_kick,
 381 };
 382
 383 enum {
 384         DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 385         DIV4_ZX, DIV4_ZS, DIV4_HP,
 386         DIV4_NR };
 387
 388 static struct clk div4_clks[DIV4_NR] = {
 389         [DIV4_I]        = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
 390         [DIV4_M3]       = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
 391         [DIV4_B]        = SH_CLK_DIV4(&pll1_clk, FRQCRA,  8, 0x0dff, CLK_ENABLE_ON_INIT),
 392         [DIV4_M1]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  4, 0x1dff, 0),
 393         [DIV4_M2]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  0, 0x1dff, 0),
 394         [DIV4_ZX]       = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
 395         [DIV4_ZS]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  8, 0x0dff, 0),
 396         [DIV4_HP]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  4, 0x0dff, 0),
 397 };
 398
 399 enum {
 400         DIV6_ZB,
 401         DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
 402         DIV6_MMC0, DIV6_MMC1,
 403         DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
 404         DIV6_FSIA, DIV6_FSIB,
 405         DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
 406         DIV6_NR };
 407
 408 static struct clk *div6_parents[8] = {
 409         [0] = &pll1_div2_clk,
 410         [1] = &pll2s_clk,
 411         [3] = &extal2_clk,
 412         [4] = &main_div2_clk,
 413         [6] = &extalr_clk,
 414 };
 415
 416 static struct clk *fsia_parents[4] = {
 417         [0] = &pll1_div2_clk,
 418         [1] = &pll2s_clk,
 419         [2] = &fsiack_clk,
 420 };
 421
 422 static struct clk *fsib_parents[4] = {
 423         [0] = &pll1_div2_clk,
 424         [1] = &pll2s_clk,
 425         [2] = &fsibck_clk,
 426 };
 427
 428 static struct clk *mp_parents[4] = {
 429         [0] = &pll1_div2_clk,
 430         [1] = &pll2s_clk,
 431         [2] = &extal2_clk,
 432         [3] = &extal2_clk,
 433 };
 434
 435 static struct clk *m4_parents[2] = {
 436         [0] = &pll2s_clk,
 437 };
 438
 439 static struct clk *hsi_parents[4] = {
 440         [0] = &pll2h_clk,
 441         [1] = &pll1_div2_clk,
 442         [3] = &pll2s_clk,
 443 };
 444
 445 /*** FIXME ***
 446  * SH_CLK_DIV6_EXT() macro doesn't care .mapping
 447  * but, it is necessary on R-Car (= ioremap() base CPG)
 448  * The difference between
 449  * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
 450  * is only .mapping
 451  */
 452 #define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents,                     \
 453                             _num_parents, _src_shift, _src_width)       \
 454 {                                                                       \
 455         .enable_reg     = (void __iomem *)_reg,                         \
 456         .enable_bit     = 0, /* unused */                               \
 457         .flags          = _flags | CLK_MASK_DIV_ON_DISABLE,             \
 458         .div_mask       = SH_CLK_DIV6_MSK,                              \
 459         .parent_table   = _parents,                                     \
 460         .parent_num     = _num_parents,                                 \
 461         .src_shift      = _src_shift,                                   \
 462         .src_width      = _src_width,                                   \
 463         .mapping        = &cpg_mapping,                                 \
 464 }
 465
 466 static struct clk div6_clks[DIV6_NR] = {
 467         [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
 468                                 div6_parents, 2, 7, 1),
 469         [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
 470                                 div6_parents, 2, 6, 2),
 471         [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
 472                                 div6_parents, 2, 6, 2),
 473         [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
 474                                 div6_parents, 2, 6, 2),
 475         [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
 476                                 div6_parents, 2, 6, 2),
 477         [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
 478                                 div6_parents, 2, 6, 2),
 479         [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
 480                                 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
 481         [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
 482                                 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
 483         [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
 484                                 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
 485         [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
 486                                 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
 487         [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
 488                                 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
 489         [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
 490                                 fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
 491         [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
 492                                 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
 493         [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
 494                                 mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
 495         /* pll2s will be selected always for M4 */
 496         [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
 497                                 m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
 498         [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
 499                                 hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
 500         [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
 501                                 mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
 502 };
 503
 504 /* MSTP */
 505 enum {
 506         MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
 507         MSTP315, MSTP314, MSTP313, MSTP312, MSTP305,
 508         MSTP522,
 509         MSTP_NR
 510 };
 511
 512 static struct clk mstp_clks[MSTP_NR] = {
 513         [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 4, 0), /* SCIFA0 */
 514         [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 3, 0), /* SCIFA1 */
 515         [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 6, 0), /* SCIFB0 */
 516         [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 7, 0), /* SCIFB1 */
 517         [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 16, 0), /* SCIFB2 */
 518         [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 17, 0), /* SCIFB3 */
 519         [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
 520         [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
 521         [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
 522         [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
 523         [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
 524         [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
 525 };
 526
 527 static struct clk_lookup lookups[] = {
 528         /* main clock */
 529         CLKDEV_CON_ID("extal1",                 &extal1_clk),
 530         CLKDEV_CON_ID("extal1_div2",            &extal1_div2_clk),
 531         CLKDEV_CON_ID("extal2",                 &extal2_clk),
 532         CLKDEV_CON_ID("extal2_div2",            &extal2_div2_clk),
 533         CLKDEV_CON_ID("extal2_div4",            &extal2_div4_clk),
 534         CLKDEV_CON_ID("fsiack",                 &fsiack_clk),
 535         CLKDEV_CON_ID("fsibck",                 &fsibck_clk),
 536
 537         /* pll clock */
 538         CLKDEV_CON_ID("pll1",                   &pll1_clk),
 539         CLKDEV_CON_ID("pll1_div2",              &pll1_div2_clk),
 540         CLKDEV_CON_ID("pll2",                   &pll2_clk),
 541         CLKDEV_CON_ID("pll2s",                  &pll2s_clk),
 542         CLKDEV_CON_ID("pll2h",                  &pll2h_clk),
 543
 544         /* CPU clock */
 545         CLKDEV_DEV_ID("cpufreq-cpu0",           &z_clk),
 546
 547         /* DIV6 */
 548         CLKDEV_CON_ID("zb",                     &div6_clks[DIV6_ZB]),
 549         CLKDEV_CON_ID("vck1",                   &div6_clks[DIV6_VCK1]),
 550         CLKDEV_CON_ID("vck2",                   &div6_clks[DIV6_VCK2]),
 551         CLKDEV_CON_ID("vck3",                   &div6_clks[DIV6_VCK3]),
 552         CLKDEV_CON_ID("vck4",                   &div6_clks[DIV6_VCK4]),
 553         CLKDEV_CON_ID("vck5",                   &div6_clks[DIV6_VCK5]),
 554         CLKDEV_CON_ID("fsia",                   &div6_clks[DIV6_FSIA]),
 555         CLKDEV_CON_ID("fsib",                   &div6_clks[DIV6_FSIB]),
 556         CLKDEV_CON_ID("mp",                     &div6_clks[DIV6_MP]),
 557         CLKDEV_CON_ID("m4",                     &div6_clks[DIV6_M4]),
 558         CLKDEV_CON_ID("hsi",                    &div6_clks[DIV6_HSI]),
 559         CLKDEV_CON_ID("spuv",                   &div6_clks[DIV6_SPUV]),
 560
 561         /* MSTP */
 562         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
 563         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
 564         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
 565         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
 566         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
 567         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
 568         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
 569         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
 570         CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
 571         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
 572         CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
 573         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
 574         CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
 575         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
 576         CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
 577         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
 578         CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
 579
 580         /* for DT */
 581         CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
 582 };
 583
 584 void __init r8a73a4_clock_init(void)
 585 {
 586         void __iomem *reg;
 587         int k, ret = 0;
 588         u32 ckscr;
 589
 590         atomic_set(&frqcr_lock, -1);
 591
 592         reg = ioremap_nocache(CKSCR, PAGE_SIZE);
 593         BUG_ON(!reg);
 594         ckscr = ioread32(reg);
 595         iounmap(reg);
 596
 597         switch ((ckscr >> 28) & 0x3) {
 598         case 0:
 599                 main_clk.parent = &extal1_clk;
 600                 break;
 601         case 1:
 602                 main_clk.parent = &extal1_div2_clk;
 603                 break;
 604         case 2:
 605                 main_clk.parent = &extal2_clk;
 606                 break;
 607         case 3:
 608                 main_clk.parent = &extal2_div2_clk;
 609                 break;
 610         }
 611
 612         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 613                 ret = clk_register(main_clks[k]);
 614
 615         if (!ret)
 616                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 617
 618         if (!ret)
 619                 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
 620
 621         if (!ret)
 622                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 623
 624         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 625
 626         if (!ret)
 627                 shmobile_clk_init();
 628         else
 629                 panic("failed to setup r8a73a4 clocks\n");
 630 }