arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   6 #include <dt-bindings/soc/qcom,gsbi.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8
   9 / {
  10         model = "Qualcomm APQ8064";
  11         compatible = "qcom,apq8064";
  12         interrupt-parent = <&intc>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         compatible = "qcom,krait";
  20                         enable-method = "qcom,kpss-acc-v1";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                         qcom,acc = <&acc0>;
  25                         qcom,saw = <&saw0>;
  26                 };
  27
  28                 cpu@1 {
  29                         compatible = "qcom,krait";
  30                         enable-method = "qcom,kpss-acc-v1";
  31                         device_type = "cpu";
  32                         reg = <1>;
  33                         next-level-cache = <&L2>;
  34                         qcom,acc = <&acc1>;
  35                         qcom,saw = <&saw1>;
  36                 };
  37
  38                 cpu@2 {
  39                         compatible = "qcom,krait";
  40                         enable-method = "qcom,kpss-acc-v1";
  41                         device_type = "cpu";
  42                         reg = <2>;
  43                         next-level-cache = <&L2>;
  44                         qcom,acc = <&acc2>;
  45                         qcom,saw = <&saw2>;
  46                 };
  47
  48                 cpu@3 {
  49                         compatible = "qcom,krait";
  50                         enable-method = "qcom,kpss-acc-v1";
  51                         device_type = "cpu";
  52                         reg = <3>;
  53                         next-level-cache = <&L2>;
  54                         qcom,acc = <&acc3>;
  55                         qcom,saw = <&saw3>;
  56                 };
  57
  58                 L2: l2-cache {
  59                         compatible = "cache";
  60                         cache-level = <2>;
  61                 };
  62         };
  63
  64         cpu-pmu {
  65                 compatible = "qcom,krait-pmu";
  66                 interrupts = <1 10 0x304>;
  67         };
  68
  69         soc: soc {
  70                 #address-cells = <1>;
  71                 #size-cells = <1>;
  72                 ranges;
  73                 compatible = "simple-bus";
  74
  75                 tlmm_pinmux: pinctrl@800000 {
  76                         compatible = "qcom,apq8064-pinctrl";
  77                         reg = <0x800000 0x4000>;
  78
  79                         gpio-controller;
  80                         #gpio-cells = <2>;
  81                         interrupt-controller;
  82                         #interrupt-cells = <2>;
  83                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
  84
  85                         pinctrl-names = "default";
  86                         pinctrl-0 = <&ps_hold>;
  87
  88                         sdc4_gpios: sdc4-gpios {
  89                                 pios {
  90                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
  91                                         function = "sdc4";
  92                                 };
  93                         };
  94
  95                         ps_hold: ps_hold {
  96                                 mux {
  97                                         pins = "gpio78";
  98                                         function = "ps_hold";
  99                                 };
 100                         };
 101                 };
 102
 103                 intc: interrupt-controller@2000000 {
 104                         compatible = "qcom,msm-qgic2";
 105                         interrupt-controller;
 106                         #interrupt-cells = <3>;
 107                         reg = <0x02000000 0x1000>,
 108                               <0x02002000 0x1000>;
 109                 };
 110
 111                 timer@200a000 {
 112                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 113                         interrupts = <1 1 0x301>,
 114                                      <1 2 0x301>,
 115                                      <1 3 0x301>;
 116                         reg = <0x0200a000 0x100>;
 117                         clock-frequency = <27000000>,
 118                                           <32768>;
 119                         cpu-offset = <0x80000>;
 120                 };
 121
 122                 acc0: clock-controller@2088000 {
 123                         compatible = "qcom,kpss-acc-v1";
 124                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 125                 };
 126
 127                 acc1: clock-controller@2098000 {
 128                         compatible = "qcom,kpss-acc-v1";
 129                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 130                 };
 131
 132                 acc2: clock-controller@20a8000 {
 133                         compatible = "qcom,kpss-acc-v1";
 134                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 135                 };
 136
 137                 acc3: clock-controller@20b8000 {
 138                         compatible = "qcom,kpss-acc-v1";
 139                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 140                 };
 141
 142                 saw0: power-controller@2089000 {
 143                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 144                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 145                         regulator;
 146                 };
 147
 148                 saw1: power-controller@2099000 {
 149                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 150                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 151                         regulator;
 152                 };
 153
 154                 saw2: power-controller@20a9000 {
 155                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 156                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 157                         regulator;
 158                 };
 159
 160                 saw3: power-controller@20b9000 {
 161                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 162                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 163                         regulator;
 164                 };
 165
 166                 gsbi1: gsbi@12440000 {
 167                         status = "disabled";
 168                         compatible = "qcom,gsbi-v1.0.0";
 169                         cell-index = <1>;
 170                         reg = <0x12440000 0x100>;
 171                         clocks = <&gcc GSBI1_H_CLK>;
 172                         clock-names = "iface";
 173                         #address-cells = <1>;
 174                         #size-cells = <1>;
 175                         ranges;
 176
 177                         syscon-tcsr = <&tcsr>;
 178
 179                         i2c1: i2c@12460000 {
 180                                 compatible = "qcom,i2c-qup-v1.1.1";
 181                                 reg = <0x12460000 0x1000>;
 182                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 183                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 184                                 clock-names = "core", "iface";
 185                                 #address-cells = <1>;
 186                                 #size-cells = <0>;
 187                         };
 188                 };
 189
 190                 gsbi2: gsbi@12480000 {
 191                         status = "disabled";
 192                         compatible = "qcom,gsbi-v1.0.0";
 193                         cell-index = <2>;
 194                         reg = <0x12480000 0x100>;
 195                         clocks = <&gcc GSBI2_H_CLK>;
 196                         clock-names = "iface";
 197                         #address-cells = <1>;
 198                         #size-cells = <1>;
 199                         ranges;
 200
 201                         syscon-tcsr = <&tcsr>;
 202
 203                         i2c2: i2c@124a0000 {
 204                                 compatible = "qcom,i2c-qup-v1.1.1";
 205                                 reg = <0x124a0000 0x1000>;
 206                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 207                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 208                                 clock-names = "core", "iface";
 209                                 #address-cells = <1>;
 210                                 #size-cells = <0>;
 211                         };
 212                 };
 213
 214                 gsbi7: gsbi@16600000 {
 215                         status = "disabled";
 216                         compatible = "qcom,gsbi-v1.0.0";
 217                         cell-index = <7>;
 218                         reg = <0x16600000 0x100>;
 219                         clocks = <&gcc GSBI7_H_CLK>;
 220                         clock-names = "iface";
 221                         #address-cells = <1>;
 222                         #size-cells = <1>;
 223                         ranges;
 224
 225                         syscon-tcsr = <&tcsr>;
 226
 227                         serial@16640000 {
 228                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 229                                 reg = <0x16640000 0x1000>,
 230                                       <0x16600000 0x1000>;
 231                                 interrupts = <0 158 0x0>;
 232                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 233                                 clock-names = "core", "iface";
 234                                 status = "disabled";
 235                         };
 236                 };
 237
 238                 qcom,ssbi@500000 {
 239                         compatible = "qcom,ssbi";
 240                         reg = <0x00500000 0x1000>;
 241                         qcom,controller-type = "pmic-arbiter";
 242                 };
 243
 244                 gcc: clock-controller@900000 {
 245                         compatible = "qcom,gcc-apq8064";
 246                         reg = <0x00900000 0x4000>;
 247                         #clock-cells = <1>;
 248                         #reset-cells = <1>;
 249                 };
 250
 251                 lcc: clock-controller@28000000 {
 252                         compatible = "qcom,lcc-apq8064";
 253                         reg = <0x28000000 0x1000>;
 254                         #clock-cells = <1>;
 255                         #reset-cells = <1>;
 256                 };
 257
 258                 mmcc: clock-controller@4000000 {
 259                         compatible = "qcom,mmcc-apq8064";
 260                         reg = <0x4000000 0x1000>;
 261                         #clock-cells = <1>;
 262                         #reset-cells = <1>;
 263                 };
 264
 265                 /* Temporary fixed regulator */
 266                 vsdcc_fixed: vsdcc-regulator {
 267                         compatible = "regulator-fixed";
 268                         regulator-name = "SDCC Power";
 269                         regulator-min-microvolt = <2700000>;
 270                         regulator-max-microvolt = <2700000>;
 271                         regulator-always-on;
 272                 };
 273
 274                 sdcc1bam:dma@12402000{
 275                         compatible = "qcom,bam-v1.3.0";
 276                         reg = <0x12402000 0x8000>;
 277                         interrupts = <0 98 0>;
 278                         clocks = <&gcc SDC1_H_CLK>;
 279                         clock-names = "bam_clk";
 280                         #dma-cells = <1>;
 281                         qcom,ee = <0>;
 282                 };
 283
 284                 sdcc3bam:dma@12182000{
 285                         compatible = "qcom,bam-v1.3.0";
 286                         reg = <0x12182000 0x8000>;
 287                         interrupts = <0 96 0>;
 288                         clocks = <&gcc SDC3_H_CLK>;
 289                         clock-names = "bam_clk";
 290                         #dma-cells = <1>;
 291                         qcom,ee = <0>;
 292                 };
 293
 294                 sdcc4bam:dma@121c2000{
 295                         compatible = "qcom,bam-v1.3.0";
 296                         reg = <0x121c2000 0x8000>;
 297                         interrupts = <0 95 0>;
 298                         clocks = <&gcc SDC4_H_CLK>;
 299                         clock-names = "bam_clk";
 300                         #dma-cells = <1>;
 301                         qcom,ee = <0>;
 302                 };
 303
 304                 amba {
 305                         compatible = "arm,amba-bus";
 306                         #address-cells = <1>;
 307                         #size-cells = <1>;
 308                         ranges;
 309                         sdcc1: sdcc@12400000 {
 310                                 status          = "disabled";
 311                                 compatible      = "arm,pl18x", "arm,primecell";
 312                                 arm,primecell-periphid = <0x00051180>;
 313                                 reg             = <0x12400000 0x2000>;
 314                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 315                                 interrupt-names = "cmd_irq";
 316                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 317                                 clock-names     = "mclk", "apb_pclk";
 318                                 bus-width       = <8>;
 319                                 max-frequency   = <96000000>;
 320                                 non-removable;
 321                                 cap-sd-highspeed;
 322                                 cap-mmc-highspeed;
 323                                 vmmc-supply = <&vsdcc_fixed>;
 324                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 325                                 dma-names = "tx", "rx";
 326                         };
 327
 328                         sdcc3: sdcc@12180000 {
 329                                 compatible      = "arm,pl18x", "arm,primecell";
 330                                 arm,primecell-periphid = <0x00051180>;
 331                                 status          = "disabled";
 332                                 reg             = <0x12180000 0x2000>;
 333                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 334                                 interrupt-names = "cmd_irq";
 335                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 336                                 clock-names     = "mclk", "apb_pclk";
 337                                 bus-width       = <4>;
 338                                 cap-sd-highspeed;
 339                                 cap-mmc-highspeed;
 340                                 max-frequency   = <192000000>;
 341                                 no-1-8-v;
 342                                 vmmc-supply = <&vsdcc_fixed>;
 343                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 344                                 dma-names = "tx", "rx";
 345                         };
 346
 347                         sdcc4: sdcc@121c0000 {
 348                                 compatible      = "arm,pl18x", "arm,primecell";
 349                                 arm,primecell-periphid = <0x00051180>;
 350                                 status          = "disabled";
 351                                 reg             = <0x121c0000 0x2000>;
 352                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 353                                 interrupt-names = "cmd_irq";
 354                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 355                                 clock-names     = "mclk", "apb_pclk";
 356                                 bus-width       = <4>;
 357                                 cap-sd-highspeed;
 358                                 cap-mmc-highspeed;
 359                                 max-frequency   = <48000000>;
 360                                 vmmc-supply = <&vsdcc_fixed>;
 361                                 vqmmc-supply = <&vsdcc_fixed>;
 362                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 363                                 dma-names = "tx", "rx";
 364                                 pinctrl-names = "default";
 365                                 pinctrl-0 = <&sdc4_gpios>;
 366                         };
 367                 };
 368
 369                 tcsr: syscon@1a400000 {
 370                         compatible = "qcom,tcsr-apq8064", "syscon";
 371                         reg = <0x1a400000 0x100>;
 372                 };
 373         };
 374 };