arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         compatible = "ti,omap4430", "ti,omap4";
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 i2c0 = &i2c1;
  21                 i2c1 = &i2c2;
  22                 i2c2 = &i2c3;
  23                 i2c3 = &i2c4;
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 serial3 = &uart4;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a9";
  36                         device_type = "cpu";
  37                         next-level-cache = <&L2>;
  38                         reg = <0x0>;
  39                 };
  40                 cpu@1 {
  41                         compatible = "arm,cortex-a9";
  42                         device_type = "cpu";
  43                         next-level-cache = <&L2>;
  44                         reg = <0x1>;
  45                 };
  46         };
  47
  48         gic: interrupt-controller@48241000 {
  49                 compatible = "arm,cortex-a9-gic";
  50                 interrupt-controller;
  51                 #interrupt-cells = <3>;
  52                 reg = <0x48241000 0x1000>,
  53                       <0x48240100 0x0100>;
  54         };
  55
  56         L2: l2-cache-controller@48242000 {
  57                 compatible = "arm,pl310-cache";
  58                 reg = <0x48242000 0x1000>;
  59                 cache-unified;
  60                 cache-level = <2>;
  61         };
  62
  63         local-timer@48240600 {
  64                 compatible = "arm,cortex-a9-twd-timer";
  65                 reg = <0x48240600 0x20>;
  66                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
  67         };
  68
  69         /*
  70          * The soc node represents the soc top level view. It is uses for IPs
  71          * that are not memory mapped in the MPU view or for the MPU itself.
  72          */
  73         soc {
  74                 compatible = "ti,omap-infra";
  75                 mpu {
  76                         compatible = "ti,omap4-mpu";
  77                         ti,hwmods = "mpu";
  78                 };
  79
  80                 dsp {
  81                         compatible = "ti,omap3-c64";
  82                         ti,hwmods = "dsp";
  83                 };
  84
  85                 iva {
  86                         compatible = "ti,ivahd";
  87                         ti,hwmods = "iva";
  88                 };
  89         };
  90
  91         /*
  92          * XXX: Use a flat representation of the OMAP4 interconnect.
  93          * The real OMAP interconnect network is quite complex.
  94          * Since that will not bring real advantage to represent that in DT for
  95          * the moment, just use a fake OCP bus entry to represent the whole bus
  96          * hierarchy.
  97          */
  98         ocp {
  99                 compatible = "ti,omap4-l3-noc", "simple-bus";
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 104                 reg = <0x44000000 0x1000>,
 105                       <0x44800000 0x2000>,
 106                       <0x45000000 0x1000>;
 107                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 108                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 109
 110                 cm1: cm1@4a004000 {
 111                         compatible = "ti,omap4-cm1";
 112                         reg = <0x4a004000 0x2000>;
 113
 114                         cm1_clocks: clocks {
 115                                 #address-cells = <1>;
 116                                 #size-cells = <0>;
 117                         };
 118
 119                         cm1_clockdomains: clockdomains {
 120                         };
 121                 };
 122
 123                 prm: prm@4a306000 {
 124                         compatible = "ti,omap4-prm";
 125                         reg = <0x4a306000 0x3000>;
 126
 127                         prm_clocks: clocks {
 128                                 #address-cells = <1>;
 129                                 #size-cells = <0>;
 130                         };
 131
 132                         prm_clockdomains: clockdomains {
 133                         };
 134                 };
 135
 136                 cm2: cm2@4a008000 {
 137                         compatible = "ti,omap4-cm2";
 138                         reg = <0x4a008000 0x3000>;
 139
 140                         cm2_clocks: clocks {
 141                                 #address-cells = <1>;
 142                                 #size-cells = <0>;
 143                         };
 144
 145                         cm2_clockdomains: clockdomains {
 146                         };
 147                 };
 148
 149                 scrm: scrm@4a30a000 {
 150                         compatible = "ti,omap4-scrm";
 151                         reg = <0x4a30a000 0x2000>;
 152
 153                         scrm_clocks: clocks {
 154                                 #address-cells = <1>;
 155                                 #size-cells = <0>;
 156                         };
 157
 158                         scrm_clockdomains: clockdomains {
 159                         };
 160                 };
 161
 162                 counter32k: counter@4a304000 {
 163                         compatible = "ti,omap-counter32k";
 164                         reg = <0x4a304000 0x20>;
 165                         ti,hwmods = "counter_32k";
 166                 };
 167
 168                 omap4_pmx_core: pinmux@4a100040 {
 169                         compatible = "ti,omap4-padconf", "pinctrl-single";
 170                         reg = <0x4a100040 0x0196>;
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         #interrupt-cells = <1>;
 174                         interrupt-controller;
 175                         pinctrl-single,register-width = <16>;
 176                         pinctrl-single,function-mask = <0x7fff>;
 177                 };
 178                 omap4_pmx_wkup: pinmux@4a31e040 {
 179                         compatible = "ti,omap4-padconf", "pinctrl-single";
 180                         reg = <0x4a31e040 0x0038>;
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183                         #interrupt-cells = <1>;
 184                         interrupt-controller;
 185                         pinctrl-single,register-width = <16>;
 186                         pinctrl-single,function-mask = <0x7fff>;
 187                 };
 188
 189                 sdma: dma-controller@4a056000 {
 190                         compatible = "ti,omap4430-sdma";
 191                         reg = <0x4a056000 0x1000>;
 192                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 193                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 194                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 195                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 196                         #dma-cells = <1>;
 197                         #dma-channels = <32>;
 198                         #dma-requests = <127>;
 199                 };
 200
 201                 gpio1: gpio@4a310000 {
 202                         compatible = "ti,omap4-gpio";
 203                         reg = <0x4a310000 0x200>;
 204                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 205                         ti,hwmods = "gpio1";
 206                         ti,gpio-always-on;
 207                         gpio-controller;
 208                         #gpio-cells = <2>;
 209                         interrupt-controller;
 210                         #interrupt-cells = <2>;
 211                 };
 212
 213                 gpio2: gpio@48055000 {
 214                         compatible = "ti,omap4-gpio";
 215                         reg = <0x48055000 0x200>;
 216                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 217                         ti,hwmods = "gpio2";
 218                         gpio-controller;
 219                         #gpio-cells = <2>;
 220                         interrupt-controller;
 221                         #interrupt-cells = <2>;
 222                 };
 223
 224                 gpio3: gpio@48057000 {
 225                         compatible = "ti,omap4-gpio";
 226                         reg = <0x48057000 0x200>;
 227                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 228                         ti,hwmods = "gpio3";
 229                         gpio-controller;
 230                         #gpio-cells = <2>;
 231                         interrupt-controller;
 232                         #interrupt-cells = <2>;
 233                 };
 234
 235                 gpio4: gpio@48059000 {
 236                         compatible = "ti,omap4-gpio";
 237                         reg = <0x48059000 0x200>;
 238                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 239                         ti,hwmods = "gpio4";
 240                         gpio-controller;
 241                         #gpio-cells = <2>;
 242                         interrupt-controller;
 243                         #interrupt-cells = <2>;
 244                 };
 245
 246                 gpio5: gpio@4805b000 {
 247                         compatible = "ti,omap4-gpio";
 248                         reg = <0x4805b000 0x200>;
 249                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 250                         ti,hwmods = "gpio5";
 251                         gpio-controller;
 252                         #gpio-cells = <2>;
 253                         interrupt-controller;
 254                         #interrupt-cells = <2>;
 255                 };
 256
 257                 gpio6: gpio@4805d000 {
 258                         compatible = "ti,omap4-gpio";
 259                         reg = <0x4805d000 0x200>;
 260                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 261                         ti,hwmods = "gpio6";
 262                         gpio-controller;
 263                         #gpio-cells = <2>;
 264                         interrupt-controller;
 265                         #interrupt-cells = <2>;
 266                 };
 267
 268                 gpmc: gpmc@50000000 {
 269                         compatible = "ti,omap4430-gpmc";
 270                         reg = <0x50000000 0x1000>;
 271                         #address-cells = <2>;
 272                         #size-cells = <1>;
 273                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 274                         gpmc,num-cs = <8>;
 275                         gpmc,num-waitpins = <4>;
 276                         ti,hwmods = "gpmc";
 277                         ti,no-idle-on-init;
 278                         clocks = <&l3_div_ck>;
 279                         clock-names = "fck";
 280                 };
 281
 282                 uart1: serial@4806a000 {
 283                         compatible = "ti,omap4-uart";
 284                         reg = <0x4806a000 0x100>;
 285                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 286                         ti,hwmods = "uart1";
 287                         clock-frequency = <48000000>;
 288                 };
 289
 290                 uart2: serial@4806c000 {
 291                         compatible = "ti,omap4-uart";
 292                         reg = <0x4806c000 0x100>;
 293                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 294                         ti,hwmods = "uart2";
 295                         clock-frequency = <48000000>;
 296                 };
 297
 298                 uart3: serial@48020000 {
 299                         compatible = "ti,omap4-uart";
 300                         reg = <0x48020000 0x100>;
 301                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 302                         ti,hwmods = "uart3";
 303                         clock-frequency = <48000000>;
 304                 };
 305
 306                 uart4: serial@4806e000 {
 307                         compatible = "ti,omap4-uart";
 308                         reg = <0x4806e000 0x100>;
 309                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 310                         ti,hwmods = "uart4";
 311                         clock-frequency = <48000000>;
 312                 };
 313
 314                 hwspinlock: spinlock@4a0f6000 {
 315                         compatible = "ti,omap4-hwspinlock";
 316                         reg = <0x4a0f6000 0x1000>;
 317                         ti,hwmods = "spinlock";
 318                 };
 319
 320                 i2c1: i2c@48070000 {
 321                         compatible = "ti,omap4-i2c";
 322                         reg = <0x48070000 0x100>;
 323                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 324                         #address-cells = <1>;
 325                         #size-cells = <0>;
 326                         ti,hwmods = "i2c1";
 327                 };
 328
 329                 i2c2: i2c@48072000 {
 330                         compatible = "ti,omap4-i2c";
 331                         reg = <0x48072000 0x100>;
 332                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         ti,hwmods = "i2c2";
 336                 };
 337
 338                 i2c3: i2c@48060000 {
 339                         compatible = "ti,omap4-i2c";
 340                         reg = <0x48060000 0x100>;
 341                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344                         ti,hwmods = "i2c3";
 345                 };
 346
 347                 i2c4: i2c@48350000 {
 348                         compatible = "ti,omap4-i2c";
 349                         reg = <0x48350000 0x100>;
 350                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 351                         #address-cells = <1>;
 352                         #size-cells = <0>;
 353                         ti,hwmods = "i2c4";
 354                 };
 355
 356                 mcspi1: spi@48098000 {
 357                         compatible = "ti,omap4-mcspi";
 358                         reg = <0x48098000 0x200>;
 359                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 360                         #address-cells = <1>;
 361                         #size-cells = <0>;
 362                         ti,hwmods = "mcspi1";
 363                         ti,spi-num-cs = <4>;
 364                         dmas = <&sdma 35>,
 365                                <&sdma 36>,
 366                                <&sdma 37>,
 367                                <&sdma 38>,
 368                                <&sdma 39>,
 369                                <&sdma 40>,
 370                                <&sdma 41>,
 371                                <&sdma 42>;
 372                         dma-names = "tx0", "rx0", "tx1", "rx1",
 373                                     "tx2", "rx2", "tx3", "rx3";
 374                 };
 375
 376                 mcspi2: spi@4809a000 {
 377                         compatible = "ti,omap4-mcspi";
 378                         reg = <0x4809a000 0x200>;
 379                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         ti,hwmods = "mcspi2";
 383                         ti,spi-num-cs = <2>;
 384                         dmas = <&sdma 43>,
 385                                <&sdma 44>,
 386                                <&sdma 45>,
 387                                <&sdma 46>;
 388                         dma-names = "tx0", "rx0", "tx1", "rx1";
 389                 };
 390
 391                 mcspi3: spi@480b8000 {
 392                         compatible = "ti,omap4-mcspi";
 393                         reg = <0x480b8000 0x200>;
 394                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 395                         #address-cells = <1>;
 396                         #size-cells = <0>;
 397                         ti,hwmods = "mcspi3";
 398                         ti,spi-num-cs = <2>;
 399                         dmas = <&sdma 15>, <&sdma 16>;
 400                         dma-names = "tx0", "rx0";
 401                 };
 402
 403                 mcspi4: spi@480ba000 {
 404                         compatible = "ti,omap4-mcspi";
 405                         reg = <0x480ba000 0x200>;
 406                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 407                         #address-cells = <1>;
 408                         #size-cells = <0>;
 409                         ti,hwmods = "mcspi4";
 410                         ti,spi-num-cs = <1>;
 411                         dmas = <&sdma 70>, <&sdma 71>;
 412                         dma-names = "tx0", "rx0";
 413                 };
 414
 415                 mmc1: mmc@4809c000 {
 416                         compatible = "ti,omap4-hsmmc";
 417                         reg = <0x4809c000 0x400>;
 418                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 419                         ti,hwmods = "mmc1";
 420                         ti,dual-volt;
 421                         ti,needs-special-reset;
 422                         dmas = <&sdma 61>, <&sdma 62>;
 423                         dma-names = "tx", "rx";
 424                 };
 425
 426                 mmc2: mmc@480b4000 {
 427                         compatible = "ti,omap4-hsmmc";
 428                         reg = <0x480b4000 0x400>;
 429                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 430                         ti,hwmods = "mmc2";
 431                         ti,needs-special-reset;
 432                         dmas = <&sdma 47>, <&sdma 48>;
 433                         dma-names = "tx", "rx";
 434                 };
 435
 436                 mmc3: mmc@480ad000 {
 437                         compatible = "ti,omap4-hsmmc";
 438                         reg = <0x480ad000 0x400>;
 439                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 440                         ti,hwmods = "mmc3";
 441                         ti,needs-special-reset;
 442                         dmas = <&sdma 77>, <&sdma 78>;
 443                         dma-names = "tx", "rx";
 444                 };
 445
 446                 mmc4: mmc@480d1000 {
 447                         compatible = "ti,omap4-hsmmc";
 448                         reg = <0x480d1000 0x400>;
 449                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 450                         ti,hwmods = "mmc4";
 451                         ti,needs-special-reset;
 452                         dmas = <&sdma 57>, <&sdma 58>;
 453                         dma-names = "tx", "rx";
 454                 };
 455
 456                 mmc5: mmc@480d5000 {
 457                         compatible = "ti,omap4-hsmmc";
 458                         reg = <0x480d5000 0x400>;
 459                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 460                         ti,hwmods = "mmc5";
 461                         ti,needs-special-reset;
 462                         dmas = <&sdma 59>, <&sdma 60>;
 463                         dma-names = "tx", "rx";
 464                 };
 465
 466                 wdt2: wdt@4a314000 {
 467                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 468                         reg = <0x4a314000 0x80>;
 469                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 470                         ti,hwmods = "wd_timer2";
 471                 };
 472
 473                 mcpdm: mcpdm@40132000 {
 474                         compatible = "ti,omap4-mcpdm";
 475                         reg = <0x40132000 0x7f>, /* MPU private access */
 476                               <0x49032000 0x7f>; /* L3 Interconnect */
 477                         reg-names = "mpu", "dma";
 478                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 479                         ti,hwmods = "mcpdm";
 480                         dmas = <&sdma 65>,
 481                                <&sdma 66>;
 482                         dma-names = "up_link", "dn_link";
 483                 };
 484
 485                 dmic: dmic@4012e000 {
 486                         compatible = "ti,omap4-dmic";
 487                         reg = <0x4012e000 0x7f>, /* MPU private access */
 488                               <0x4902e000 0x7f>; /* L3 Interconnect */
 489                         reg-names = "mpu", "dma";
 490                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 491                         ti,hwmods = "dmic";
 492                         dmas = <&sdma 67>;
 493                         dma-names = "up_link";
 494                 };
 495
 496                 mcbsp1: mcbsp@40122000 {
 497                         compatible = "ti,omap4-mcbsp";
 498                         reg = <0x40122000 0xff>, /* MPU private access */
 499                               <0x49022000 0xff>; /* L3 Interconnect */
 500                         reg-names = "mpu", "dma";
 501                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 502                         interrupt-names = "common";
 503                         ti,buffer-size = <128>;
 504                         ti,hwmods = "mcbsp1";
 505                         dmas = <&sdma 33>,
 506                                <&sdma 34>;
 507                         dma-names = "tx", "rx";
 508                 };
 509
 510                 mcbsp2: mcbsp@40124000 {
 511                         compatible = "ti,omap4-mcbsp";
 512                         reg = <0x40124000 0xff>, /* MPU private access */
 513                               <0x49024000 0xff>; /* L3 Interconnect */
 514                         reg-names = "mpu", "dma";
 515                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 516                         interrupt-names = "common";
 517                         ti,buffer-size = <128>;
 518                         ti,hwmods = "mcbsp2";
 519                         dmas = <&sdma 17>,
 520                                <&sdma 18>;
 521                         dma-names = "tx", "rx";
 522                 };
 523
 524                 mcbsp3: mcbsp@40126000 {
 525                         compatible = "ti,omap4-mcbsp";
 526                         reg = <0x40126000 0xff>, /* MPU private access */
 527                               <0x49026000 0xff>; /* L3 Interconnect */
 528                         reg-names = "mpu", "dma";
 529                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 530                         interrupt-names = "common";
 531                         ti,buffer-size = <128>;
 532                         ti,hwmods = "mcbsp3";
 533                         dmas = <&sdma 19>,
 534                                <&sdma 20>;
 535                         dma-names = "tx", "rx";
 536                 };
 537
 538                 mcbsp4: mcbsp@48096000 {
 539                         compatible = "ti,omap4-mcbsp";
 540                         reg = <0x48096000 0xff>; /* L4 Interconnect */
 541                         reg-names = "mpu";
 542                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 543                         interrupt-names = "common";
 544                         ti,buffer-size = <128>;
 545                         ti,hwmods = "mcbsp4";
 546                         dmas = <&sdma 31>,
 547                                <&sdma 32>;
 548                         dma-names = "tx", "rx";
 549                 };
 550
 551                 keypad: keypad@4a31c000 {
 552                         compatible = "ti,omap4-keypad";
 553                         reg = <0x4a31c000 0x80>;
 554                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 555                         reg-names = "mpu";
 556                         ti,hwmods = "kbd";
 557                 };
 558
 559                 emif1: emif@4c000000 {
 560                         compatible = "ti,emif-4d";
 561                         reg = <0x4c000000 0x100>;
 562                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 563                         ti,hwmods = "emif1";
 564                         ti,no-idle-on-init;
 565                         phy-type = <1>;
 566                         hw-caps-read-idle-ctrl;
 567                         hw-caps-ll-interface;
 568                         hw-caps-temp-alert;
 569                 };
 570
 571                 emif2: emif@4d000000 {
 572                         compatible = "ti,emif-4d";
 573                         reg = <0x4d000000 0x100>;
 574                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 575                         ti,hwmods = "emif2";
 576                         ti,no-idle-on-init;
 577                         phy-type = <1>;
 578                         hw-caps-read-idle-ctrl;
 579                         hw-caps-ll-interface;
 580                         hw-caps-temp-alert;
 581                 };
 582
 583                 ocp2scp@4a0ad000 {
 584                         compatible = "ti,omap-ocp2scp";
 585                         reg = <0x4a0ad000 0x1f>;
 586                         #address-cells = <1>;
 587                         #size-cells = <1>;
 588                         ranges;
 589                         ti,hwmods = "ocp2scp_usb_phy";
 590                         usb2_phy: usb2phy@4a0ad080 {
 591                                 compatible = "ti,omap-usb2";
 592                                 reg = <0x4a0ad080 0x58>;
 593                                 ctrl-module = <&omap_control_usb2phy>;
 594                                 #phy-cells = <0>;
 595                         };
 596                 };
 597
 598                 timer1: timer@4a318000 {
 599                         compatible = "ti,omap3430-timer";
 600                         reg = <0x4a318000 0x80>;
 601                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 602                         ti,hwmods = "timer1";
 603                         ti,timer-alwon;
 604                 };
 605
 606                 timer2: timer@48032000 {
 607                         compatible = "ti,omap3430-timer";
 608                         reg = <0x48032000 0x80>;
 609                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 610                         ti,hwmods = "timer2";
 611                 };
 612
 613                 timer3: timer@48034000 {
 614                         compatible = "ti,omap4430-timer";
 615                         reg = <0x48034000 0x80>;
 616                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 617                         ti,hwmods = "timer3";
 618                 };
 619
 620                 timer4: timer@48036000 {
 621                         compatible = "ti,omap4430-timer";
 622                         reg = <0x48036000 0x80>;
 623                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 624                         ti,hwmods = "timer4";
 625                 };
 626
 627                 timer5: timer@40138000 {
 628                         compatible = "ti,omap4430-timer";
 629                         reg = <0x40138000 0x80>,
 630                               <0x49038000 0x80>;
 631                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 632                         ti,hwmods = "timer5";
 633                         ti,timer-dsp;
 634                 };
 635
 636                 timer6: timer@4013a000 {
 637                         compatible = "ti,omap4430-timer";
 638                         reg = <0x4013a000 0x80>,
 639                               <0x4903a000 0x80>;
 640                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 641                         ti,hwmods = "timer6";
 642                         ti,timer-dsp;
 643                 };
 644
 645                 timer7: timer@4013c000 {
 646                         compatible = "ti,omap4430-timer";
 647                         reg = <0x4013c000 0x80>,
 648                               <0x4903c000 0x80>;
 649                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 650                         ti,hwmods = "timer7";
 651                         ti,timer-dsp;
 652                 };
 653
 654                 timer8: timer@4013e000 {
 655                         compatible = "ti,omap4430-timer";
 656                         reg = <0x4013e000 0x80>,
 657                               <0x4903e000 0x80>;
 658                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 659                         ti,hwmods = "timer8";
 660                         ti,timer-pwm;
 661                         ti,timer-dsp;
 662                 };
 663
 664                 timer9: timer@4803e000 {
 665                         compatible = "ti,omap4430-timer";
 666                         reg = <0x4803e000 0x80>;
 667                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 668                         ti,hwmods = "timer9";
 669                         ti,timer-pwm;
 670                 };
 671
 672                 timer10: timer@48086000 {
 673                         compatible = "ti,omap3430-timer";
 674                         reg = <0x48086000 0x80>;
 675                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 676                         ti,hwmods = "timer10";
 677                         ti,timer-pwm;
 678                 };
 679
 680                 timer11: timer@48088000 {
 681                         compatible = "ti,omap4430-timer";
 682                         reg = <0x48088000 0x80>;
 683                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 684                         ti,hwmods = "timer11";
 685                         ti,timer-pwm;
 686                 };
 687
 688                 usbhstll: usbhstll@4a062000 {
 689                         compatible = "ti,usbhs-tll";
 690                         reg = <0x4a062000 0x1000>;
 691                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 692                         ti,hwmods = "usb_tll_hs";
 693                 };
 694
 695                 usbhshost: usbhshost@4a064000 {
 696                         compatible = "ti,usbhs-host";
 697                         reg = <0x4a064000 0x800>;
 698                         ti,hwmods = "usb_host_hs";
 699                         #address-cells = <1>;
 700                         #size-cells = <1>;
 701                         ranges;
 702
 703                         usbhsohci: ohci@4a064800 {
 704                                 compatible = "ti,ohci-omap3", "usb-ohci";
 705                                 reg = <0x4a064800 0x400>;
 706                                 interrupt-parent = <&gic>;
 707                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 708                         };
 709
 710                         usbhsehci: ehci@4a064c00 {
 711                                 compatible = "ti,ehci-omap", "usb-ehci";
 712                                 reg = <0x4a064c00 0x400>;
 713                                 interrupt-parent = <&gic>;
 714                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 715                         };
 716                 };
 717
 718                 omap_control_usb2phy: control-phy@4a002300 {
 719                         compatible = "ti,control-phy-usb2";
 720                         reg = <0x4a002300 0x4>;
 721                         reg-names = "power";
 722                 };
 723
 724                 omap_control_usbotg: control-phy@4a00233c {
 725                         compatible = "ti,control-phy-otghs";
 726                         reg = <0x4a00233c 0x4>;
 727                         reg-names = "otghs_control";
 728                 };
 729
 730                 usb_otg_hs: usb_otg_hs@4a0ab000 {
 731                         compatible = "ti,omap4-musb";
 732                         reg = <0x4a0ab000 0x7ff>;
 733                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 734                         interrupt-names = "mc", "dma";
 735                         ti,hwmods = "usb_otg_hs";
 736                         usb-phy = <&usb2_phy>;
 737                         phys = <&usb2_phy>;
 738                         phy-names = "usb2-phy";
 739                         multipoint = <1>;
 740                         num-eps = <16>;
 741                         ram-bits = <12>;
 742                         ctrl-module = <&omap_control_usbotg>;
 743                 };
 744
 745                 aes: aes@4b501000 {
 746                         compatible = "ti,omap4-aes";
 747                         ti,hwmods = "aes";
 748                         reg = <0x4b501000 0xa0>;
 749                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 750                         dmas = <&sdma 111>, <&sdma 110>;
 751                         dma-names = "tx", "rx";
 752                 };
 753
 754                 des: des@480a5000 {
 755                         compatible = "ti,omap4-des";
 756                         ti,hwmods = "des";
 757                         reg = <0x480a5000 0xa0>;
 758                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 759                         dmas = <&sdma 117>, <&sdma 116>;
 760                         dma-names = "tx", "rx";
 761                 };
 762         };
 763 };
 764
 765 /include/ "omap44xx-clocks.dtsi"