arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         compatible = "ti,omap4430", "ti,omap4";
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 i2c0 = &i2c1;
  21                 i2c1 = &i2c2;
  22                 i2c2 = &i2c3;
  23                 i2c3 = &i2c4;
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 serial3 = &uart4;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a9";
  36                         device_type = "cpu";
  37                         next-level-cache = <&L2>;
  38                         reg = <0x0>;
  39
  40                         clocks = <&dpll_mpu_ck>;
  41                         clock-names = "cpu";
  42
  43                         clock-latency = <300000>; /* From omap-cpufreq driver */
  44                 };
  45                 cpu@1 {
  46                         compatible = "arm,cortex-a9";
  47                         device_type = "cpu";
  48                         next-level-cache = <&L2>;
  49                         reg = <0x1>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@48241000 {
  54                 compatible = "arm,cortex-a9-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 reg = <0x48241000 0x1000>,
  58                       <0x48240100 0x0100>;
  59         };
  60
  61         L2: l2-cache-controller@48242000 {
  62                 compatible = "arm,pl310-cache";
  63                 reg = <0x48242000 0x1000>;
  64                 cache-unified;
  65                 cache-level = <2>;
  66         };
  67
  68         local-timer@48240600 {
  69                 compatible = "arm,cortex-a9-twd-timer";
  70                 reg = <0x48240600 0x20>;
  71                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
  72         };
  73
  74         /*
  75          * The soc node represents the soc top level view. It is uses for IPs
  76          * that are not memory mapped in the MPU view or for the MPU itself.
  77          */
  78         soc {
  79                 compatible = "ti,omap-infra";
  80                 mpu {
  81                         compatible = "ti,omap4-mpu";
  82                         ti,hwmods = "mpu";
  83                 };
  84
  85                 dsp {
  86                         compatible = "ti,omap3-c64";
  87                         ti,hwmods = "dsp";
  88                 };
  89
  90                 iva {
  91                         compatible = "ti,ivahd";
  92                         ti,hwmods = "iva";
  93                 };
  94         };
  95
  96         /*
  97          * XXX: Use a flat representation of the OMAP4 interconnect.
  98          * The real OMAP interconnect network is quite complex.
  99          * Since that will not bring real advantage to represent that in DT for
 100          * the moment, just use a fake OCP bus entry to represent the whole bus
 101          * hierarchy.
 102          */
 103         ocp {
 104                 compatible = "ti,omap4-l3-noc", "simple-bus";
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 ranges;
 108                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 109                 reg = <0x44000000 0x1000>,
 110                       <0x44800000 0x2000>,
 111                       <0x45000000 0x1000>;
 112                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 113                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 114
 115                 cm1: cm1@4a004000 {
 116                         compatible = "ti,omap4-cm1";
 117                         reg = <0x4a004000 0x2000>;
 118
 119                         cm1_clocks: clocks {
 120                                 #address-cells = <1>;
 121                                 #size-cells = <0>;
 122                         };
 123
 124                         cm1_clockdomains: clockdomains {
 125                         };
 126                 };
 127
 128                 prm: prm@4a306000 {
 129                         compatible = "ti,omap4-prm";
 130                         reg = <0x4a306000 0x3000>;
 131
 132                         prm_clocks: clocks {
 133                                 #address-cells = <1>;
 134                                 #size-cells = <0>;
 135                         };
 136
 137                         prm_clockdomains: clockdomains {
 138                         };
 139                 };
 140
 141                 cm2: cm2@4a008000 {
 142                         compatible = "ti,omap4-cm2";
 143                         reg = <0x4a008000 0x3000>;
 144
 145                         cm2_clocks: clocks {
 146                                 #address-cells = <1>;
 147                                 #size-cells = <0>;
 148                         };
 149
 150                         cm2_clockdomains: clockdomains {
 151                         };
 152                 };
 153
 154                 scrm: scrm@4a30a000 {
 155                         compatible = "ti,omap4-scrm";
 156                         reg = <0x4a30a000 0x2000>;
 157
 158                         scrm_clocks: clocks {
 159                                 #address-cells = <1>;
 160                                 #size-cells = <0>;
 161                         };
 162
 163                         scrm_clockdomains: clockdomains {
 164                         };
 165                 };
 166
 167                 counter32k: counter@4a304000 {
 168                         compatible = "ti,omap-counter32k";
 169                         reg = <0x4a304000 0x20>;
 170                         ti,hwmods = "counter_32k";
 171                 };
 172
 173                 omap4_pmx_core: pinmux@4a100040 {
 174                         compatible = "ti,omap4-padconf", "pinctrl-single";
 175                         reg = <0x4a100040 0x0196>;
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         #interrupt-cells = <1>;
 179                         interrupt-controller;
 180                         pinctrl-single,register-width = <16>;
 181                         pinctrl-single,function-mask = <0x7fff>;
 182                 };
 183                 omap4_pmx_wkup: pinmux@4a31e040 {
 184                         compatible = "ti,omap4-padconf", "pinctrl-single";
 185                         reg = <0x4a31e040 0x0038>;
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188                         #interrupt-cells = <1>;
 189                         interrupt-controller;
 190                         pinctrl-single,register-width = <16>;
 191                         pinctrl-single,function-mask = <0x7fff>;
 192                 };
 193
 194                 sdma: dma-controller@4a056000 {
 195                         compatible = "ti,omap4430-sdma";
 196                         reg = <0x4a056000 0x1000>;
 197                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 201                         #dma-cells = <1>;
 202                         #dma-channels = <32>;
 203                         #dma-requests = <127>;
 204                 };
 205
 206                 gpio1: gpio@4a310000 {
 207                         compatible = "ti,omap4-gpio";
 208                         reg = <0x4a310000 0x200>;
 209                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 210                         ti,hwmods = "gpio1";
 211                         ti,gpio-always-on;
 212                         gpio-controller;
 213                         #gpio-cells = <2>;
 214                         interrupt-controller;
 215                         #interrupt-cells = <2>;
 216                 };
 217
 218                 gpio2: gpio@48055000 {
 219                         compatible = "ti,omap4-gpio";
 220                         reg = <0x48055000 0x200>;
 221                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 222                         ti,hwmods = "gpio2";
 223                         gpio-controller;
 224                         #gpio-cells = <2>;
 225                         interrupt-controller;
 226                         #interrupt-cells = <2>;
 227                 };
 228
 229                 gpio3: gpio@48057000 {
 230                         compatible = "ti,omap4-gpio";
 231                         reg = <0x48057000 0x200>;
 232                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 233                         ti,hwmods = "gpio3";
 234                         gpio-controller;
 235                         #gpio-cells = <2>;
 236                         interrupt-controller;
 237                         #interrupt-cells = <2>;
 238                 };
 239
 240                 gpio4: gpio@48059000 {
 241                         compatible = "ti,omap4-gpio";
 242                         reg = <0x48059000 0x200>;
 243                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 244                         ti,hwmods = "gpio4";
 245                         gpio-controller;
 246                         #gpio-cells = <2>;
 247                         interrupt-controller;
 248                         #interrupt-cells = <2>;
 249                 };
 250
 251                 gpio5: gpio@4805b000 {
 252                         compatible = "ti,omap4-gpio";
 253                         reg = <0x4805b000 0x200>;
 254                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 255                         ti,hwmods = "gpio5";
 256                         gpio-controller;
 257                         #gpio-cells = <2>;
 258                         interrupt-controller;
 259                         #interrupt-cells = <2>;
 260                 };
 261
 262                 gpio6: gpio@4805d000 {
 263                         compatible = "ti,omap4-gpio";
 264                         reg = <0x4805d000 0x200>;
 265                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 266                         ti,hwmods = "gpio6";
 267                         gpio-controller;
 268                         #gpio-cells = <2>;
 269                         interrupt-controller;
 270                         #interrupt-cells = <2>;
 271                 };
 272
 273                 gpmc: gpmc@50000000 {
 274                         compatible = "ti,omap4430-gpmc";
 275                         reg = <0x50000000 0x1000>;
 276                         #address-cells = <2>;
 277                         #size-cells = <1>;
 278                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 279                         gpmc,num-cs = <8>;
 280                         gpmc,num-waitpins = <4>;
 281                         ti,hwmods = "gpmc";
 282                         ti,no-idle-on-init;
 283                 };
 284
 285                 uart1: serial@4806a000 {
 286                         compatible = "ti,omap4-uart";
 287                         reg = <0x4806a000 0x100>;
 288                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 289                         ti,hwmods = "uart1";
 290                         clock-frequency = <48000000>;
 291                 };
 292
 293                 uart2: serial@4806c000 {
 294                         compatible = "ti,omap4-uart";
 295                         reg = <0x4806c000 0x100>;
 296                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 297                         ti,hwmods = "uart2";
 298                         clock-frequency = <48000000>;
 299                 };
 300
 301                 uart3: serial@48020000 {
 302                         compatible = "ti,omap4-uart";
 303                         reg = <0x48020000 0x100>;
 304                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 305                         ti,hwmods = "uart3";
 306                         clock-frequency = <48000000>;
 307                 };
 308
 309                 uart4: serial@4806e000 {
 310                         compatible = "ti,omap4-uart";
 311                         reg = <0x4806e000 0x100>;
 312                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 313                         ti,hwmods = "uart4";
 314                         clock-frequency = <48000000>;
 315                 };
 316
 317                 hwspinlock: spinlock@4a0f6000 {
 318                         compatible = "ti,omap4-hwspinlock";
 319                         reg = <0x4a0f6000 0x1000>;
 320                         ti,hwmods = "spinlock";
 321                         #hwlock-cells = <1>;
 322                 };
 323
 324                 i2c1: i2c@48070000 {
 325                         compatible = "ti,omap4-i2c";
 326                         reg = <0x48070000 0x100>;
 327                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                         ti,hwmods = "i2c1";
 331                 };
 332
 333                 i2c2: i2c@48072000 {
 334                         compatible = "ti,omap4-i2c";
 335                         reg = <0x48072000 0x100>;
 336                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 337                         #address-cells = <1>;
 338                         #size-cells = <0>;
 339                         ti,hwmods = "i2c2";
 340                 };
 341
 342                 i2c3: i2c@48060000 {
 343                         compatible = "ti,omap4-i2c";
 344                         reg = <0x48060000 0x100>;
 345                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         ti,hwmods = "i2c3";
 349                 };
 350
 351                 i2c4: i2c@48350000 {
 352                         compatible = "ti,omap4-i2c";
 353                         reg = <0x48350000 0x100>;
 354                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         ti,hwmods = "i2c4";
 358                 };
 359
 360                 mcspi1: spi@48098000 {
 361                         compatible = "ti,omap4-mcspi";
 362                         reg = <0x48098000 0x200>;
 363                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         ti,hwmods = "mcspi1";
 367                         ti,spi-num-cs = <4>;
 368                         dmas = <&sdma 35>,
 369                                <&sdma 36>,
 370                                <&sdma 37>,
 371                                <&sdma 38>,
 372                                <&sdma 39>,
 373                                <&sdma 40>,
 374                                <&sdma 41>,
 375                                <&sdma 42>;
 376                         dma-names = "tx0", "rx0", "tx1", "rx1",
 377                                     "tx2", "rx2", "tx3", "rx3";
 378                 };
 379
 380                 mcspi2: spi@4809a000 {
 381                         compatible = "ti,omap4-mcspi";
 382                         reg = <0x4809a000 0x200>;
 383                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386                         ti,hwmods = "mcspi2";
 387                         ti,spi-num-cs = <2>;
 388                         dmas = <&sdma 43>,
 389                                <&sdma 44>,
 390                                <&sdma 45>,
 391                                <&sdma 46>;
 392                         dma-names = "tx0", "rx0", "tx1", "rx1";
 393                 };
 394
 395                 mcspi3: spi@480b8000 {
 396                         compatible = "ti,omap4-mcspi";
 397                         reg = <0x480b8000 0x200>;
 398                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         ti,hwmods = "mcspi3";
 402                         ti,spi-num-cs = <2>;
 403                         dmas = <&sdma 15>, <&sdma 16>;
 404                         dma-names = "tx0", "rx0";
 405                 };
 406
 407                 mcspi4: spi@480ba000 {
 408                         compatible = "ti,omap4-mcspi";
 409                         reg = <0x480ba000 0x200>;
 410                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         ti,hwmods = "mcspi4";
 414                         ti,spi-num-cs = <1>;
 415                         dmas = <&sdma 70>, <&sdma 71>;
 416                         dma-names = "tx0", "rx0";
 417                 };
 418
 419                 mmc1: mmc@4809c000 {
 420                         compatible = "ti,omap4-hsmmc";
 421                         reg = <0x4809c000 0x400>;
 422                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 423                         ti,hwmods = "mmc1";
 424                         ti,dual-volt;
 425                         ti,needs-special-reset;
 426                         dmas = <&sdma 61>, <&sdma 62>;
 427                         dma-names = "tx", "rx";
 428                 };
 429
 430                 mmc2: mmc@480b4000 {
 431                         compatible = "ti,omap4-hsmmc";
 432                         reg = <0x480b4000 0x400>;
 433                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 434                         ti,hwmods = "mmc2";
 435                         ti,needs-special-reset;
 436                         dmas = <&sdma 47>, <&sdma 48>;
 437                         dma-names = "tx", "rx";
 438                 };
 439
 440                 mmc3: mmc@480ad000 {
 441                         compatible = "ti,omap4-hsmmc";
 442                         reg = <0x480ad000 0x400>;
 443                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 444                         ti,hwmods = "mmc3";
 445                         ti,needs-special-reset;
 446                         dmas = <&sdma 77>, <&sdma 78>;
 447                         dma-names = "tx", "rx";
 448                 };
 449
 450                 mmc4: mmc@480d1000 {
 451                         compatible = "ti,omap4-hsmmc";
 452                         reg = <0x480d1000 0x400>;
 453                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 454                         ti,hwmods = "mmc4";
 455                         ti,needs-special-reset;
 456                         dmas = <&sdma 57>, <&sdma 58>;
 457                         dma-names = "tx", "rx";
 458                 };
 459
 460                 mmc5: mmc@480d5000 {
 461                         compatible = "ti,omap4-hsmmc";
 462                         reg = <0x480d5000 0x400>;
 463                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 464                         ti,hwmods = "mmc5";
 465                         ti,needs-special-reset;
 466                         dmas = <&sdma 59>, <&sdma 60>;
 467                         dma-names = "tx", "rx";
 468                 };
 469
 470                 mmu_dsp: mmu@4a066000 {
 471                         compatible = "ti,omap4-iommu";
 472                         reg = <0x4a066000 0x100>;
 473                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 474                         ti,hwmods = "mmu_dsp";
 475                 };
 476
 477                 mmu_ipu: mmu@55082000 {
 478                         compatible = "ti,omap4-iommu";
 479                         reg = <0x55082000 0x100>;
 480                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 481                         ti,hwmods = "mmu_ipu";
 482                         ti,iommu-bus-err-back;
 483                 };
 484
 485                 wdt2: wdt@4a314000 {
 486                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 487                         reg = <0x4a314000 0x80>;
 488                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 489                         ti,hwmods = "wd_timer2";
 490                 };
 491
 492                 mcpdm: mcpdm@40132000 {
 493                         compatible = "ti,omap4-mcpdm";
 494                         reg = <0x40132000 0x7f>, /* MPU private access */
 495                               <0x49032000 0x7f>; /* L3 Interconnect */
 496                         reg-names = "mpu", "dma";
 497                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 498                         ti,hwmods = "mcpdm";
 499                         dmas = <&sdma 65>,
 500                                <&sdma 66>;
 501                         dma-names = "up_link", "dn_link";
 502                         status = "disabled";
 503                 };
 504
 505                 dmic: dmic@4012e000 {
 506                         compatible = "ti,omap4-dmic";
 507                         reg = <0x4012e000 0x7f>, /* MPU private access */
 508                               <0x4902e000 0x7f>; /* L3 Interconnect */
 509                         reg-names = "mpu", "dma";
 510                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 511                         ti,hwmods = "dmic";
 512                         dmas = <&sdma 67>;
 513                         dma-names = "up_link";
 514                         status = "disabled";
 515                 };
 516
 517                 mcbsp1: mcbsp@40122000 {
 518                         compatible = "ti,omap4-mcbsp";
 519                         reg = <0x40122000 0xff>, /* MPU private access */
 520                               <0x49022000 0xff>; /* L3 Interconnect */
 521                         reg-names = "mpu", "dma";
 522                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 523                         interrupt-names = "common";
 524                         ti,buffer-size = <128>;
 525                         ti,hwmods = "mcbsp1";
 526                         dmas = <&sdma 33>,
 527                                <&sdma 34>;
 528                         dma-names = "tx", "rx";
 529                         status = "disabled";
 530                 };
 531
 532                 mcbsp2: mcbsp@40124000 {
 533                         compatible = "ti,omap4-mcbsp";
 534                         reg = <0x40124000 0xff>, /* MPU private access */
 535                               <0x49024000 0xff>; /* L3 Interconnect */
 536                         reg-names = "mpu", "dma";
 537                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 538                         interrupt-names = "common";
 539                         ti,buffer-size = <128>;
 540                         ti,hwmods = "mcbsp2";
 541                         dmas = <&sdma 17>,
 542                                <&sdma 18>;
 543                         dma-names = "tx", "rx";
 544                         status = "disabled";
 545                 };
 546
 547                 mcbsp3: mcbsp@40126000 {
 548                         compatible = "ti,omap4-mcbsp";
 549                         reg = <0x40126000 0xff>, /* MPU private access */
 550                               <0x49026000 0xff>; /* L3 Interconnect */
 551                         reg-names = "mpu", "dma";
 552                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 553                         interrupt-names = "common";
 554                         ti,buffer-size = <128>;
 555                         ti,hwmods = "mcbsp3";
 556                         dmas = <&sdma 19>,
 557                                <&sdma 20>;
 558                         dma-names = "tx", "rx";
 559                         status = "disabled";
 560                 };
 561
 562                 mcbsp4: mcbsp@48096000 {
 563                         compatible = "ti,omap4-mcbsp";
 564                         reg = <0x48096000 0xff>; /* L4 Interconnect */
 565                         reg-names = "mpu";
 566                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 567                         interrupt-names = "common";
 568                         ti,buffer-size = <128>;
 569                         ti,hwmods = "mcbsp4";
 570                         dmas = <&sdma 31>,
 571                                <&sdma 32>;
 572                         dma-names = "tx", "rx";
 573                         status = "disabled";
 574                 };
 575
 576                 keypad: keypad@4a31c000 {
 577                         compatible = "ti,omap4-keypad";
 578                         reg = <0x4a31c000 0x80>;
 579                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 580                         reg-names = "mpu";
 581                         ti,hwmods = "kbd";
 582                 };
 583
 584                 dmm@4e000000 {
 585                         compatible = "ti,omap4-dmm";
 586                         reg = <0x4e000000 0x800>;
 587                         interrupts = <0 113 0x4>;
 588                         ti,hwmods = "dmm";
 589                 };
 590
 591                 emif1: emif@4c000000 {
 592                         compatible = "ti,emif-4d";
 593                         reg = <0x4c000000 0x100>;
 594                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 595                         ti,hwmods = "emif1";
 596                         ti,no-idle-on-init;
 597                         phy-type = <1>;
 598                         hw-caps-read-idle-ctrl;
 599                         hw-caps-ll-interface;
 600                         hw-caps-temp-alert;
 601                 };
 602
 603                 emif2: emif@4d000000 {
 604                         compatible = "ti,emif-4d";
 605                         reg = <0x4d000000 0x100>;
 606                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 607                         ti,hwmods = "emif2";
 608                         ti,no-idle-on-init;
 609                         phy-type = <1>;
 610                         hw-caps-read-idle-ctrl;
 611                         hw-caps-ll-interface;
 612                         hw-caps-temp-alert;
 613                 };
 614
 615                 ocp2scp@4a0ad000 {
 616                         compatible = "ti,omap-ocp2scp";
 617                         reg = <0x4a0ad000 0x1f>;
 618                         #address-cells = <1>;
 619                         #size-cells = <1>;
 620                         ranges;
 621                         ti,hwmods = "ocp2scp_usb_phy";
 622                         usb2_phy: usb2phy@4a0ad080 {
 623                                 compatible = "ti,omap-usb2";
 624                                 reg = <0x4a0ad080 0x58>;
 625                                 ctrl-module = <&omap_control_usb2phy>;
 626                                 #phy-cells = <0>;
 627                         };
 628                 };
 629
 630                 timer1: timer@4a318000 {
 631                         compatible = "ti,omap3430-timer";
 632                         reg = <0x4a318000 0x80>;
 633                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 634                         ti,hwmods = "timer1";
 635                         ti,timer-alwon;
 636                 };
 637
 638                 timer2: timer@48032000 {
 639                         compatible = "ti,omap3430-timer";
 640                         reg = <0x48032000 0x80>;
 641                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 642                         ti,hwmods = "timer2";
 643                 };
 644
 645                 timer3: timer@48034000 {
 646                         compatible = "ti,omap4430-timer";
 647                         reg = <0x48034000 0x80>;
 648                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 649                         ti,hwmods = "timer3";
 650                 };
 651
 652                 timer4: timer@48036000 {
 653                         compatible = "ti,omap4430-timer";
 654                         reg = <0x48036000 0x80>;
 655                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 656                         ti,hwmods = "timer4";
 657                 };
 658
 659                 timer5: timer@40138000 {
 660                         compatible = "ti,omap4430-timer";
 661                         reg = <0x40138000 0x80>,
 662                               <0x49038000 0x80>;
 663                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 664                         ti,hwmods = "timer5";
 665                         ti,timer-dsp;
 666                 };
 667
 668                 timer6: timer@4013a000 {
 669                         compatible = "ti,omap4430-timer";
 670                         reg = <0x4013a000 0x80>,
 671                               <0x4903a000 0x80>;
 672                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 673                         ti,hwmods = "timer6";
 674                         ti,timer-dsp;
 675                 };
 676
 677                 timer7: timer@4013c000 {
 678                         compatible = "ti,omap4430-timer";
 679                         reg = <0x4013c000 0x80>,
 680                               <0x4903c000 0x80>;
 681                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 682                         ti,hwmods = "timer7";
 683                         ti,timer-dsp;
 684                 };
 685
 686                 timer8: timer@4013e000 {
 687                         compatible = "ti,omap4430-timer";
 688                         reg = <0x4013e000 0x80>,
 689                               <0x4903e000 0x80>;
 690                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 691                         ti,hwmods = "timer8";
 692                         ti,timer-pwm;
 693                         ti,timer-dsp;
 694                 };
 695
 696                 timer9: timer@4803e000 {
 697                         compatible = "ti,omap4430-timer";
 698                         reg = <0x4803e000 0x80>;
 699                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 700                         ti,hwmods = "timer9";
 701                         ti,timer-pwm;
 702                 };
 703
 704                 timer10: timer@48086000 {
 705                         compatible = "ti,omap3430-timer";
 706                         reg = <0x48086000 0x80>;
 707                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 708                         ti,hwmods = "timer10";
 709                         ti,timer-pwm;
 710                 };
 711
 712                 timer11: timer@48088000 {
 713                         compatible = "ti,omap4430-timer";
 714                         reg = <0x48088000 0x80>;
 715                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 716                         ti,hwmods = "timer11";
 717                         ti,timer-pwm;
 718                 };
 719
 720                 usbhstll: usbhstll@4a062000 {
 721                         compatible = "ti,usbhs-tll";
 722                         reg = <0x4a062000 0x1000>;
 723                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 724                         ti,hwmods = "usb_tll_hs";
 725                 };
 726
 727                 usbhshost: usbhshost@4a064000 {
 728                         compatible = "ti,usbhs-host";
 729                         reg = <0x4a064000 0x800>;
 730                         ti,hwmods = "usb_host_hs";
 731                         #address-cells = <1>;
 732                         #size-cells = <1>;
 733                         ranges;
 734
 735                         usbhsohci: ohci@4a064800 {
 736                                 compatible = "ti,ohci-omap3";
 737                                 reg = <0x4a064800 0x400>;
 738                                 interrupt-parent = <&gic>;
 739                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 740                         };
 741
 742                         usbhsehci: ehci@4a064c00 {
 743                                 compatible = "ti,ehci-omap";
 744                                 reg = <0x4a064c00 0x400>;
 745                                 interrupt-parent = <&gic>;
 746                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 747                         };
 748                 };
 749
 750                 omap_control_usb2phy: control-phy@4a002300 {
 751                         compatible = "ti,control-phy-usb2";
 752                         reg = <0x4a002300 0x4>;
 753                         reg-names = "power";
 754                 };
 755
 756                 omap_control_usbotg: control-phy@4a00233c {
 757                         compatible = "ti,control-phy-otghs";
 758                         reg = <0x4a00233c 0x4>;
 759                         reg-names = "otghs_control";
 760                 };
 761
 762                 usb_otg_hs: usb_otg_hs@4a0ab000 {
 763                         compatible = "ti,omap4-musb";
 764                         reg = <0x4a0ab000 0x7ff>;
 765                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 766                         interrupt-names = "mc", "dma";
 767                         ti,hwmods = "usb_otg_hs";
 768                         usb-phy = <&usb2_phy>;
 769                         phys = <&usb2_phy>;
 770                         phy-names = "usb2-phy";
 771                         multipoint = <1>;
 772                         num-eps = <16>;
 773                         ram-bits = <12>;
 774                         ctrl-module = <&omap_control_usbotg>;
 775                 };
 776
 777                 aes: aes@4b501000 {
 778                         compatible = "ti,omap4-aes";
 779                         ti,hwmods = "aes";
 780                         reg = <0x4b501000 0xa0>;
 781                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 782                         dmas = <&sdma 111>, <&sdma 110>;
 783                         dma-names = "tx", "rx";
 784                 };
 785
 786                 des: des@480a5000 {
 787                         compatible = "ti,omap4-des";
 788                         ti,hwmods = "des";
 789                         reg = <0x480a5000 0xa0>;
 790                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 791                         dmas = <&sdma 117>, <&sdma 116>;
 792                         dma-names = "tx", "rx";
 793                 };
 794
 795                 abb_mpu: regulator-abb-mpu {
 796                         compatible = "ti,abb-v2";
 797                         regulator-name = "abb_mpu";
 798                         #address-cells = <0>;
 799                         #size-cells = <0>;
 800                         ti,tranxdone-status-mask = <0x80>;
 801                         clocks = <&sys_clkin_ck>;
 802                         ti,settling-time = <50>;
 803                         ti,clock-cycles = <16>;
 804
 805                         status = "disabled";
 806                 };
 807
 808                 abb_iva: regulator-abb-iva {
 809                         compatible = "ti,abb-v2";
 810                         regulator-name = "abb_iva";
 811                         #address-cells = <0>;
 812                         #size-cells = <0>;
 813                         ti,tranxdone-status-mask = <0x80000000>;
 814                         clocks = <&sys_clkin_ck>;
 815                         ti,settling-time = <50>;
 816                         ti,clock-cycles = <16>;
 817
 818                         status = "disabled";
 819                 };
 820
 821                 dss: dss@58000000 {
 822                         compatible = "ti,omap4-dss";
 823                         reg = <0x58000000 0x80>;
 824                         status = "disabled";
 825                         ti,hwmods = "dss_core";
 826                         clocks = <&dss_dss_clk>;
 827                         clock-names = "fck";
 828                         #address-cells = <1>;
 829                         #size-cells = <1>;
 830                         ranges;
 831
 832                         dispc@58001000 {
 833                                 compatible = "ti,omap4-dispc";
 834                                 reg = <0x58001000 0x1000>;
 835                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 836                                 ti,hwmods = "dss_dispc";
 837                                 clocks = <&dss_dss_clk>;
 838                                 clock-names = "fck";
 839                         };
 840
 841                         rfbi: encoder@58002000  {
 842                                 compatible = "ti,omap4-rfbi";
 843                                 reg = <0x58002000 0x1000>;
 844                                 status = "disabled";
 845                                 ti,hwmods = "dss_rfbi";
 846                                 clocks = <&dss_dss_clk>, <&dss_fck>;
 847                                 clock-names = "fck", "ick";
 848                         };
 849
 850                         venc: encoder@58003000 {
 851                                 compatible = "ti,omap4-venc";
 852                                 reg = <0x58003000 0x1000>;
 853                                 status = "disabled";
 854                                 ti,hwmods = "dss_venc";
 855                                 clocks = <&dss_tv_clk>;
 856                                 clock-names = "fck";
 857                         };
 858
 859                         dsi1: encoder@58004000 {
 860                                 compatible = "ti,omap4-dsi";
 861                                 reg = <0x58004000 0x200>,
 862                                       <0x58004200 0x40>,
 863                                       <0x58004300 0x20>;
 864                                 reg-names = "proto", "phy", "pll";
 865                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 866                                 status = "disabled";
 867                                 ti,hwmods = "dss_dsi1";
 868                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 869                                 clock-names = "fck", "sys_clk";
 870                         };
 871
 872                         dsi2: encoder@58005000 {
 873                                 compatible = "ti,omap4-dsi";
 874                                 reg = <0x58005000 0x200>,
 875                                       <0x58005200 0x40>,
 876                                       <0x58005300 0x20>;
 877                                 reg-names = "proto", "phy", "pll";
 878                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 879                                 status = "disabled";
 880                                 ti,hwmods = "dss_dsi2";
 881                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 882                                 clock-names = "fck", "sys_clk";
 883                         };
 884
 885                         hdmi: encoder@58006000 {
 886                                 compatible = "ti,omap4-hdmi";
 887                                 reg = <0x58006000 0x200>,
 888                                       <0x58006200 0x100>,
 889                                       <0x58006300 0x100>,
 890                                       <0x58006400 0x1000>;
 891                                 reg-names = "wp", "pll", "phy", "core";
 892                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 893                                 status = "disabled";
 894                                 ti,hwmods = "dss_hdmi";
 895                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
 896                                 clock-names = "fck", "sys_clk";
 897                         };
 898                 };
 899         };
 900 };
 901
 902 /include/ "omap44xx-clocks.dtsi"