arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         compatible = "ti,omap4430", "ti,omap4";
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 i2c0 = &i2c1;
  21                 i2c1 = &i2c2;
  22                 i2c2 = &i2c3;
  23                 i2c3 = &i2c4;
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 serial3 = &uart4;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a9";
  36                         device_type = "cpu";
  37                         next-level-cache = <&L2>;
  38                         reg = <0x0>;
  39
  40                         clocks = <&dpll_mpu_ck>;
  41                         clock-names = "cpu";
  42
  43                         clock-latency = <300000>; /* From omap-cpufreq driver */
  44                 };
  45                 cpu@1 {
  46                         compatible = "arm,cortex-a9";
  47                         device_type = "cpu";
  48                         next-level-cache = <&L2>;
  49                         reg = <0x1>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@48241000 {
  54                 compatible = "arm,cortex-a9-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 reg = <0x48241000 0x1000>,
  58                       <0x48240100 0x0100>;
  59         };
  60
  61         L2: l2-cache-controller@48242000 {
  62                 compatible = "arm,pl310-cache";
  63                 reg = <0x48242000 0x1000>;
  64                 cache-unified;
  65                 cache-level = <2>;
  66         };
  67
  68         local-timer@48240600 {
  69                 compatible = "arm,cortex-a9-twd-timer";
  70                 reg = <0x48240600 0x20>;
  71                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
  72         };
  73
  74         /*
  75          * The soc node represents the soc top level view. It is uses for IPs
  76          * that are not memory mapped in the MPU view or for the MPU itself.
  77          */
  78         soc {
  79                 compatible = "ti,omap-infra";
  80                 mpu {
  81                         compatible = "ti,omap4-mpu";
  82                         ti,hwmods = "mpu";
  83                 };
  84
  85                 dsp {
  86                         compatible = "ti,omap3-c64";
  87                         ti,hwmods = "dsp";
  88                 };
  89
  90                 iva {
  91                         compatible = "ti,ivahd";
  92                         ti,hwmods = "iva";
  93                 };
  94         };
  95
  96         /*
  97          * XXX: Use a flat representation of the OMAP4 interconnect.
  98          * The real OMAP interconnect network is quite complex.
  99          * Since that will not bring real advantage to represent that in DT for
 100          * the moment, just use a fake OCP bus entry to represent the whole bus
 101          * hierarchy.
 102          */
 103         ocp {
 104                 compatible = "ti,omap4-l3-noc", "simple-bus";
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 ranges;
 108                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 109                 reg = <0x44000000 0x1000>,
 110                       <0x44800000 0x2000>,
 111                       <0x45000000 0x1000>;
 112                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 113                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 114
 115                 cm1: cm1@4a004000 {
 116                         compatible = "ti,omap4-cm1";
 117                         reg = <0x4a004000 0x2000>;
 118
 119                         cm1_clocks: clocks {
 120                                 #address-cells = <1>;
 121                                 #size-cells = <0>;
 122                         };
 123
 124                         cm1_clockdomains: clockdomains {
 125                         };
 126                 };
 127
 128                 prm: prm@4a306000 {
 129                         compatible = "ti,omap4-prm";
 130                         reg = <0x4a306000 0x3000>;
 131
 132                         prm_clocks: clocks {
 133                                 #address-cells = <1>;
 134                                 #size-cells = <0>;
 135                         };
 136
 137                         prm_clockdomains: clockdomains {
 138                         };
 139                 };
 140
 141                 cm2: cm2@4a008000 {
 142                         compatible = "ti,omap4-cm2";
 143                         reg = <0x4a008000 0x3000>;
 144
 145                         cm2_clocks: clocks {
 146                                 #address-cells = <1>;
 147                                 #size-cells = <0>;
 148                         };
 149
 150                         cm2_clockdomains: clockdomains {
 151                         };
 152                 };
 153
 154                 scrm: scrm@4a30a000 {
 155                         compatible = "ti,omap4-scrm";
 156                         reg = <0x4a30a000 0x2000>;
 157
 158                         scrm_clocks: clocks {
 159                                 #address-cells = <1>;
 160                                 #size-cells = <0>;
 161                         };
 162
 163                         scrm_clockdomains: clockdomains {
 164                         };
 165                 };
 166
 167                 counter32k: counter@4a304000 {
 168                         compatible = "ti,omap-counter32k";
 169                         reg = <0x4a304000 0x20>;
 170                         ti,hwmods = "counter_32k";
 171                 };
 172
 173                 omap4_pmx_core: pinmux@4a100040 {
 174                         compatible = "ti,omap4-padconf", "pinctrl-single";
 175                         reg = <0x4a100040 0x0196>;
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         #interrupt-cells = <1>;
 179                         interrupt-controller;
 180                         pinctrl-single,register-width = <16>;
 181                         pinctrl-single,function-mask = <0x7fff>;
 182                 };
 183                 omap4_pmx_wkup: pinmux@4a31e040 {
 184                         compatible = "ti,omap4-padconf", "pinctrl-single";
 185                         reg = <0x4a31e040 0x0038>;
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188                         #interrupt-cells = <1>;
 189                         interrupt-controller;
 190                         pinctrl-single,register-width = <16>;
 191                         pinctrl-single,function-mask = <0x7fff>;
 192                 };
 193
 194                 omap4_padconf_global: tisyscon@4a1005a0 {
 195                         compatible = "syscon";
 196                         reg = <0x4a1005a0 0x170>;
 197                 };
 198
 199                 pbias_regulator: pbias_regulator {
 200                         compatible = "ti,pbias-omap";
 201                         reg = <0x60 0x4>;
 202                         syscon = <&omap4_padconf_global>;
 203                         pbias_mmc_reg: pbias_mmc_omap4 {
 204                                 regulator-name = "pbias_mmc_omap4";
 205                                 regulator-min-microvolt = <1800000>;
 206                                 regulator-max-microvolt = <3000000>;
 207                         };
 208                 };
 209
 210                 sdma: dma-controller@4a056000 {
 211                         compatible = "ti,omap4430-sdma";
 212                         reg = <0x4a056000 0x1000>;
 213                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 214                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 217                         #dma-cells = <1>;
 218                         #dma-channels = <32>;
 219                         #dma-requests = <127>;
 220                 };
 221
 222                 gpio1: gpio@4a310000 {
 223                         compatible = "ti,omap4-gpio";
 224                         reg = <0x4a310000 0x200>;
 225                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 226                         ti,hwmods = "gpio1";
 227                         ti,gpio-always-on;
 228                         gpio-controller;
 229                         #gpio-cells = <2>;
 230                         interrupt-controller;
 231                         #interrupt-cells = <2>;
 232                 };
 233
 234                 gpio2: gpio@48055000 {
 235                         compatible = "ti,omap4-gpio";
 236                         reg = <0x48055000 0x200>;
 237                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 238                         ti,hwmods = "gpio2";
 239                         gpio-controller;
 240                         #gpio-cells = <2>;
 241                         interrupt-controller;
 242                         #interrupt-cells = <2>;
 243                 };
 244
 245                 gpio3: gpio@48057000 {
 246                         compatible = "ti,omap4-gpio";
 247                         reg = <0x48057000 0x200>;
 248                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 249                         ti,hwmods = "gpio3";
 250                         gpio-controller;
 251                         #gpio-cells = <2>;
 252                         interrupt-controller;
 253                         #interrupt-cells = <2>;
 254                 };
 255
 256                 gpio4: gpio@48059000 {
 257                         compatible = "ti,omap4-gpio";
 258                         reg = <0x48059000 0x200>;
 259                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 260                         ti,hwmods = "gpio4";
 261                         gpio-controller;
 262                         #gpio-cells = <2>;
 263                         interrupt-controller;
 264                         #interrupt-cells = <2>;
 265                 };
 266
 267                 gpio5: gpio@4805b000 {
 268                         compatible = "ti,omap4-gpio";
 269                         reg = <0x4805b000 0x200>;
 270                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 271                         ti,hwmods = "gpio5";
 272                         gpio-controller;
 273                         #gpio-cells = <2>;
 274                         interrupt-controller;
 275                         #interrupt-cells = <2>;
 276                 };
 277
 278                 gpio6: gpio@4805d000 {
 279                         compatible = "ti,omap4-gpio";
 280                         reg = <0x4805d000 0x200>;
 281                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 282                         ti,hwmods = "gpio6";
 283                         gpio-controller;
 284                         #gpio-cells = <2>;
 285                         interrupt-controller;
 286                         #interrupt-cells = <2>;
 287                 };
 288
 289                 gpmc: gpmc@50000000 {
 290                         compatible = "ti,omap4430-gpmc";
 291                         reg = <0x50000000 0x1000>;
 292                         #address-cells = <2>;
 293                         #size-cells = <1>;
 294                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 295                         gpmc,num-cs = <8>;
 296                         gpmc,num-waitpins = <4>;
 297                         ti,hwmods = "gpmc";
 298                         ti,no-idle-on-init;
 299                         clocks = <&l3_div_ck>;
 300                         clock-names = "fck";
 301                 };
 302
 303                 uart1: serial@4806a000 {
 304                         compatible = "ti,omap4-uart";
 305                         reg = <0x4806a000 0x100>;
 306                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 307                         ti,hwmods = "uart1";
 308                         clock-frequency = <48000000>;
 309                 };
 310
 311                 uart2: serial@4806c000 {
 312                         compatible = "ti,omap4-uart";
 313                         reg = <0x4806c000 0x100>;
 314                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 315                         ti,hwmods = "uart2";
 316                         clock-frequency = <48000000>;
 317                 };
 318
 319                 uart3: serial@48020000 {
 320                         compatible = "ti,omap4-uart";
 321                         reg = <0x48020000 0x100>;
 322                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 323                         ti,hwmods = "uart3";
 324                         clock-frequency = <48000000>;
 325                 };
 326
 327                 uart4: serial@4806e000 {
 328                         compatible = "ti,omap4-uart";
 329                         reg = <0x4806e000 0x100>;
 330                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 331                         ti,hwmods = "uart4";
 332                         clock-frequency = <48000000>;
 333                 };
 334
 335                 hwspinlock: spinlock@4a0f6000 {
 336                         compatible = "ti,omap4-hwspinlock";
 337                         reg = <0x4a0f6000 0x1000>;
 338                         ti,hwmods = "spinlock";
 339                         #hwlock-cells = <1>;
 340                 };
 341
 342                 i2c1: i2c@48070000 {
 343                         compatible = "ti,omap4-i2c";
 344                         reg = <0x48070000 0x100>;
 345                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         ti,hwmods = "i2c1";
 349                 };
 350
 351                 i2c2: i2c@48072000 {
 352                         compatible = "ti,omap4-i2c";
 353                         reg = <0x48072000 0x100>;
 354                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         ti,hwmods = "i2c2";
 358                 };
 359
 360                 i2c3: i2c@48060000 {
 361                         compatible = "ti,omap4-i2c";
 362                         reg = <0x48060000 0x100>;
 363                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         ti,hwmods = "i2c3";
 367                 };
 368
 369                 i2c4: i2c@48350000 {
 370                         compatible = "ti,omap4-i2c";
 371                         reg = <0x48350000 0x100>;
 372                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         ti,hwmods = "i2c4";
 376                 };
 377
 378                 mcspi1: spi@48098000 {
 379                         compatible = "ti,omap4-mcspi";
 380                         reg = <0x48098000 0x200>;
 381                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 382                         #address-cells = <1>;
 383                         #size-cells = <0>;
 384                         ti,hwmods = "mcspi1";
 385                         ti,spi-num-cs = <4>;
 386                         dmas = <&sdma 35>,
 387                                <&sdma 36>,
 388                                <&sdma 37>,
 389                                <&sdma 38>,
 390                                <&sdma 39>,
 391                                <&sdma 40>,
 392                                <&sdma 41>,
 393                                <&sdma 42>;
 394                         dma-names = "tx0", "rx0", "tx1", "rx1",
 395                                     "tx2", "rx2", "tx3", "rx3";
 396                 };
 397
 398                 mcspi2: spi@4809a000 {
 399                         compatible = "ti,omap4-mcspi";
 400                         reg = <0x4809a000 0x200>;
 401                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         ti,hwmods = "mcspi2";
 405                         ti,spi-num-cs = <2>;
 406                         dmas = <&sdma 43>,
 407                                <&sdma 44>,
 408                                <&sdma 45>,
 409                                <&sdma 46>;
 410                         dma-names = "tx0", "rx0", "tx1", "rx1";
 411                 };
 412
 413                 mcspi3: spi@480b8000 {
 414                         compatible = "ti,omap4-mcspi";
 415                         reg = <0x480b8000 0x200>;
 416                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 417                         #address-cells = <1>;
 418                         #size-cells = <0>;
 419                         ti,hwmods = "mcspi3";
 420                         ti,spi-num-cs = <2>;
 421                         dmas = <&sdma 15>, <&sdma 16>;
 422                         dma-names = "tx0", "rx0";
 423                 };
 424
 425                 mcspi4: spi@480ba000 {
 426                         compatible = "ti,omap4-mcspi";
 427                         reg = <0x480ba000 0x200>;
 428                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         ti,hwmods = "mcspi4";
 432                         ti,spi-num-cs = <1>;
 433                         dmas = <&sdma 70>, <&sdma 71>;
 434                         dma-names = "tx0", "rx0";
 435                 };
 436
 437                 mmc1: mmc@4809c000 {
 438                         compatible = "ti,omap4-hsmmc";
 439                         reg = <0x4809c000 0x400>;
 440                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 441                         ti,hwmods = "mmc1";
 442                         ti,dual-volt;
 443                         ti,needs-special-reset;
 444                         dmas = <&sdma 61>, <&sdma 62>;
 445                         dma-names = "tx", "rx";
 446                         pbias-supply = <&pbias_mmc_reg>;
 447                 };
 448
 449                 mmc2: mmc@480b4000 {
 450                         compatible = "ti,omap4-hsmmc";
 451                         reg = <0x480b4000 0x400>;
 452                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 453                         ti,hwmods = "mmc2";
 454                         ti,needs-special-reset;
 455                         dmas = <&sdma 47>, <&sdma 48>;
 456                         dma-names = "tx", "rx";
 457                 };
 458
 459                 mmc3: mmc@480ad000 {
 460                         compatible = "ti,omap4-hsmmc";
 461                         reg = <0x480ad000 0x400>;
 462                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 463                         ti,hwmods = "mmc3";
 464                         ti,needs-special-reset;
 465                         dmas = <&sdma 77>, <&sdma 78>;
 466                         dma-names = "tx", "rx";
 467                 };
 468
 469                 mmc4: mmc@480d1000 {
 470                         compatible = "ti,omap4-hsmmc";
 471                         reg = <0x480d1000 0x400>;
 472                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 473                         ti,hwmods = "mmc4";
 474                         ti,needs-special-reset;
 475                         dmas = <&sdma 57>, <&sdma 58>;
 476                         dma-names = "tx", "rx";
 477                 };
 478
 479                 mmc5: mmc@480d5000 {
 480                         compatible = "ti,omap4-hsmmc";
 481                         reg = <0x480d5000 0x400>;
 482                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 483                         ti,hwmods = "mmc5";
 484                         ti,needs-special-reset;
 485                         dmas = <&sdma 59>, <&sdma 60>;
 486                         dma-names = "tx", "rx";
 487                 };
 488
 489                 mmu_dsp: mmu@4a066000 {
 490                         compatible = "ti,omap4-iommu";
 491                         reg = <0x4a066000 0x100>;
 492                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 493                         ti,hwmods = "mmu_dsp";
 494                 };
 495
 496                 mmu_ipu: mmu@55082000 {
 497                         compatible = "ti,omap4-iommu";
 498                         reg = <0x55082000 0x100>;
 499                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 500                         ti,hwmods = "mmu_ipu";
 501                         ti,iommu-bus-err-back;
 502                 };
 503
 504                 wdt2: wdt@4a314000 {
 505                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 506                         reg = <0x4a314000 0x80>;
 507                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 508                         ti,hwmods = "wd_timer2";
 509                 };
 510
 511                 mcpdm: mcpdm@40132000 {
 512                         compatible = "ti,omap4-mcpdm";
 513                         reg = <0x40132000 0x7f>, /* MPU private access */
 514                               <0x49032000 0x7f>; /* L3 Interconnect */
 515                         reg-names = "mpu", "dma";
 516                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 517                         ti,hwmods = "mcpdm";
 518                         dmas = <&sdma 65>,
 519                                <&sdma 66>;
 520                         dma-names = "up_link", "dn_link";
 521                         status = "disabled";
 522                 };
 523
 524                 dmic: dmic@4012e000 {
 525                         compatible = "ti,omap4-dmic";
 526                         reg = <0x4012e000 0x7f>, /* MPU private access */
 527                               <0x4902e000 0x7f>; /* L3 Interconnect */
 528                         reg-names = "mpu", "dma";
 529                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 530                         ti,hwmods = "dmic";
 531                         dmas = <&sdma 67>;
 532                         dma-names = "up_link";
 533                         status = "disabled";
 534                 };
 535
 536                 mcbsp1: mcbsp@40122000 {
 537                         compatible = "ti,omap4-mcbsp";
 538                         reg = <0x40122000 0xff>, /* MPU private access */
 539                               <0x49022000 0xff>; /* L3 Interconnect */
 540                         reg-names = "mpu", "dma";
 541                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 542                         interrupt-names = "common";
 543                         ti,buffer-size = <128>;
 544                         ti,hwmods = "mcbsp1";
 545                         dmas = <&sdma 33>,
 546                                <&sdma 34>;
 547                         dma-names = "tx", "rx";
 548                         status = "disabled";
 549                 };
 550
 551                 mcbsp2: mcbsp@40124000 {
 552                         compatible = "ti,omap4-mcbsp";
 553                         reg = <0x40124000 0xff>, /* MPU private access */
 554                               <0x49024000 0xff>; /* L3 Interconnect */
 555                         reg-names = "mpu", "dma";
 556                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 557                         interrupt-names = "common";
 558                         ti,buffer-size = <128>;
 559                         ti,hwmods = "mcbsp2";
 560                         dmas = <&sdma 17>,
 561                                <&sdma 18>;
 562                         dma-names = "tx", "rx";
 563                         status = "disabled";
 564                 };
 565
 566                 mcbsp3: mcbsp@40126000 {
 567                         compatible = "ti,omap4-mcbsp";
 568                         reg = <0x40126000 0xff>, /* MPU private access */
 569                               <0x49026000 0xff>; /* L3 Interconnect */
 570                         reg-names = "mpu", "dma";
 571                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 572                         interrupt-names = "common";
 573                         ti,buffer-size = <128>;
 574                         ti,hwmods = "mcbsp3";
 575                         dmas = <&sdma 19>,
 576                                <&sdma 20>;
 577                         dma-names = "tx", "rx";
 578                         status = "disabled";
 579                 };
 580
 581                 mcbsp4: mcbsp@48096000 {
 582                         compatible = "ti,omap4-mcbsp";
 583                         reg = <0x48096000 0xff>; /* L4 Interconnect */
 584                         reg-names = "mpu";
 585                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 586                         interrupt-names = "common";
 587                         ti,buffer-size = <128>;
 588                         ti,hwmods = "mcbsp4";
 589                         dmas = <&sdma 31>,
 590                                <&sdma 32>;
 591                         dma-names = "tx", "rx";
 592                         status = "disabled";
 593                 };
 594
 595                 keypad: keypad@4a31c000 {
 596                         compatible = "ti,omap4-keypad";
 597                         reg = <0x4a31c000 0x80>;
 598                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 599                         reg-names = "mpu";
 600                         ti,hwmods = "kbd";
 601                 };
 602
 603                 dmm@4e000000 {
 604                         compatible = "ti,omap4-dmm";
 605                         reg = <0x4e000000 0x800>;
 606                         interrupts = <0 113 0x4>;
 607                         ti,hwmods = "dmm";
 608                 };
 609
 610                 emif1: emif@4c000000 {
 611                         compatible = "ti,emif-4d";
 612                         reg = <0x4c000000 0x100>;
 613                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 614                         ti,hwmods = "emif1";
 615                         ti,no-idle-on-init;
 616                         phy-type = <1>;
 617                         hw-caps-read-idle-ctrl;
 618                         hw-caps-ll-interface;
 619                         hw-caps-temp-alert;
 620                 };
 621
 622                 emif2: emif@4d000000 {
 623                         compatible = "ti,emif-4d";
 624                         reg = <0x4d000000 0x100>;
 625                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 626                         ti,hwmods = "emif2";
 627                         ti,no-idle-on-init;
 628                         phy-type = <1>;
 629                         hw-caps-read-idle-ctrl;
 630                         hw-caps-ll-interface;
 631                         hw-caps-temp-alert;
 632                 };
 633
 634                 ocp2scp@4a0ad000 {
 635                         compatible = "ti,omap-ocp2scp";
 636                         reg = <0x4a0ad000 0x1f>;
 637                         #address-cells = <1>;
 638                         #size-cells = <1>;
 639                         ranges;
 640                         ti,hwmods = "ocp2scp_usb_phy";
 641                         usb2_phy: usb2phy@4a0ad080 {
 642                                 compatible = "ti,omap-usb2";
 643                                 reg = <0x4a0ad080 0x58>;
 644                                 ctrl-module = <&omap_control_usb2phy>;
 645                                 #phy-cells = <0>;
 646                         };
 647                 };
 648
 649                 timer1: timer@4a318000 {
 650                         compatible = "ti,omap3430-timer";
 651                         reg = <0x4a318000 0x80>;
 652                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 653                         ti,hwmods = "timer1";
 654                         ti,timer-alwon;
 655                 };
 656
 657                 timer2: timer@48032000 {
 658                         compatible = "ti,omap3430-timer";
 659                         reg = <0x48032000 0x80>;
 660                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 661                         ti,hwmods = "timer2";
 662                 };
 663
 664                 timer3: timer@48034000 {
 665                         compatible = "ti,omap4430-timer";
 666                         reg = <0x48034000 0x80>;
 667                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 668                         ti,hwmods = "timer3";
 669                 };
 670
 671                 timer4: timer@48036000 {
 672                         compatible = "ti,omap4430-timer";
 673                         reg = <0x48036000 0x80>;
 674                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 675                         ti,hwmods = "timer4";
 676                 };
 677
 678                 timer5: timer@40138000 {
 679                         compatible = "ti,omap4430-timer";
 680                         reg = <0x40138000 0x80>,
 681                               <0x49038000 0x80>;
 682                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 683                         ti,hwmods = "timer5";
 684                         ti,timer-dsp;
 685                 };
 686
 687                 timer6: timer@4013a000 {
 688                         compatible = "ti,omap4430-timer";
 689                         reg = <0x4013a000 0x80>,
 690                               <0x4903a000 0x80>;
 691                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 692                         ti,hwmods = "timer6";
 693                         ti,timer-dsp;
 694                 };
 695
 696                 timer7: timer@4013c000 {
 697                         compatible = "ti,omap4430-timer";
 698                         reg = <0x4013c000 0x80>,
 699                               <0x4903c000 0x80>;
 700                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 701                         ti,hwmods = "timer7";
 702                         ti,timer-dsp;
 703                 };
 704
 705                 timer8: timer@4013e000 {
 706                         compatible = "ti,omap4430-timer";
 707                         reg = <0x4013e000 0x80>,
 708                               <0x4903e000 0x80>;
 709                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 710                         ti,hwmods = "timer8";
 711                         ti,timer-pwm;
 712                         ti,timer-dsp;
 713                 };
 714
 715                 timer9: timer@4803e000 {
 716                         compatible = "ti,omap4430-timer";
 717                         reg = <0x4803e000 0x80>;
 718                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 719                         ti,hwmods = "timer9";
 720                         ti,timer-pwm;
 721                 };
 722
 723                 timer10: timer@48086000 {
 724                         compatible = "ti,omap3430-timer";
 725                         reg = <0x48086000 0x80>;
 726                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 727                         ti,hwmods = "timer10";
 728                         ti,timer-pwm;
 729                 };
 730
 731                 timer11: timer@48088000 {
 732                         compatible = "ti,omap4430-timer";
 733                         reg = <0x48088000 0x80>;
 734                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 735                         ti,hwmods = "timer11";
 736                         ti,timer-pwm;
 737                 };
 738
 739                 usbhstll: usbhstll@4a062000 {
 740                         compatible = "ti,usbhs-tll";
 741                         reg = <0x4a062000 0x1000>;
 742                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 743                         ti,hwmods = "usb_tll_hs";
 744                 };
 745
 746                 usbhshost: usbhshost@4a064000 {
 747                         compatible = "ti,usbhs-host";
 748                         reg = <0x4a064000 0x800>;
 749                         ti,hwmods = "usb_host_hs";
 750                         #address-cells = <1>;
 751                         #size-cells = <1>;
 752                         ranges;
 753                         clocks = <&init_60m_fclk>,
 754                                  <&xclk60mhsp1_ck>,
 755                                  <&xclk60mhsp2_ck>;
 756                         clock-names = "refclk_60m_int",
 757                                       "refclk_60m_ext_p1",
 758                                       "refclk_60m_ext_p2";
 759
 760                         usbhsohci: ohci@4a064800 {
 761                                 compatible = "ti,ohci-omap3";
 762                                 reg = <0x4a064800 0x400>;
 763                                 interrupt-parent = <&gic>;
 764                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 765                         };
 766
 767                         usbhsehci: ehci@4a064c00 {
 768                                 compatible = "ti,ehci-omap";
 769                                 reg = <0x4a064c00 0x400>;
 770                                 interrupt-parent = <&gic>;
 771                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 772                         };
 773                 };
 774
 775                 omap_control_usb2phy: control-phy@4a002300 {
 776                         compatible = "ti,control-phy-usb2";
 777                         reg = <0x4a002300 0x4>;
 778                         reg-names = "power";
 779                 };
 780
 781                 omap_control_usbotg: control-phy@4a00233c {
 782                         compatible = "ti,control-phy-otghs";
 783                         reg = <0x4a00233c 0x4>;
 784                         reg-names = "otghs_control";
 785                 };
 786
 787                 usb_otg_hs: usb_otg_hs@4a0ab000 {
 788                         compatible = "ti,omap4-musb";
 789                         reg = <0x4a0ab000 0x7ff>;
 790                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 791                         interrupt-names = "mc", "dma";
 792                         ti,hwmods = "usb_otg_hs";
 793                         usb-phy = <&usb2_phy>;
 794                         phys = <&usb2_phy>;
 795                         phy-names = "usb2-phy";
 796                         multipoint = <1>;
 797                         num-eps = <16>;
 798                         ram-bits = <12>;
 799                         ctrl-module = <&omap_control_usbotg>;
 800                 };
 801
 802                 aes: aes@4b501000 {
 803                         compatible = "ti,omap4-aes";
 804                         ti,hwmods = "aes";
 805                         reg = <0x4b501000 0xa0>;
 806                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 807                         dmas = <&sdma 111>, <&sdma 110>;
 808                         dma-names = "tx", "rx";
 809                 };
 810
 811                 des: des@480a5000 {
 812                         compatible = "ti,omap4-des";
 813                         ti,hwmods = "des";
 814                         reg = <0x480a5000 0xa0>;
 815                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 816                         dmas = <&sdma 117>, <&sdma 116>;
 817                         dma-names = "tx", "rx";
 818                 };
 819
 820                 abb_mpu: regulator-abb-mpu {
 821                         compatible = "ti,abb-v2";
 822                         regulator-name = "abb_mpu";
 823                         #address-cells = <0>;
 824                         #size-cells = <0>;
 825                         ti,tranxdone-status-mask = <0x80>;
 826                         clocks = <&sys_clkin_ck>;
 827                         ti,settling-time = <50>;
 828                         ti,clock-cycles = <16>;
 829
 830                         status = "disabled";
 831                 };
 832
 833                 abb_iva: regulator-abb-iva {
 834                         compatible = "ti,abb-v2";
 835                         regulator-name = "abb_iva";
 836                         #address-cells = <0>;
 837                         #size-cells = <0>;
 838                         ti,tranxdone-status-mask = <0x80000000>;
 839                         clocks = <&sys_clkin_ck>;
 840                         ti,settling-time = <50>;
 841                         ti,clock-cycles = <16>;
 842
 843                         status = "disabled";
 844                 };
 845
 846                 dss: dss@58000000 {
 847                         compatible = "ti,omap4-dss";
 848                         reg = <0x58000000 0x80>;
 849                         status = "disabled";
 850                         ti,hwmods = "dss_core";
 851                         clocks = <&dss_dss_clk>;
 852                         clock-names = "fck";
 853                         #address-cells = <1>;
 854                         #size-cells = <1>;
 855                         ranges;
 856
 857                         dispc@58001000 {
 858                                 compatible = "ti,omap4-dispc";
 859                                 reg = <0x58001000 0x1000>;
 860                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 861                                 ti,hwmods = "dss_dispc";
 862                                 clocks = <&dss_dss_clk>;
 863                                 clock-names = "fck";
 864                         };
 865
 866                         rfbi: encoder@58002000  {
 867                                 compatible = "ti,omap4-rfbi";
 868                                 reg = <0x58002000 0x1000>;
 869                                 status = "disabled";
 870                                 ti,hwmods = "dss_rfbi";
 871                                 clocks = <&dss_dss_clk>, <&dss_fck>;
 872                                 clock-names = "fck", "ick";
 873                         };
 874
 875                         venc: encoder@58003000 {
 876                                 compatible = "ti,omap4-venc";
 877                                 reg = <0x58003000 0x1000>;
 878                                 status = "disabled";
 879                                 ti,hwmods = "dss_venc";
 880                                 clocks = <&dss_tv_clk>;
 881                                 clock-names = "fck";
 882                         };
 883
 884                         dsi1: encoder@58004000 {
 885                                 compatible = "ti,omap4-dsi";
 886                                 reg = <0x58004000 0x200>,
 887                                       <0x58004200 0x40>,
 888                                       <0x58004300 0x20>;
 889                                 reg-names = "proto", "phy", "pll";
 890                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 891                                 status = "disabled";
 892                                 ti,hwmods = "dss_dsi1";
 893                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 894                                 clock-names = "fck", "sys_clk";
 895                         };
 896
 897                         dsi2: encoder@58005000 {
 898                                 compatible = "ti,omap4-dsi";
 899                                 reg = <0x58005000 0x200>,
 900                                       <0x58005200 0x40>,
 901                                       <0x58005300 0x20>;
 902                                 reg-names = "proto", "phy", "pll";
 903                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 904                                 status = "disabled";
 905                                 ti,hwmods = "dss_dsi2";
 906                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 907                                 clock-names = "fck", "sys_clk";
 908                         };
 909
 910                         hdmi: encoder@58006000 {
 911                                 compatible = "ti,omap4-hdmi";
 912                                 reg = <0x58006000 0x200>,
 913                                       <0x58006200 0x100>,
 914                                       <0x58006300 0x100>,
 915                                       <0x58006400 0x1000>;
 916                                 reg-names = "wp", "pll", "phy", "core";
 917                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 918                                 status = "disabled";
 919                                 ti,hwmods = "dss_hdmi";
 920                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
 921                                 clock-names = "fck", "sys_clk";
 922                         };
 923                 };
 924         };
 925 };
 926
 927 /include/ "omap44xx-clocks.dtsi"