arch/arm/boot/dts/integratorcp.dts

   1 /*
   2  * Device Tree for the ARM Integrator/CP platform
   3  */
   4
   5 /dts-v1/;
   6 /include/ "integrator.dtsi"
   7
   8 / {
   9         model = "ARM Integrator/CP";
  10         compatible = "arm,integrator-cp";
  11
  12         chosen {
  13                 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
  14         };
  15
  16         syscon {
  17                 compatible = "arm,integrator-cp-syscon";
  18                 reg = <0xcb000000 0x100>;
  19         };
  20
  21         timer0: timer@13000000 {
  22                 /* TIMER0 runs @ 25MHz */
  23                 compatible = "arm,integrator-cp-timer";
  24                 status = "disabled";
  25         };
  26
  27         timer1: timer@13000100 {
  28                 /* TIMER1 runs @ 1MHz */
  29                 compatible = "arm,integrator-cp-timer";
  30         };
  31
  32         timer2: timer@13000200 {
  33                 /* TIMER2 runs @ 1MHz */
  34                 compatible = "arm,integrator-cp-timer";
  35         };
  36
  37         pic: pic@14000000 {
  38                 valid-mask = <0x1fc003ff>;
  39         };
  40
  41         cic: cic@10000040 {
  42                 compatible = "arm,versatile-fpga-irq";
  43                 #interrupt-cells = <1>;
  44                 interrupt-controller;
  45                 reg = <0x10000040 0x100>;
  46                 clear-mask = <0xffffffff>;
  47                 valid-mask = <0x00000007>;
  48         };
  49
  50         /* The SIC is cascaded off IRQ 26 on the PIC */
  51         sic: sic@ca000000 {
  52                 compatible = "arm,versatile-fpga-irq";
  53                 interrupt-parent = <&pic>;
  54                 interrupts = <26>;
  55                 #interrupt-cells = <1>;
  56                 interrupt-controller;
  57                 reg = <0xca000000 0x100>;
  58                 clear-mask = <0x00000fff>;
  59                 valid-mask = <0x00000fff>;
  60         };
  61
  62         ethernet@c8000000 {
  63                 compatible = "smsc,lan91c111";
  64                 reg = <0xc8000000 0x10>;
  65                 interrupt-parent = <&pic>;
  66                 interrupts = <27>;
  67         };
  68
  69         fpga {
  70                 /*
  71                  * These PrimeCells are at the same location and using
  72                  * the same interrupts in all Integrators, but in the CP
  73                  * slightly newer versions are deployed.
  74                  */
  75                 rtc@15000000 {
  76                         compatible = "arm,pl031", "arm,primecell";
  77                 };
  78
  79                 uart@16000000 {
  80                         compatible = "arm,pl011", "arm,primecell";
  81                 };
  82
  83                 uart@17000000 {
  84                         compatible = "arm,pl011", "arm,primecell";
  85                 };
  86
  87                 kmi@18000000 {
  88                         compatible = "arm,pl050", "arm,primecell";
  89                 };
  90
  91                 kmi@19000000 {
  92                         compatible = "arm,pl050", "arm,primecell";
  93                 };
  94
  95                 /*
  96                  * These PrimeCells are only available on the Integrator/CP
  97                  */
  98                 mmc@1c000000 {
  99                         compatible = "arm,pl180", "arm,primecell";
 100                         reg = <0x1c000000 0x1000>;
 101                         interrupts = <23 24>;
 102                         max-frequency = <515633>;
 103                 };
 104
 105                 aaci@1d000000 {
 106                         compatible = "arm,pl041", "arm,primecell";
 107                         reg = <0x1d000000 0x1000>;
 108                         interrupts = <25>;
 109                 };
 110
 111                 clcd@c0000000 {
 112                         compatible = "arm,pl110", "arm,primecell";
 113                         reg = <0xC0000000 0x1000>;
 114                         interrupts = <22>;
 115                 };
 116         };
 117 };