arch/arm/boot/dts/imx53-qsb-common.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "imx53.dtsi"
  14
  15 / {
  16         memory {
  17                 reg = <0x70000000 0x40000000>;
  18         };
  19
  20         display@di0 {
  21                 compatible = "fsl,imx-parallel-display";
  22                 crtcs = <&ipu 0>;
  23                 interface-pix-fmt = "rgb565";
  24                 pinctrl-names = "default";
  25                 pinctrl-0 = <&pinctrl_ipu_disp0>;
  26                 status = "disabled";
  27                 display-timings {
  28                         claawvga {
  29                                 native-mode;
  30                                 clock-frequency = <27000000>;
  31                                 hactive = <800>;
  32                                 vactive = <480>;
  33                                 hback-porch = <40>;
  34                                 hfront-porch = <60>;
  35                                 vback-porch = <10>;
  36                                 vfront-porch = <10>;
  37                                 hsync-len = <20>;
  38                                 vsync-len = <10>;
  39                                 hsync-active = <0>;
  40                                 vsync-active = <0>;
  41                                 de-active = <1>;
  42                                 pixelclk-active = <0>;
  43                         };
  44                 };
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49
  50                 power {
  51                         label = "Power Button";
  52                         gpios = <&gpio1 8 0>;
  53                         linux,code = <116>; /* KEY_POWER */
  54                 };
  55
  56                 volume-up {
  57                         label = "Volume Up";
  58                         gpios = <&gpio2 14 0>;
  59                         linux,code = <115>; /* KEY_VOLUMEUP */
  60                         gpio-key,wakeup;
  61                 };
  62
  63                 volume-down {
  64                         label = "Volume Down";
  65                         gpios = <&gpio2 15 0>;
  66                         linux,code = <114>; /* KEY_VOLUMEDOWN */
  67                         gpio-key,wakeup;
  68                 };
  69         };
  70
  71         leds {
  72                 compatible = "gpio-leds";
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&led_pin_gpio7_7>;
  75
  76                 user {
  77                         label = "Heartbeat";
  78                         gpios = <&gpio7 7 0>;
  79                         linux,default-trigger = "heartbeat";
  80                 };
  81         };
  82
  83         regulators {
  84                 compatible = "simple-bus";
  85                 #address-cells = <1>;
  86                 #size-cells = <0>;
  87
  88                 reg_3p2v: regulator@0 {
  89                         compatible = "regulator-fixed";
  90                         reg = <0>;
  91                         regulator-name = "3P2V";
  92                         regulator-min-microvolt = <3200000>;
  93                         regulator-max-microvolt = <3200000>;
  94                         regulator-always-on;
  95                 };
  96
  97                 reg_usb_vbus: regulator@1 {
  98                         compatible = "regulator-fixed";
  99                         reg = <1>;
 100                         regulator-name = "usb_vbus";
 101                         regulator-min-microvolt = <5000000>;
 102                         regulator-max-microvolt = <5000000>;
 103                         gpio = <&gpio7 8 0>;
 104                         enable-active-high;
 105                 };
 106         };
 107
 108         sound {
 109                 compatible = "fsl,imx53-qsb-sgtl5000",
 110                              "fsl,imx-audio-sgtl5000";
 111                 model = "imx53-qsb-sgtl5000";
 112                 ssi-controller = <&ssi2>;
 113                 audio-codec = <&sgtl5000>;
 114                 audio-routing =
 115                         "MIC_IN", "Mic Jack",
 116                         "Mic Jack", "Mic Bias",
 117                         "Headphone Jack", "HP_OUT";
 118                 mux-int-port = <2>;
 119                 mux-ext-port = <5>;
 120         };
 121 };
 122
 123 &esdhc1 {
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&pinctrl_esdhc1>;
 126         status = "okay";
 127 };
 128
 129 &ssi2 {
 130         fsl,mode = "i2s-slave";
 131         status = "okay";
 132 };
 133
 134 &esdhc3 {
 135         pinctrl-names = "default";
 136         pinctrl-0 = <&pinctrl_esdhc3>;
 137         cd-gpios = <&gpio3 11 0>;
 138         wp-gpios = <&gpio3 12 0>;
 139         bus-width = <8>;
 140         status = "okay";
 141 };
 142
 143 &iomuxc {
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&pinctrl_hog>;
 146
 147         imx53-qsb {
 148                 pinctrl_hog: hoggrp {
 149                         fsl,pins = <
 150                                 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
 151                                 MX53_PAD_GPIO_8__GPIO1_8          0x80000000
 152                                 MX53_PAD_PATA_DATA14__GPIO2_14    0x80000000
 153                                 MX53_PAD_PATA_DATA15__GPIO2_15    0x80000000
 154                                 MX53_PAD_EIM_DA11__GPIO3_11       0x80000000
 155                                 MX53_PAD_EIM_DA12__GPIO3_12       0x80000000
 156                                 MX53_PAD_PATA_DA_0__GPIO7_6       0x80000000
 157                                 MX53_PAD_PATA_DA_2__GPIO7_8       0x80000000
 158                                 MX53_PAD_GPIO_16__GPIO7_11        0x80000000
 159                         >;
 160                 };
 161
 162                 led_pin_gpio7_7: led_gpio7_7@0 {
 163                         fsl,pins = <
 164                                 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
 165                         >;
 166                 };
 167
 168                 pinctrl_audmux: audmuxgrp {
 169                         fsl,pins = <
 170                                 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC      0x80000000
 171                                 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD      0x80000000
 172                                 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS     0x80000000
 173                                 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD      0x80000000
 174                         >;
 175                 };
 176
 177                 pinctrl_esdhc1: esdhc1grp {
 178                         fsl,pins = <
 179                                 MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
 180                                 MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
 181                                 MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
 182                                 MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
 183                                 MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
 184                                 MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
 185                         >;
 186                 };
 187
 188                 pinctrl_esdhc3: esdhc3grp {
 189                         fsl,pins = <
 190                                 MX53_PAD_PATA_DATA8__ESDHC3_DAT0        0x1d5
 191                                 MX53_PAD_PATA_DATA9__ESDHC3_DAT1        0x1d5
 192                                 MX53_PAD_PATA_DATA10__ESDHC3_DAT2       0x1d5
 193                                 MX53_PAD_PATA_DATA11__ESDHC3_DAT3       0x1d5
 194                                 MX53_PAD_PATA_DATA0__ESDHC3_DAT4        0x1d5
 195                                 MX53_PAD_PATA_DATA1__ESDHC3_DAT5        0x1d5
 196                                 MX53_PAD_PATA_DATA2__ESDHC3_DAT6        0x1d5
 197                                 MX53_PAD_PATA_DATA3__ESDHC3_DAT7        0x1d5
 198                                 MX53_PAD_PATA_RESET_B__ESDHC3_CMD       0x1d5
 199                                 MX53_PAD_PATA_IORDY__ESDHC3_CLK         0x1d5
 200                         >;
 201                 };
 202
 203                 pinctrl_fec: fecgrp {
 204                         fsl,pins = <
 205                                 MX53_PAD_FEC_MDC__FEC_MDC               0x80000000
 206                                 MX53_PAD_FEC_MDIO__FEC_MDIO             0x80000000
 207                                 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x80000000
 208                                 MX53_PAD_FEC_RX_ER__FEC_RX_ER           0x80000000
 209                                 MX53_PAD_FEC_CRS_DV__FEC_RX_DV          0x80000000
 210                                 MX53_PAD_FEC_RXD1__FEC_RDATA_1          0x80000000
 211                                 MX53_PAD_FEC_RXD0__FEC_RDATA_0          0x80000000
 212                                 MX53_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
 213                                 MX53_PAD_FEC_TXD1__FEC_TDATA_1          0x80000000
 214                                 MX53_PAD_FEC_TXD0__FEC_TDATA_0          0x80000000
 215                         >;
 216                 };
 217
 218                 pinctrl_i2c1: i2c1grp {
 219                         fsl,pins = <
 220                                 MX53_PAD_CSI0_DAT8__I2C1_SDA            0xc0000000
 221                                 MX53_PAD_CSI0_DAT9__I2C1_SCL            0xc0000000
 222                         >;
 223                 };
 224
 225                 pinctrl_i2c2: i2c2grp {
 226                         fsl,pins = <
 227                                 MX53_PAD_KEY_ROW3__I2C2_SDA             0xc0000000
 228                                 MX53_PAD_KEY_COL3__I2C2_SCL             0xc0000000
 229                         >;
 230                 };
 231
 232                 pinctrl_ipu_disp0: ipudisp0grp {
 233                         fsl,pins = <
 234                                 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
 235                                 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15       0x5
 236                                 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         0x5
 237                                 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3         0x5
 238                                 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0    0x5
 239                                 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1    0x5
 240                                 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2    0x5
 241                                 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3    0x5
 242                                 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4    0x5
 243                                 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5    0x5
 244                                 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6    0x5
 245                                 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7    0x5
 246                                 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8    0x5
 247                                 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9    0x5
 248                                 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10  0x5
 249                                 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11  0x5
 250                                 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12  0x5
 251                                 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13  0x5
 252                                 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14  0x5
 253                                 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15  0x5
 254                                 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16  0x5
 255                                 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17  0x5
 256                                 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18  0x5
 257                                 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19  0x5
 258                                 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20  0x5
 259                                 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21  0x5
 260                                 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22  0x5
 261                                 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23  0x5
 262                         >;
 263                 };
 264
 265                 pinctrl_uart1: uart1grp {
 266                         fsl,pins = <
 267                                 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX      0x1e4
 268                                 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX      0x1e4
 269                         >;
 270                 };
 271         };
 272 };
 273
 274 &uart1 {
 275         pinctrl-names = "default";
 276         pinctrl-0 = <&pinctrl_uart1>;
 277         status = "okay";
 278 };
 279
 280 &i2c2 {
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&pinctrl_i2c2>;
 283         status = "okay";
 284
 285         sgtl5000: codec@0a {
 286                 compatible = "fsl,sgtl5000";
 287                 reg = <0x0a>;
 288                 VDDA-supply = <&reg_3p2v>;
 289                 VDDIO-supply = <&reg_3p2v>;
 290                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
 291         };
 292 };
 293
 294 &i2c1 {
 295         pinctrl-names = "default";
 296         pinctrl-0 = <&pinctrl_i2c1>;
 297         status = "okay";
 298
 299         accelerometer: mma8450@1c {
 300                 compatible = "fsl,mma8450";
 301                 reg = <0x1c>;
 302         };
 303 };
 304
 305 &audmux {
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_audmux>;
 308         status = "okay";
 309 };
 310
 311 &fec {
 312         pinctrl-names = "default";
 313         pinctrl-0 = <&pinctrl_fec>;
 314         phy-mode = "rmii";
 315         phy-reset-gpios = <&gpio7 6 0>;
 316         status = "okay";
 317 };
 318
 319 &sata {
 320         status = "okay";
 321 };
 322
 323 &vpu {
 324         status = "okay";
 325 };
 326
 327 &usbh1 {
 328         vbus-supply = <&reg_usb_vbus>;
 329         phy_type = "utmi";
 330         status = "okay";
 331 };
 332
 333 &usbotg {
 334         dr_mode = "peripheral";
 335         status = "okay";
 336 };