arch/arm/boot/dts/imx53-mba53.dts

   1 /*
   2  * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
   3  * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /dts-v1/;
  14 #include "imx53-tqma53.dtsi"
  15
  16 / {
  17         model = "TQ MBa53 starter kit";
  18         compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
  19
  20         backlight {
  21                 compatible = "pwm-backlight";
  22                 pwms = <&pwm2 0 50000>;
  23                 brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
  24                 default-brightness-level = <10>;
  25                 enable-gpios = <&gpio7 7 0>;
  26                 power-supply = <&reg_backlight>;
  27         };
  28
  29         disp1: display@disp1 {
  30                 compatible = "fsl,imx-parallel-display";
  31                 pinctrl-names = "default";
  32                 pinctrl-0 = <&pinctrl_disp1_1>;
  33                 crtcs = <&ipu 1>;
  34                 interface-pix-fmt = "rgb24";
  35                 status = "disabled";
  36         };
  37
  38         regulators {
  39                 compatible = "simple-bus";
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42
  43                 reg_backlight: regulator@0 {
  44                         compatible = "regulator-fixed";
  45                         reg = <0>;
  46                         regulator-name = "lcd-supply";
  47                         gpio = <&gpio2 5 0>;
  48                         startup-delay-us = <5000>;
  49                 };
  50
  51                 reg_3p2v: regulator@1 {
  52                         compatible = "regulator-fixed";
  53                         reg = <1>;
  54                         regulator-name = "3P2V";
  55                         regulator-min-microvolt = <3200000>;
  56                         regulator-max-microvolt = <3200000>;
  57                         regulator-always-on;
  58                 };
  59         };
  60
  61         sound {
  62                 compatible = "tq,imx53-mba53-sgtl5000",
  63                              "fsl,imx-audio-sgtl5000";
  64                 model = "imx53-mba53-sgtl5000";
  65                 ssi-controller = <&ssi2>;
  66                 audio-codec = <&codec>;
  67                 audio-routing =
  68                         "MIC_IN", "Mic Jack",
  69                         "Mic Jack", "Mic Bias",
  70                         "Headphone Jack", "HP_OUT";
  71                 mux-int-port = <2>;
  72                 mux-ext-port = <5>;
  73         };
  74 };
  75
  76 &ldb {
  77         pinctrl-names = "default";
  78         pinctrl-0 = <&pinctrl_lvds1_1>;
  79         status = "disabled";
  80 };
  81
  82 &iomuxc {
  83         lvds1 {
  84                 pinctrl_lvds1_1: lvds1-grp1 {
  85                         fsl,pins = <
  86                                 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
  87                                 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
  88                                 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
  89                                 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
  90                                 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
  91                         >;
  92                 };
  93
  94                 pinctrl_lvds1_2: lvds1-grp2 {
  95                         fsl,pins = <
  96                                 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
  97                                 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
  98                                 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
  99                                 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
 100                                 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
 101                         >;
 102                 };
 103         };
 104
 105         disp1 {
 106                 pinctrl_disp1_1: disp1-grp1 {
 107                         fsl,pins = <
 108                                 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
 109                                 MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x80000000 /* DISP1_DRDY */
 110                                 MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x80000000 /* DISP1_HSYNC */
 111                                 MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x80000000 /* DISP1_VSYNC */
 112                                 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
 113                                 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
 114                                 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
 115                                 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
 116                                 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
 117                                 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
 118                                 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
 119                                 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
 120                                 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
 121                                 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
 122                                 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
 123                                 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
 124                                 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
 125                                 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
 126                                 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x80000000
 127                                 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x80000000
 128                                 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x80000000
 129                                 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x80000000
 130                                 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x80000000
 131                                 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x80000000
 132                                 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x80000000
 133                                 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x80000000
 134                                 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x80000000
 135                                 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
 136                         >;
 137                 };
 138         };
 139
 140         tve {
 141                 pinctrl_vga_sync_1: vgasync-grp1 {
 142                         fsl,pins = <
 143                                 /* VGA_VSYNC, HSYNC with max drive strength */
 144                                 MX53_PAD_EIM_CS1__IPU_DI1_PIN6     0xe6
 145                                 MX53_PAD_EIM_DA15__IPU_DI1_PIN4    0xe6
 146                         >;
 147                 };
 148         };
 149 };
 150
 151 &cspi {
 152         status = "okay";
 153 };
 154
 155 &audmux {
 156         status = "okay";
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_audmux>;
 159 };
 160
 161 &i2c2 {
 162         codec: sgtl5000@a {
 163                 compatible = "fsl,sgtl5000";
 164                 reg = <0x0a>;
 165                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
 166                 VDDA-supply = <&reg_3p2v>;
 167                 VDDIO-supply = <&reg_3p2v>;
 168         };
 169
 170         expander: pca9554@20 {
 171                 compatible = "pca9554";
 172                 reg = <0x20>;
 173                 interrupts = <109>;
 174                 #gpio-cells = <2>;
 175                 gpio-controller;
 176         };
 177
 178         sensor2: lm75@49 {
 179                 compatible = "lm75";
 180                 reg = <0x49>;
 181         };
 182 };
 183
 184 &fec {
 185         phy-reset-gpios = <&gpio7 6 0>;
 186         status = "okay";
 187 };
 188
 189 &esdhc2 {
 190         status = "okay";
 191 };
 192
 193 &uart3 {
 194         status = "okay";
 195 };
 196
 197 &ecspi1 {
 198         status = "okay";
 199 };
 200
 201 &usbotg {
 202         dr_mode = "host";
 203         status = "okay";
 204 };
 205
 206 &usbh1 {
 207         status = "okay";
 208 };
 209
 210 &uart1 {
 211         status = "okay";
 212 };
 213
 214 &ssi2 {
 215         fsl,mode = "i2s-slave";
 216         status = "okay";
 217 };
 218
 219 &uart2 {
 220         status = "okay";
 221 };
 222
 223 &can1 {
 224         status = "okay";
 225 };
 226
 227 &can2 {
 228         status = "okay";
 229 };
 230
 231 &i2c3 {
 232         status = "okay";
 233 };
 234
 235 &tve {
 236         pinctrl-names = "default";
 237         pinctrl-0 = <&pinctrl_vga_sync_1>;
 238         ddc = <&i2c3>;
 239         fsl,tve-mode = "vga";
 240         fsl,hsync-pin = <4>;
 241         fsl,vsync-pin = <6>;
 242         status = "okay";
 243 };