arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         compatible = "ti,dra7xx";
  20         interrupt-parent = <&gic>;
  21
  22         aliases {
  23                 i2c0 = &i2c1;
  24                 i2c1 = &i2c2;
  25                 i2c2 = &i2c3;
  26                 i2c3 = &i2c4;
  27                 i2c4 = &i2c5;
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 serial3 = &uart4;
  32                 serial4 = &uart5;
  33                 serial5 = &uart6;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu0: cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0>;
  44
  45                         operating-points = <
  46                                 /* kHz    uV */
  47                                 1000000 1060000
  48                                 1176000 1160000
  49                                 >;
  50
  51                         clocks = <&dpll_mpu_ck>;
  52                         clock-names = "cpu";
  53
  54                         clock-latency = <300000>; /* From omap-cpufreq driver */
  55                 };
  56                 cpu@1 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <1>;
  60                 };
  61         };
  62
  63         timer {
  64                 compatible = "arm,armv7-timer";
  65                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  66                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  67                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  68                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  69         };
  70
  71         gic: interrupt-controller@48211000 {
  72                 compatible = "arm,cortex-a15-gic";
  73                 interrupt-controller;
  74                 #interrupt-cells = <3>;
  75                 reg = <0x48211000 0x1000>,
  76                       <0x48212000 0x1000>,
  77                       <0x48214000 0x2000>,
  78                       <0x48216000 0x2000>;
  79                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  80         };
  81
  82         /*
  83          * The soc node represents the soc top level view. It is uses for IPs
  84          * that are not memory mapped in the MPU view or for the MPU itself.
  85          */
  86         soc {
  87                 compatible = "ti,omap-infra";
  88                 mpu {
  89                         compatible = "ti,omap5-mpu";
  90                         ti,hwmods = "mpu";
  91                 };
  92         };
  93
  94         /*
  95          * XXX: Use a flat representation of the SOC interconnect.
  96          * The real OMAP interconnect network is quite complex.
  97          * Since that will not bring real advantage to represent that in DT for
  98          * the moment, just use a fake OCP bus entry to represent the whole bus
  99          * hierarchy.
 100          */
 101         ocp {
 102                 compatible = "ti,omap4-l3-noc", "simple-bus";
 103                 #address-cells = <1>;
 104                 #size-cells = <1>;
 105                 ranges;
 106                 ti,hwmods = "l3_main_1", "l3_main_2";
 107                 reg = <0x44000000 0x2000>,
 108                       <0x44800000 0x3000>;
 109                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 110                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 111
 112                 prm: prm@4ae06000 {
 113                         compatible = "ti,dra7-prm";
 114                         reg = <0x4ae06000 0x3000>;
 115
 116                         prm_clocks: clocks {
 117                                 #address-cells = <1>;
 118                                 #size-cells = <0>;
 119                         };
 120
 121                         prm_clockdomains: clockdomains {
 122                         };
 123                 };
 124
 125                 cm_core_aon: cm_core_aon@4a005000 {
 126                         compatible = "ti,dra7-cm-core-aon";
 127                         reg = <0x4a005000 0x2000>;
 128
 129                         cm_core_aon_clocks: clocks {
 130                                 #address-cells = <1>;
 131                                 #size-cells = <0>;
 132                         };
 133
 134                         cm_core_aon_clockdomains: clockdomains {
 135                         };
 136                 };
 137
 138                 cm_core: cm_core@4a008000 {
 139                         compatible = "ti,dra7-cm-core";
 140                         reg = <0x4a008000 0x3000>;
 141
 142                         cm_core_clocks: clocks {
 143                                 #address-cells = <1>;
 144                                 #size-cells = <0>;
 145                         };
 146
 147                         cm_core_clockdomains: clockdomains {
 148                         };
 149                 };
 150
 151                 counter32k: counter@4ae04000 {
 152                         compatible = "ti,omap-counter32k";
 153                         reg = <0x4ae04000 0x40>;
 154                         ti,hwmods = "counter_32k";
 155                 };
 156
 157                 dra7_pmx_core: pinmux@4a003400 {
 158                         compatible = "pinctrl-single";
 159                         reg = <0x4a003400 0x0464>;
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162                         pinctrl-single,register-width = <32>;
 163                         pinctrl-single,function-mask = <0x3fffffff>;
 164                 };
 165
 166                 sdma: dma-controller@4a056000 {
 167                         compatible = "ti,omap4430-sdma";
 168                         reg = <0x4a056000 0x1000>;
 169                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 170                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 171                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 172                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 173                         #dma-cells = <1>;
 174                         #dma-channels = <32>;
 175                         #dma-requests = <127>;
 176                 };
 177
 178                 gpio1: gpio@4ae10000 {
 179                         compatible = "ti,omap4-gpio";
 180                         reg = <0x4ae10000 0x200>;
 181                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 182                         ti,hwmods = "gpio1";
 183                         gpio-controller;
 184                         #gpio-cells = <2>;
 185                         interrupt-controller;
 186                         #interrupt-cells = <1>;
 187                 };
 188
 189                 gpio2: gpio@48055000 {
 190                         compatible = "ti,omap4-gpio";
 191                         reg = <0x48055000 0x200>;
 192                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 193                         ti,hwmods = "gpio2";
 194                         gpio-controller;
 195                         #gpio-cells = <2>;
 196                         interrupt-controller;
 197                         #interrupt-cells = <1>;
 198                 };
 199
 200                 gpio3: gpio@48057000 {
 201                         compatible = "ti,omap4-gpio";
 202                         reg = <0x48057000 0x200>;
 203                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 204                         ti,hwmods = "gpio3";
 205                         gpio-controller;
 206                         #gpio-cells = <2>;
 207                         interrupt-controller;
 208                         #interrupt-cells = <1>;
 209                 };
 210
 211                 gpio4: gpio@48059000 {
 212                         compatible = "ti,omap4-gpio";
 213                         reg = <0x48059000 0x200>;
 214                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 215                         ti,hwmods = "gpio4";
 216                         gpio-controller;
 217                         #gpio-cells = <2>;
 218                         interrupt-controller;
 219                         #interrupt-cells = <1>;
 220                 };
 221
 222                 gpio5: gpio@4805b000 {
 223                         compatible = "ti,omap4-gpio";
 224                         reg = <0x4805b000 0x200>;
 225                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 226                         ti,hwmods = "gpio5";
 227                         gpio-controller;
 228                         #gpio-cells = <2>;
 229                         interrupt-controller;
 230                         #interrupt-cells = <1>;
 231                 };
 232
 233                 gpio6: gpio@4805d000 {
 234                         compatible = "ti,omap4-gpio";
 235                         reg = <0x4805d000 0x200>;
 236                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 237                         ti,hwmods = "gpio6";
 238                         gpio-controller;
 239                         #gpio-cells = <2>;
 240                         interrupt-controller;
 241                         #interrupt-cells = <1>;
 242                 };
 243
 244                 gpio7: gpio@48051000 {
 245                         compatible = "ti,omap4-gpio";
 246                         reg = <0x48051000 0x200>;
 247                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 248                         ti,hwmods = "gpio7";
 249                         gpio-controller;
 250                         #gpio-cells = <2>;
 251                         interrupt-controller;
 252                         #interrupt-cells = <1>;
 253                 };
 254
 255                 gpio8: gpio@48053000 {
 256                         compatible = "ti,omap4-gpio";
 257                         reg = <0x48053000 0x200>;
 258                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 259                         ti,hwmods = "gpio8";
 260                         gpio-controller;
 261                         #gpio-cells = <2>;
 262                         interrupt-controller;
 263                         #interrupt-cells = <1>;
 264                 };
 265
 266                 uart1: serial@4806a000 {
 267                         compatible = "ti,omap4-uart";
 268                         reg = <0x4806a000 0x100>;
 269                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 270                         ti,hwmods = "uart1";
 271                         clock-frequency = <48000000>;
 272                         status = "disabled";
 273                 };
 274
 275                 uart2: serial@4806c000 {
 276                         compatible = "ti,omap4-uart";
 277                         reg = <0x4806c000 0x100>;
 278                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 279                         ti,hwmods = "uart2";
 280                         clock-frequency = <48000000>;
 281                         status = "disabled";
 282                 };
 283
 284                 uart3: serial@48020000 {
 285                         compatible = "ti,omap4-uart";
 286                         reg = <0x48020000 0x100>;
 287                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 288                         ti,hwmods = "uart3";
 289                         clock-frequency = <48000000>;
 290                         status = "disabled";
 291                 };
 292
 293                 uart4: serial@4806e000 {
 294                         compatible = "ti,omap4-uart";
 295                         reg = <0x4806e000 0x100>;
 296                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 297                         ti,hwmods = "uart4";
 298                         clock-frequency = <48000000>;
 299                         status = "disabled";
 300                 };
 301
 302                 uart5: serial@48066000 {
 303                         compatible = "ti,omap4-uart";
 304                         reg = <0x48066000 0x100>;
 305                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 306                         ti,hwmods = "uart5";
 307                         clock-frequency = <48000000>;
 308                         status = "disabled";
 309                 };
 310
 311                 uart6: serial@48068000 {
 312                         compatible = "ti,omap4-uart";
 313                         reg = <0x48068000 0x100>;
 314                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 315                         ti,hwmods = "uart6";
 316                         clock-frequency = <48000000>;
 317                         status = "disabled";
 318                 };
 319
 320                 uart7: serial@48420000 {
 321                         compatible = "ti,omap4-uart";
 322                         reg = <0x48420000 0x100>;
 323                         ti,hwmods = "uart7";
 324                         clock-frequency = <48000000>;
 325                         status = "disabled";
 326                 };
 327
 328                 uart8: serial@48422000 {
 329                         compatible = "ti,omap4-uart";
 330                         reg = <0x48422000 0x100>;
 331                         ti,hwmods = "uart8";
 332                         clock-frequency = <48000000>;
 333                         status = "disabled";
 334                 };
 335
 336                 uart9: serial@48424000 {
 337                         compatible = "ti,omap4-uart";
 338                         reg = <0x48424000 0x100>;
 339                         ti,hwmods = "uart9";
 340                         clock-frequency = <48000000>;
 341                         status = "disabled";
 342                 };
 343
 344                 uart10: serial@4ae2b000 {
 345                         compatible = "ti,omap4-uart";
 346                         reg = <0x4ae2b000 0x100>;
 347                         ti,hwmods = "uart10";
 348                         clock-frequency = <48000000>;
 349                         status = "disabled";
 350                 };
 351
 352                 timer1: timer@4ae18000 {
 353                         compatible = "ti,omap5430-timer";
 354                         reg = <0x4ae18000 0x80>;
 355                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 356                         ti,hwmods = "timer1";
 357                         ti,timer-alwon;
 358                 };
 359
 360                 timer2: timer@48032000 {
 361                         compatible = "ti,omap5430-timer";
 362                         reg = <0x48032000 0x80>;
 363                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 364                         ti,hwmods = "timer2";
 365                 };
 366
 367                 timer3: timer@48034000 {
 368                         compatible = "ti,omap5430-timer";
 369                         reg = <0x48034000 0x80>;
 370                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 371                         ti,hwmods = "timer3";
 372                 };
 373
 374                 timer4: timer@48036000 {
 375                         compatible = "ti,omap5430-timer";
 376                         reg = <0x48036000 0x80>;
 377                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 378                         ti,hwmods = "timer4";
 379                 };
 380
 381                 timer5: timer@48820000 {
 382                         compatible = "ti,omap5430-timer";
 383                         reg = <0x48820000 0x80>;
 384                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 385                         ti,hwmods = "timer5";
 386                         ti,timer-dsp;
 387                 };
 388
 389                 timer6: timer@48822000 {
 390                         compatible = "ti,omap5430-timer";
 391                         reg = <0x48822000 0x80>;
 392                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 393                         ti,hwmods = "timer6";
 394                         ti,timer-dsp;
 395                         ti,timer-pwm;
 396                 };
 397
 398                 timer7: timer@48824000 {
 399                         compatible = "ti,omap5430-timer";
 400                         reg = <0x48824000 0x80>;
 401                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 402                         ti,hwmods = "timer7";
 403                         ti,timer-dsp;
 404                 };
 405
 406                 timer8: timer@48826000 {
 407                         compatible = "ti,omap5430-timer";
 408                         reg = <0x48826000 0x80>;
 409                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 410                         ti,hwmods = "timer8";
 411                         ti,timer-dsp;
 412                         ti,timer-pwm;
 413                 };
 414
 415                 timer9: timer@4803e000 {
 416                         compatible = "ti,omap5430-timer";
 417                         reg = <0x4803e000 0x80>;
 418                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 419                         ti,hwmods = "timer9";
 420                 };
 421
 422                 timer10: timer@48086000 {
 423                         compatible = "ti,omap5430-timer";
 424                         reg = <0x48086000 0x80>;
 425                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 426                         ti,hwmods = "timer10";
 427                 };
 428
 429                 timer11: timer@48088000 {
 430                         compatible = "ti,omap5430-timer";
 431                         reg = <0x48088000 0x80>;
 432                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 433                         ti,hwmods = "timer11";
 434                         ti,timer-pwm;
 435                 };
 436
 437                 timer13: timer@48828000 {
 438                         compatible = "ti,omap5430-timer";
 439                         reg = <0x48828000 0x80>;
 440                         ti,hwmods = "timer13";
 441                         status = "disabled";
 442                 };
 443
 444                 timer14: timer@4882a000 {
 445                         compatible = "ti,omap5430-timer";
 446                         reg = <0x4882a000 0x80>;
 447                         ti,hwmods = "timer14";
 448                         status = "disabled";
 449                 };
 450
 451                 timer15: timer@4882c000 {
 452                         compatible = "ti,omap5430-timer";
 453                         reg = <0x4882c000 0x80>;
 454                         ti,hwmods = "timer15";
 455                         status = "disabled";
 456                 };
 457
 458                 timer16: timer@4882e000 {
 459                         compatible = "ti,omap5430-timer";
 460                         reg = <0x4882e000 0x80>;
 461                         ti,hwmods = "timer16";
 462                         status = "disabled";
 463                 };
 464
 465                 wdt2: wdt@4ae14000 {
 466                         compatible = "ti,omap4-wdt";
 467                         reg = <0x4ae14000 0x80>;
 468                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 469                         ti,hwmods = "wd_timer2";
 470                 };
 471
 472                 hwspinlock: spinlock@4a0f6000 {
 473                         compatible = "ti,omap4-hwspinlock";
 474                         reg = <0x4a0f6000 0x1000>;
 475                         ti,hwmods = "spinlock";
 476                         #hwlock-cells = <1>;
 477                 };
 478
 479                 dmm@4e000000 {
 480                         compatible = "ti,omap5-dmm";
 481                         reg = <0x4e000000 0x800>;
 482                         interrupts = <0 113 0x4>;
 483                         ti,hwmods = "dmm";
 484                 };
 485
 486                 i2c1: i2c@48070000 {
 487                         compatible = "ti,omap4-i2c";
 488                         reg = <0x48070000 0x100>;
 489                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 490                         #address-cells = <1>;
 491                         #size-cells = <0>;
 492                         ti,hwmods = "i2c1";
 493                         status = "disabled";
 494                 };
 495
 496                 i2c2: i2c@48072000 {
 497                         compatible = "ti,omap4-i2c";
 498                         reg = <0x48072000 0x100>;
 499                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 500                         #address-cells = <1>;
 501                         #size-cells = <0>;
 502                         ti,hwmods = "i2c2";
 503                         status = "disabled";
 504                 };
 505
 506                 i2c3: i2c@48060000 {
 507                         compatible = "ti,omap4-i2c";
 508                         reg = <0x48060000 0x100>;
 509                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 510                         #address-cells = <1>;
 511                         #size-cells = <0>;
 512                         ti,hwmods = "i2c3";
 513                         status = "disabled";
 514                 };
 515
 516                 i2c4: i2c@4807a000 {
 517                         compatible = "ti,omap4-i2c";
 518                         reg = <0x4807a000 0x100>;
 519                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 520                         #address-cells = <1>;
 521                         #size-cells = <0>;
 522                         ti,hwmods = "i2c4";
 523                         status = "disabled";
 524                 };
 525
 526                 i2c5: i2c@4807c000 {
 527                         compatible = "ti,omap4-i2c";
 528                         reg = <0x4807c000 0x100>;
 529                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         ti,hwmods = "i2c5";
 533                         status = "disabled";
 534                 };
 535
 536                 mmc1: mmc@4809c000 {
 537                         compatible = "ti,omap4-hsmmc";
 538                         reg = <0x4809c000 0x400>;
 539                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 540                         ti,hwmods = "mmc1";
 541                         ti,dual-volt;
 542                         ti,needs-special-reset;
 543                         dmas = <&sdma 61>, <&sdma 62>;
 544                         dma-names = "tx", "rx";
 545                         status = "disabled";
 546                 };
 547
 548                 mmc2: mmc@480b4000 {
 549                         compatible = "ti,omap4-hsmmc";
 550                         reg = <0x480b4000 0x400>;
 551                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 552                         ti,hwmods = "mmc2";
 553                         ti,needs-special-reset;
 554                         dmas = <&sdma 47>, <&sdma 48>;
 555                         dma-names = "tx", "rx";
 556                         status = "disabled";
 557                 };
 558
 559                 mmc3: mmc@480ad000 {
 560                         compatible = "ti,omap4-hsmmc";
 561                         reg = <0x480ad000 0x400>;
 562                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 563                         ti,hwmods = "mmc3";
 564                         ti,needs-special-reset;
 565                         dmas = <&sdma 77>, <&sdma 78>;
 566                         dma-names = "tx", "rx";
 567                         status = "disabled";
 568                 };
 569
 570                 mmc4: mmc@480d1000 {
 571                         compatible = "ti,omap4-hsmmc";
 572                         reg = <0x480d1000 0x400>;
 573                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 574                         ti,hwmods = "mmc4";
 575                         ti,needs-special-reset;
 576                         dmas = <&sdma 57>, <&sdma 58>;
 577                         dma-names = "tx", "rx";
 578                         status = "disabled";
 579                 };
 580
 581                 abb_mpu: regulator-abb-mpu {
 582                         compatible = "ti,abb-v3";
 583                         regulator-name = "abb_mpu";
 584                         #address-cells = <0>;
 585                         #size-cells = <0>;
 586                         clocks = <&sys_clkin1>;
 587                         ti,settling-time = <50>;
 588                         ti,clock-cycles = <16>;
 589
 590                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 591                               <0x4ae06014 0x4>, <0x4a003b20 0x8>,
 592                               <0x4ae0c158 0x4>;
 593                         reg-names = "setup-address", "control-address",
 594                                     "int-address", "efuse-address",
 595                                     "ldo-address";
 596                         ti,tranxdone-status-mask = <0x80>;
 597                         /* LDOVBBMPU_FBB_MUX_CTRL */
 598                         ti,ldovbb-override-mask = <0x400>;
 599                         /* LDOVBBMPU_FBB_VSET_OUT */
 600                         ti,ldovbb-vset-mask = <0x1F>;
 601
 602                         /*
 603                          * NOTE: only FBB mode used but actual vset will
 604                          * determine final biasing
 605                          */
 606                         ti,abb_info = <
 607                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 608                         1060000         0       0x0     0 0x02000000 0x01F00000
 609                         1160000         0       0x4     0 0x02000000 0x01F00000
 610                         1210000         0       0x8     0 0x02000000 0x01F00000
 611                         >;
 612                 };
 613
 614                 abb_ivahd: regulator-abb-ivahd {
 615                         compatible = "ti,abb-v3";
 616                         regulator-name = "abb_ivahd";
 617                         #address-cells = <0>;
 618                         #size-cells = <0>;
 619                         clocks = <&sys_clkin1>;
 620                         ti,settling-time = <50>;
 621                         ti,clock-cycles = <16>;
 622
 623                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 624                               <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
 625                               <0x4a002470 0x4>;
 626                         reg-names = "setup-address", "control-address",
 627                                     "int-address", "efuse-address",
 628                                     "ldo-address";
 629                         ti,tranxdone-status-mask = <0x40000000>;
 630                         /* LDOVBBIVA_FBB_MUX_CTRL */
 631                         ti,ldovbb-override-mask = <0x400>;
 632                         /* LDOVBBIVA_FBB_VSET_OUT */
 633                         ti,ldovbb-vset-mask = <0x1F>;
 634
 635                         /*
 636                          * NOTE: only FBB mode used but actual vset will
 637                          * determine final biasing
 638                          */
 639                         ti,abb_info = <
 640                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 641                         1055000         0       0x0     0 0x02000000 0x01F00000
 642                         1150000         0       0x4     0 0x02000000 0x01F00000
 643                         1250000         0       0x8     0 0x02000000 0x01F00000
 644                         >;
 645                 };
 646
 647                 abb_dspeve: regulator-abb-dspeve {
 648                         compatible = "ti,abb-v3";
 649                         regulator-name = "abb_dspeve";
 650                         #address-cells = <0>;
 651                         #size-cells = <0>;
 652                         clocks = <&sys_clkin1>;
 653                         ti,settling-time = <50>;
 654                         ti,clock-cycles = <16>;
 655
 656                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 657                               <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
 658                               <0x4a00246c 0x4>;
 659                         reg-names = "setup-address", "control-address",
 660                                     "int-address", "efuse-address",
 661                                     "ldo-address";
 662                         ti,tranxdone-status-mask = <0x20000000>;
 663                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 664                         ti,ldovbb-override-mask = <0x400>;
 665                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 666                         ti,ldovbb-vset-mask = <0x1F>;
 667
 668                         /*
 669                          * NOTE: only FBB mode used but actual vset will
 670                          * determine final biasing
 671                          */
 672                         ti,abb_info = <
 673                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 674                         1055000         0       0x0     0 0x02000000 0x01F00000
 675                         1150000         0       0x4     0 0x02000000 0x01F00000
 676                         1250000         0       0x8     0 0x02000000 0x01F00000
 677                         >;
 678                 };
 679
 680                 abb_gpu: regulator-abb-gpu {
 681                         compatible = "ti,abb-v3";
 682                         regulator-name = "abb_gpu";
 683                         #address-cells = <0>;
 684                         #size-cells = <0>;
 685                         clocks = <&sys_clkin1>;
 686                         ti,settling-time = <50>;
 687                         ti,clock-cycles = <16>;
 688
 689                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
 690                               <0x4ae06010 0x4>, <0x4a003b08 0x8>,
 691                               <0x4ae0c154 0x4>;
 692                         reg-names = "setup-address", "control-address",
 693                                     "int-address", "efuse-address",
 694                                     "ldo-address";
 695                         ti,tranxdone-status-mask = <0x10000000>;
 696                         /* LDOVBBGPU_FBB_MUX_CTRL */
 697                         ti,ldovbb-override-mask = <0x400>;
 698                         /* LDOVBBGPU_FBB_VSET_OUT */
 699                         ti,ldovbb-vset-mask = <0x1F>;
 700
 701                         /*
 702                          * NOTE: only FBB mode used but actual vset will
 703                          * determine final biasing
 704                          */
 705                         ti,abb_info = <
 706                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 707                         1090000         0       0x0     0 0x02000000 0x01F00000
 708                         1210000         0       0x4     0 0x02000000 0x01F00000
 709                         1280000         0       0x8     0 0x02000000 0x01F00000
 710                         >;
 711                 };
 712
 713                 mcspi1: spi@48098000 {
 714                         compatible = "ti,omap4-mcspi";
 715                         reg = <0x48098000 0x200>;
 716                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 717                         #address-cells = <1>;
 718                         #size-cells = <0>;
 719                         ti,hwmods = "mcspi1";
 720                         ti,spi-num-cs = <4>;
 721                         dmas = <&sdma 35>,
 722                                <&sdma 36>,
 723                                <&sdma 37>,
 724                                <&sdma 38>,
 725                                <&sdma 39>,
 726                                <&sdma 40>,
 727                                <&sdma 41>,
 728                                <&sdma 42>;
 729                         dma-names = "tx0", "rx0", "tx1", "rx1",
 730                                     "tx2", "rx2", "tx3", "rx3";
 731                         status = "disabled";
 732                 };
 733
 734                 mcspi2: spi@4809a000 {
 735                         compatible = "ti,omap4-mcspi";
 736                         reg = <0x4809a000 0x200>;
 737                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 738                         #address-cells = <1>;
 739                         #size-cells = <0>;
 740                         ti,hwmods = "mcspi2";
 741                         ti,spi-num-cs = <2>;
 742                         dmas = <&sdma 43>,
 743                                <&sdma 44>,
 744                                <&sdma 45>,
 745                                <&sdma 46>;
 746                         dma-names = "tx0", "rx0", "tx1", "rx1";
 747                         status = "disabled";
 748                 };
 749
 750                 mcspi3: spi@480b8000 {
 751                         compatible = "ti,omap4-mcspi";
 752                         reg = <0x480b8000 0x200>;
 753                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 754                         #address-cells = <1>;
 755                         #size-cells = <0>;
 756                         ti,hwmods = "mcspi3";
 757                         ti,spi-num-cs = <2>;
 758                         dmas = <&sdma 15>, <&sdma 16>;
 759                         dma-names = "tx0", "rx0";
 760                         status = "disabled";
 761                 };
 762
 763                 mcspi4: spi@480ba000 {
 764                         compatible = "ti,omap4-mcspi";
 765                         reg = <0x480ba000 0x200>;
 766                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 767                         #address-cells = <1>;
 768                         #size-cells = <0>;
 769                         ti,hwmods = "mcspi4";
 770                         ti,spi-num-cs = <1>;
 771                         dmas = <&sdma 70>, <&sdma 71>;
 772                         dma-names = "tx0", "rx0";
 773                         status = "disabled";
 774                 };
 775         };
 776 };
 777
 778 /include/ "dra7xx-clocks.dtsi"