arch/arm/boot/dts/armada-375.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 375 family SoC
   3  *
   4  * Copyright (C) 2014 Marvell
   5  *
   6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2.  This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include "skeleton.dtsi"
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17
  18 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  19
  20 / {
  21         model = "Marvell Armada 375 family SoC";
  22         compatible = "marvell,armada375";
  23
  24         aliases {
  25                 gpio0 = &gpio0;
  26                 gpio1 = &gpio1;
  27                 gpio2 = &gpio2;
  28         };
  29
  30         clocks {
  31                 /* 2 GHz fixed main PLL */
  32                 mainpll: mainpll {
  33                         compatible = "fixed-clock";
  34                         #clock-cells = <0>;
  35                         clock-frequency = <2000000000>;
  36                 };
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42                 cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a9";
  45                         reg = <0>;
  46                 };
  47                 cpu@1 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a9";
  50                         reg = <1>;
  51                 };
  52         };
  53
  54         soc {
  55                 compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
  56                 #address-cells = <2>;
  57                 #size-cells = <1>;
  58                 controller = <&mbusc>;
  59                 interrupt-parent = <&gic>;
  60                 pcie-mem-aperture = <0xe0000000 0x8000000>;
  61                 pcie-io-aperture  = <0xe8000000 0x100000>;
  62
  63                 bootrom {
  64                         compatible = "marvell,bootrom";
  65                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
  66                 };
  67
  68                 devbus-bootcs {
  69                         compatible = "marvell,mvebu-devbus";
  70                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
  71                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         clocks = <&coreclk 0>;
  75                         status = "disabled";
  76                 };
  77
  78                 devbus-cs0 {
  79                         compatible = "marvell,mvebu-devbus";
  80                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
  81                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
  82                         #address-cells = <1>;
  83                         #size-cells = <1>;
  84                         clocks = <&coreclk 0>;
  85                         status = "disabled";
  86                 };
  87
  88                 devbus-cs1 {
  89                         compatible = "marvell,mvebu-devbus";
  90                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
  91                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
  92                         #address-cells = <1>;
  93                         #size-cells = <1>;
  94                         clocks = <&coreclk 0>;
  95                         status = "disabled";
  96                 };
  97
  98                 devbus-cs2 {
  99                         compatible = "marvell,mvebu-devbus";
 100                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
 101                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104                         clocks = <&coreclk 0>;
 105                         status = "disabled";
 106                 };
 107
 108                 devbus-cs3 {
 109                         compatible = "marvell,mvebu-devbus";
 110                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
 111                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
 112                         #address-cells = <1>;
 113                         #size-cells = <1>;
 114                         clocks = <&coreclk 0>;
 115                         status = "disabled";
 116                 };
 117
 118                 internal-regs {
 119                         compatible = "simple-bus";
 120                         #address-cells = <1>;
 121                         #size-cells = <1>;
 122                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 123
 124                         L2: cache-controller@8000 {
 125                                 compatible = "arm,pl310-cache";
 126                                 reg = <0x8000 0x1000>;
 127                                 cache-unified;
 128                                 cache-level = <2>;
 129                         };
 130
 131                         timer@c600 {
 132                                 compatible = "arm,cortex-a9-twd-timer";
 133                                 reg = <0xc600 0x20>;
 134                                 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
 135                                 clocks = <&coreclk 2>;
 136                         };
 137
 138                         gic: interrupt-controller@d000 {
 139                                 compatible = "arm,cortex-a9-gic";
 140                                 #interrupt-cells = <3>;
 141                                 #size-cells = <0>;
 142                                 interrupt-controller;
 143                                 reg = <0xd000 0x1000>,
 144                                       <0xc100 0x100>;
 145                         };
 146
 147                         spi0: spi@10600 {
 148                                 compatible = "marvell,orion-spi";
 149                                 reg = <0x10600 0x50>;
 150                                 #address-cells = <1>;
 151                                 #size-cells = <0>;
 152                                 cell-index = <0>;
 153                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 154                                 clocks = <&coreclk 0>;
 155                                 status = "disabled";
 156                         };
 157
 158                         spi1: spi@10680 {
 159                                 compatible = "marvell,orion-spi";
 160                                 reg = <0x10680 0x50>;
 161                                 #address-cells = <1>;
 162                                 #size-cells = <0>;
 163                                 cell-index = <1>;
 164                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 165                                 clocks = <&coreclk 0>;
 166                                 status = "disabled";
 167                         };
 168
 169                         i2c0: i2c@11000 {
 170                                 compatible = "marvell,mv64xxx-i2c";
 171                                 reg = <0x11000 0x20>;
 172                                 #address-cells = <1>;
 173                                 #size-cells = <0>;
 174                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 175                                 timeout-ms = <1000>;
 176                                 clocks = <&coreclk 0>;
 177                                 status = "disabled";
 178                         };
 179
 180                         i2c1: i2c@11100 {
 181                                 compatible = "marvell,mv64xxx-i2c";
 182                                 reg = <0x11100 0x20>;
 183                                 #address-cells = <1>;
 184                                 #size-cells = <0>;
 185                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 186                                 timeout-ms = <1000>;
 187                                 clocks = <&coreclk 0>;
 188                                 status = "disabled";
 189                         };
 190
 191                         serial@12000 {
 192                                 compatible = "snps,dw-apb-uart";
 193                                 reg = <0x12000 0x100>;
 194                                 reg-shift = <2>;
 195                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 196                                 reg-io-width = <1>;
 197                                 status = "disabled";
 198                         };
 199
 200                         serial@12100 {
 201                                 compatible = "snps,dw-apb-uart";
 202                                 reg = <0x12100 0x100>;
 203                                 reg-shift = <2>;
 204                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 205                                 reg-io-width = <1>;
 206                                 status = "disabled";
 207                         };
 208
 209                         pinctrl {
 210                                 compatible = "marvell,mv88f6720-pinctrl";
 211                                 reg = <0x18000 0x24>;
 212
 213                                 i2c0_pins: i2c0-pins {
 214                                         marvell,pins = "mpp14",  "mpp15";
 215                                         marvell,function = "i2c0";
 216                                 };
 217
 218                                 i2c1_pins: i2c1-pins {
 219                                         marvell,pins = "mpp61",  "mpp62";
 220                                         marvell,function = "i2c1";
 221                                 };
 222
 223                                 nand_pins: nand-pins {
 224                                         marvell,pins = "mpp0", "mpp1", "mpp2",
 225                                                 "mpp3", "mpp4", "mpp5",
 226                                                 "mpp6", "mpp7", "mpp8",
 227                                                 "mpp9", "mpp10", "mpp11",
 228                                                 "mpp12", "mpp13";
 229                                         marvell,function = "nand";
 230                                 };
 231
 232                                 sdio_pins: sdio-pins {
 233                                         marvell,pins = "mpp24",  "mpp25", "mpp26",
 234                                                      "mpp27", "mpp28", "mpp29";
 235                                         marvell,function = "sd";
 236                                 };
 237
 238                                 spi0_pins: spi0-pins {
 239                                         marvell,pins = "mpp0",  "mpp1", "mpp4",
 240                                                      "mpp5", "mpp8", "mpp9";
 241                                         marvell,function = "spi0";
 242                                 };
 243                         };
 244
 245                         gpio0: gpio@18100 {
 246                                 compatible = "marvell,orion-gpio";
 247                                 reg = <0x18100 0x40>;
 248                                 ngpios = <32>;
 249                                 gpio-controller;
 250                                 #gpio-cells = <2>;
 251                                 interrupt-controller;
 252                                 #interrupt-cells = <2>;
 253                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 254                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 255                                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 256                                              <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 257                         };
 258
 259                         gpio1: gpio@18140 {
 260                                 compatible = "marvell,orion-gpio";
 261                                 reg = <0x18140 0x40>;
 262                                 ngpios = <32>;
 263                                 gpio-controller;
 264                                 #gpio-cells = <2>;
 265                                 interrupt-controller;
 266                                 #interrupt-cells = <2>;
 267                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 268                                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 269                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 270                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 271                         };
 272
 273                         gpio2: gpio@18180 {
 274                                 compatible = "marvell,orion-gpio";
 275                                 reg = <0x18180 0x40>;
 276                                 ngpios = <3>;
 277                                 gpio-controller;
 278                                 #gpio-cells = <2>;
 279                                 interrupt-controller;
 280                                 #interrupt-cells = <2>;
 281                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 282                         };
 283
 284                         system-controller@18200 {
 285                                 compatible = "marvell,armada-375-system-controller";
 286                                 reg = <0x18200 0x100>;
 287                         };
 288
 289                         gateclk: clock-gating-control@18220 {
 290                                 compatible = "marvell,armada-375-gating-clock";
 291                                 reg = <0x18220 0x4>;
 292                                 clocks = <&coreclk 0>;
 293                                 #clock-cells = <1>;
 294                         };
 295
 296                         mbusc: mbus-controller@20000 {
 297                                 compatible = "marvell,mbus-controller";
 298                                 reg = <0x20000 0x100>, <0x20180 0x20>;
 299                         };
 300
 301                         mpic: interrupt-controller@20000 {
 302                                 compatible = "marvell,mpic";
 303                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 304                                 #interrupt-cells = <1>;
 305                                 #size-cells = <1>;
 306                                 interrupt-controller;
 307                                 msi-controller;
 308                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 309                         };
 310
 311                         timer@20300 {
 312                                 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
 313                                 reg = <0x20300 0x30>, <0x21040 0x30>;
 314                                 interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
 315                                                       <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 316                                                       <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 317                                                       <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 318                                                       <&mpic 5>,
 319                                                       <&mpic 6>;
 320                                 clocks = <&coreclk 0>;
 321                         };
 322
 323                         xor@60800 {
 324                                 compatible = "marvell,orion-xor";
 325                                 reg = <0x60800 0x100
 326                                        0x60A00 0x100>;
 327                                 clocks = <&gateclk 22>;
 328                                 status = "okay";
 329
 330                                 xor00 {
 331                                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 332                                         dmacap,memcpy;
 333                                         dmacap,xor;
 334                                 };
 335                                 xor01 {
 336                                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 337                                         dmacap,memcpy;
 338                                         dmacap,xor;
 339                                         dmacap,memset;
 340                                 };
 341                         };
 342
 343                         xor@60900 {
 344                                 compatible = "marvell,orion-xor";
 345                                 reg = <0x60900 0x100
 346                                        0x60b00 0x100>;
 347                                 clocks = <&gateclk 23>;
 348                                 status = "okay";
 349
 350                                 xor10 {
 351                                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 352                                         dmacap,memcpy;
 353                                         dmacap,xor;
 354                                 };
 355                                 xor11 {
 356                                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 357                                         dmacap,memcpy;
 358                                         dmacap,xor;
 359                                         dmacap,memset;
 360                                 };
 361                         };
 362
 363                         sata@a0000 {
 364                                 compatible = "marvell,orion-sata";
 365                                 reg = <0xa0000 0x5000>;
 366                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 367                                 clocks = <&gateclk 14>, <&gateclk 20>;
 368                                 clock-names = "0", "1";
 369                                 status = "disabled";
 370                         };
 371
 372                         nand@d0000 {
 373                                 compatible = "marvell,armada370-nand";
 374                                 reg = <0xd0000 0x54>;
 375                                 #address-cells = <1>;
 376                                 #size-cells = <1>;
 377                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 378                                 clocks = <&gateclk 11>;
 379                                 status = "disabled";
 380                         };
 381
 382                         mvsdio@d4000 {
 383                                 compatible = "marvell,orion-sdio";
 384                                 reg = <0xd4000 0x200>;
 385                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 386                                 clocks = <&gateclk 17>;
 387                                 bus-width = <4>;
 388                                 cap-sdio-irq;
 389                                 cap-sd-highspeed;
 390                                 cap-mmc-highspeed;
 391                                 status = "disabled";
 392                         };
 393
 394                         coreclk: mvebu-sar@e8204 {
 395                                 compatible = "marvell,armada-375-core-clock";
 396                                 reg = <0xe8204 0x04>;
 397                                 #clock-cells = <1>;
 398                         };
 399
 400                         coredivclk: corediv-clock@e8250 {
 401                                 compatible = "marvell,armada-375-corediv-clock";
 402                                 reg = <0xe8250 0xc>;
 403                                 #clock-cells = <1>;
 404                                 clocks = <&mainpll>;
 405                                 clock-output-names = "nand";
 406                         };
 407                 };
 408
 409                 pcie-controller {
 410                         compatible = "marvell,armada-370-pcie";
 411                         status = "disabled";
 412                         device_type = "pci";
 413
 414                         #address-cells = <3>;
 415                         #size-cells = <2>;
 416
 417                         msi-parent = <&mpic>;
 418                         bus-range = <0x00 0xff>;
 419
 420                         ranges =
 421                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
 422                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
 423                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
 424                                 0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
 425                                 0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
 426                                 0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;
 427
 428                         pcie@1,0 {
 429                                 device_type = "pci";
 430                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 431                                 reg = <0x0800 0 0 0 0>;
 432                                 #address-cells = <3>;
 433                                 #size-cells = <2>;
 434                                 #interrupt-cells = <1>;
 435                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 436                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 437                                 interrupt-map-mask = <0 0 0 0>;
 438                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 439                                 marvell,pcie-port = <0>;
 440                                 marvell,pcie-lane = <0>;
 441                                 clocks = <&gateclk 5>;
 442                                 status = "disabled";
 443                         };
 444
 445                         pcie@2,0 {
 446                                 device_type = "pci";
 447                                 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 448                                 reg = <0x1000 0 0 0 0>;
 449                                 #address-cells = <3>;
 450                                 #size-cells = <2>;
 451                                 #interrupt-cells = <1>;
 452                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 453                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 454                                 interrupt-map-mask = <0 0 0 0>;
 455                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 456                                 marvell,pcie-port = <0>;
 457                                 marvell,pcie-lane = <1>;
 458                                 clocks = <&gateclk 6>;
 459                                 status = "disabled";
 460                         };
 461
 462                 };
 463         };
 464 };